Planar Jfet with Enhanced Channel Control

The present U.S. non-provisional patent application is related to and claims priority benefit of earlier-filed U.S. provisional patent application titled “Planar JFET with Enhanced Channel Control,” Ser. No. 63/704,400, filed Oct. 7, 2024, and U.S. provisional patent application titled “Planar JFET with Buried Gate,” Ser. No. 63/682,250, filed Aug. 12, 2024. The entire content of each of the identified earlier-filed applications is incorporated by reference as if fully set forth herein.

The present disclosure relates to junction field-effect transistors and methods of making them, and, more particularly, the various examples described herein concern a planar junction field-effect transistor with enhanced channel control, and a method of making a planar junction field-effect transistor with enhanced channel control.

A junction field-effect transistor (JFET) is an active, voltage-controlled semiconductor device, in which varying an electrical voltage between a gate and a source controls an electrical current flowing through a semiconductor channel between a drain and the source. Applications for JFETs include amplifiers, switches, resistors, regulators, oscillators, and choppers. It is generally desirable to improve the performance and reduce the cost of JFETs, but it can be difficult to do so.

This background discussion is intended to provide related information, and is not necessarily prior art.

Examples provide a planar JFET with enhanced channel control, and a method of making a planar JFET with enhanced channel control. Broadly, a second gate component divides a channel into multiple paths for electrical current to flow between the source and the drain. Examples advantageously provide improved performance, including improved channel control and lower electrical resistance to electrical current flow through the channel.

In an example, a planar JFET with enhanced channel control may include a source, a drain spaced apart from the source, a channel extending between the source and the drain, a first gate including a left first gate component and a right first gate component, and a second gate. The second gate may include a front second gate component located between and spaced apart from the source and the drain, and include a first side and a second side. The front second gate component may divide the channel into a first non-linear channel path and a second non-linear channel path. The first non-linear channel path may extend from the source toward the drain, turn and extend along the front second gate component in a first direction, and turn around the first side of the front second gate component and extend to the drain, wherein the front second gate component and the left first gate component cooperate to control a first electrical current flowing through the first non-linear channel path. The second non-linear channel path may extend from the source toward the drain, turn and extend along the front second gate component in a second direction, and turn around the second side of the front second gate component and extend to the drain, wherein the front second gate component and the right first gate component cooperate to control a second electrical current flowing through the second non-linear channel path.

The preceding example may further include any one or more of the following features. The front second gate component may be located at least partially between the left first gate component and the drain, and the front second gate component may be located at least partially between the right first gate component and the drain. The left first gate component may extend at least partially along the first side of the front second gate component, and the right first gate component may extend at least partially along the second side of the front second gate component. The front second gate component may be spaced apart from the source by a distance that is at least sufficient to achieve a breakdown voltage between the front second gate component and the source. The front second gate component may extend between two-tenths (0.2) and two (2) micrometers in a first dimension and between two-tenths (0.2) and two (2) micrometers in a second dimension. The source may include an N+ material, the drain may include an N+ substrate material, and the first gate and the second gate may include a P+ material. The front second gate component may include an extension in a third dimension, and the second gate may include a rear second gate component extending at an angle from the extension of the front second gate component. The planar JFET may further include a first electrical terminal provided on the source, a second electrical terminal provided on the drain, a third electrical terminal provided on the left first gate component, a fourth electrical terminal provided on the right first gate component, and a fifth electrical terminal provided on the rear second gate component.

In another example, a planar JFET with enhanced channel control may include a volume of semiconductor material, a source, a drain, a channel, a first gate, and a second gate. The volume of semiconductor material may include a first end, a second end, a first side, and a second side. The source may be located at the first end of the semiconductor material, the drain may be located at the second end and spaced apart from and opposite the source, and the channel may extend between the source and the drain through the semiconductor material. The first gate may include a left first gate component located at the first end and the first side of the volume of semiconductor material and spaced apart from the source, and a right first gate component located at the first end and the second side of the volume of semiconductor material and adjacent to and spaced apart from the source. The second gate may include a front second gate component and a rear second gate component. The front second gate component may be located spaced apart from and between the source and the drain and surrounded in two dimensions by the volume of semiconductor material, and the front second gate component may be located at least partially between the left first gate component and the drain and at least partially between the right first gate component and the drain, and may include a first side and a second side and an extension in a third dimension through the volume of semiconductor material. The rear second gate component may extend from the extension of the front second gate component to a surface at the first end of the volume of semiconductor material. The front second gate component may divide the channel into a first non-linear channel path and a second non-linear channel path. The first non-linear channel path may extend from the source toward the drain, turn and extend along the front second gate component in a first direction, and turn around the first side of the front second gate component and extend to the drain, wherein the front second gate component and the left first gate component cooperate to control a first electrical current flowing through the first non-linear channel path. The second non-linear channel path may extend from the source toward the drain, turn and extend along the front second gate component in a second direction, and turn around the second side of the front second gate component and extend to the drain, wherein the front second gate component and the right first gate component cooperate to control a second electrical current flowing through the second non-linear channel path.

The preceding example may further include any one or more of the following features. The front second gate component may be spaced apart from the source by a distance that is at least sufficient to achieve a breakdown voltage between the front second gate component and the source. The front second gate component extends between two-tenths (0.2) and two (2) micrometers in a first dimension and between two-tenths (0.2) and two (2) micrometers in a second dimension. The volume of semiconductor material may include an N-type epitaxial semiconductor material, the source may include an N+ material, the drain may include an N+ substrate material, and the first gate and the second gate may include a P+ material. The planar JFET may further include a first electrical terminal provided on the source, a second electrical terminal provided on the drain, a third electrical terminal provided on the left first gate component, a fourth electrical terminal provided on the right first gate component, and a fifth electrical terminal provided on the rear second gate component.

In another example, a planar JFET with enhanced channel control may include a volume of semiconductor material, a source, a drain, a channel, a first gate, and a second gate. The volume of semiconductor material may include a first end, a second end, a first side, and a second side. The source may be located at the first end of the semiconductor material, the drain may be located at the second end and spaced apart from and opposite the source, and the channel may extend between the source and the drain through the semiconductor material. The first gate may include a left first gate component located at the first end and the first side of the volume of semiconductor material and spaced apart from the source, and a right first gate component located at the first end and the second side of the volume of semiconductor material and spaced apart from the source. The second gate may include a front second gate component and a rear second gate component. The front second gate component may be located spaced apart from and between the source and the drain and surrounded in two dimensions by the volume of semiconductor material, and the front second gate component may be located at least partially between the left first gate component and the drain and at least partially between the right first gate component and the drain, and may include a first side and a second side, and the left first gate component extends at least partially along the first side of the front second gate component and the right first gate component extends at least partially along the second side of the front second gate component, and the front first gate component further includes an extension in a third dimension through the volume of semiconductor material. The rear second gate component may extend from the extension of the front second gate component to a surface at the first end of the volume of semiconductor material. The front second gate component may divide the channel into a first non-linear channel path and a second non-linear channel path. The first non-linear channel path may extend from the source toward the drain, turn and extend along the front second gate component in a first direction, and turn around the first side of the front second gate component and extend to the drain, wherein the front second gate component and the left first gate component cooperate to control a first electrical current flowing through the first non-linear channel path. The second non-linear channel path may extend from the source toward the drain, turn and extend along the front second gate component in a second direction, and turn around the second side of the front second gate component and extend to the drain, wherein the front second gate component and the right first gate component cooperate to control a second electrical current flowing through the second non-linear channel path.

The preceding example may further include any one or more of the following features. The front second gate component may be spaced apart from the source by a distance that is at least sufficient to achieve a breakdown voltage between the front second gate component and the source. The front second gate component extends between two-tenths (0.2) and two (2) micrometers in a first dimension and between two-tenths (0.2) and two (2 ) micrometers in a second dimension. The volume of semiconductor material may include an N-type epitaxial semiconductor material, the source may include an N+ material, the drain may include an N+ substrate material, and the first gate and the second gate may include a P+ material. The planar JFET may further include a first electrical terminal provided on the source, a second electrical terminal provided on the drain, a third electrical terminal provided on the left first gate component, a fourth electrical terminal provided on the right first gate component, and a fifth electrical terminal provided on the rear second gate component.

This summary is not intended to identify essential features of the examples, and is not intended to be used to limit the scope of the claims. These and other aspects of the present examples are described below in greater detail.

The figures are not intended to limit the examples to the specific details depict. The drawings are not necessarily to scale.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and in which are shown, by way of illustration, specific examples in which the present disclosure may be practiced. These examples are described in sufficient detail to enable a person of ordinary skill in the art to practice the present disclosure. However, other examples may be utilized, and structural, material, procedural, operational, and other changes may be made without departing from the scope of the disclosure. Unless clearly understood or expressly identified otherwise, structures, materials, procedures, operations, and other aspects described in the context of one example may be incorporated into other examples.

The illustrations presented herein are not meant to be actual views of any particular method, system, device, or structure, but are merely idealized representations that are employed to describe the examples of the present disclosure. The drawings presented herein are not necessarily drawn to scale. Similar structures or components in the various drawings may retain the same or similar numbering for the convenience of the reader; however, any similarity in numbering does not necessarily mean that the structures or components are necessarily identical in size, composition, configuration, or any other property.

Terms of relative location and direction (e.g., above, below, left, right, upper, lower, front, rear) may be used to facilitate the present descriptions of examples with reference to the figures, but unless clearly understood or expressly identified otherwise, these terms are not meant to be limiting with regard to location, direction, or overall orientation, and may, for example, change as a result of a change in overall orientation.

Thus, it will be readily understood that the components of the examples as generally described herein and illustrated in the drawings could be arranged and designed in a wide variety of different configurations. Thus, the following description of various examples is not intended to limit the scope of the present disclosure but is merely representative of various examples.

Examples provide a planar JFET with enhanced channel control, and a method of making a planar JFET with enhanced channel control. Broadly, a second gate component is configured and positioned to divide a channel into multiple paths for electrical current to flow between the source and the drain. Examples advantageously provide improved performance, including improved gate control and a lower electric resistance to current flow through the semiconductor material between the source and drain when the device is “on,” i.e., examples provide a lower RDS (on) compared to that of a typical JFET.

1 3 FIGS.- 1 3 FIGS.- 20 22 24 26 28 30 32 Referring to, a first example of a planar JFETwith enhanced channel control may include a volume of semiconductor material, a source, a drain, a channel, a first gate, and a second gate. The relative locations of these components are described below with respect to the X, Y, and Z axes, or dimensions, overlaid onto. It will be understood that these axes, or dimensions, like other terms of relative location or direction, are used to facilitate the present description with reference to the figures and, unless expressly stated, are not meant to be limiting with regard to location, direction, or overall orientation.

22 22 24 22 28 24 26 22 24 28 22 24 28 22 24 26 24 26 26 24 32 24 26 28 28 28 32 The volume of semiconductor materialmay include a first end, a second end, a first side, and a second side. The first end may be spaced apart from the second end along the Y axis, and the first side may be spaced apart from the second side along the X axis. The semiconductor materialmay be or include an N-type epitaxial semiconductor material. The sourcemay be located at or near the first end of the semiconductor materialand provide an entrance for the majority charge carriers (e.g., electrons for N-channel) into the channel. The sourcemay be constructed from or include an N+ material. The drainmay be located at or near the second end of the semiconductor material, spaced apart from and opposite the source, and provide an exit for the majority charge carriers from the channel. According to some aspects, however, the drain may alternatively be located relative to the volume of semiconductor material(such as on the same end as the source). The drainmay be constructed from or include an N+ substrate material. The channelmay be provided by the semiconductor materialbetween the sourceand the drainand through which the majority charge carriers move, i.e., through which electric current flows. It will be appreciated that the majority charge carriers, which are, in this present example, electrons, flow from the sourceto the drain, and the conventional current, Id, flows from the drainto the source. As discussed below, the position of the second gatebetween the sourceand the drainresults in the channelbeing divided into two pathsA,B which extend around opposite sides of the second gate.

30 30 30 30 22 24 30 22 24 30 30 30 30 The first gatemay include a left first gate componentA and a right first gate componentB. The left first gate componentA may be generally located at the first end and the first side of the semiconductor materialadjacent to and spaced apart from the source, The right first gate componentB may be generally located at the first end and the second side of the semiconductor materialadjacent to and spaced apart from the source. The left and right first gate componentsA,B may be constructed from or include P+ material. As discussed below, the left and right first gate componentsA,B may be electrically connected to the same voltage source.

32 32 32 32 22 24 26 30 30 26 32 32 22 32 32 32 22 2 3 FIGS.and The second gatemay include a front second gate componentA and a rear second gate componentB. The front second gate componentA may be embedded, or “buried,” within the semiconductor material, generally between the first and second ends and between the first and second sides, so as to be positioned between and spaced apart from the sourceand the drainand at least partly between (in the vertical direction) and spaced apart from the left and right first gate componentsA,B and the drain. The cross-sectional X, Y dimensions of the front second gate componentA may be between two-tenths (0.2) and two (2) micrometers in width and between two-tenths (0.2) and two (2) micrometers in height. As seen in, the front second gate componentA may include an extension along a Z axis through the semiconductor material. The rear second gate componentB may be located at an end of the extension of the front second gate componentA, and extend at an angle from the front second gate componentA (e.g., ninety (90) degrees) to a surface of the volume of semiconductor materialto provide an exposed surface for coupling with an electrical terminal.

32 22 22 32 32 22 32 32 32 Thus, the front second gate componentA may be surrounded in a first dimension, X, and a second dimension, Y, by the semiconductor materialand extend along the Z axis through the semiconductor material, and the rear second gate componentB may extend from the end of the front second gate componentA at an angle relative to the Z axis to a surface of the volume of semiconductor material. The front and rear second gate componentsA,B may be constructed from or include a P+ material. In operation, the front second gate componentA may function as the primary shielding and gate controlling node.

28 24 26 22 32 24 28 28 28 28 22 30 32 32 26 30 32 29 28 28 22 30 32 32 26 30 32 29 28 30 30 32 28 28 32 24 The channelinitially extends from the sourcetoward the drain, i.e., in the direction of the second end of the semiconductor material. The position of the front second gate componentA beneath the sourcedivides the channelinto the first and second non-linear channel pathsA,B. The first channel pathA turns and extends in the direction of the first side of the semiconductor materialand runs between the left first gate componentA and a first side of the front second gate componentA, before turning around the first side of the front second gate componentA and extending toward the drain. The left first gate componentA and the left first side of the second gate componentA cooperate to provide a first control pointA for controlling an electrical current flowing through the first channel pathA. The second channel pathB turns and extends in the direction of the second side of the semiconductor materialand runs between the right first gate componentA and a second side of the front second gate componentA, before turning around the second side of the front second gate componentA and extending toward the drain. The right first gate componentB and the second side of the second gate componentA cooperate to provide a second control pointB for controlling an electrical current flowing through the second channel pathB. The distance between the left and right first gate componentsA,B and the front second gate componentA, i.e., the width of the first and second channel pathsA,B, may be sufficient to achieve the breakdown voltage (BVgs) between the front second gate componentA and the source.

24 40 26 42 30 44 30 46 32 48 2 FIG. The sourcemay include a first electrical terminal, the drainmay include a second electrical terminal, the left first gate componentA may include a third electrical terminal, the right first gate componentB may include a fourth electrical terminal, and the rear second gate componentB may include a fifth electrical terminal(seen in) for facilitating connections to appropriate voltage sources, as described below.

40 42 24 26 40 44 26 24 24 30 32 28 26 24 28 24 32 20 30 32 29 29 28 28 In operation, an input voltage, Vds, may be applied across the first and second electrical terminals,to cause electron drift/movement from the sourceto the drain; and a control voltage, Vgs, may be applied across the first and third electrical terminals,to control the width of the depletion region at the P-N junctions where the charge carriers of the P- and N-type materials diffuse into each other, which “depletes” the available concentrations of majority charge carrier in each material, and thereby control the current, Id, from the drainto source. Thus, the source, the first gate, and the second gatemay cooperate under Vgs to control the current, Id, through the channel. If Vgs=0 V and Vds>0 V, electrons drift, or move, from the source to the drain, resulting in a current, Id, from the drainto the source, and increased depletion regions at the P-N junctions. If Vds=pinch-off voltage (Vp), then the depletion regions increase in size and grow sufficiently close to each other across the channelthat the current, Id, through the channel cannot increase and so is at its maximum, Id=(max drain current (Idss)). In the present examples, the shielding of the sourceby the lower second gate componentA reduces a reverse bias leakage current and provides a higher breakdown voltage (BVgs) for the JFET. Further, the first and second gates,cooperate to create separate control pointsA,B, for controlling current flow through the channel pathsA,B.

4 FIG. 5 FIGS.A-C 120 20 120 20 Referring to, a first example of a methodof making a planar JFET with enhanced channel control, such as the planar JFETdescribed above, may include the operations set forth below. Referring additionally to, example results are shown of the operations of the method, which may be stages in the manufacture of the planar JFET.

226 26 22 226 122 226 22 22 226 5 FIG.A An N+ substrate, which may become the drain, may be provided, and the volume of semiconductor materialmay be grown or otherwise provided on the N+ substrate, as shown in operationand seen in. The N+ substratemay be or include a 4H—SiC material, and the semiconductor materialmay be or include an N-type epitaxial semiconductor material. The volume of semiconductor materialmay include a first end, a second end, a first side, and a second side, and the N+ substratemay be located at the second cnd.

232 32 22 124 232 22 232 232 22 5 FIG.A A first structure of P+ materialA, which may become the front second gate componentA, may be implanted (using, e.g., an ion implanter) or otherwise provided, or “buried,” within the volume of semiconductor material, generally between the first and second ends and between the first and second sides, as shown in operationand also seen in. The first structure of P+ materialA, may be surrounded (as seen in cross-sectional elevation view) in a first dimension, X, and a second dimension, Y, by the semiconductor material. The cross-sectional (X, Y) dimensions of the first structure of P+ materialA may be between two-tenths (0.2) and two (2) micrometers in width and between two-tenths (0.2) and two (2) micrometers in height. The first structure of P+ materialA may include an extension along a Z axis through the semiconductor material.

232 32 232 232 22 126 32 232 22 22 232 22 5 FIG.A 2 FIG. A second structure of P+ materialB, which may become a rear second gate componentB, may be implanted or otherwise provided so as to be located at an end of the extension of the first structure of P+ materialA, and extend at an angle from the end of the first structure of P+ materialA (e.g., ninety (90) degrees) to a surface of the volume of semiconductor materialto provide an exposed surface for coupling with an electrical terminal, as shown in operationand also seen (in broken line) in(and seen as the resulting rear second gate componentB in). Thus, the first structure of P+ materialA may be surrounded in a first dimension, X, and a second dimension, Y, by the semiconductor materialand extend along a Z axis through the semiconductor material, and the second structure of P+ materialB may extend at an angle relative to the Z axis to the surface of the volume of semiconductor material.

224 24 22 128 5 FIG.B A structure of N+ material, which may become the source, may be implanted or otherwise provided at or near the first end, approximately centered between the first and second sides of the semiconductor material, as shown in stepand seen in.

230 30 30 22 130 230 22 224 232 5 FIG.B A third structure of P+ materialA, which may become the first componentA of the first gate, may be implanted in the volume of semiconductor material, as shown in operationand also seen in. The third structure of P+ materialA may be generally located at the first end and the first side of the semiconductor materialspaced apart from the N+ source materialand partially above a first side of the first P+ structureA.

230 30 30 22 132 230 22 224 232 232 230 226 232 232 226 5 FIG.B A fourth structure of P+ materialB, which may become the second componentB of the first gate, may be implanted in the volume of semiconductor material, as shown in stepand also seen in. The fourth structure of P+ materialB may be generally located at the first end and the second side of the semiconductor materialspaced apart the N+ source materialand partially above a second side of the first P+ structureA. Thus, the first structure of P+ materialA may be located at least partially between the third structure of P+ materialA and the N+ drain substrate, and the first structure of P+ materialB may be located at least partially between the fourth structure of P+ materialB and the N+ drain substrate.

20 232 32 232 224 28 28 28 226 230 30 232 29 28 230 230 232 29 28 In the finished JFET, the first structure of P+ materialA (i.e., the front second gate componentA), may function as the primary shielding and gate controlling node. The positioning of the first structure of P+ materialA beneath the N+ source materialprovides a “shield,” and divides the channelinto first and second nonlinear channel pathsA,B which extend in opposite directions before turning toward the N+ drain substrate, as discussed above. Further, the third P+ structureA (i.e., the left first gate componentA) and the first side of the first P+ structureA cooperate to provide a first control pointA for controlling an electrical current flowing through the first channel pathA, and the fourth P+ structureB (i.e., the right first gate componentB) and the second side of the first P+ structureA cooperate to provide a second control pointB for controlling an electrical current flowing through the second channel pathB, as discussed above.

230 230 232 28 28 32 24 The distance between the third and fourth P+ structuresA,B and the first P+ structureA, i.e., the width of the first and second channel portionsA,B, may be sufficient to achieve the breakdown voltage (BVgs) between the front second gate componentA and the source.

40 224 42 226 44 230 46 230 48 232 134 2 FIG. 5 FIG.C A first electrical terminalmay be provided on the N+ source material, a second electrical terminalmay be provided on the N+ drain substrate, a third electrical terminalmay be provided on the third P+ structureA, a fourth electrical terminalmay be provided on the fourth P+ structureB, and a fifth electrical terminalmay be provided on the second P+ structureB (seen in), as shown in stepand seen in, for facilitating connections to appropriate voltage sources, as described above.

Additional processing may be performed as desired.

6 7 FIGS.and 6 7 FIGS.and 320 322 324 326 328 330 332 Referring to, a second example of a planar JFETwith a buried gate may include a volume of semiconductor material, a source, a drain, a channel, a first gate, and a second gate. The relative locations of these components are described below with respect to the X, Y, and Z axes, or dimensions, overlaid onto. It will be understood that these axes, or dimensions, like other terms of relative location or direction, are used to facilitate the present description with reference to the figures and, unless expressly stated, are not meant to be limiting with regard to location, direction, or overall orientation.

322 322 324 322 328 324 326 322 324 328 22 324 328 322 324 326 324 326 326 324 332 324 326 328 328 328 332 The volume of semiconductor materialmay include a first end, a second end, a first side, and a second side. The first end may be spaced apart from the second end along the Y axis, and the first side may be spaced apart from the second side along the X axis. The semiconductor materialmay be or include an N-type epitaxial semiconductor material. The sourcemay be located at or near the first end of the semiconductor materialand provide an entrance for the majority charge carriers (e.g., electrons for N-channel) into the channel. The sourcemay be constructed from or include an N+ material. The drainmay be located at or near the second end of the semiconductor material, spaced apart from and opposite the source, and provide an exit for the majority charge carriers from the channel. According to some aspects, however, the drain may alternatively be located relative to the volume of semiconductor material(such as on the same end as the source). The drainmay be constructed from or include an N+ substrate material. The channelmay be provided by the semiconductor materialbetween the sourceand the drainand through which the majority charge carriers move, i.e., through which electric current flows. It will be appreciated that the majority charge carriers, which are, in this present example, electrons, flow from the sourceto the drain, and the conventional current, Id, flows from the drainto the source. As discussed below, the position of the second gatebetween the sourceand the drainresults in the channelbeing divided into two pathsA,B which extend around opposite sides of the second gate.

330 330 330 330 322 324 330 322 324 330 330 330 330 The first gatemay include a left first gate componentA and a right first gate componentB. The left first gate componentA may be generally located at the first end and the first side of the semiconductor materialspaced apart from the source. The right first gate componentB may be generally located at the first end and second side of the semiconductor materialspaced apart from the source. The left and right first gate componentsA,B may be constructed from or include P+ material. As discussed below, the left and right first gate componentsA,B may be electrically connected to the same voltage source.

332 332 332 332 322 324 326 330 330 332 332 322 332 332 332 322 6 7 FIGS.and The second gatemay include a front second gate componentA and a rear second gate componentB. The front second gate componentA may be located, or “buried” within the semiconductor material, generally between the first and second ends and between the first and second sides, so as to be positioned between and spaced apart from the sourceand the drainand at least partly between (in the lateral direction) and spaced apart from the first and right first gate componentsA,B. The cross-sectional (X, Y) dimensions of the front second gate componentA may be between two-tenths (0.2) and two (2) micrometers in width and between two-tenths (0.2) and two (2) micrometers in height. As seen in, the front second gate componentA may include an extension along a Z axis through the semiconductor material. The rear second gate componentB may be located at an end of the extension of the front second gate componentA, and extend at an angle from the front second gate componentA (e.g., ninety (90) degrees) to a surface of the volume of semiconductor materialto provide an exposed surface for coupling with an electrical terminal.

332 322 332 332 322 332 332 332 Thus, the front second gate componentA may be surrounded in a first dimension, X, and a second dimension, Y, by the semiconductor material of the channel and extend along the Z axis through the semiconductor material. The rear second gate componentB may extend from the end of the front second gate componentA at an angle relative to the Z axis to the surface of the volume of semiconductor material. The front and rear second gate componentsA,B may be constructed from or include a P+ material. In operation, the front second gate componentA may function as the primary shielding and gate controlling node.

328 324 326 322 332 328 328 328 328 332 330 332 326 330 332 329 328 328 322 332 330 332 326 330 332 329 328 330 330 332 328 328 332 324 The channelinitially extends from the sourcetoward the drain(i.e., in the direction of the second end of the semiconductor material). The position of the front second gate componentA beneath the source divides the channelinto the first and second channel pathsA,B. The first channel pathA turns and extends in the direction of the first side of the semiconductor material before turning around the first side of the front second gate componentA and extending between the left first gate componentA and the first side of the front second gate componentA and toward the drain. The left first gate componentA and the first side of the front second gate componentA cooperate to provide a first control pointA for controlling an electrical current flowing through the first channel pathA. The second channel pathB turns and extends in the direction of the second side of the semiconductor materialbefore turning around the second side of the front second gate componentA and extending between the right first gate componentA and the second side of the front second gate componentA and toward the drain. The left first gate componentA and the second side of the second gate componentA cooperate to provide a second control pointB for controlling an electrical current flowing through the second channel pathB. The distance between the first and right first gate componentsA,B and the front second gate componentA, i.e., the width of the first and second channel pathsA,B may be sufficient to achieve the breakdown voltage (BVgs) between the front second gate componentA and the source.

324 340 326 342 330 344 330 346 332 348 The sourcemay include a first electrical terminal, the drainmay include a second electrical terminal, the left first gate componentA may include a third electrical terminal, the right first gate componentB may include a fourth electrical terminal, and the rear second gate componentB may include a fifth electrical terminalfor facilitating connections to appropriate voltage sources, as described below.

340 342 324 326 340 344 326 324 324 330 332 328 326 324 328 324 332 320 330 332 329 329 328 328 In operation, an input voltage, Vds, may be applied across the first and second electrical terminals,to cause electron drift/movement from the sourceto the drain; and a control voltage, Vgs, may be applied across the first and third electrical terminals,to control the width of the depletion region at the P-N junctions where the charge carriers of the P-and N-type materials diffuse into each other, which “depletes” the available concentrations of majority charge carrier in each material, and thereby control the current, Id, from the drainto source. Thus, the source, the first gate, and the second gatemay cooperate under Vgs to control the current, Id, through the channel. If Vgs=0 V and Vds>0 V, electrons drift, or move, from the source to the drain, resulting in a current, Id, from the drainto the source, and increased depletion regions at the P-N junctions. If Vds=pinch-off voltage (Vp), then the depletion regions increase in size and grow sufficiently close to each other across the channelthat the current, Id, through the channel cannot increase and so is at its maximum, Id=(max drain current (Idss)). In the present examples, the shielding of the sourceby the lower second gate componentA reduces a reverse bias leakage current and provides a higher breakdown voltage (BVgs) for the JFET. The first and second gates,cooperate to create separate control pointsA,B, for controlling current flow through the channel pathsA,B.

8 FIG. 9 FIGS.A-C 420 320 420 320 Referring to, a second example of a methodof making a planar JFET with enhanced channel control, such as the planar JFETdescribed above, may include the operations set forth below. Referring additionally to, example results are shown of the operations of the method, which may be stages in the manufacture of the planar JFET.

526 326 322 526 422 526 322 322 526 9 FIG.A An N+ substrate, which may become the drain, may be provided, and the volume of semiconductor materialmay be grown or otherwise provided on the N+ substrate, as shown inand seen in. The N+ substratemay be or include a 4H—SiC material, and the semiconductor materialmay be or include an N-type epitaxial semiconductor material. The volume of semiconductor materialmay include a first end, a second end, a first side, and a second side, and the N+ substratemay be located at the second end.

532 332 322 424 532 322 532 532 322 9 FIG.A A first structure of P+ materialA, which may become the front second gate componentA, may be implanted (using, e.g., an ion implanter) or otherwise provided, or “buried,” within the volume of semiconductor material, generally between the first and second ends and between the first and second sides, as shown in operationand also seen in. The first structure of P+ materialA, may be surrounded (as seen in cross-sectional elevation view) in a first dimension, X, and a second dimension, Y, by the semiconductor material. The cross-sectional (X, Y) dimensions of the first structure of P+ materialA may be between two-tenths (0.2) and two (2) micrometers in width and between two-tenths (0.2) and two (2) micrometers in height. The first structure of P+ materialA may include an extension along a Z axis through the semiconductor material.

532 332 532 532 532 322 426 332 532 322 322 532 322 9 FIG.A 7 FIG. A second structure of P+ materialB, which may become a rear second gate componentB, may be implanted or otherwise provided so as to be located at an end of the extension of the first structure of P+ materialA along the Z-axis. The second structure of P+ materialB may extend at an angle from the end of the first structure of P+ materialA (e.g., ninety (90) degrees) to a surface of the volume of semiconductor materialto provide an exposed surface for coupling with an electrical terminal, as shown in operationand also seen (in broken line) in(and seen as the resulting rear second gate componentB in). Thus, the first structure of P+ materialA may be surrounded in a first dimension, X, and a second dimension, Y, by the semiconductor materialand extend along a Z axis through the semiconductor material; and the second structure of P+ materialB may extend at an angle relative to the Z axis to the surface of the volume of semiconductor material.

524 324 322 428 9 FIG.B A structure of N+ material, which may become the source, may be implanted or otherwise provided at or near the first end, centered between the first and second sides of the semiconductor material, as shown in stepand seen in.

530 330 330 322 430 530 322 524 9 FIG.B A third structure of P+ materialA, which may become the left first gate componentA of the first gate, may be implanted in the volume of semiconductor material, as shown in stepand also seen in. The third structure of P+ materialA may be generally located at the first end and the first side of the semiconductor materialadjacent to and spaced apart from the N+ source material.

530 330 330 322 432 530 322 524 530 532 530 532 9 FIG.B A fourth structure of P+ materialB, which may become the right second gate componentB of the first gate, may be implanted in the volume of semiconductor material, as shown in stepand also seen in. The fourth structure of P+ materialB may be generally located at the first end and the second side of the semiconductor materialadjacent to and spaced apart the N+ source material. Thus, the third structure of P+ materialA may extend at least partially along a first side of the first structure of P+ materialA, and the fourth structure of P+ materialB may extend at least partially along a second side of the first structure of P+ materialA.

320 532 332 232 524 28 328 328 526 530 330 532 329 328 530 530 532 329 328 In the finished JFET, the first structure of P+ materialA (i.e., the front second gate componentA), may function as the primary shielding and gate controlling node. The positioning of the first structure of P+ materialA beneath the N+ source materialprovides a “shield,” and divides the channelinto first and second channel pathsA,B which extend in opposite directions before turning toward the N+ drain substrate, as discussed above. Further, the third P+ structureA (i.e., the left first gate componentA) and the first side of the first P+ structureA cooperate to provide a first control pointA for controlling an electrical current flowing through the first channel pathA, and the fourth P+ structureB (i.e., the right first gate componentB) and the second side of the first P+ structureA cooperate to provide a second control pointB for controlling an electrical current flowing through the second channel pathB, as discussed above.

530 530 532 328 328 332 324 The distance between the third and fourth P+ structuresA,B and the first P+ structureA, i.e., the width of the first and second channel portionsA,B, may be sufficient to achieve the breakdown voltage (BVgs) between the front second gate componentA and the source.

340 524 342 526 344 530 346 530 348 532 434 7 FIG. 9 FIG.C A first electrical terminalmay be provided on the N+ source material, a second electrical terminalmay be provided on the N+ drain substrate, a third electrical terminalmay be provided on the third P+ structureA, a fourth electrical terminalmay be provided on the fourth P+ structureB, and a fifth electrical terminalmay be provided on the second P+ structureB (seen in), as shown in operationand seen in, for facilitating connections to appropriate voltage sources, as described above.

Additional processing may be performed as desired.

Although described herein with regard or in relation to one or more particular kinds of electronic devices (e.g., junction field-effect transistors, metal oxide semiconductor field-effect transistors), the technology may be more broadly applicable to one or more other kinds of electronic devices as well. One with ordinary skill in the art will recognize that the technology described herein may, when applicable, be implemented in enhancement mode or depletion mode. Further, the technology described herein may, when applicable, be implemented as an N-channel or P-channel device, wherein, in general, regions that are N-doped or P-doped in N-channel implementations may be, respectively, P-doped or N-doped in P-channel implementations. Additionally, the various example materials identified herein may, in some aspects, be replaced or supplemented with substantially any other suitable material. For example, gate material may include polysilicon, a metal or alloy of metals, or other suitable material; gate oxide or dielectric may include silicon dioxide, aluminum oxide, hafnium dioxide, silicon nitride, or other suitable material; and semiconductor material may include silicon carbide, gallium nitride, zinc oxide, or other suitable material.

Additionally, in general, unless otherwise specified or unless one with ordinary skill in the art would understand otherwise, doping concentrations for contact implants may be approximately between 10{circumflex over ( )}18 and 10{circumflex over ( )}22; doping concentrations for channel and threshold forming implants may be approximately between 10{circumflex over ( )}16 and 10{circumflex over ( )}17; doping concentrations for shielding implants may be approximately between 10{circumflex over ( )}17 and 10{circumflex over ( )}19; and doping concentrations for conductivity improvement implants (e.g., N-doping in the junction field-effect transistor neck region of a metal oxide semiconductor field-effect transistor) may be approximately between 10{circumflex over ( )}16 and 10{circumflex over ( )}17. Relatedly, a structure or region may contain two or more different doping doses. For example, one with ordinary skill in the art will recognize that some P-wells may contain a lower dose P-well portion and a higher dose unclamped inductive switching portion.

Additionally, although only one or a few instances of a device or apparatus may be described herein, it will be appreciated that some applications may involve many such devices or apparatuses, which may be different from, substantially similar to, or identical to the described device or apparatus, and which may be arranged (e.g., in an array) on a larger extension of the volume of semiconductor material. In that light, references to a right or left side of a volume of semiconductor material may be to the conceptual limit of a particular unit cell and not to an actual physical end of the material.

While the present disclosure has been described herein with respect to certain illustrated examples, those of ordinary skill in the art will recognize and appreciate that the present disclosure is not so limited. Rather, many additions, deletions, and modifications to the illustrated and described examples may be made without departing from the scope of the disclosure as hereinafter claimed along with their legal equivalents. In addition, features from one example may be combined with features of another example while still being encompassed within the scope of the disclosure as contemplated by the inventors.