Computing System Capable of Detecting Interleaving Configuration

35 The present application claims priority underU.S.C § 119(a) to Korean Application No. 10-2024-0110095, filed in the Korean Intellectual Property Office on Aug. 16, 2024, the entire contents of which are incorporated herein by reference.

Various embodiments of the present teachings relate to a computing system and, more particularly, to a computing system capable of detecting an interleaving configuration.

Recently, there has been increasing interest in computing systems that compute machine learning algorithms using acceleration systems and software. In general, the computing system includes a memory device (or a processing-in-memory (PIM) device), a controller, and a processing unit. The memory device (or PIM device) includes a plurality of memory banks, and memory interleaving may be applied for efficient operation of the computing system. The memory interleaving is configured based on an address mapping order defined in the controller. In some computing systems, a single processing unit is combined with various types of memory devices (or PIM devices) and controllers. In this case, a process is required to enable the processing unit to know information about the interleaving configuration, that is, the address mapping order, defined by the memory device (or PIM device) and the controller.

A computing system according to an embodiment of the present disclosure may include a plurality of memory banks, each of the plurality of memory banks storing a plurality of unique identification data, a memory controller configured to control an access operation on the memory device, based on an address mapping order, and a processing unit coupled to the memory device through the memory controller. The processing unit may be configured to detect the address mapping order, based on the plurality of unique identification data of the memory device.

A computing system according to an embodiment of the present disclosure may include a memory device including a plurality of memory banks, each of the plurality of memory banks storing a plurality of unique identification data, a memory controller configured to control an access operation on the memory device, based on an address mapping order, a processing unit coupled to the memory device through the memory controller, and a firmware configured to perform a boot process. The firmware may be configured to detect the address mapping order based on the plurality of unique identification data of the memory device and transmit the detected address mapping order to the processing unit while performing the booting process.

A computing system according to an embodiment of the present disclosure may include a processing-in-memory (PIM) device including a plurality of memory banks and a plurality of processing elements, a memory controller configured to control, based on a first address mapping order, a memory access operation for the PIM device and control, based on a second address mapping order, an arithmetic operation of the PIM device, and a processing unit coupled to the PIM device through the memory controller. Each of the plurality of memory banks may include a plurality of unique identification data. The processing unit may be configured to detect the first address mapping order, based on the plurality of unique identification data of the PIM device.

Terms such as “first” and “second” are used to distinguish between various elements and do not imply size, order, priority, quantity, or importance of the elements. For example, a first element may be referred to as a second element in one example, and the second element may be referred to as a first element in another example.

When an element is referred to as “connected” or “coupled” to another element, the elements may be connected directly or through one or more intervening elements between the elements. When two elements are referred to as “directly connected” or “directly coupled,” one element is directly connected or directly coupled to the other element without an intervening element between the two elements.

Terms such as “over,” “on,” “inside,” “higher,” “high,” “low,” “left,” “right,” “column,” “row,” “level,” and other terms implying relative spatial relationship or orientation are utilized only for the purpose of ease of description or reference to a drawing and are not otherwise limiting.

Embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of embodiments are provided as examples for illustrative purposes to describe concepts that are disclosed in the present application. Examples or embodiments in accordance with the concepts may be carried out in various forms, and the scope of the present disclosure is not limited to the examples or embodiments described in this specification.

It should be understood that the various embodiments described below take DRAM as an example as a memory device, but are not limited thereto. For example, the same may be applied to static random access memory (SRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, etc.), graphics double data rate synchronous DRAM (GDDR, GDDR2, GDDR3, etc.), quad data rate DRAM (QDR DRAM), RAMBUS XDR DRAM (XDR DRAM), fast page mode DRAM (FPM DRAM), video DRAM (VDRAM), extended data output DRAM (EDO DRAM), burst EDO DRAM (BEDO DRAM), multibank DRAM (MDRAM), synchronous graphics RAM (SGRAM), and/or other various forms of DRAM.

1 FIG. 100 is a block diagram illustrating a computing systemaccording to an embodiment of the present disclosure.

1 FIG. 1 FIG. 100 110 120 130 110 0 1 0 1 110 110 0 1 0 1 0 0 1 1 th th th th th th th Referring to, the computing systemincludes a memory device, a memory controller, and a processing unit. The memory deviceincludes a plurality of memory banks, for example, first to “N”(“N” is a natural number) memory banks BK()-BK(N−). Although not shown in, each of the first to “N”memory banks BK()-BK(N−) may include a memory cell array including a plurality of memory cells. In an embodiment, the memory devicemay be a volatile memory device, such as a DRAM device. In another embodiment, the memory devicemay be a nonvolatile memory device, such as a NAND memory device. The first to “N”memory banks BK()-BK(N−) include data storage regions in which a plurality of unique identification data, for example, first to “N”unique identification data UID()-UID(N−) are stored. For example, the first memory bank BK() includes a first data storage region in which the first unique identification data UID() is stored. Similarly, the “N”memory bank BK(N−) includes an “N”data storage region in which the “N”unique identification data UID(N−) is stored.

th th th th 0 1 0 1 110 0 1 Each of the first to “N”memory banks BK()-BK(N−) may include a plurality of rows and first to “F”of column regions. The plurality of rows include a first row group in which a data read operation and a data write operation are performed and a second row group in which the first to “N”unique identification data UID()-UID(N−) are stored. Each of the first to “F”(“F” is a natural number of 2 or more) of column regions may have a size equal to an access granularity of the memory device. Among the first to “N”th unique identification data UID()-UID(N−), a “K”th (“K” is a natural number from 1 to “N) unique identification data includes first to “T”th (“T” is (the number of rows belonging to the second row groupדF”)) portions stored in the rows belonging to the second row group of a “K”th memory bank.

120 110 110 110 110 110 110 120 121 120 121 110 The memory controllercontrols an access operation on the memory device. In an embodiment, the access operation includes a read operation for reading data from the memory deviceand a write operation for writing data to the memory device. When the memory deviceis a DRAM device, the access operation on the memory devicemay include a refresh operation of the memory device. The memory controllerincludes an address mapping tablein which an address mapping order is defined. The memory controllercontrols, based on the address mapping order defined in the address mapping table, the access operation on the memory device.

130 110 120 130 100 130 130 110 110 120 130 121 110 120 130 121 110 The processing unitis coupled to the memory devicethrough the memory controller. In an embodiment, the processing unitis configured to process instructions of an operating system for driving the computing systemor instructions of an application program at the request of a user. In an embodiment, the processing unitis a central processing unit (CPU). The processing unitrequests data read from the memory deviceor data write to the memory device. The memory controllerthat receives a data read request from the processing unitreads data, based on the address mapping order defined in the address mapping table, from the memory device. The memory controllerthat receives a data write request from the processing unitwrites data, based on the address mapping order defined in the address mapping table, to the memory device.

130 0 1 0 1 130 120 120 0 1 110 0 1 120 130 0 1 120 121 120 th th th th th The processing unitis configured to detect the address mapping order, based on the first to “N”unique identification data UID()-UID(N-) stored in the first to “N”memory banks BK()-BK(N−). To this end, the processing unitperforms a unique identification data read request operation for the unique identification data to the memory controller. The memory controllerthat is requested to read the unique identification data reads the first to “N”unique identification data UID()-UID(N-) from the memory deviceto store the first to “N”unique identification data UID()-UID(N−) in a read buffer within the memory controller. The processing unitanalyzes the first to “N”unique identification data UID()-UID(N−) stored in the read buffer within the memory controllerto detect the address mapping order defined in the address mapping tableof the memory controller.

2 FIG. 110 illustrates an embodiment of a memory deviceincluded in a computing system according to an embodiment of the present disclosure.

2 FIG. 110 0 3 110 110 0 3 Referring to, the memory deviceincludes a plurality of memory banks, for example, first to fourth memory banks BK()-BK(). The memory deviceincluding four memory banks is only an example, and the memory devicemay include more than four memory banks. Each of the first to fourth memory banks BK()-BK() includes a plurality of rows and a plurality of columns. Memory cells are arranged in each of the regions where the plurality of rows and the plurality of columns intersect.

0 3 2 2 0 1 0 3 0 0 3 0 1 0 3 1 1 0 3 1 2 1 0 3 2 1 th th th th th th th In an embodiment, each of the first to fourth memory banks BK()-BK() has “M+” rows, for example, first to “M+”(“M” is a natural number) rows R()-R(M+). Each of the rows of each of the first to fourth memory banks BK()-BK() may be specified by a row address. For example, the first row R() of each of the first to fourth memory banks BK()-BK() is specified by a first row address RA(). The “M”row R(M−) of each of the first to fourth memory banks BK()-BK() is specified by an “M”row address RA(M−). The “M+”row R(M) of each of the first to fourth memory banks BK()-BK() is specified by an “M+”row address RA(M). The “M+”row R(M+) of each of the first to fourth memory banks BK()-BK() is specified by an “M+”row address RA(M+).

0 3 110 110 120 130 0 3 0 3 0 3 110 0 3 0 3 8 0 3 0 0 1 1 2 10 3 11 1 FIG. 1 FIG. In an embodiment, the plurality of columns included in each of the first to fourth memory banks BK()-BK() constitute column regions having a size equal to the access granularity of the memory device. In an embodiment, the access granularity of the memory devicemay have a size equal to a size of a cache line within the memory controllerofor the processing unitof. In an embodiment, each of the first to fourth memory banks BK()-BK() has four column regions, for example, first to fourth column regions C()-C(). However, this is just an example, and each of the first to fourth memory banks BK()-BK() may have more than four column regions. In an embodiment, when an access granularity for the memory deviceis 32 bytes, each of the first to fourth column regions C()-C() has a size of 32 bytes. In this case, each of the first to fourth column regions C()-C() includes 256 columns for the 32 bytes *bits/byte. The first to fourth column regions C()-C() may be specified by first to fourth column addresses CA00-CA11, respectively. That is, the first column region C() may be specified by the first column address CA, the second column region C() may be specified by the second column address CA, the third column region C() may be specified by the third column address CA, and the fourth column region C() may be specified by the fourth column address CA.

2 0 1 0 3 130 120 0 1 0 3 0 1 1 2 1 0 3 1 2 1 0 3 h th th h th th 1 FIG. 1 FIG. In an embodiment, the first to “M+”rows R()-R(M+) of each of the first to fourth memory banks BK()-BK() are divided into a first row group and a second row group. The first row group may be defined as a row region in which data can be stored by the processing unitofand the memory controllerof. Accordingly, general data read operations and data write operations may be performed on the first row group. The second row group may be defined as a row region in which the unique identification data UID()-UID(N−) is stored. For the unique identification data UID()-UID() stored in the second row group, only a data read operation is performed, and a data write operation is not performed. In an embodiment, the first row group includes the first to “M”rows R()-R(M−), and the second row group includes the “M+”row R(M) and the “M+”row R(M+). Accordingly, the second row group of the first to fourth memory banks BK()-BK(), that is, the “M+”row R(M) and the “M+”row R(M+), maintains a state in which the unique identification data UID()-UID() is stored.

0 0 3 1 0 0 3 2 1 0 0 3 10 13 0 0 0 0 3 0 3 1 0 0 10 13 0 3 2 1 0 0 10 0 0 1 2 1 1 11 0 1 1 2 1 2 12 0 2 1 2 1 3 13 0 3 1 2 1 th th th th th th th th th th th th The first unique identification data UID() is stored in the first to fourth column regions C()-C() of the “M+”row R(M) of the first memory bank BK() and the first to fourth column regions C()-C() of the “M+”row R(M+). The first unique identification data UID() includes a plurality of portions A-Aand A-A. The number of the plurality of portions constituting the first unique identification data UID() corresponds to “the number of rows belonging to the second row group×the number of column regions belonging to one row”. Accordingly, the first unique identification data UID() includes four portions of the first unique identification data UID(), for example, the first to fourth portions A-Astored in the first to fourth column regions C ()-C() of the “M+”row R(M) of the first memory bank BK(), respectively, and four portions of the first unique identification data UID(), for example, fifth to eighth portions A-Astored in the first to fourth column regions C()-C() of the “M+”row R(M+) of the first memory bank BK(), respectively. The first portion Aand the fifth portion Aof the first unique identification data UID() are stored in the first column regions C() of the “M+”row R(M) and the “M+”row R(M+), respectively. The second portion Aand the sixth portion Aof the first unique identification data UID() are stored in the second column regions C() of the “M+”row R(M) and the “M+”row R(M+), respectively. The third portion Aand the seventh portion Aof the first unique identification data UID() are stored in the third column regions C() of the“M+”row R(M) and the “M+”row R(M+), respectively. In addition, the fourth portion Aand the eighth portion Aof the first unique identification data UID() are stored in the fourth column regions C() of the “M+”row R(M) and the “M+”row R(M+), respectively.

0 3 10 13 0 0 0 0 3 10 13 0 0 3 0 1 10 13 0 2 1 th th Each of the first to eighth portions A-Aand A-Aof the first unique identification data UID(), stored in the first memory bank BK() includes unique data that specifies the first memory bank BK() (hereinafter, referred to as “first bank identification data”). Each of the first to eighth portions A-Aand A-Aof the first unique identification data UID() includes data that specifies a row (hereinafter, referred to as “first row identification data”). In an embodiment, each of the first to fourth portions A-Aof the first unique identification data UID(), stored in the “M+”row R(M) has a first binary value, for example, binary value “0” as the first row identification data. On the other hand, each of the fifth to eighth portions A-Aof the first unique identification data UID(), stored in the “M+”row R(M+) has a second binary value, for example, binary value “1”as the first row identification data.

0 3 10 13 0 0 10 0 0 1 11 0 1 2 12 0 2 3 13 0 3 In addition, each of the first to eighth portions A-Aand A-Aof the first unique identification data UID() also includes data that specifies a column region (hereinafter, referred to as “first column identification data”). The first and fifth portions Aand Aof the first unique identification data UID(), stored in the first column region C() have first binary values, for example, binary values “00” as the first row identification data. The second and sixth portions Aand Aof the first unique identification data UID(), stored in the second column region C() have second binary values, for example, binary values “01” as the first column identification data. The third and seventh portions Aand Aof the first unique identification data UID(), stored in the third column region C() have third binary values, for example, binary values “10” as the first column identification data. The fourth and eighth portions Aand Aof the first unique identification data UID(), stored in the fourth column region C() have fourth binary values, for example, binary values “11” as the first column identification data.

1 0 3 1 0 3 2 1 1 1 0 3 10 13 0 3 10 13 1 1 0 3 1 0 3 1 1 10 13 1 0 3 2 1 1 0 10 1 0 1 2 1 1 11 1 1 1 2 1 2 12 1 2 1 2 1 3 13 1 3 1 2 1 th th th th th th th th th th th th The second unique identification data UID() is stored in the first to fourth column regions C()-C() of the “M+”row R(M) and the first to fourth column regions C()-C() of the “M+”row R(M+) of the second memory bank BK(). The second unique identification data UID() includes a plurality of portions B-Band B-B. The number of the plurality of portions B-Band B-Bconstituting the second unique identification data UID() corresponds to “the number of rows belonging to the second row group×the number of column regions belonging to one row”. Accordingly, the second unique identification data UID() includes first to fourth portions B-Bof the second unique identification data UID(), stored in the first to fourth column regions C()-C() of the “M+”row R(M) of the second memory bank BK(), respectively, and fifth to eighth portions B-Bof the second unique identification data UID(), stored in the first to fourth column regions C()-C() of the “M+”row R(M+) of the second memory bank BK(), respectively. The first and fifth portions Band Bof the second unique identification data UID() are stored in the first column regions C() of the “M+”row R(M) and the “M+”row R(M+), respectively. The second and sixth portions Band Bof the second unique identification data UID() are stored in the second column regions C() of the “M+”row R(M) and the “M+”row R(M+), respectively. The third and seventh portions Band Bof the second unique identification data UID() are stored in the third column regions C() of the “M+”row R(M) and the “M+”row R(M+), respectively. In addition, the fourth and eighth portions Band Bof the second unique identification data UID() are stored in the fourth column regions C() of the “M+”row R(M) and the “M+”row R(M+), respectively.

0 3 10 13 1 1 1 0 3 10 13 1 0 3 1 1 10 13 1 2 1 th th Each of the first to eighth portions B-Band B-Bof the second unique identification data UID(), stored in the second memory bank BK() includes unique data that specifies the second memory bank BK() (hereinafter, referred to as “second bank identification data”). Each of the first to eighth portions B-Bl and B-Bof the second unique identification data UID() includes data that specifies a row (hereinafter, referred to as “second row identification data”). In an embodiment, each of the first to fourth portions B-Bof the second unique identification data UID(), stored in the “M+”row R(M) has a first binary value, for example, binary value “0” as the second row identification data. On the other hand, each of the fifth to eighth portions B-Bof the second unique identification data UID(), stored in the “M+”row R(M+) has a second binary value, for example, binary value “1” as the second row identification data.

0 3 10 13 1 0 10 1 0 1 11 1 1 2 12 1 2 3 13 1 3 In addition, each of the first to eighth portions B-Band B-Bof the second unique identification data UID() also includes data that specifies a column region (hereinafter, referred to as “second column identification data”). The first and fifth portions Band Bof the second unique identification data UID(), stored in the first column region C() have first binary values, for example, binary values “00” as the second row identification data. The second and sixth portions Band Bof the second unique identification data UID(), stored in the second column region C() have second binary values, for example, binary values “01” as the second column identification data. The third and seventh portions Band Bof the second unique identification data UID(), stored in the third column region C() have third binary values, for example, binary values “10”, as the second column identification data. The fourth and eighth portions Band Bof the second unique identification data UID(), stored in the fourth column region C() have fourth binary values, for example, binary values “11”as the second column identification data.

2 0 3 1 0 3 2 1 2 2 0 3 10 13 0 3 10 13 2 2 0 3 2 0 3 1 2 10 13 2 0 3 2 1 2 0 10 2 0 1 2 1 1 11 2 1 1 2 1 2 12 2 2 1 2 1 3 13 2 3 1 2 1 th th th th th th th th th th th th The third unique identification data UID() is stored in the first to fourth column regions C()-C() of the “M+”row R(M) and the first to fourth column regions C()-C() of the “M+”row R(M+) of the third memory bank BK(). The third unique identification data UID() includes a plurality of portions C-Cand C-C. The number of the plurality of portions C-Cand C-Cconstituting the third unique identification data UID() corresponds to “the number of rows belonging to the second row group×the number of column regions belonging to one row”. Accordingly, the third unique identification data UID() includes first to fourth portions C-Cof the third unique identification data UID(), stored in the first to fourth column regions C()-C() of the “M+”row R(M) of the third memory bank BK(), respectively, and the fifth to eighth portions C-Cof the third unique identification data UID(), stored in the first to fourth column regions C()-C() of the “M+”row R(M+) of the third memory bank BK(), respectively. The first and fifth portions Cand Cof the third unique identification data UID() are stored in the first column regions C() of the “M+”row R(M) and the “M+”row R(M+), respectively. The second and sixth portions Cand Cof the third unique identification data UID() are stored in the second column regions C() of the “M+”row R(M) and the “M+”row R(M+), respectively. The third and seventh portions Cand Cof the third unique identification data UID() are stored in the third column regions C() of the “M+”row R(M) and the “M+”row R(M+), respectively. In addition, the fourth and eighth portions Cand Cof the third unique identification data UID() are stored in the fourth column regions C() of the “M+”row R(M) and the “M+”row R(M+), respectively.

0 3 10 13 2 2 2 0 3 10 13 2 0 3 2 1 10 13 2 2 1 th th Each of the first to eighth portions C-Cand C-Cof the third unique identification data UID(), stored in the third memory bank BK() includes unique data that specifies the third memory bank BK() (hereinafter, referred to as “third bank identification data”). Each of the first to eighth portions C-Cand C-Cof the third unique identification data UID() includes data that specifies a row (hereinafter, referred to as “third row identification data”). In an embodiment, each of the first to fourth portions C-Cof the third unique identification data UID(), stored in the “M+”row R(M) has a first binary value, for example, binary value “0” as the third row identification data. On the other hand, each of the fifth to eighth portions C-Cof the third unique identification data UID(), stored in the “M+”row R(M+) has a second binary value, for example, binary value “1”as the third row identification data.

0 3 10 13 2 0 10 2 0 1 11 2 1 2 12 2 2 3 13 2 3 In addition, each of the first to eighth portions C-Cand C-Cof the third unique identification data UID() also includes data that specifies a column region (hereinafter, referred to as “third column identification data”). The first and fifth portions Cand Cof the third unique identification data UID(), stored in the first column region C() have first binary values, for example, binary values “00” as the third row identification data. The second and sixth portions Cand Cof the third unique identification data UID(), stored in the second column region C() have second binary values, for example, binary values “01” as the third column identification data. The third and seventh portions Cand Cof the third unique identification data UID(), stored in the third column region C() have third binary values, for example, binary values “10” as the third column identification data. The fourth and eighth portions Cand Cof the third unique identification data UID(), stored in the fourth column region C() have fourth binary values, for example, binary values “11” as the third column identification data.

3 0 3 1 0 3 2 1 3 3 0 3 10 13 0 3 10 13 3 3 0 3 2 0 3 1 3 10 13 3 0 3 2 1 3 0 10 3 0 1 2 1 1 11 3 1 1 2 1 2 12 3 2 1 2 1 3 13 3 3 1 2 1 th th th th th th th th th th th th The fourth unique identification data UID() is stored in the first to fourth column regions C()-C() of the “M+”row R(M) and the first to fourth column regions C()-C() of the “M+”row R(M+) of the fourth memory bank BK(). The fourth unique identification data UID() includes a plurality of portions D-Dand D-D. The number of the plurality of portions D-Dand D-Dconstituting the fourth unique identification data UID() corresponds to “the number of rows belonging to the second row group ×the number of column regions belonging to one row”. Accordingly, the fourth unique identification data UID() includes first to fourth portions D-Dof the fourth unique identification data UID(), stored in the first to fourth column regions C()-C() of the “M+”row R(M) of the fourth memory bank BK(), respectively, and the fifth to eighth portions D-Dof the fourth unique identification data UID(), stored in the first to fourth column regions C()-C() of the “M+”row R(M+) of the fourth memory bank BK(), respectively. The first and fifth portions Dand Dof the fourth unique identification data UID() are stored in the first column region C() of the “M+”row R(M) and the “M+”row R(M+), respectively. The second and sixth portions Dand Dof the fourth unique identification data UID() are stored in the second column region C() of the “M+”row R(M) and the “M+”row R(M+), respectively. The third and seventh portions Dand Dof the fourth unique identification data UID() are stored in the third column region C() of the “M+”row R(M) and the “M+”row R(M+), respectively. In addition, the fourth and eighth portions Dand Dof the fourth unique identification data UID() are stored in the fourth column region C() of the “M+”row R(M) and the “M+”row R(M+), respectively.

0 3 10 13 3 3 3 0 3 10 13 3 0 3 3 1 10 13 3 2 1 th th Each of the first to eighth portions D-Dand D-Dof the fourth unique identification data UID(), stored in the fourth memory bank BK() includes unique data that specifies the fourth memory bank BK() (hereinafter, referred to as “fourth bank identification data”). Each of the first to eighth portions D-Dand D-Dof the fourth unique identification data UID() includes data that specifies a row (hereinafter, referred to as “fourth row identification data”). In an embodiment, each of the first to fourth portions D-Dof the fourth unique identification data UID() stored in the “M+”row R(M) has a first binary value, for example, binary value “0” as the fourth row identification data. On the other hand, each of the fifth to eighth portions D-Dof the fourth unique identification data UID(), stored in the “M+”row R(M+) has a second binary value, for example, binary value “1” as the fourth row identification data.

0 3 10 13 3 0 10 3 0 1 11 3 1 2 12 3 2 3 13 3 3 In addition, each of the first to eighth portions D-Dand D-Dof the fourth unique identification data UID() also has data that specifies a column region (hereinafter, referred to as “fourth column identification data”). The first and fifth portions Dand Dof the fourth unique identification data UID(), stored in the first column region C() has first binary values, for example, binary values “00” as the fourth row identification data. The second and sixth portions Dand Dof the fourth unique identification data UID(), stored in the second column region C() have second binary values, for example, binary values “01” as the fourth column identification data. The third and seventh portions Dand Dof the fourth unique identification data UID(), stored in the third column region C() have third binary values, for example, binary values “10” as the fourth column identification data. The fourth and eighth portions Dand Dof the fourth unique identification data UID(), stored in the fourth column region C() have fourth binary values, for example, binary values “11”as the fourth column identification data.

3 FIG. 2 FIG. illustrates an example of first to eighth portions of first unique identification data stored in the first memory bank of the memory device of.

3 FIG. 2 FIG. 2 FIG. 0 3 10 13 0 0 0 3 0 0 1 2 1 0 3 10 13 0 th th Referring totogether with, each of the first to eighth portions A-Aand A-Aof the first unique identification data UID() includes column identification bits COL BITS, a row identification bit R BIT, and identification data bits ID DATA BITS. As described with reference, as each of the rows of the first memory bank BK() includes four column regions C()-C(), each of the column identification bits COL BITS has a value of “n” that satisfies a condition of “2n≥4” (where “4” represents the number of column regions), that is, a size of 2-bit. As the first unique identification data UID() in the first memory bank BK() is stored in two rows, that is, the “M+”row R(M) and the “M+”row R(M+), the row identification bit R BIT has a value of “m” that satisfies a condition of “2m≥2”, that is, a size of 1-bit. Because each of the first to eighth portions A-Aand A-Aof the first unique identification data UID() has a size of an access granularity, the identification data bits ID DATA BITS have a bit size obtained by subtracting the number of bits of column identification bits COL BITS and the number of bits of row identification bits R BIT from the access granularity.

0 3 10 13 0 0 10 0 0 0 1 11 0 1 0 2 12 0 2 0 3 13 0 3 0 2 FIG. 3 FIG. The column identification bits COL BITS of each of the first to eighth portions A-Aand A-Aconstituting the first unique identification data UID() have binary values corresponding to the first column identification data. As illustrated inand, the first and fifth portions Aand Aof the first unique identification data UID(), stored in the first column region C() of the first memory bank BK() have binary values of “00” stored in the column bits COL BITS as the first column identification data. The second and sixth portions Aand Aof the first unique identification data UID(), stored in the second column region C() of the first memory bank BK() have binary values of “01” stored in the column bits COL BITS as the first column identification data. The third and seventh portions Aand Aof the first unique identification data UID(), stored in the third column region C() of the first memory bank BK() have binary values of “10” stored in the column bits COL BITS as the first column identification data. In addition, the fourth and eighth portions Aand Aof the first unique identification data UID(), stored in the fourth column region C() of the first memory bank BK() have binary values of “11” stored in the column bits COL BITS as the first column identification data.

0 3 10 13 0 0 3 0 1 0 10 13 0 2 1 0 2 3 FIGS.and th th The row identification bit R BIT of each of the first to eighth portions A-Aand A-Aconstituting the first unique identification data UID() has a binary value corresponding to first row identification data. As illustrated in, each of the first to fourth portions A-Aof the first unique identification data UID(), stored in the “M+”row R(M) of the first memory bank BK() has a binary value of “0” stored in the row bit R BIT as the first row identification data. Each of the fifth to eighth portions A-Aof the first unique identification data UID(), stored in the “M+”row R(M+) of the first memory bank BK() has a binary value of “1” stored in the row bit R BIT as the first row identification data.

0 3 10 13 0 0 0 3 10 13 0 0 0 3 10 13 0 In the identification data bits ID DATA BITS of the first to eighth portions A-Aand A-Aconstituting the first unique identification data UID(), binary values that specify the first memory bank BK() are stored as first bank identification data DATA_A. Because the first to eighth portions A-Aand A-Aconstituting the first unique identification data UID() are all stored in the first memory bank BK(), the first bank identification data DATA_A stored in the identification data bits ID DATA BITS of the first to eighth portions A-Aand A-Aconstituting the first unique identification data UID() may all include the same binary values.

0 3 10 13 0 0 3 10 13 0 0 0 3 10 13 0 0 3 10 13 0 In this way, through the binary values of the first bank identification data DATA_A stored in the identification data bits ID DATA BITS of the first to eighth portions A-Aand A-Aconstituting the first unique identification data UID(), it is possible to determine whether the memory bank in which the first to eighth portions A-Aand A-Aconstituting the first unique identification data UID() are stored is the first memory bank BK(). In addition, through the binary values of the first column identification data and the binary values of the first row identification data, respectively stored in the column bits COL BITS and the row bits R BIT of the first to eighth portions A-Aand A-Aconstituting the first unique identification data UID(), it is possible to determine which row and which column region each of the first to eighth portions A-Aand A-Aconstituting the first unique identification data UID() is stored in.

4 FIG. 2 FIG. illustrates an example of first to eighth portions of second unique identification data stored in the second memory bank of the memory device of.

4 FIG. 2 FIG. 3 FIG. 0 3 10 13 1 0 3 10 13 1 0 3 10 13 1 0 3 10 13 1 0 3 10 13 1 Referring totogether with, each of the first to eighth portions B-Band B-Bconstituting the second unique identification data UID() includes column identification bits COL BITS, a row identification bit R BIT, and identification data bits ID DATA BITS. The composition of the column identification bits COL BITS and the row identification bit R BIT included in the first to eighth portions B-Band B-Bconstituting the second unique identification data UID() may be substantially the same as the composition of the column identification bits COL BITS and the row identification bit R BIT included in the first to eighth portions A-Aand A-Aconstituting the first unique identification data UID() described with reference to. Accordingly, the column identification bits COL BITS of each of the first to eighth portions B-Band B-Bconstituting the second unique identification data UID() have binary values corresponding to second column identification data. In addition, the row identification bit R BIT of each of the first to eighth portions B-Band B-Bconstituting the second unique identification data UID() has a binary value corresponding to second row identification data.

0 3 10 13 1 1 0 3 10 13 1 1 0 3 10 13 1 In the identification data bits ID DATA BITS of the first to eighth portions B-Band B-Bconstituting the second unique identification data UID(), binary values that specify the second memory bank BK() are stored as second bank identification data DATA_B. Because the first to eighth portions B-Band B-Bconstituting the second unique identification data UID() are all stored in the second memory bank BK(), the second bank identification data DATA_B stored in the identification data bits ID DATA BITS of the first to eighth portions B-Band B-Bconstituting the second unique identification data UID() may all include the same binary values.

0 3 10 13 1 0 3 10 13 1 1 0 3 10 13 1 0 3 10 13 1 In this way, through the binary values of the second bank identification data DATA_B stored in the identification data bits ID DATA BITS of the first to eighth portions B-Band B-Bconstituting the second unique identification data UID(), it is possible to determine whether the memory bank in which the first to eighth portions B-Band B-Bconstituting the second unique identification data UID() are stored is the second memory bank BK(). In addition, through the binary values of the second column identification data and the binary values of the second row identification data, respectively stored in the column bits COL BITS and the row bits R BIT of each of the first to eighth portions B-Band B-Bconstituting the second unique identification data UID(), it is possible to determine which row and which column region each of the first to eighth portions B-Band B-Bconstituting the second unique identification data UID() are stored in.

5 FIG. 2 FIG. illustrates an example of first to eighth portions of third unique identification data stored in the third memory bank of the memory device of.

5 FIG. 2 FIG. 3 FIG. 0 3 10 13 2 0 3 10 13 2 0 3 10 13 0 0 3 10 13 2 0 3 10 13 2 Referring totogether with, each of the first to eighth portions C-Cand C-Cof the third unique identification data UID() includes column identification bits COL BITS, a row identification bit R BIT, and identification data bits ID DATA BITS. The composition of the column identification bits COL BITS and the row identification bit R BIT included in each of the first to eighth portions C-Cand C-Cconstituting the third unique identification data UID() may be substantially the same as the composition of the column identification bits COL BITS and the row identification bit R BIT of each of the first to eighth portions A-Aand A-Aconstituting the first unique identification data UID() described with reference. Accordingly, the column identification bits COL BITS of each of the first to eighth portions C-Cand C-Cconstituting the third unique identification data UID() have binary values corresponding to third column identification data. In addition, the row identification bit R BIT of each of the first to eighth portions C-Cand C-Cconstituting the third unique identification data UID() has a binary value corresponding to third row identification data.

0 3 10 13 2 2 0 3 10 13 2 2 0 3 10 13 2 In the identification data bits ID DATA BITS of the first to eighth portions C-Cand C-Cconstituting the third unique identification data UID(), binary values that specify the third memory bank BK() are stored as third bank identification data DATA_C. Because the first to eighth portions C-Cand C-Cconstituting the third unique identification data UID() are all stored in the third memory bank BK(), the third bank identification data DATA_C stored in the identification data bits ID DATA BITS of the first to eighth portions C-Cand C-Cconstituting the third unique identification data UID() may all include the same binary values.

0 3 10 13 2 0 3 10 13 2 2 0 3 10 13 2 0 3 10 13 2 In this way, through the binary values of the third bank identification data DATA_C stored in the identification data bits ID DATA BITS of the first to eighth portions C-Cand C-Cconstituting the third unique identification data UID(), it is possible to determine whether the memory bank in which the first to eighth portions C-Cand C-Cconstituting the third unique identification data UID() are stored is the third memory bank BK(). In addition, through the binary values of the third column identification data and the binary values of the third row identification data stored in the column bits COL BITS and the row bits R BIT of the first to eighth portions C-Cand C-Cconstituting the third unique identification data UID(), it is possible to determine which row and which column region each of the first to eighth portions C-Cand C-Cconstituting the third unique identification data UID() are stored in.

6 FIG. 2 FIG. illustrates an example of first to eighth portions of fourth unique identification data stored in the fourth memory bank of the memory device of.

6 FIG. 2 FIG. 3 FIG. 0 3 10 13 3 0 3 10 13 3 0 3 10 13 0 0 3 10 13 3 0 3 10 13 3 Referring totogether with, each of the first to eighth portions D-Dand D-Dconstituting the fourth unique identification data UID() includes column identification bits COL BITS, a row identification bit R BIT, and identification data bits ID DATA BITS. The compositions of the column identification bits COL BITS and the row identification bit R BIT included in each of the first to eighth portions D-Dand D-Dconstituting the fourth unique identification data UID() may be substantially the same as the composition of the column identification bits COL BITS and row identification bits R BIT included in each of the first to eighth portions A-Aand A-Aconstituting the first unique identification data UID() described with reference to. Accordingly, the column identification bits COL BITS of each of the first to eighth portions D-Dand D-Dconstituting the fourth unique identification data UID() have binary values corresponding to fourth column identification data. In addition, the row identification bits R BIT of each of the first to eighth portions D-Dand D-Dconstituting the fourth unique identification data UID() has a binary value corresponding to fourth row identification data.

0 3 10 13 3 3 0 3 10 13 3 3 0 3 10 13 3 In the identification data bits ID DATA BITS of the first to eighth portions D-Dand D-Dconstituting the fourth unique identification data UID(), binary values that specify the fourth memory bank BK() are stored as fourth bank identification data DATA_D. Because the first to eighth portions D-Dand D-Dconstituting the fourth unique identification data UID() are stored in the fourth memory bank BK(), the fourth bank identification data DATA_D stored in the identification data bits ID DATA BITS of the first to eighth portions D-Dand D-Dconstituting the fourth unique identification data UID() may include the same binary values.

0 3 10 13 3 0 3 10 13 3 3 0 3 10 13 3 0 3 10 13 3 In this way, through the binary values of the fourth bank identification data DATA_D stored in the identification data bits ID DATA BITS of the first to eighth portions D-Dand D-Dconstituting the fourth unique identification data UID(), it is possible to determine whether the memory bank in which the first to eighth portions D-Dand D-Dconstituting the fourth unique identification data UID() are stored is the fourth memory bank BK(). In addition, through the binary values of the fourth column identification data and the binary value of the fourth row identification data, respectively stored in the column bits COL BITS and the row bits R BIT of the first to eighth portions D-Dand D-Dconstituting the fourth unique identification data UID(), it is possible to determine which row and which column region each of the first to eighth portions D-Dand D-Dconstituting the fourth unique identification data UID() are stored in.

7 FIG. 120 1 illustrates an embodiment of a memory controller() included in a computing system according to the present disclosure.

7 FIG. 7 FIG. 1 FIG. 120 1 121 122 1 123 124 120 1 121 Referring to, the memory controller() includes an address mapping table, an address generator(), a read buffer, and a nonvolatile memory (NVM). Although not shown in, the memory controller() may include various components for accessing a memory device, such as a command generator and a write buffer. As described with reference to, an address mapping order is defined in the address mapping table. In an example, the address mapping order represents a decoding order between banks, rows, and columns. In another example, the address mapping order represents a decoding order between channels, banks, rows, and columns. In another example, the address mapping order represents a decoding order between ranks, channels, banks, rows, and columns.

122 1 123 123 123 124 123 123 124 123 The address generator() generates a physical address corresponding to the address mapping order for a virtual address transmitted from a processing unit to transmit the physical address to a memory device. The read bufferhas a plurality of storage regions in which read data read out from the memory device is stored. The read data stored in the read buffermay be transmitted to the processing unit. Some physically continuous storage regions among the plurality of storage regions of the read buffermay be separately allocated to store unique identification data read from the memory device (hereinafter, referred to as “unique identification read data”). The nonvolatile memory (NVM)receives the unique identification read data stored in the read bufferfrom the read bufferand stores the unique identification read data. Accordingly, the processing unit may detect, based on the unique identification read data stored in the nonvolatile memory, the address mapping order, regardless of whether the unique identification read data is stored in the read buffer.

8 FIG. is a flow chart illustrating a process of detecting an address mapping order in a computing system according to the present disclosure.

8 FIG. 1 FIG. 7 FIG. 110 130 123 124 120 123 124 120 120 130 123 124 Referring to, together withand, in operation S, a processing unitdetermine whether unique identification read data exists in a read bufferor a nonvolatile memoryof a memory controller. When the unique identification read data exists in the read bufferor the nonvolatile memoryof the memory controller, in operation S, the processing unitdetects the address mapping order, based on the unique identification read data stored in the read bufferor the nonvolatile memory. The process of detecting, based on the unique identification read data, the address mapping order is described in more detail below.

123 124 120 130 130 123 120 140 120 110 130 120 150 120 110 123 160 120 123 124 120 124 160 When the unique identification read data does not exist in the read bufferor nonvolatile memoryof the memory controller, in operation S, the processing unitallocates physically continuous storage regions in the read bufferof the memory controlleras storage regions for storing the unique identification data. In operation S, the memory controllerreads the unique identification data from a memory device. To this end, the processing unittransmits a read request for the unique identification data to the memory controller. In operation S, the memory controllerstores the unique identification data that is read from the memory deviceas the unique identification read data in the allocated storage regions of the read buffer. In operation S, the memory controllersaves the unique identification read data stored in the read bufferin the nonvolatile memory. In operation S, the address mapping order is detected based on the unique identification read data stored in the nonvolatile memory. In other embodiments, the operation Smay be skipped.

9 FIG. 10 FIG. 9 FIG. 210 illustrates an example of first to fourth unique identification data stored in a memory devicein a computing system according to the present disclosure.illustrates an example of unique identification read data stored in a read buffer through a read process for the first to fourth unique identification data of.

9 FIG. 210 0 3 0 3 1 0 3 0 3 0 3 0 3 0 0 3 1 0 0 3 1 1 0 3 1 0 3 1 2 0 3 2 0 3 1 3 0 3 3 th th th th th First, as shown in, it is assumed that the memory deviceincludes first to fourth memory banks BK()-BK() and the first to fourth unique identification data UID()-UID() are stored in an “M+”row R(M) of each of the first to fourth memory banks BK()-BK(), respectively. In addition, it is assumed that each of the first to fourth memory banks BK()-BK() includes first to fourth column regions C()-C(). Accordingly, first to fourth portions A-Aof the first unique identification data UID() are stored in the first to fourth column regions C()-C() of the “M+”row R(M) of the first memory bank BK(), respectively. In the first to fourth column regions C()-C() of the “M+”row R(M) of the second memory bank BK(), first to fourth portions B-Bof the second unique identification data UID() are stored, respectively. In the first to fourth column regions C()-C() of the “M+”row R(M) of the third memory bank BK(), first to fourth portions C-Cof the third unique identification data UID() are stored, respectively. In addition, in the first to fourth column regions C()-C() of the “M+”row R(M) of the fourth memory bank BK(), first to fourth portions D-Dof the fourth unique identification data UID() are stored, respectively.

130 3 120 123 120 123 130 123 120 123 120 0 3 210 0 3 123 120 123 130 The processing unittransmits a read request for the first to fourth unique identification data UID() to the memory controller. When there is the unique identification read data in the read buffer, the memory controllertransmits the unique identification read data stored in the read bufferto the processing unit. When there is no unique identification read data within the read buffer, the memory controllerallocates physically continuous storage regions within the read buffer. The memory controllerreads the first to fourth unique identification data UID()-UID() from the memory deviceand stores the first to fourth unique identification data UID()-UID() as the unique identification read data in the allocated storage regions of the read buffer. The memory controllertransmits the unique identification read data stored in the read bufferto the processing unit.

10 FIG. 123 210 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 210 123 0 3 1 0 0 3 1 1 0 3 1 2 0 3 1 3 130 th th th th As shown in, a case where the unique identification read data stored in the allocated storage region of the read bufferis transmitted from the memory devicein the order of “A, A, A, A, B, B, B, B, C, C, C, C, D, D, D, D” is taken as an example. In this case, the first unique identification data UID(), the second unique identification data UID(), the third unique identification data UID(), and the fourth unique identification data UID() are read from the memory deviceto the read bufferin that order. That is, a read operation is first performed on the first to fourth column regions C()-C() of the “M+”row R(M) of the first memory bank BK(). Next, a read operation is performed on the first to fourth column regions C()-C() of the “M+”row R(M) of the second memory bank BK(). Next, a read operation is performed on the first to fourth column regions C()-C() of the “M+”row R(M) of the third memory bank BK(). Finally, a read operation is performed on the first to fourth column regions C()-C() of the “M+”row R(M) of the fourth memory bank BK(). That is, among the columns, banks, and rows which constitute the address mapping, the read operation is performed in the following order: column increases first, followed by bank increases. Accordingly, the processing unitmay detect that the address mapping is defined in the order of row-bank-column.

11 FIG. 9 FIG. illustrates an example of unique identification read data stored in a read buffer through a read process for the first to fourth unique identification data of.

11 FIG. 123 210 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 0 1 2 3 210 123 0 1 0 3 1 1 0 3 2 1 0 3 3 1 0 3 130 th th th th As shown in, a case where unique identification read data stored in an allocated storage region of a read bufferis transmitted from a memory devicein the order of “A, B, C, D, A, B, C, D, A, B, C, D, A, B, C, D” is taken as an example. In this case, the first portions A, B, C, D, the second portions A, B, C, D, the third portions A, B, C, D, and the fourth portions A, B, C, Dof the first unique identification data UID(), the second unique identification data UID(), the third unique identification data UID(), and the third unique identification data UID() are read from the memory deviceto the read bufferin that order. That is, first, a read operation is sequentially performed on the first column region C() of the “M+”row R(M) of each of the first to fourth memory banks BK()-BK(). Next, a read operation is sequentially performed on the second column region C() of the “M+”row R(M) of each of the first to fourth memory banks BK()-BK(). Next, a read operation is sequentially performed on the third column region C() of the “M+”row R(M) of each of the first to fourth memory banks BK()-BK(). Finally, a read operation is sequentially performed on the fourth column region C() of the “M+”row R(M) of each of the first to fourth memory banks BK()-BK(). That is, among the columns, banks, and rows which constitute the address mapping, the read operation is performed in the following order: bank increases first, followed by column increases. Accordingly, the processing unitmay detect that the address mapping is defined in the order of row-column-bank.

12 FIG. 12 FIG. 7 FIG. 120 2 illustrates an embodiment of a memory controller() included in a computing system according to the present disclosure. In, the same reference numerals as inrepresent the same components, and duplicate description is omitted below.

12 FIG. 120 2 121 122 2 123 124 122 2 222 222 121 121 222 121 120 2 122 2 120 2 222 Referring to, the memory controller() includes an address mapping table, an address generator(), a read buffer, and a nonvolatile memory (NVM). The address generator() includes an address mapping changing circuit. The address mapping changing circuitis configured to change the address mapping order defined in the address mapping table. For example, when the address mapping order is defined in the order of row-bank-column in the address mapping table, the address mapping changing circuitchanges the address mapping order into the order of row-column-bank. In an example, the processing unit detects the address mapping order defined in the address mapping tablethrough a read operation on unique identification data included in the memory device. The processing unit may request the memory controller() to generate addresses in an address mapping order different from the detected address mapping order for efficient operation of the memory system. The address generator() of the memory controller() generates an address remapped in the requested address mapping order through the address mapping changing circuitin response to the request from the processing unit and transmit the remapped address to the memory device.

13 FIG. 13 FIG. 1 FIG. 300 is a block diagram illustrating a computing systemaccording to an embodiment of the present disclosure. In, the same reference numerals as inrepresent the same components, and duplicate description is omitted below.

13 FIG. 1 FIG. 6 FIG. 7 FIG. 12 FIG. 300 110 120 130 340 110 0 1 0 1 120 120 1 120 2 th th Referring to, the computing systemincludes a memory device, a memory controller, a processing unit, and a firmware. The memory deviceincludes first to “N”unique identification data UID()-UID(N−) stored in first to “N”memory banks BK()-BK(N−), respectively, as described with reference toto. A configuration of the memory controllermay be the same as the configuration of the memory controller() described with reference toor the configuration of the memory controller() described with reference to.

340 300 340 120 130 340 300 140 110 340 110 110 340 110 110 340 110 number of column bits 2 The firmwaremay be configured in a form of a ROM in which commands and data for executing basic operation and control of the computing systemare stored. The firmwareis coupled to the memory controllerand the processing unit. The firmwareis configured to allow a booting process of the computing systemto be performed. For example, the firmwareallows hardware diagnosis, date and time setting, boot mode setting, boot order setting, etc. to be performed through the boot process. When the memory devicehas serial presence detect (SPD) information (or SPD data), the firmwaremay calculate a burst length of the memory device, the number of bits of the column address, the number of bits of the row address, the number of bits of the bank address, the number of channels, etc. through the SPD information of the memory deviceduring the booting process. In this case, the firmwarecalculates the row size using the SPD information read from the memory device. The row size may be calculated by the formula “access granularity×2”. For example, when the access granularity is 1 byte and the number of bits in the column address is “2”, the row size is calculated as 1-byte ×2=4 bytes. When the memory devicedoes not have the SPD information, the firmwaremay have data regarding the burst length of the memory device, the number of bits in the column address, the number of bits in the row address, the number of bits in the bank address, the number of channels, etc.

340 0 3 (number of bits of column address) (number of bits of bank address) 2 2 2 FIG. The firmwarecalculates the number of portions of the unique identification data to be read, corresponding to the calculated row size. In an example, the number of portions of the unique identification data to be read may be calculated by the formula “burst length×2×2.” For example, when information is obtained through the SPD information that the burst length is “1”, the number of bits of column address is “2”, and the number of bits of bank address is “2,” a read operation may be performed on 16 portions of the unique identification data to be read, which is 2×1×2=16 portions of the unique identification data. In an example, as described with reference to, when the portions of the unique identification data are stored in two or more rows, the portions of the unique identification data up to twice the calculated number may be read to read the portions of the unique identification data stored in all column regions. That is, when the number of portions of the unique identification data to be read through the SPD information is calculated as “16,” a read operation is performed for up to “32” portions of the unique identification data. In this case, even though one of the first to fourth column regions C()-C() is read, the portions of the unique identification data stored in all column regions can be read.

340 110 340 123 120 340 110 123 340 123 124 340 124 340 130 Once the number of portions of the unique identification data to be read is calculated, the firmwareperforms a read operation on the unique identification data of the memory device. Specifically, the firmwareallocates physically continuous storage regions in the read bufferof the memory controlleras storage regions to store the unique identification data. The firmwarereads the unique identification data from the memory deviceand stores the read unique identification data as the unique identification read data in the allocated storage regions of the read buffer. The firmwarestores the unique identification data stored in the read bufferin the nonvolatile memory. In addition, the firmwaredetects an address mapping order, based on the unique identification read data stored in the nonvolatile memory. The firmwareprovides the detected address mapping order to the processing unit.

110 120 300 340 300 110 120 120 340 120 In an example, when the configurations of the memory deviceand the memory controllerin the computing systemare changed, the firmwareperforms a read process for the unique identification data. In the computing system, when the configurations of the memory deviceand the memory controllerare not changed, that is, when a read process for the unique identification data has been performed previously and the unique identification read data is stored in the memory controller, the firmwaredetects the memory mapping order through the unique identification read data stored in the memory controllerwithout performing the read process for the unique identification data during the boot process.

14 FIG. 14 FIG. 400 400 410 420 430 is a block diagram illustrating a computing systemaccording to an embodiment of the present disclosure. Referring to, the computing systemincludes a processing-in-memory (PIM) device, a memory controller, and a processing unit.

410 0 1 0 1 0 1 0 1 0 1 th th th th th The PIM deviceincludes a plurality of memory banks, for example, first to “N”memory banks BK()-BK(N−) (“N” is a natural number), a global buffer GB, and a plurality of processing elements, for example, first to “N”processing elements PE()-PE(N−). The first to “N”processing elements PE()-PE(N−) are coupled to the first to “N”memory banks BK()-BK(N−), respectively. The first to “N”processing elements PE()-PE(N−) are coupled to the global buffer GB in common.

th th th th th th th 0 1 0 1 0 1 0 0 1 1 0 1 410 2 FIG. 6 FIG. Each of the first to “N”memory banks BK()-BK(N−) includes a memory cell array including a plurality of memory cells. The first to “N”memory banks BK()-BK(N−) include data storage regions in which a plurality of unique identification data, for example, first to “N”unique identification data UID()-UID(N−) are stored. For example, the first memory bank BK() includes a first data storage region in which the first unique identification data UID() is stored. Similarly, the “N”memory bank BK(N−) includes an “N”data storage region in which the “N”unique identification data UID(N−) is stored. The method of storing the unique identification data described with reference totomay be equally applied to a method of storing the unique identification data in the first to “N”memory banks BK()-BK(N−) of the PIM device.

th th th th th th th 0 1 0 1 0 1 0 1 0 1 0 1 0 1 The first to “N”processing elements PE()-PE(N−) receive data from the first to “N”memory banks BK()-BK(N−), respectively, and perform an arithmetic operation using the received data. In an embodiment, each of the first to “N”processing elements PE()-PE(N−) includes a multiplication and accumulation (MAC) operation circuit. In this case, the MAC operation circuit may include a plurality of multipliers, an adder tree, and an accumulator. The accumulator may include an adder and a latch circuit. In a process of performing the arithmetic operation, the first to “N”processing elements PE()-PE(N−) receive weight data W from the first to “N”memory banks BK()-BK(N−), respectively. In addition, the first to “N”processing elements PE()-PE(N−) commonly receive vector data V from the global buffer GB. The first to “N”processing elements PE()-PE(N−) perform the arithmetic operation using the weight data W and the vector data V to generate the arithmetic result data.

420 410 420 410 410 410 410 110 410 420 410 410 0 1 1 FIG. th The memory controllercontrols the memory access operation and the arithmetic operation on the PIM device. The memory controllercontrols the memory access operation of the PIM devicethrough memory access commands, for example, a read command and a write command. In an example, the memory access operation on the PIM deviceincludes a read operation of reading data from the PIM deviceand a write operation of writing data to the PIM device. The description on the access operation for the memory devicedescribed with reference tomay be equally applied to the access operation for the PIM device. The memory controllercontrols the arithmetic operation of the PIM devicethrough an arithmetic command. The arithmetic operation of the PIM devicemay be performed by the first to “N”processing elements PE()-PE(N−).

420 421 423 420 410 421 121 421 423 0 1 410 0 1 0 1 410 423 123 423 1 FIG. 1 FIG. th th th The memory controllerincludes an address mapping tablein which an address mapping order is defined and a read buffer. The memory controllercontrols the memory access operation of the PIM device, based on the address mapping order defined by the address mapping table. The configuration of the address mapping tabledescribed with reference tomay be equally applied to the address mapping table. The read bufferstores the data read from the first to “N”memory banks BK()-BK(N−) of the PIM device. The first to “N”unique identification data UID()-UID(N−) read from the first to “N”memory banks BK()-BK(N−) of the PIM deviceare stored in specific regions of the read buffer. The configuration of the read bufferdescribed with reference tomay be equally applied to the read buffer.

430 410 420 430 400 430 430 410 430 410 110 420 420 430 410 421 420 430 410 421 430 410 420 420 430 410 The processing unitis coupled to the PIM devicethrough the memory controller. In an embodiment, the processing unitis configured to process commands of an operating system for driving the computing systemor commands of an application program at the request of a user. In an embodiment, the processing unitmay be a central processing unit CPU. The processing unitrequests memory access operation or arithmetic operation to the PIM device. In an embodiment, the processing unittransmits a request for data read from the PIM deviceor data write to the memory deviceto the memory controller. The memory controllerthat receives the data read request from the processing unitreads data from the PIM device, based on the address mapping order defined in the address mapping table. The memory controllerthat receives a data write request from the processing unitwrites data to the PIM device, based on the address mapping order defined in the address mapping table. In an embodiment, the processing unittransmits a request for an arithmetic operation in the PIM deviceto the memory controller. The memory controllerthat receives the arithmetic operation request from the processing unittransmits an arithmetic command to the PIM device.

430 0 1 0 1 410 430 420 420 0 1 410 0 1 423 420 430 0 1 423 420 421 420 0 1 300 th th th th th th 14 FIG. 13 FIG. The processing unitis configured to detect the address mapping order, based on the first to “N”unique identification data UID()-UID(N−) stored in the first to “N”memory banks BK()-BK(N−) of the PIM device, respectively. To this end, the processing unitperforms a unique identification data read request operation for unique identification data to the memory controller. The memory controllerthat is requested to read the unique identification data reads the first to “N”unique identification data UID()-UID(N−) from the PIM deviceand stores the first to “N”unique identification data UID()-UID(N−) in the read bufferwithin the memory controller. The processing unitanalyzes the first to “N”unique identification data UID()-UID(N−) stored in the read bufferwithin the memory controllerto detect the address mapping order defined in the address mapping tableof the memory controller. Although not shown in, detection of the address mapping order using the first to “N”unique identification data UID()-UID(N−) may also be performed during the booting process, similarly to the computing systemdescribed with reference to.

15 FIG. 14 FIG. 420 is a diagram illustrating an embodiment of a memory controllerincluded in a computing system according to an embodiment of the present disclosure, for example, as shown in the computing system of.

15 FIG. 15 FIG. 14 FIG. 420 421 422 423 424 425 420 421 Referring to, the memory controllerincludes an address mapping table, an address generator, a read buffer, a nonvolatile memory (NVM), and a mode setting circuit. Although not shown in, the memory controllermay include various components for controlling memory access and arithmetic operations for the PIM device, such as a command generator and a write buffer. As described with reference to, an address mapping order is defined in the address mapping table. In an example, the address mapping order represents a decoding order between banks, rows, and columns. In another example, the address mapping order represents a decoding order between channels, banks, rows, and columns. In another example, the address mapping order represents a decoding order between ranks, channels, banks, rows, and columns.

422 423 423 423 424 423 423 424 423 422 522 522 421 421 522 The address generatorgenerates a physical address corresponding to the address mapping order for a virtual address transmitted from the processing unit to transmit the physical address to the PIM device. The read bufferhas a plurality of storage regions in which read data read from the PIM device is stored. The read data stored in the read bufferis transmitted to the processing unit. Some physically continuous storage regions of the plurality of storage regions of the read bufferare separately allocated to store the unique identification data read from the PIM device, that is, the unique identification read data. The nonvolatile memory (NVM)receives the unique identification read data stored in the read bufferfrom the read bufferand stores the unique identification read data. Accordingly, the processing unit can detect the address mapping order, based on the unique identification read data stored in the nonvolatile memory, regardless of whether the unique identification read data is stored in the read buffer. The address generatorincludes an address mapping changing circuit. The address mapping changing circuitmay be configured to change the address mapping order defined in the address mapping table. For example, when the address mapping order is defined in the order of row-bank-column in the address mapping table, the address mapping changing circuitmay change the address mapping order into the order of row-column-bank.

522 425 522 422 421 522 522 In an embodiment, the address mapping changing circuitmay be enabled or disabled by a mode control signal M_CTRL transmitted from the mode setting circuit. The mode control signal M_CTRL may be a first mode control signal corresponding to a memory access mode, or may be a second mode control signal corresponding to an arithmetic mode. For example, the address mapping changing circuitis disabled when the mode control signal M_CTRL is the first mode control signal. In this case, the address generatorgenerates an address corresponding to the first address mapping order defined in the address mapping table. When the mode control signal M_STRL is the second mode control signal, the address mapping changing circuitis enabled. In this case, the address mapping changing circuitgenerates an address corresponding to the second address mapping order.

425 425 522 422 522 425 522 422 522 The mode setting circuitoutputs the first mode control signal or the second mode control signal as the mode control signal by the signal transmitted from the processing unit. In an embodiment, when a request for a memory access operation of the PIM device is transmitted from the processing unit, the mode setting circuitgenerates the first mode control signal to transmit the first mode control signal to the address mapping changing circuitof the address generator. In this case, the address mapping changing circuitis disabled. When a request for an arithmetic operation of the PIM device is transmitted from the processing unit, the mode setting circuitgenerates the second mode control signal to transmit the second mode control signal to the address mapping changing circuitof the address generator. In this case, the address mapping changing circuitis enabled.

16 FIG. 15 FIG. is a diagram illustrating an example of a matrix multiplication operation performed in a PIM device included in a computing system according to an embodiment of the present disclosure, for example, as shown in.

16 FIG. 15 FIG. 410 610 620 630 610 620 630 4 610 1 1 64 1 1 2 64 2 1 3 64 3 1 4 64 4 620 1 64 630 1 4 th th th th th th Referring totogether with, the PIM deviceperforms a matrix multiplication operation on a weight matrixand a vector matrixto generate a result matrix. In an example below, the weight matrixhas four rows and sixty-four columns, and the vector matrixhas sixty-four rows and one column. In this case, the result matrixincludes four () rows and one column. The weight matrixincludes first to 64weight data W()-W() of a first row, first to 64weight data W()-W() of a second row, first to 64weight data W()-W() of a third row, and first to 64weight data W()-W() of a fourth row. The vector matrixincludes first to 64vector data V-Vof a first column. In addition, the result matrixincludes first to 64result data MAC_RST-MAC_RSTof a first column.

610 620 630 0 1 410 0 1 610 620 0 1 th th th In an embodiment, the process of performing the matrix multiplication operation on the weight matrixand the vector matrixto generate the result matrixis performed in the MAC operation method in the first to “N”processing elements PE()-PE(N−) of the PIM device. That is, the matrix multiplication operation in the first to “N”processing elements PE()-PE(N−) is performed multiple times by repeating the matrix multiplication operation for sub-groups of the weight matrixand a sub-group of the vector matrixdepending on the hardware resources of the first to “N”processing elements PE()-PE(N−).

17 FIG. 16 FIG. 410 0 3 0 3 is a block diagram illustrating a method of storing weight data in memory banks of a PIM device for parallel execution of a matrix multiplication operation, for example, as shown in. In the following examples, a PIM deviceis exemplified as including first to fourth memory banks BK()-BK() and first to fourth processing elements PE()-PE().

17 FIG. 16 FIG. 1 1 64 1 1 2 64 2 1 3 64 3 1 4 64 4 610 0 3 1 1 64 1 1 2 64 2 1 3 64 3 1 4 64 4 610 0 0 3 410 1 64 620 410 Referring totogether with, the weight data W()-W(), W()-W(), W()-W(), and W()-W() of the weight matrixare stored in the first to fourth memory banks BK()-BK(), respectively. In an example, the weight data W()-W(), W()-W(), W()-W(), and W()-W() of the weight matrixare stored in the same row, for example, in a first row R() of each of the first to fourth memory banks BK()-BK() of the PIM device. The vector data V-Vof the vector matrixis stored in a global buffer GB of the PIM device.

0 3 410 610 0 3 1 1 64 1 610 0 0 1 2 64 2 610 0 1 1 3 64 3 610 0 2 1 4 64 4 610 0 3 16 FIG. 16 FIG. th th th th As the first to fourth processing elements PE()-PE() of the PIM devicereceive the vector data V from the global buffer GB, to perform the matrix multiplication operation ofin parallel, the weight data of the first to fourth rows of the weight matrixofis stored in the first to fourth memory banks BK()-BK(), respectively. Specifically, the first to 64weight data W()-W() of the first row of the weight matrixare stored in the first row R() of the first memory bank BK(), the first to 64weight data W()-W() of the second row of the weight matrixare stored in the first row R() of the second memory bank BK(), the first to 64weight data W()-W() of the third row of the weight matrixare stored in the first row R() of the third memory bank BK(), and the first to 64weight data W()-W() of the fourth row of the weight matrixare stored in the first row R() of the fourth memory bank BK().

0 3 410 0 1 1 64 1 610 0 1 1 2 64 2 610 1 2 1 3 64 3 610 2 3 1 3 64 3 610 3 0 3 610 0 3 1 64 th th th th th For one of a plurality of MAC operations performed in the first to fourth processing elements PE()-PE() of the PIM device, the first processing unit PE() receives some of the first to 64weight data W()-W() of the first row of the weight matrixfrom the first memory bank BK(). The second processing unit PE() receives some of the first to 64weight data W()-W() of the second row of the weight matrixfrom the second memory bank BK(). The third processing unit PE() receives some of the first to 64weight data W()-W() of the third row of the weight matrixfrom the third memory bank BK(). In addition, the fourth processing unit PE() receives some of the first to 64weight data W()-W() of the fourth row of the weight matrixfrom the fourth memory bank BK(). The weight data transmitted to the first to fourth processing elements PE()-PE() is the weight data included in different rows of the weight matrix, but is the weight data included in the same columns. On the other hand, the first to fourth processing elements PE()-PE() commonly receive some of the first to 64vector data V-Vfrom the global buffer GB.

18 FIG. 17 FIG. 0 3 illustrates a first MAC operation process in which the method of storing weight data ofis applied. Hereinafter, it is assumed that each of the first to fourth processing elements PE()-PE() is configured to perform the MAC operations on sixteen weight data and sixteen vector data at a time.

18 FIG. 16 FIG. 16 FIG. 0 1 1 16 1 610 0 1 16 620 0 1 1 16 1 610 1 16 620 1 1 1 1 0 1 1 th th th th Referring to, the first processing element PE() receives the first to 16weight data W()-W() of the first row of the weight matrixoffrom the first memory bank BK() and receives the first to 16vector data V-Vof the vector matrixoffrom the global buffer GB. The first processing element PE() performs multiplication and addition on the first to 16weight data W()-W() of the first row of the weight matrixand the first to 16vector data V-Vof the vector matrixto generate first multiplication and addition data MA(). The first multiplication and addition data MA() is latched in the first processing element PE() as first MAC result data MAC().

1 1 2 16 2 610 1 1 16 620 1 1 2 16 2 610 1 16 620 1 2 1 2 1 1 2 th th th th The second processing element PE() receives the first to 16weight data W()-W() of the second row of the weight matrixfrom the second memory bank BK() and receives the first to 16vector data V-Vof the vector matrixfrom the global buffer GB. The second processing element PE() performs the multiplication and addition on the first to 16weight data W()-W() of the second row of the weight matrixand the first to 16vector data V-Vof the vector matrixto generate first multiplication and addition data MA(). The first multiplication and addition data MA() is latched in the second processing element PE() as first MAC result data MAC().

2 1 3 16 3 610 2 1 16 620 2 1 3 16 3 610 1 16 620 1 3 1 3 2 1 3 th th th th The third processing element PE() receives the first to 16weight data W()-W() of the third row of the weight matrixfrom the third memory bank BK() and receives the first to 16vector data V-Vof the vector matrixfrom the global buffer GB. The third processing element PE() performs the multiplication and addition on the first to 16weight data W()-W() of the third row of the weight matrixand the first to 16vector data V-Vof the vector matrixto generate first multiplication and addition data MA(). The first multiplication and addition data MA() is latched in the third processing element PE() as first MAC result data MAC().

3 1 4 16 4 610 3 1 16 620 3 1 4 16 4 610 1 16 620 1 4 1 4 3 1 4 th th th th In addition, the fourth processing element PE() receives the first to 16weight data W()-W() of the fourth row of the weight matrixfrom the fourth memory bank BK() and receives the first to 16vector data V-Vof the vector matrixfrom the global buffer GB. The fourth processing element PE() performs the multiplication and addition on the first to 16weight data W()-W() of the fourth row of the weight matrixand the first to 16vector data V-Vof the vector matrixto generate first multiplication and addition data MA(). The first multiplication and addition data MA() is latched in the fourth processing element PE() as first MAC result data MAC().

19 FIG. 17 FIG. illustrates a second MAC operation process in which the method of storing weight data ofis applied.

19 FIG. 16 FIG. 16 FIG. 0 17 1 32 1 610 0 17 32 620 0 17 1 32 1 610 17 32 620 2 1 0 2 1 1 1 0 2 1 th nd th nd th nd th nd Referring to, the first processing element PE() receives the 17to 32weight data W()-W() of the first row of the weight matrixoffrom the first memory bank BK() and receives the 17to 32vector data V-Vof the vector matrixoffrom the global buffer GB. The first processing element PE() performs the multiplication and addition on the 17to 32weight data W()-W() of the first row of the weight matrixand the 17to 32vector data V-Vof the vector matrixto generate second multiplication and addition data MA(). The first processing element PE() performs accumulative addition on the second multiplication and addition data MA() and the first MAC result data MAC() and latches result data of the accumulative addition in the first processing element PE() as second MAC result data MAC().

1 17 2 32 2 610 1 17 32 620 1 17 2 32 2 610 17 32 620 2 2 1 2 2 1 2 1 2 2 th nd th nd th nd th nd The second processing element PE() receives the 17to 32weight data W()-W() of the second row of the weight matrixfrom the second memory bank BK() and receives the 17to 32vector data V-Vof the vector matrixfrom the global buffer GB. The second processing element PE() performs the multiplication and addition on the 17to 32weight data W()-W() of the second row of the weight matrixand the 17to 32vector data V-Vof the vector matrixto generate second multiplication and addition data MA(). The second processing element PE() performs the accumulative addition on the second multiplication and the addition data MA() and the first MAC result data MAC() and latches result data of the accumulative addition in the second processing element PE() as second MAC result data MAC().

2 17 3 32 3 610 2 17 32 620 2 17 3 32 3 610 17 32 620 2 3 2 2 3 1 3 2 2 3 th nd th nd th nd th nd The third processing element PE() receives the 17to 32weight data W()-W() of the third row of the weight matrixfrom the third memory bank BK() and receives the 17to 32vector data V-Vof the vector matrixfrom the global buffer GB. The third processing element PE() performs the multiplication and addition on the 17to 32weight data W()-W() of the third row of the weight matrixand the 17to 32vector data V-Vof the vector matrixto generate second multiplication and addition data MA(). The third processing element PE() performs the accumulative addition on the second multiplication and addition data MA() and the first MAC result data MAC() and latches result data of the accumulative addition in the third processing element PE() as second MAC result data MAC().

3 17 4 32 4 610 3 17 32 620 3 17 4 32 4 610 17 32 620 2 4 3 2 4 1 4 3 2 4 th nd th nd th nd th nd 16 FIG. 16 FIG. In addition, the fourth processing element PE() receives the 17to 32weight data W()-W() of the fourth row of the weight matrixoffrom the fourth memory bank BK() and receives the 17to 32vector data V-Vof the vector matrixoffrom the global buffer GB. The fourth processing element PE() performs the multiplication and addition on the 17to 32weight data W()-W() of the fourth row of the weight matrixand the 17to 32vector data V-Vof the vector matrixto generate second multiplication and addition data MA(). The fourth processing element PE() performs the accumulative addition on the second multiplication and addition data MA() and the first MAC result data MAC() and latches result data of the accumulative addition in the fourth processing element PE() as second MAC result data MAC().

20 FIG. 17 FIG. illustrates a third MAC operation process in which the method of storing weight data ofis applied.

20 FIG. 16 FIG. 16 FIG. 0 33 1 48 1 610 0 33 48 620 0 33 1 48 1 610 33 48 620 3 1 0 3 1 2 1 0 3 1 rd th rd th rd th rd th Referring to, the first processing element PE() receives the 33to 48weight data W()-W() of the first row of the weight matrixoffrom the first memory bank BK() and receives the 33to 48vector data V-Vof the vector matrixoffrom the global buffer GB. The first processing element PE() performs multiplication and addition on the 33to 48weight data W()-W() of the first row of the weight matrixand the 33to 48vector data V-Vof the vector matrixto generate third multiplication and addition data MA(). The first processing element PE() performs accumulative addition on the third multiplication and addition data MA() and the second MAC result data MAC() and latches result data of the accumulative addition in the first processing element PE() as third MAC result data MAC().

1 33 2 48 2 610 1 33 48 620 1 33 2 48 2 610 33 48 620 3 2 1 3 2 2 2 1 3 2 rd th rd th rd th rd th The second processing element PE() receives the 33to 48weight data W()-W() of the second row of the weight matrixfrom the second memory bank BK() and receives the 33to 48vector data V-Vof the vector matrixfrom the global buffer GB. The second processing element PE() performs the multiplication and addition on the 33to 48weight data W()-W() of the second row of the weight matrixand the 33to 48vector data V-Vof the vector matrixto generate third multiplication and addition data MA(). The second processing element PE() performs the accumulative addition on the third multiplication and addition data MA() and the second MAC result data MAC() and latches result data of the accumulative addition in the second processing element PE() as third MAC result data MAC().

2 33 3 48 3 610 2 33 48 620 2 33 3 48 3 610 33 48 620 3 3 2 3 3 2 3 2 3 3 rd th rd th rd th rd th 16 FIG. 16 FIG. The third processing element PE() receives the 33to 48weight data W()-W() of the third row of the weight matrixoffrom the third memory bank BK() and receives the 33to 48vector data V-Vof the vector matrixoffrom the global buffer GB. The third processing element PE() performs the multiplication and addition on the 33to 48weight data W()-W() of the third row of the weight matrixand the 33to 48vector data V-Vof the vector matrixto generate third multiplication and addition data MA(). The third processing element PE() performs the accumulative addition on the third multiplication and addition data MA() and the second MAC result data MAC() and latches result data of the accumulative addition in the third processing element PE() as third MAC result data MAC().

3 33 4 48 4 610 3 33 48 620 3 33 4 48 4 610 33 48 620 3 4 3 3 4 2 4 3 3 4 rd th rd th rd th rd th In addition, the fourth processing element PE() receives the 33to 48weight data W()-W() of the fourth row of the weight matrixfrom the fourth memory bank BK() and receives the 33to 48vector data V-Vof the vector matrixfrom the global buffer GB. The fourth processing element PE() performs the multiplication and addition on the 33to 48weight data W()-W() of the fourth row of the weight matrixand the 33to 48vector data V-Vof the vector matrixto generate third multiplication and addition data MA(). The fourth processing element PE() performs the accumulative addition on the third multiplication and addition data MA() and the second MAC result data MAC() and latches result data of the accumulative addition in the fourth processing element PE() as third MAC result data MAC().

21 FIG. 17 FIG. illustrates a fourth MAC operation process in which the method of storing weight data ofis applied.

21 FIG. 16 FIG. 16 FIG. 16 FIG. 0 49 1 64 1 610 0 49 49 64 620 0 49 1 64 1 610 49 64 620 4 1 0 4 1 3 1 1 630 th th th th th th th th Referring to, the first processing element PE() receives the 49to 64weight data W()-W() of the first row of the weight matrixoffrom the first memory bank BK() and receives theto 64vector data V-Vof the vector matrixoffrom the global buffer GB. The first processing element PE() performs multiplication and addition on the 49to 64weight data W()-W() of the first row of the weight matrixand the 49to 64vector data V-Vof the vector matrixto generate fourth multiplication and addition data MA(). The first processing element PE() performs accumulative addition on the fourth multiplication and addition data MA() and the third MAC result data MAC() and outputs result data of the accumulative addition as first MAC result data MAC_RSTof the result matrixof.

1 49 2 64 2 610 1 49 64 620 1 49 2 64 2 610 49 64 620 4 2 1 4 2 3 2 2 630 th th th th th th th th The second processing element PE() receives the 49to 64weight data W()-W() of the second row of the weight matrixfrom the second memory bank BK() and receives the 49to 64vector data V-Vof the vector matrixfrom the global buffer GB. The second processing element PE() performs the multiplication and addition on the 49to 64weight data W()-W() of the second row of the weight matrixand the 49to 64vector data V-Vof the vector matrixto generate fourth multiplication and addition data MA(). The second processing element PE() performs the accumulative addition on the fourth multiplication and addition data MA() and the third MAC result data MAC() and outputs result data of the accumulative addition as second MAC result data MAC_RSTof the result matrix.

2 49 3 64 3 610 2 49 64 620 2 49 3 64 3 610 49 64 620 4 3 2 4 3 3 3 3 630 th th th th th th th th The third processing element PE() receives the 49to 64weight data W()-W() of the third row of the weight matrixfrom the third memory bank BK() and receives the 49to 64vector data V-Vof the vector matrixfrom the global buffer GB. The third processing element PE() performs the multiplication and addition on the 49to 64weight data W()-W() of the third row of the weight matrixand the 49to 64vector data V-Vof the vector matrixto generate fourth multiplication and addition data MA(). The third processing element PE() performs the accumulative addition on the fourth multiplication and addition data MA() and the third MAC result data MAC() and outputs result data of the accumulative addition as third MAC result data MAC_RSTof the result matrix.

3 49 4 64 4 610 3 49 64 620 3 49 4 64 4 610 49 64 620 4 4 3 4 4 3 4 4 630 th th th th th th th th In addition, the fourth processing element PE() receives the 49to 64weight data W()-W() of the fourth row of the weight matrixfrom the fourth memory bank BK() and receives the 49to 64vector data V-Vof the vector matrixfrom the global buffer GB. The fourth processing element PE() performs the multiplication and addition on the 49to 64weight data W()-W() of the fourth row of the weight matrixand the 49to 64vector data V-Vof the vector matrixto generate fourth multiplication and addition data MA(). The fourth processing element PE() performs the accumulative addition on the fourth multiplication and addition data MA() and the third MAC result data MAC() and outputs result data of the accumulative addition as fourth MAC result data MAC_RSTof the result matrix.

22 FIG. 22 FIG. 14 FIG. th illustrates an example of a process in which weight data is stored in a PIM device in a computing system according to an address mapping order defined in an address mapping table. Specifically,illustrates the process in which first to 64weight data of a first row of a weight matrix are stored in a PIM device in the computing system ofaccording to a first address mapping order defined in the address mapping table. Hereinafter, it is assumed that the first address mapping order is “row-column-bank”. In addition, it is assumed that the access granularity of the PIM device is 32 bytes (that is, 256 bits) and each of the weight data includes 16 bits.

22 FIG. 16 FIG. 22 FIG. 430 1 1 64 1 610 420 610 430 1 1 64 1 1 2 64 2 1 3 64 3 1 4 64 4 420 th th th th th Referring to, the processing unittransmits the first to 64weight data W()-W() of the first row of the weight matrixofto the memory controllerin the order in which the columns of the weight matrixincrease. Although not shown in, the processing unitsequentially transmits the first to 64weight data W()-W() of the first row, the first to 64weight data W()-W() of the second row, the first to 64weight data W()-W() of the third row, and the first to 64weight data W()-W() of the fourth row to the memory controller.

420 420 1 1 64 1 1 2 64 2 1 3 64 3 1 4 64 4 0 3 410 420 0 3 410 0 3 410 0 3 410 When the address mapping changing circuit of the memory controlleris in a disabled state, the memory controllerwrites the weight data W()-W(), W()-W(), W()-W(), and W()-W() to the first to fourth memory banks BK()-BK() of the PIM device, respectively, according to the first address mapping order of “row-column-bank”. That is, the memory controllerfirst stores the weight data in the first to fourth memory banks BK()-BK() of the PIM devicein a manner in which the bank address increases, then stores the weight data in the first to fourth memory banks BK()-BK() of the PIM devicein a manner in which the column address increases, and finally stores the weight data in the first to fourth memory banks BK()-BK() of the PIM devicein a manner in which the row address increases.

420 1 1 64 1 610 1 1 16 1 610 0 0 0 420 17 1 32 1 610 0 0 1 420 33 1 48 1 610 0 0 2 420 49 1 64 1 610 0 0 3 th th th nd rd th th th Accordingly, the memory controllerwrites 16 weight data constituting an access granularity among the first to 64weight data W()-W() of the first row of the weight matrix, that is, the first to 16weight data W()-W() of the first row of the weight matrix, to the first row R() and the first column region C() of the first memory bank BK() corresponding to the first row address, the first column address, and the first bank address, respectively. Next, the memory controllerwrites the 17to 32weight data W()-W() of the first row of the weight matrixto the first row R() and the first column region C() of the second memory bank BK() corresponding to the first row address, the first column address, and the second bank address, respectively. Next, the memory controllerwrites the 33to 48weight data W()-W() of the first row of the weight matrixto the first row R() and the first column region C() of the third memory bank BK() corresponding to the first row address, the first column address, and the third bank address, respectively. Finally, the memory controllerwrites the 49to 64weight data W()-W() of the first row of the weight matrixto the first row R() and the first column region C() of the fourth memory bank BK(), corresponding to the first row address, the first column address, and the fourth bank address, respectively.

th th th nd rd th th th 1 1 64 1 610 0 3 420 0 3 420 1 2 16 2 610 0 1 0 420 17 2 32 2 610 0 1 1 420 33 2 48 2 610 0 1 2 420 49 2 64 2 610 0 1 3 22 FIG. In the process of writing the first to 64weight data W()-W() of the first row of the weight matrixto the first to fourth memory banks BK()-BK(), because the bank addresses are all increased from the first bank address to the fourth bank address, the memory controllerwrites the remaining weight data to the first to fourth memory banks BK()-BK() by increasing the bank address again while increasing the column address from the first column address to the second column address. Accordingly, although not shown in, the memory controllerwrites the first to 16weight data W()-W() of the second row of the weight matrixto the first row R() and the second column region C() of the first memory bank BK() corresponding to the first row address, the second column address, and the first bank address, respectively. Next, the memory controllerwrites the 17to 32weight data W()-W() of the second row of the weight matrixto the first row R() and the second column region C() of the second memory bank BK() corresponding to the first row address, the second column address, and the second bank address, respectively. Next, the memory controllerwrites the 33to 48weight data W()-W() of the second row of the weight matrixto the first row R() and the second column region C() of the third memory bank BK() corresponding to the first row address, the second column address, and the third bank address, respectively. Finally, the memory controllerwrites the 49to 64weight data W()-W() of the second row of the weight matrixto the first row R() and the second column region C() of the fourth memory bank BK() corresponding to the first row address, the second column address, and the fourth bank address, respectively.

420 0 3 420 1 3 16 3 610 0 2 0 420 17 3 32 3 610 0 2 1 420 33 3 48 3 610 0 2 2 420 49 3 64 3 610 0 2 3 th th nd rd th th th Next, the memory controllerwrites the remaining weight data to the first to fourth memory banks BK()-BK() by increasing the bank address again while increasing the column address from the second column address to the third column address. Accordingly, the memory controllerwrites the first to 16weight data W()-W() of the third row of the weight matrixto the first row R() and the third column region C() of the first memory bank BK() corresponding to the first row address, the third column address, and the first bank address, respectively. Next, the memory controllerwrites the 17to 32weight data W()-W() of the third row of the weight matrixto the first row R() and the third column region C() of the second memory bank BK() corresponding to the first row address, the third column address, and the second bank address, respectively. Next, the memory controllerwrites the 33to 48weight data W()-W() of the third row of the weight matrixto the first row R() and the third column region C() of the third memory bank BK() corresponding to the first row address, the third column address, and the third bank address, respectively. Finally, the memory controllerwrites the 49to 64weight data W()-W() of the third row of the weight matrixto the first row R() and the third column region C() of the fourth memory bank BK() corresponding to the first row address, the third column address, and the fourth bank address, respectively.

420 0 3 420 1 4 16 4 610 0 3 0 420 17 4 32 4 610 0 3 1 420 33 4 48 4 610 0 3 2 420 49 4 64 4 610 0 3 3 th th nd rd th th th Next, the memory controllerwrites the remaining weight data to the first to fourth memory banks BK()-BK() by increasing the bank address again while increasing the column address from the third column address to the fourth column address. Accordingly, the memory controllerwrites the first to 16weight data W()-W() of the fourth row of the weight matrixto the first row R() and the fourth column region C() of the first memory bank BK() corresponding to the first row address, the fourth column address, and the first bank address, respectively. Next, the memory controllerwrites the 17to 32weight data W()-W() of the fourth row of the weight matrixto the first row R() and the fourth column region C() of the second memory bank BK() corresponding to the first row address, the fourth column address, and the second bank address, respectively. Next, the memory controllerwrites the 33to 48weight data W()-W() of the fourth row of the weight matrixto the first row R() and the fourth column region C() of the third memory bank BK() corresponding to the first row address, the fourth column address, and the third bank address, respectively. Finally, the memory controllerwrites the 49to 64weight data W()-W() of the fourth row of the weight matrixto the first row R() and the fourth column region C() of the fourth memory bank BK() corresponding to the first row address, the fourth column address, and the fourth bank address, respectively.

th th th th 1 1 64 1 0 3 410 1 2 64 2 0 3 410 1 3 64 3 0 3 410 1 4 64 4 0 3 410 0 3 17 FIG. 21 FIG. According to the storing method, the first to 64weight data W()-W() of the first row of the weight matrix are distributed and stored in sixteen weight units in the first to fourth memory banks BK()-BK() of the PIM device. The first to 64weight data W()-W() of the second row of the weight matrix are also distributed and stored in sixteen weight units in the first to fourth memory banks BK()-BK() of the PIM device. The first to 64weight data W()-W() of the third row of the weight matrix are also distributed and stored in sixteen weight units in the first to fourth memory banks BK()-BK() of the PIM device. Additionally, the first to 64weight data W()-W() of the fourth row of the weight matrix are also distributed and stored in sixteen weight units in the first to fourth memory banks BK()-BK() of the PIM device. In this case, as described with reference toto, the MAC operations in the first to fourth processing elements PE()-PE() are not performed in parallel.

23 FIG. 26 FIG. 14 FIG. 22 FIG. 16 FIG. th th th 430 1 1 64 1 610 420 610 toillustrate a process in which first to 64weight data of a first row of a weight matrix and first to 64weight data of a fourth row of the weight matrix are stored in a PIM device according to a second address mapping order in a computing system according to an embodiment of the present disclosure, for example, as shown in. As described with reference to, in the present example, it is assumed that the processing unittransmits the first to 64weight data W()-W() of the first row of the weight matrixofto the memory controllerin the order in which the columns of the weight matrixincrease.

23 FIG. 420 420 1 1 64 1 1 2 64 2 1 3 64 3 1 4 64 4 0 3 410 420 0 3 410 0 3 410 0 3 410 First, referring to, when the address mapping changing circuit of the memory controlleris enabled, the memory controllerwrites the weight data (W()-W(), W()-W(), W()-W(), W()-W()) to the first to fourth memory banks (BK()-BK()) of the PIM deviceaccording to the second address mapping order of “row-bank-column” rather than the first address mapping order of “row-column-bank”. That is, the memory controllerfirst stores the weight data in the first to fourth memory banks BK()-BK()of the PIM devicein a manner in which the column address increases, stores the weight data in the first to fourth memory banks BK()-BK() of the PIM devicein such a manner in which the bank address increases, and finally stores the eight data in the first to fourth memory banks BK()-BK() of the PIM devicein a manner in which the row address increases.

420 1 1 64 1 610 1 1 16 1 610 0 0 0 420 17 1 32 1 610 0 1 0 420 33 1 48 1 610 0 2 0 420 49 1 64 1 610 0 3 0 th th th nd rd th th th Accordingly, the memory controllerwrites sixteen weight data constituting an access granularity among the first to 64weight data W()-W() of the first row of the weight matrix, that is, the first to 16weight data W()-W() of the first row of the weight matrix, to the first row R() and the first column region C() of the first memory bank BK() corresponding to the first row address, the first bank address, and the first column address, respectively. Next, the memory controllerwrites the 17to 32weight data W()-W() of the first row of the weight matrixto the first row R() and the second column region C() of the first memory bank BK() corresponding to the first row address, the first bank address, and the second column address, respectively. Next, the memory controllerwrites the 33to 48weight data W()-W() of the first row of the weight matrixto the first row R() and the third column region C() of the first memory bank BK() corresponding to the first row address, the first bank address, and the third column address, respectively. Finally, the memory controllerwrites the 49to 64weight data W()-W() of the first row of the weight matrixto the first row R() and the fourth column region C() of the first memory bank BK() corresponding to the first row address, the first bank address, and the fourth column address, respectively.

24 FIG. th th th nd rd th th th 1 1 64 1 610 0 420 420 1 2 16 2 610 0 0 1 420 17 2 32 2 610 0 1 1 420 33 2 48 2 610 0 2 1 420 49 1 64 1 610 0 3 1 Next, referring to, in the process of writing the first to 64weight data W()-W() of the first row of the weight matrixto the first memory bank BK(), because the column addresses are all increased from the first column address to the fourth column address, the memory controllerperforms a write operation for the remaining weight data by increasing the column address again while increasing the bank address from the first bank address to the second bank address. Specifically, the memory controllerwrites the first to 16weight data W()-W() of the second row of the weight matrixto the first row R() and the first column region C() of the second memory bank BK() corresponding to the first row address, the second bank address, and the first column address, respectively. Next, the memory controllerwrites the 17to 32weight data W()-W() of the second row of the weight matrixto the first row R() and the second column region C() of the second memory bank BK() corresponding to the first row address, the second bank address, and the second column address, respectively. Next, the memory controllerwrites the 33to 48weight data W()-W() of the second row of the weight matrixto the first row R() and the third column region C() of the second memory bank BK() corresponding to the first row address, the second bank address, and the third column address, respectively. Finally, the memory controllerwrites the 49to 64weight data W()-W() of the second row of the weight matrixto the first row R() and the fourth column region C() of the second memory bank BK() corresponding to the first row address, the second bank address, and the fourth column address, respectively.

25 FIG. th th th nd rd th th th 1 2 64 2 610 1 420 420 1 3 16 3 610 0 0 2 420 17 3 32 3 610 0 1 2 420 33 3 48 3 610 0 2 2 420 49 3 64 3 610 0 3 2 Next, referring to, in the process of writing the first to 64weight data W()-W() of the second row of the weight matrixin the second memory bank BK(), because the column addresses are all increased from the first column address to the fourth column address, the memory controllerperforms a write operation for the remaining weight data by increasing the column address again while increasing the bank address from the second bank address to the third bank address. Specifically, the memory controllerwrites the first to 16weight data W()-W() of the third row of the weight matrixto the first row R() and the first column region C() of the third memory bank BK() corresponding to the first row address, the third bank address, and the first column address, respectively. Next, the memory controllerwrites the 17to 32weight data W()-W() of the third row of the weight matrixto the first row R() and the second column region C() of the third memory bank BK() corresponding to the first row address, the third bank address, and the second column address, respectively. Next, the memory controllerwrites the 33to 48weight data W()-W() of the third row of the weight matrixto the first row R() and the third column region C() of the third memory bank BK() corresponding to the first row address, the third bank address, and the third column address, respectively. Finally, the memory controllerwrites the 49to 64weight data W()-W() of the third row of the weight matrixto the first row R() and the fourth column region C() of the third memory bank BK() corresponding to the first row address, the third bank address, and the fourth column address, respectively.

26 FIG. th th th nd rd th th th 1 3 64 3 610 2 420 420 1 4 16 4 610 0 0 3 420 17 4 32 4 610 0 1 3 420 33 4 48 4 610 0 2 3 420 49 4 64 4 610 0 3 3 Next, referring to, in the process of writing the first to 64weight data W()-W() of the third row of the weight matrixto the third memory bank BK(), because the column addresses are all increased from the first column address to the fourth column address, the memory controllerperforms a write operation for the remaining weight data by increasing the column address again while increasing the bank address from the third bank address to the fourth bank address. Specifically, the memory controllerwrites the first to 16weight data W()-W() of the fourth row of the weight matrixto the first row R() and the first column region C() of the fourth memory bank BK() corresponding to the first row address, the fourth bank address, and the first column address, respectively. Next, the memory controllerwrites the 17to 32weight data W()-W() of the fourth row of the weight matrixto the first row R() and the second column region C() of the fourth memory bank BK() corresponding to the first row address, the fourth bank address, and the second column address, respectively. Next, the memory controllerwrites the 33to 48weight data W()-W() of the fourth row of the weight matrixto the first row R() and the third column region C() of the fourth memory bank BK() corresponding to the first row address, the fourth bank address, and the third column address, respectively. Finally, the memory controllerwrites the 49to 64weight data W()-W() of the fourth row of the weight matrixto the first row R() and the fourth column region C() of the fourth memory bank BK() corresponding to the first row address, the fourth bank address, and the fourth column address, respectively.

23 FIG. 26 FIG. 17 FIG. 21 FIG. 420 610 410 1 1 64 1 610 0 1 2 64 2 1 1 3 64 3 2 1 4 64 4 3 0 3 th th th th As described with reference toto, when the address mapping changing circuit of the memory controlleris enabled and the weight data of the weight matrixis written to the PIM device, the first to 64weight data W()-W() of the first row of the weight matrixare stored in the first memory bank BK(), the first to 64weight data W()-W() of the second row are stored in the second memory bank BK(), the first to 64weight data W()-W() of the third row are stored in the third memory bank BK(), and the first to 64weight data W()-W() of the fourth row are stored in the fourth memory bank BK(). Therefore, in this case, as described with reference toto, the MAC operations in the first to fourth processing elements PE()-PE() are performed in parallel.

A limited number of possible embodiments for the present teachings have been presented above for illustrative purposes. Those of ordinary skill in the art will appreciate that various modifications, additions, and substitutions are possible. While this patent document contains many specifics, these should not be construed as limitations on the scope of the present teachings or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features that are described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable sub-combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub-combination or variation of a sub-combination.