IC Package SoC Edges Recess Structure to Reduce Hybrid Bond Stresses for Molded Chip-on-Wafer

Embodiments described herein relate to semiconductor packaging, more particularly to forming recesses for directly bonded structures.

The current market demand for portable and mobile electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, portable players, gaming, and other mobile devices requires the integration of more performance and features into increasingly smaller spaces. As a result, various multiple-die packaging solutions such as system in package (SiP) and package on package (PoP) have become more popular to meet the demand for higher die/component density devices.

There are many different possibilities for arranging multiple dies in an SiP. For example, vertical integration of die in SiP structures has evolved into 2.5D solutions and 3D solutions. In 2.5D solutions the multiple dies may be flip chip bonded on an interposer that may include through vias as well as fan out wiring. Various 3D solutions exist. In one implementation multiple dies may be stacked on top of one another on an SiP substrate, and connected with off-chip wire bonds or solder bumps. In other traditional 3D solutions hybrid bonding using wafer on wafer (WoW) or chip on wafer (CoW) techniques is utilized. In a WoW solution, the top and bottom device area dimensions are exactly matched, and each layer is restricted to one technology node. In a CoW solution multiple top wafers (chips) can be integrated onto the same bottom wafer with defined area and technology node.

Hybrid bonding including metal-metal and oxide-oxide bonding has generally been adopted as a suitable technology for mass production of high-density input/output (I/O) chips with ultra-small pad pitches. A traditional hybrid bonding sequence includes three main operations including oxide-to-oxide initial bonding at room temperature, heating to close dishing gap, and then further heating to compress metal-to-metal bonds. After the hybrid bonding process there can be follow up processing and device finishing operations depending upon the particular application. Modern integrated circuit (IC) fabrication techniques commonly utilize molding compound such as epoxy molding compound to encapsulate the hybrid bonded dies for various reasons including to protect brittle material from mechanical damage and to smooth out a surface to facilitate downstream wafer-level processing.

Embodiments describe electronic packages and methods in which a recess is formed in a die to mitigate bonding interface stress concentrations related to the direct bonding process. In an embodiment, a recess may be formed in a die (e.g., etching, laser grooving, etc.), where a width of the recess may extend from a perimeter edge to a recessed edge of the die, and a depth of the recess may extend a top surface to a recess floor of the die. In one embodiment, gap fill material fills the recess. In another embodiment, gap fill material does not fill the recess.

As a result of the direct bonding process (e.g., fusion bonding, hybrid bonding, etc.) in which a die is directly bonded to an interposer, for example, it has been observed that the die may have a certain level of intrinsic warpage, where such warpage may create high stress concentrations at the edges and corners of the die. In some instances, the high stress concentrations at the edges and corners of the die cause the bonds formed during the direct bonding process to become unbonded (e.g., delamination). Even in instances where the direct bonding process does not cause delamination, the bonds may be weakened so that subsequent stresses from downstream fabrication processes may ultimately cause delamination. For example, high peeling stress concentrations may form when the bonded structure is trying to bend due to thermal or mechanical loadings, such as with epoxy molding compound (“EMC”) expansion at elevated temperatures. Additionally, high shear stress concentrations may form as the bonded structure tries to shrink or expand together with other packaging and system components (e.g., substrate, printed circuit board, etc.). In embodiments, a recess may be formed in the die in order to shift the high stress concentrations from the edges and corners, where the die may be especially vulnerable to delamination, to an inner region, where the die may be less vulnerable to delamination. In this way, the recess may help to reduce the risk of hybrid bonding or fusion bonding delamination at the edges and corners of the die. In some embodiments, gap fill material (e.g., EMC, etc.) applied during the encapsulation process may fill the recess. In other embodiments, gap fill material applied during the encapsulation process may not fill the recess.

In various embodiments, description is made with reference to figures. However, certain embodiments may be practiced without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details are set forth, such as specific configurations, dimensions and processes, etc., in order to provide a thorough understanding of the embodiments. In other instances, well-known semiconductor processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the embodiments. Reference throughout this specification to “one embodiment” means that a particular feature, structure, configuration, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments.

The terms “to”, “between”, and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer “on” another layer or bonded “to” or in “contact” with another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers.

1 1 FIGS.A-B 1 FIG.A 1 FIG.B 1 FIG.A 100 100 110 130 110 118 120 118 120 120 151 120 Referring now to,is a cross-sectional side view illustration of an electronic package with a die that includes a sloped recess filled with gap fill material in accordance with embodiments;is a cross-sectional side view illustration of an electronic package with a die that includes a substantially flat recess filled with gap fill material in accordance with embodiments. Electronic packagemay include a plurality of dies bonded to an electronic component. For example, in, electronic packageincludes a plurality of dies, such as die, and electronic component. Diemay include semiconductor layerand back-end-of-the-line (“BEOL”) build-up structure. Semiconductor layermay include a bulk silicon substrate, silicon-on-insulator (“SOI”) substrate, etc. and may also include an epitaxial device layer. It should be noted that silicon is an exemplary substrate material and that other semiconductor substrate materials are contemplated. BEOL build-up structuremay include electrical routing as is customary, as well as optional metal sealing structures (e.g., seal rings) to function as both a physical barrier from moisture and impurity ingress, as well as to provide mechanical integrity. In instances where BEOL build-up structureincludes metal sealing structures (e.g., seal rings), such metal sealing structures may be located underneath recess floor. Further, BEOL build-up structuremay include a plurality of metal wiring layers and dielectric layers, referred to as interlayer dielectrics (“ILD”) as is common in microelectronic manufacturing.

1 FIG.A 130 130 138 140 138 140 130 142 138 144 146 104 In further reference to, electronic componentcan be a variety of components such as a second die, an interposer, etc. Electronic componentmay include semiconductor layer(which can also be a bulk layer formed of silicon) and BEOL build-up structure. Alternatively, semiconductor layercan be substituted with another bulk material, such as glass. BEOL build-up structuremay include electrical routing, an optional seal ring, and optional die-to-die routing between other components that may be bonded to electronic component. In addition, a plurality of through vias(e.g., through silicon vias, through glass vias, etc.) can extend through the semiconductor layerand backside layerto make contact with terminals, onto which solder bumps(which can also be solder tips) may be placed.

1 FIG.A 110 130 110 112 114 116 120 130 132 134 136 140 116 136 112 132 Still referring to, diemay be directly bonded to electronic component. Direct bonding may be accomplished using suitable techniques, such as fusion bonding (e.g., dielectric-dielectric bonds) or hybrid bonding (e.g., metal-metal bonds and dielectric-dielectric bonds), where the dielectric materials used by hybrid and/or fusion bonding can be inorganic-based or organic-based materials. For example, diemay include bonding surface, a plurality of metal bond pads, and dielectric bonding layeron BEOL build-up structure. Similarly, electronic componentmay include bonding surface, a plurality of metal bond pads, and dielectric bonding layeron BEOL build-up structure. Dielectric bonding layers,may be formed of an insulating material, such as an oxide (e.g., silicon oxide, silicon nitride, silicon carbon nitride, etc.). Further, bonding surfaces,may be planarized (e.g., chemical mechanical polishing (“CMP”)) to facilitate fusion or hybrid bonding, where such planarized bonding surfaces may be directly bonded to one another at (and diffused across) a bonding interface.

It has been observed that the direct bonding processes (e.g., fusion bonding, hybrid bonding, etc.) may cause residual stress in the BEOL build-up structures and dielectric bonding layers of a die. The residual stress may in turn cause a certain level of intrinsic warpage in the die, which may weaken or even break the bonds formed during the direct bonding process, especially the bonds near the edges or corners of the die where stress concentrations may be high. In addition, it has been observed that subsequent downstream processes may add to the high stress concentrations near the edges or corners of the die. For example, as a result of the encapsulation process, molding compound material (e.g., epoxy molding compound) may cause high peeling stress concentrations near the edges of corners of the die when applying thermal loads to an electronic package due to the mismatched coefficient of thermal expansion between the molding compound material and the die it encapsulates. In embodiments, a recess may be formed in the die to shift the high stress concentrations from the edges and corners of the die to an inner area or region where the direct bonds may be stronger and the die stiffer.

1 FIG.A 1 FIG.A 1 FIG.B 1 FIG.B 1 1 FIGS.A-B 110 150 110 150 150 150 150 110 151 113 160 160 150 132 111 110 160 161 100 In further reference to, dieincludes recessto mitigate bonding interface stress concentrations near the corners and edges of die. Recessmay be formed by any suitable method, such as etching (e.g., wet etch, dry etch, etc.), laser grooving, etc. Further, the shape of recessmay depend on the method used to form the recess. In one example, the sloped shape of recessinmay be formed by laser grooving or wet etching, which is generally isotropic so that the etchants remove material uniformly in all directions. In another example, the L-shape of recessinmay be formed in dieby dry etching, which is highly anisotropic and allows for precise control over the profile of the etch. In addition, for the L-shaped of recess illustrated in, recess flooris substantially flat and orthogonal to perimeter edge. Further, gap fill material(e.g., epoxy molding compound (“EMC”), etc.) may laterally surround the plurality of dies and fill the spaces between dies. In the examples of, gap fill materialfills recess, extending from bonding surfaceto top surfaceof die. In such instances, gap fill materialmay form part of diced edgeof electronic packageafter singulation.

1 FIG.A 150 113 153 113 153 150 110 1 111 151 110 2 151 121 120 2 2 120 Still referring to, recesshas a width, w, that extends from perimeter edgeto recess edge. In some embodiments, the width, w, that extends from perimeter edgeto recess edgeis between 200 μm to 1 mm. Further, recesshas a depth that extends through a partial thickness of die, t, from top surfaceto recess floor, where a remaining thickness of die, t, extends from recess floorto top surfaceof BEOL build-up structure. In some instances, the remaining thickness of the die after forming the recess relates to the risk of delamination. In some embodiments, the remaining thickness, t, is between 30-100 μm. In one example, during reliability risk tests in which electronic packages undergo sub-zero temperature cycles, it has been observed that the delamination risk may be reduced by approximately 14% as compared to conventional methods where the remaining thickness is approximately 100 μm, and reduced by approximately 56% as compared to conventional methods where the remaining thickness is approximately 30 μm. In another example, during assembly risk tests in which electronic packages undergo “reflow” temperature cycles, it has been observed that the delamination risk may be reduced by approximately 64% as compared to conventional methods where the remaining thickness is approximately 100 μm, and reduced by approximately 99.99% as compared to conventional methods where the remaining thickness is approximately 30 μm. It should be noted that the remaining thickness, t, may not be so thin so as to potentially damage the sensitive low-k dielectric layers in BEOL build-up structure.

2 2 FIGS.A-C 2 FIG.A 2 FIG.B 2 FIG.C 2 FIG.A 2 FIG.A 2 2 FIGS.B-C 150 150 110 150 113 153 110 Referring now to,is a schematic top layout view of a first example arrangement of a plurality of dies in accordance with embodiments;is a schematic top layout view of a second example arrangement of a plurality of dies in accordance with embodiments;is a schematic top layout view of a third example arrangement of a plurality of dies in accordance with embodiments. In embodiments, recessmay be formed around a perimeter of each of the plurality of dies, respectively. For example, as illustrated in, recesssurrounds a perimeter of die, where recessmay be defined by perimeter edgeand recess edgeof die. In addition, it is to be appreciated that the particular arrangement of dies inis exemplary and that embodiments are applicable to a variety of other arrangements that may include a different number of dies and dummy features, DMY, such as the example arrangements illustrated in, although other configurations are also contemplated.

3 FIG. 4 4 FIGS.A-D 3 FIG. 4 4 FIGS.A-D 3 FIG. 4 4 FIGS.A-D 4 FIG.B 1 FIG.A 1 FIG.B 4 FIG.C 4010 112 110 132 130 4020 150 110 150 110 110 150 150 151 113 150 113 153 150 110 1 111 110 151 110 2 151 121 120 110 2 4030 160 160 150 4040 160 130 100 160 161 100 Referring now toand,is a flow chart andare schematic cross-sectional side view illustrations of a first method for forming a recess filled with gap fill material in accordance with embodiments. In the interest of clarity and conciseness, the method ofis described concurrently with the illustrations of. At operation, bonding surfaceof diemay be directly bonded (e.g., fusion bonded, hybrid bonded, etc.) to bonding surfaceof electronic component. At operation, recessmay be formed to mitigate the stress concentrations that may have accumulated near the edges or corners of dieduring the direct bonding process. In the example illustrated in, recessis formed by masking a center portion of each of the plurality of diesand wet etching the unmasked portions of each of the plurality of diesto remove the edges and corners. Since wet etching is generally isotropic, the etchants remove material uniformly in all directions and form a sloped recess, similar to the example of. In some embodiments, recessmay be formed by dry etching, which is highly anisotropic and, as a result, may form an L-shaped recess, where recess flooris substantially flat and orthogonal to perimeter edge, similar to the example of. Further, the etching process may be performed to control the width, w, of recess, which extends from perimeter edgeto recess edge. Similarly, the etching process may be performed to control the depth of recess, which extends through a partial thickness of die, t, from top surfaceof dieto recess floor. In embodiments, the remaining thickness of die, t, which extends from recess floorto top surfaceof BEOL build-up structure, may relate to the risk of delamination. In one example, the risk of delamination may be significantly reduced where the remaining thickness of die, t, is approximately 30 μm. At operation, an encapsulation process may be performed where gap fill material(e.g., EMC) may laterally surround the plurality of dies and fill the spaces between dies, where the encapsulation process may then be followed by a grinding operation to expose the dies. In the example of, gap fill materialfills recess. At operation, a cutting operation (e.g., dicing, etc.) may be performed to cut through gap fill materialand electronic componentto singulate electronic package. In such instances, gap fill materialmay form part of diced edgeof electronic package.

5 FIG. 6 6 FIGS.A-D 5 FIG. 6 6 FIGS.A-D 5 FIG. 6 6 FIGS.A-D 1 FIG.A 1 FIG.B 1 FIG.A 6 FIG.C 5010 150 5020 200 150 150 150 150 150 110 1 111 151 110 2 151 121 120 2 5030 130 5040 160 160 150 100 160 161 100 Referring now toand,is a flow chart andare schematic cross-sectional side view illustrations of a second method for forming a recess filled with gap fill material in accordance with embodiments. In the interest of clarity and conciseness, the method ofis described concurrently with the illustrations of. At operation, recessmay be formed by backside laser grooving, etching (e.g., wet etch, dry etch, etc.), etc., before the singulation of the plurality of dies at operation, where such operations may be carried out on carrier wafer. In instances where recessis formed by laser grooving or wet etching, recessmay be sloped, similar to the example of. In instances where recessis formed by dry etching, recessmay be L-shaped, similar to the example of. Further, the formation of recessmay be performed to control its width, w, as well as its depth, which extends from through a partial thickness of die, t, from top surfaceto recess floor. Similar to the example of, the remaining thickness of die, t, which extends from recess floorto top surfaceof BEOL build-up structure, also relates to the risk of delamination, where it has been observed that a remaining thickness, t, of approximately 30 μm may significantly reduce the risk of delamination. At operation, the diced and recessed dies may be directly bonded (e.g., fusion bonded, hybrid bonded, etc.) to electronic component. At operation, an encapsulation process may be performed where gap fill material(e.g., EMC) may laterally surround the plurality of dies and fill the spaces between dies, where the encapsulation process may be followed by a grinding operation to expose the dies. In the example of, gap fill materialfills recess. Further, in a cutting operation (e.g., dicing, etc.) to singulate electronic package, gap fill materialmay form part of diced edgeof electronic package.

7 7 FIGS.A-B 7 FIG.A 7 FIG.B 7 7 FIGS.A-B 1 1 FIGS.A-B 7 7 FIGS.A-B 7 FIG.A 1 FIG.A 1 FIG.A 160 150 100 110 130 110 118 120 120 151 130 138 140 142 138 144 146 104 110 112 114 116 120 130 132 134 136 140 112 110 132 130 Referring now to,is a cross-sectional side view illustration of an electronic package with a die that includes a sloped recess in accordance with embodiments;is a cross-sectional side view illustration of an electronic package with a die that includes a substantially flat recess in accordance with embodiments. The embodiments described inare substantially similar to the embodiments described inwith one difference being that gap fill materialindoes not fill recess. In reference to, electronic packageincludes a plurality of dies, such as die, and electronic component. Diemay include semiconductor layer(e.g., silicon substrate, epitaxial layer, etc.) and BEOL build-up structurewith optional metal sealing structures (e.g., seal rings) as well as a plurality of metal wiring and dielectric layers (e.g., ILD), similar to the example described in. In instances where BEOL build-up structureincludes metal sealing structures (e.g., seal rings), such metal sealing structures may be located underneath recess floor. Further, electronic component(e.g., die, interposer, etc.) may include semiconductor layer(e.g., silicon, glass, etc.), BEOL build-up structure(e.g., electrical routing, seal ring, die-to-die routing, etc.) as well as a plurality of through vias(e.g., through silicon vias, through glass vias, etc.) that extend through the semiconductor layerand backside layerto make contact with terminals, onto which solder bumps(which can also be solder tips) may be placed, similar to the example described in. Further, diemay include a bonding surface, a plurality of metal bond pads, and dielectric bonding layeron BEOL build-up structure. In addition, electronic componentmay include bonding surface, a plurality of metal bond pads, and dielectric bonding layeron BEOL build-up structure. In embodiments, bonding surfaceof diemay be directly bonded (e.g., hybrid bonded, fusion bonded etc.) to bonding surfaceof electronic component.

7 FIG.A 7 FIG.A 1 FIG.A 7 FIG.B 1 FIG.B 1 FIG.A 1 FIG.A 1 1 FIGS.A-B 7 7 FIGS.A-B 1 1 FIGS.A-B 7 7 FIGS.A-B 7 FIG.A 110 150 150 150 113 153 110 1 111 151 110 2 151 121 120 160 160 150 160 132 151 160 161 100 In further reference to, dieincludes recessthat may be formed by any suitable method such as laser grooving, etc., where recessmay be sloped as illustrated in(similar to the example of) or L-shaped as illustrated in the example of(similar to the example of). Further, recesshas a width, w, that extends from perimeter edgeto recessed edge, and a depth that extends through a partial thickness of die, t, from top surfaceto recess floor, similar to the example of. In addition, the remaining thickness of die, t, which extends from recess floorto top surfaceof BEOL build-up structurerelates to the risk of delamination in the same manner described in the example of. Further, similar to the examples illustrated in, the examples illustrated ininclude gap fill materialthat may laterally surround the plurality of dies and fill the spaces between dies. However, in contrast to the examples illustrated in, gap fill materialdoes not fill recess, as illustrated in the examples of. For example, in, gap fill materialextends from bonding surfaceto recess floor. In such instances, gap fill materialmay form part of diced edgeof electronic packageafter singulation.

8 FIG. 9 9 FIGS.A-C 8 FIG. 9 9 FIGS.A-C 8 FIG. 9 9 FIGS.A-C 1 1 FIGS.A-B 7 7 FIG.A-B 9 FIG.B 1 1 FIGS.A-B 9 FIG.B 1 1 FIGS.A-B 1 1 FIGS.A-B 8010 112 110 132 130 8020 160 8030 150 160 160 132 130 151 160 161 100 150 113 153 110 1 111 151 110 2 120 Referring now toand,is a flow chart andare schematic cross-sectional side view illustrations of a method for forming a recess in accordance with embodiments. In the interest of clarity and conciseness, the method ofis described concurrently with the illustrations of. At operation, bonding surfaceof diemay be directly bonded (e.g., fusion bonded, hybrid bonded, etc.) to bonding surfaceof electronic component. At operation, an encapsulation process may be performed where gap fill material(e.g., EMC) may laterally surround the plurality of dies and fill the spaces between dies, which can be followed by a grinding operation to expose the dies. Unlike the embodiments described inin which the recesses are formed before encapsulation, the recesses in the embodiments described inare formed after encapsulation. As such, at operation, a laser grooving operation may be performed to simultaneously form recessand to remove gap fill materialto create the “empty” recess illustrated in, as opposed to the “filled” recess illustrated in. In further reference to, gap fill materialextends vertically from bonding surfaceof electronic componentto recess floor, where gap fill materialmay form part of diced edgeof electronic packageafter singulation. Similar to the embodiments described in, recesshas a width, w, that extends from perimeter edgeto recess edge, as well as a depth that extends from through a partial thickness of die, t, from top surfaceto recess floor. Also, similar to the embodiments described in, the remaining thickness of die, t, relates to the risk of delamination, where it has been observed that a remaining thickness of approximately 30 μm may significantly reduce the risk of delamination while maintaining the integrity of BEOL build-up structure.

In utilizing the various aspects of the embodiments, it would become apparent to one skilled in the art that combinations or variations of the above embodiments are possible for forming a recess for directly bonded structures. Although the embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that the appended claims are not necessarily limited to the specific features or acts described. The specific features and acts disclosed are instead to be understood as embodiments of the claims useful for illustration.