Chip with Metal-Oxide-Metal Capacitor

This application claims priority to Chinese patent application No. 202411180355.3, filed on Aug. 26, 2024, the disclosure of which is incorporated herein by reference in its entirety.

The present application relates to semiconductor technology, and in particular, to a chip with a metal-oxide-metal (MOM) capacitor.

An OLED (organic light emitting diode) as a third generation of display technology is of a current injection composite light emitting type with main advantages of high brightness, high contrast, large viewing angle, high response speed, low operating voltage, strong adaptability, high energy conversion efficiency, simple production process and the like. Due to huge technical advantages and application prospects of the OLED, the OLED has received extensive attention from bottom academia and industry.

1 a FIG. 1 c FIG. 1 a FIG. 1 b FIG. 1 c FIG. The OLED is of a current drive type. The higher a current of the OLED is, the greater the brightness is. However, the current will decay over time, resulting in a corresponding decrease in brightness, as shown into.shows a current density-brightness curve of a white OLED, wherein higher the current is, the greater the brightness is.shows a degradation curve of a current of a white OLED over time wherein a drive current decreases over time.shows a conventional drive current compensation circuit of a white OLED, wherein a capacitor C will use a metal-oxide-metal (MOM) capacitor. This is mainly due to the presence of some leakage in the circuit over time. This is mainly due to the presence of some leakage in the drive circuit over time.

2 a FIG. 2 b FIG. 151 152 151 152 Generally, the problem of the corresponding decrease of the brightness corresponding to the current of the OLED over time due to some leakage in the drive circuit over time is solved by employing the compensation circuit. However, since the compensation circuit uses a capacitor, resulting in a certain difference in itself, the compensation circuit can only solve the problem caused by some leakage. With the demand for miniaturization, a capacitor device in the compensation circuit in the drive circuit extensively uses the metal-oxide-metal capacitor to save a space. Such a metal-oxide-metal (MOM) capacitor is formed by using the thickness of metal layers and the distance between the metal layers. As shown inwhich is a schematic diagram of a stack of a plurality of layers of metal, a plurality of left-finger metal stripsand a plurality of right-finger metal stripsof the same layer of metal are interdigitated. The plurality of left-finger metal stripsare shorted and the plurality of right-finger metal stripsare connected to a substrate.is a schematic diagram of the same layer of metal-oxide-metal capacitor. Ctotal=n*Cm*f, n is a number of layers of metal, and f is a number of fingers of each layer.

3 a FIG. 3 b FIG. 1 2 Generally, due to lower density of such a metal-oxide-metal (MOM) capacitor, a larger area (more than 5 μm*5 μm for a single size) is required. For an area below the metal-oxide-metal (MOM) capacitor, in order to ensure the chemical-mechanical grinding uniformity of an active area and a metal gate, a dummy pattern area is inserted in the active area and the metal gate, and a low end of the metal-oxide-metal (MOM) capacitor of the dummy pattern area is generally connected to a P-type substrate under the dummy pattern area. The dummy pattern area of the active area under the metal-oxide-metal (MOM) capacitor may have certain parasitic capacitors at high voltage. At present, in a 28 nm display driver, the metal-oxide-metal (MOM) capacitor works in a medium-voltage area (MV) and the corresponding gate silicon oxide thickness of the metal-oxide-metal (MOM) capacitor is between 18 nm and 22 nm. There will be parasitic capacitors when a voltage is applied to a first layer of metal of the metal-oxide-metal capacitor, which affects the uniformity of the capacitor having the same circuit function, and thus affects the performance of the drive current compensation circuit.shows situation of a dummy pattern area of an existing metal capacitor area, with each area with the same requirements for functions and capacitances being different due to the difference in surrounding conditions. As shown in, parasitic capacitors (Cp, Cp) will be greatly different, and the non-uniformity of capacitances of the parasitic capacitors will lead to some degradation of the performance of the OLED (organic light emitting diode).

A technical problem to be solved by the present application is to provide a chip with a metal-oxide-metal (MOM) capacitor. A metal capacitor in the chip has a good repeatability. Moreover, the uniformity of parasitic capacitors when a high voltage is applied to the metal-oxide-metal (MOM) capacitor is improved.

To solve the technical problem mentioned above, the present application provides the chip with the metal-oxide-metal (MOM) capacitor, including at least two metal capacitor areas with the same requirements for functions and capacitances;

12 13 14 15 11 11 12 13 14 14 13 14 15 for each metal capacitor area, a gate oxide layer, a gate metal layer, a high-resistance layerand a capacitor metal layerare sequentially formed on an active areaof a substrate from bottom to top; vertical projections of the active area, the gate oxide layerand the gate metal layerare located within a vertical projection of the high-resistance layer; and insulating dielectric layers are formed between the high-resistance layerand the gate metal layerand between the high-resistance layerand the capacitor metal layer, respectively;

14 13 the resistivity of the high-resistance layeris greater than that of the gate metal layer;

14 15 the resistivity of the high-resistance layeris greater than that of the capacitor metal layer.

12 Preferably, the gate oxide layeris silicon oxide.

Preferably, the chip is an OLED driver chip.

Preferably, the OLED driver chip is fabricated by using a 28 nm high-voltage process platform.

15 Preferably, the capacitor metal layerincludes at least one layer of metal stacked sequentially from top to bottom and insulated from each other;

15 151 152 each layer of metal of the capacitor metal layerincludes a plurality of left-finger metal stripsand a plurality of right-finger metal strips; and

151 152 151 152 the plurality of left-finger metal stripsand the plurality of right-finger metal stripsare interdigitated, left ends of the left-finger metal stripsare shorted together, and right ends of the right-finger metal stripsare shorted together for connecting the substrate.

15 Preferably, the capacitor metal layersof the metal capacitor areas having the same capacitances are connected in parallel.

13 Preferably, the gate metal layeris aluminum.

13 Preferably, the capacitor metal layeris copper.

14 Preferably, the high-resistance layeris polysilicon.

14 Preferably, the high-resistance layeris P-doped polysilicon.

14 Preferably, the high-resistance layeris TiN.

14 Preferably, the high-resistance layeris aluminum-doped TiN.

11 12 13 14 15 15 2 5 FIG. In the chip with the metal-oxide-metal capacitor of the present application, each metal capacitor area with the same requirements for functions and capacitances, as a metal capacitor unit, has the active area, the gate silicon oxide layer, the gate metal layer, the high-resistance layerand the capacitor metal layerwith the same layout structure. In this way, the repeatability of a metal capacitor in the chip can be improved. Moreover, as shown in, by replacing an original irregular dummy pattern with the active area, the gate area and the high-resistance area which are regular, the metal capacitor area with the same requirements for functions and capacitances can invoke a dummy pattern area with the same requirements for functions and capacitances, which ensures the process uniformity, and can meet the process requirements of the active area and the gate area. Moreover, the physically floating high-resistance area (HiR) can shield unstable parasitic capacitors from the capacitor metal layerto the substrate, such that the dummy pattern areas between the metal-oxide-metal capacitor and the active area have the same parasitic capacitors of Cp′ at high voltage, and the uniformity of the parasitic capacitors when a high voltage is applied to the metal-oxide-metal capacitor is improved.

11 12 13 14 15 151 152 . active area;. gate oxide layer;. gate metal layer;. high-resistance layer;. capacitor metal layer;. left-finger metal strip; and. right-finger metal strip.

Technical solutions in embodiments of the present application may be described clearly and completely below in conjunction with figures in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments. The scope of protection of the present application encompasses all other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without the exercise of inventive effort.

Terms such as “first”, “second”, etc. in the present application do not indicate any order, number, or importance, but are only to distinguish different constituent parts. The phasing such as “including”, “comprising”, etc. means that an element or object preceded by the phasing encompasses an element or object and equivalents thereof listed below the phasing, but does not exclude other elements or objects. The expression such as “connected”, “coupled”, etc. is not limited to physical or mechanical connections, but may include direct or indirect electrical connections. Terms such as “upper”, “lower”, “left”, “right”, etc. are used only to indicate relative positional relations. When an absolute position of a described object is changed, the relative positional relation may be changed accordingly.

It should be noted that the embodiments of the present application and features in the embodiments may be combined with each other without contradictory.

A chip with a metal-oxide-metal capacitor includes at least two metal capacitor areas with the same requirements for functions and capacitances.

4 FIG. 12 13 14 15 11 11 12 13 14 14 13 14 15 As shown in, for each metal capacitor area, a gate oxide layer, a gate metal layer, a high-resistance layerand a capacitor metal layerare sequentially formed on an active areaof a substrate from bottom to top; vertical projections of the active area, the gate oxide layerand the gate metal layerare located within a vertical projection of the high-resistance layer; and insulating medium layers are formed between the high-resistance layerand the gate metal layerand between the high-resistance layerand the capacitor metal layer.

14 13 The resistivity of the high-resistance layeris greater than that of the gate metal layer.

14 15 The resistivity of the high-resistance layeris greater than that of the capacitor metal layer.

12 Preferably, the gate oxide layeris silicon oxide.

11 12 13 14 15 15 2 5 FIG. In the chip with the metal-oxide-metal capacitor of the embodiment I, each metal capacitor area with the same requirements for functions and capacitances, as a metal capacitor unit, has the active area, the gate silicon oxide layer, the gate metal layer, the high-resistance layerand the capacitor metal layerwith the same layout structure. In this way, the repeatability of a metal capacitor in the chip can be improved. Moreover, as shown in, by replacing an original irregular dummy pattern with the active area, the gate area and the high-resistance area which are regular, the metal capacitor area with the same requirements for functions and capacitances can invoke a dummy pattern area with the same requirements for functions and capacitances, which ensures the process uniformity, and can meet the process requirements of the active area and the gate area. Moreover, the physically floating high-resistance area (HiR) can shield unstable parasitic capacitors from the capacitor metal layerto the substrate, such that the dummy pattern areas between the metal-oxide-metal capacitor and the active area have the same parasitic capacitors of Cp′ at high voltage, and the uniformity of the parasitic capacitors when a high voltage is applied to the metal-oxide-metal capacitor is improved.

Based on the embodiment I, the chip with the metal-oxide-metal capacitor is an OLED driver chip.

Preferably, the OLED driver chip is fabricated by using a 28 nm high-voltage (HV) (greater than 12V) process platform.

28 hv With the advancement of a process node of a logic device, an OLED mass production process node most advanced at present is combined with a 28 nm high-voltage (HV) metal gate (metal gate) technology.

The chip with the metal-oxide-metal capacitor of the embodiment II can solve the problem of degradation of the performance of the OLED driver chip due to larger parasitic capacitors and non-uniformity of capacitances of the parasitic capacitors of the metal capacitor area with the same requirements for functions and capacitances for the drive current compensation in a 28 nm display driver circuit.

15 Based on the chip with the metal-oxide-metal capacitor of the embodiment I, the capacitor metal layerincludes at least one layer of metal stacked sequentially from top to bottom and insulated from each other.

15 151 152 Each layer of metal of the capacitor metal layerincludes a plurality of left-finger metal stripsand a plurality of right-finger metal strips.

151 152 151 152 The plurality of left-finger metal stripsand the plurality of right-finger metal stripsare interdigitated, left ends of the left-finger metal stripsare shorted together, and right ends of the right-finger metal stripsare shorted together for connecting the substrate.

15 Preferably, the capacitor metal layersof the metal capacitor areas having the same capacitances are connected in parallel.

13 Preferably, the gate metal layeris aluminum.

13 Preferably, the capacitor metal layeris copper.

14 Preferably, the high-resistance layeris polysilicon.

14 Preferably, the high-resistance layeris P-doped polysilicon.

14 Preferably, the high-resistance layeris TiN.

14 Preferably, the high-resistance layeris aluminum-doped TiN.

The embodiments described above are only preferred embodiments of the present application and are not intended to limit the present application. The scope of protection of the present application shall include any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application.