Display Device and Method of Manufacturing Display Device

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2024-140912, filed Aug. 22, 2024, the entire contents of which are incorporated herein by reference.

Embodiments described herein relate generally to a display device and a manufacturing method thereof.

Recently, display devices with organic light-emitting diodes (OLED) applied thereto as display elements have been put into practical use. In this type of display devices, a technique for improving the yield is required.

In general, according to one embodiment, a display device includes a substrate having a display area for displaying images, an insulating layer provided above the substrate, and a display element including a first electrode provided above the insulating layer in the display area. The first electrode includes a transparent first conductive oxide layer and a transparent second conductive oxide layer covering the first conductive oxide layer. Further, a transmittance of the second conductive oxide layer is lower than that of the first conductive oxide layer.

Furthermore, in general, according to one embodiment, a manufacturing method of a display device includes forming an insulating layer above a substrate and forming a first electrode of a display element above the insulating layer. The first electrode includes a transparent first conductive oxide layer and a transparent second conductive oxide layer covering the first conductive oxide layer. Furthermore, formation of the first electrode includes forming the first conductive oxide layer by performing a first sputtering in an atmosphere containing no water vapor and forming the second conductive oxide layer by performing a second sputtering in an atmosphere containing water vapor.

These configuration of the display device and manufacturing method of the same can improve the yield of the display device.

Embodiments will be described hereinafter with reference to the accompanying drawings.

The disclosure is merely an example, and proper changes in keeping with the spirit of the invention, which are easily conceivable by a person of ordinary skill in the art, come within the scope of the invention as a matter of course. In addition, in some cases, in order to make the description clearer, the widths, thicknesses, shapes and the like, of the respective parts are illustrated schematically in the drawings, rather than as an accurate representation of what is implemented. However, such schematic illustration is merely exemplary, and in no way restricts the interpretation of the invention. In addition, in the specification and drawings, structural elements which function in the same or a similar manner to those described in connection with preceding drawings are denoted by like reference numbers, detailed description thereof being omitted unless necessary.

In the figures, an X-axis, a Y-axis, and a Z-axis orthogonal to each other are described to facilitate understanding as needed. A direction parallel to the X-axis is referred to as an X-direction. A direction parallel to the Y-axis is referred to as a Y-direction. A direction parallel to the Z-axis is referred to as a Z-direction. The Z-direction is the normal direction of a plane including the X-direction and the Y-direction. When various elements are viewed parallel to the Z-direction, the appearance is defined as a plan view.

The display device of each embodiment is an organic electroluminescent display device comprising an organic light emitting diode (OLED) as a display element, and could be mounted on various types of electronic devices such as a television, a personal computer, a vehicle-mounted device, a tablet, a smartphone, a mobile phone, and a wearable terminal.

1 FIG. 10 10 10 is a view showing a configuration example of a display device DSP of the first embodiment. The display device DSP comprises an insulating substrate. The substratehas a display area DA for displaying an image and a surrounding area SA around the display area DA. The substratemay be glass or a resinous film having flexibility.

10 10 In the present embodiment, the substrateand the display area DA have a circular shape in plan view. The shape of each of the substrateand the display area DA in plan view is not limited to a circular shape and may be another shape such as a rectangular shape, a square shape, or an elliptic shape.

1 2 3 1 2 3 1 2 3 The display area DA comprises a plurality of pixels PX arranged in a matrix in the X-direction and the Y-direction. Each pixel PX includes a plurality of subpixels SP that display different colors. The present embodiment assumes a case where each pixel PX includes a blue subpixel SP, a green subpixel SP, and a red subpixel SP. Each pixel PX may include a subpixel SP that exhibits another color such as white in addition to the subpixels SP, SP, and SPor instead of one of the subpixels SP, SP, and SP.

The display device DSP further comprises a terminal portion T provided in the surrounding area SA. For example, a flexible printed circuit board, which applies voltage and signals for driving the display device DSP is connected to the terminal portion T.

1 1 1 2 3 4 2 3 The subpixel SP comprises a pixel circuitand a display element DE driven by the pixel circuit. The pixel circuitcomprises a pixel switch, a drive transistor, and a capacitor. The pixel switchand the drive transistorare, for example, switching elements constituted by thin-film transistors.

1 1 1 FIG. The display area DA has a plurality of scanning lines GL supplying the pixel circuitof each subpixel SP with scanning signals, a plurality of signal lines SL supplying the pixel circuitof each subpixel SP with video signals, and a plurality of power lines PL. In the example of, the scanning lines GL and the power lines PL extend in the X-direction, and the signal lines SL extend in the Y-direction.

2 2 3 4 3 4 A gate electrode of the pixel switchis connected to the scanning line GL. One of a source electrode and a drain electrode of the pixel switchis connected to the signal line SL. The other is connected to a gate electrode of the drive transistorand the capacitor. In the drive transistor, one of the source electrode and the drain electrode is connected to the power line PL and the capacitor. The other is connected to a display element DE.

1 1 The configuration of the pixel circuitis not limited to the example of the figure. For example, the pixel circuitmay comprise more thin-film transistors and capacitors.

2 FIG. 2 FIG. 1 2 3 1 3 1 3 2 is a schematic plan view showing an example of the layout of the subpixels SP, SP, and SPconstituting one pixel PX. In the example of, the subpixels SPand SPare arranged in the Y-direction. Each of the subpixels SPand SPis adjacent to the subpixel SPin the X-direction.

1 2 3 1 3 2 1 2 3 2 FIG. When the subpixels SP, SP, and SPare arranged in this layout, in the display area DA, a column in which the subpixels SPand SPare alternately arranged in the Y-direction and a column in which the plurality of subpixels SPare repeatedly arranged in the Y-direction are formed. These columns are alternately arranged in the X-direction. The layout of the subpixels SP, SP, and SPis not limited to the example of.

5 5 1 2 3 1 2 3 1 3 2 1 3 1 2 3 2 FIG. A rib layeris provided in the display area DA. The rib layerhas pixel apertures AP, AP, and APin the respective subpixels SP, SP, and SP. In the example of, the pixel apertures APand APare rectangles having the same planar size. In contrast, the pixel aperture APis a rectangle that is elongated in the Y-direction more than the pixel apertures APand APare. The shapes of the pixel aperture AP, AP, and APare not limited to this example.

1 1 1 1 1 2 2 2 2 2 3 3 3 3 3 The subpixel SPcomprises a lower electrode LE, an upper electrode UE, and an organic layer OR, which overlap the pixel aperture AP. The subpixel SPcomprises a lower electrode LE, an upper electrode UE, and an organic layer OR, which overlap the pixel aperture AP. The subpixel SPcomprises a lower electrode LE, an upper electrode UE, and an organic layer OR, which overlap the pixel aperture AP.

1 2 3 1 2 3 In the present embodiment, the lower electrodes LE, LE, and LEare examples of the first electrode. The upper electrodes UE, UE, and UEare examples of the second electrode.

1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 1 2 3 5 1 2 3 Portions that overlap the pixel aperture APof the lower electrode LE, the upper electrode UE, and the organic layer ORconstitute a display element DEof the subpixel SP. Portions that overlap the pixel aperture APof the lower electrode LE, the upper electrode UE, and the organic layer ORconstitute a display element DEof the subpixel SP. Portions that overlap the pixel aperture APof the lower electrode LE, the upper electrode UE, and the organic layer ORconstitute a display element DEof the subpixel SP. Each of the display elements DE, DE, and DEmay further include a cap layer to be described later. The rib layersurrounds each of the display elements DE, DE, and DE.

6 5 6 1 2 3 6 5 5 6 1 2 3 A conductive partitionis provided above the rib layer. The partitionfunctions as lines which apply common voltage to the upper electrodes UE, UE, and UE. The partitionentirely overlaps the rib layerand has the same planar shape as that of the rib layer. The partitionsurrounds each of the pixel apertures AP, AP, and AP.

3 FIG. 2 FIG. 1 FIG. 11 10 11 1 11 12 12 11 is a schematic cross-sectional view of the display device DSP along the III-III line of. A circuit layeris provided on the substratedescribed above. The circuit layerincludes various circuits and lines such as the pixel circuit, the scanning lines GL, the signal lines SL, and the power lines PL shown in. The circuit layeris covered with an organic insulating layer. The organic insulating layerfunctions as a planarization film, which planarizes irregularities formed by the circuit layer.

1 2 3 12 5 12 1 2 3 1 2 3 5 1 2 3 1 11 12 3 FIG. The lower electrodes LE, LE, and LEare provided on the organic insulating layer. The rib layeris provided on the organic insulating layerand the lower electrodes LE, LE, and LE. End portions of the lower electrodes LE, LE, and LEare covered with the rib layer. Although not shown in the section of, the lower electrodes LE, LEand LEare connected to the respective pixel circuitsof the circuit layerthrough respective contact holes provided in the organic insulating layer.

6 61 5 62 61 62 61 6 62 61 The partitionincludes a conductive lower portionprovided on the rib layerand an upper portionprovided on the lower portion. The upper portionhas a width greater than that of the lower portion. That is, the partitionhas an overhang shape in which both end portions of the upper portionprotrude relative to the side surfaces of the lower portion.

3 FIG. 3 FIG. 61 63 5 64 63 63 64 63 64 In the example of, the lower portionhas a bottom layerprovided on the rib layer, and a stem layerprovided on the bottom layer. For example, the bottom layeris formed to be thinner than the stem layer. In the example of, both end portions of the bottom layerprotrude relative to the side surfaces of the stem layer.

3 FIG. 62 65 66 65 66 65 65 66 In the example of, the upper portioncomprises a first top layerand a second top layerprovided on the first top layer. For example, the width of the second top layeris slightly less than that of the first top layer. The configuration is not limited to this example. The first top layerand the second top layermay have the same width.

1 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 1 2 3 61 6 The organic layer ORcovers the lower electrode LEthrough the pixel aperture AP. The upper electrode UEcovers the organic layer ORand faces the lower electrode LE. The organic layer ORcovers the lower electrode LEthrough the pixel aperture AP. The upper electrode UEcovers the organic layer ORand faces the lower electrode LE. The organic layer ORcovers the lower electrode LEthrough the pixel aperture AP. The upper electrode UEcovers the organic layer ORand faces the lower electrode LE. The upper electrodes UE, UE, and UEcontact the lower portionsof the partition.

1 1 1 2 2 2 3 3 3 1 2 3 1 2 3 The display element DEincludes a cap layer CPcovering the upper electrode UE. The display element DEincludes a cap layer CPcovering the upper electrode UE. The display element DEincludes a cap layer CPcovering the upper electrode UE. The cap layers CP, CP, and CPfunction as optical adjustment layers which improve the extraction efficiency of the light emitted from the respective organic layers OR, OR, and OR.

1 1 1 1 2 2 2 2 3 3 3 3 In the following explanation, a multilayer body including the organic layer OR, the upper electrode UE, and the cap layer CPis called a stacked film FL. A multilayer body including the organic layer OR, the upper electrode UE, and the cap layer CPis called a stacked film FL. A multilayer body including the organic layer OR, the upper electrode UE, and the cap layer CPis called a stacked film FL.

11 12 13 1 2 3 11 1 6 1 12 2 6 2 13 3 6 3 Sealing layers SE, SE, and SEare provided in the respective subpixels SP, SPand SP. The sealing layer SEcontinuously covers the display element DEand the partitionaround the display element DE. The sealing layer SEcontinuously covers the display element DEand the partitionaround the display element DE. The sealing layer SEcontinuously covers the display element DEand the partitionaround the display element DE.

3 FIG. 11 6 1 2 12 6 11 6 1 3 13 6 11 12 13 6 In the example of, the sealing layer SElocated on the partitionbetween the subpixels SPand SPis spaced apart from the sealing layer SElocated on this partition. The sealing layer SElocated on the partitionbetween the subpixels SPand SPis spaced apart from the sealing layer SElocated on this partition. Any two of the sealing layers SE, SE, and SEmay contact each other above the partition.

11 12 13 62 6 1 2 3 For example, a gap is formed between the respective sealing layers SE, SE, and SEand the upper portionof the partition. The stacked films FL, FL, and FLmay be provided in at least part of these gaps.

11 12 13 1 1 2 2 2 1 2 2 The sealing layers SE, SE, and SEare covered with a resin layer RS. The resin layer RSis covered with the sealing layer SE. The sealing layer SEis covered with a resin layer RS. The resin layers RSand RSand the sealing layer SEare continuously provided in at least the entire display area DA and partly extend in the surrounding area SA as well.

2 2 A cover member such as a polarizer, a touch panel, a protective film, or a cover glass may be further provided above the resin layer RS. This cover member may be attached to the resin layer RSvia, for example, an adhesive layer such as an optical clear adhesive (OCA).

2 1 2 3 1 2 3 The electrodes that constitute the touch panel may be provided on the sealing layer SE. Further, color filters respectively corresponding to the colors of the subpixels SP, SP, and SPmay be respectively provided above the display elements DE, DE, and DE.

12 5 11 12 13 2 5 11 12 13 2 1 2 The organic insulating layeris formed of an organic insulating material such as a polyimide. Each of the rib layerand the sealing layers SE, SE, SE, and SEis formed of an inorganic insulating material such as a silicon nitride (SiNx), a silicon oxide (SiOx), or a silicon oxynitride (SiON). For example, the rib layeris formed of a silicon oxynitride, and each of the sealing layers SE, SE, SE, and SEis formed of a silicon nitride. Each of the resin layers RSand RSis formed of, for example, a resinous material (an organic insulating material) such as an epoxy resin or an acrylic resin.

1 2 3 1 2 3 1 2 3 The upper electrodes UE, UE, and UEare formed of, for example, a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE, LE, and LEcorrespond to anodes, and the upper electrodes UE, UE, and UEcorrespond to cathodes.

1 2 3 1 2 3 1 2 3 Each of the organic layers OR, OR, and ORis composed of a plurality of thin films including light emitting layers. In one example, the organic layers OR, OR, and ORhave a structure in which a hole-injection layer, a hole-transport layer, an electron blocking layer, a light emitting layer, a hole blocking layer, an electron-transport layer, and an electron-injection layer are stacked in this order in the Z-direction. The organic layers OR, OR, and OReach may have other structures such as a tandem structure including a plurality of light emitting layers.

1 2 3 1 2 3 11 12 13 1 2 3 Each of the cap layers CP, CP, and CPhas, for example, a multilayer structure in which a plurality of transparent layers are stacked. These transparent layers may include a layer formed of an inorganic material and a layer formed of an organic material. The transparent layers have refractive indices different from each other. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE, UE, and UEand the refractive indices of the sealing layers SE, SE, and SE. At least one of the cap layers CP, CP, and CPmay be omitted.

63 64 6 63 64 64 For example, each of the bottom layerand the stem layerof the partitionis composed of a metal material. For the metal material of the bottom layer, for example, molybdenum, titanium, a titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), or a molybdenum-niobium alloy (MoNb) can be used. For the metal material of the stem layer, for example, aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), or an aluminum-silicon alloy (AlSi) can be used. The stem layermay be composed of an insulating material.

65 6 66 6 65 66 62 62 The first top layerof the partitionis formed of, for example, a metal material. The second top layerof the partitionis formed of, for example, a conductive oxide. For the metal material forming the first top layer, for example, titanium, a titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy can be used. For the conductive oxide forming the second top layer, for example, an ITO (Indium Tin Oxide), an IZO (Indium Zinc Oxide), or an IGZO (Indium Gallium Zinc Oxide) may be used. The upper portionmay comprise three or more layers or may consist of a single layer. The upper portionmay further include a layer formed of an insulating material.

6 1 2 3 61 1 2 3 1 1 2 3 Common voltage is applied to the partition. This common voltage is applied to each of the upper electrodes UE, UE, and UEthat contact the lower portions. Pixel voltages according to the video signals of the signal lines SL are applied to the lower electrodes LE, LE, and LEthrough the respective pixel circuitsprovided in the subpixels SP, SP, and SP.

1 2 3 1 1 1 2 2 2 3 3 3 The organic layers OR, OR, and ORemit light in response to the application of a voltage. Specifically, when a potential difference is formed between the lower electrode LEand the upper electrode UE, the light emitting layer of the organic layer ORemits light in a blue wavelength range. When a potential difference is formed between the lower electrode LEand the upper electrode UE, the light emitting layer of the organic layer ORemits light in a green wavelength range. When a potential difference is formed between the lower electrode LEand the upper electrode UE, the light emitting layer of the organic layer ORemits light in a red wavelength range.

1 2 3 1 2 3 1 2 3 As another example, the light emitting layers of the organic layers OR, OR, and ORmay emit light in the same color (for example, white). In this case, the display device DSP may comprise a color filter that converts the light emitted from the light emitting layers into light of colors corresponding to those of the subpixels SP, SP, and SP. In addition, the display device DSP may comprise a layer including quantum dots that are excited by the light emitted from the light emitting layers to generate the light of colors corresponding to those of the subpixels SP, SP, and SP.

4 FIG. 3 FIG. 1 2 3 1 2 3 5 is a schematic cross-sectional view showing an example of a configuration applicable to the lower electrodes LE, LE, and LE. This figure shows the vicinity of end portions E of the lower electrodes LE, LE, and LE. The end portions E are covered with the rib layer(refer to).

1 2 3 1 2 3 In the present embodiment, the lower electrodes LE, LE, and LEcomprise a reflective layer RF, a conductive oxide layer CL(the first conductive oxide layer), a conductive oxide layer CL(the second conductive oxide layer), and a conductive oxide layer CL(the third conductive oxide layer).

1 1 2 1 3 2 The conductive oxide layer CLcovers an upper surface Fof the reflective layer RF. The conductive oxide layer CLcovers the conductive oxide layer CL. The conductive oxide layer CLcovers a lower surface Fof the reflective layer RF.

1 2 3 1 2 3 The present embodiment assumes cases where the reflective layer RF is formed by silver (Ag) and the conductive oxide layers CL, CL, and CLare formed by an ITO. As other examples, the reflective layer RF may be formed by a metal material that differs from silver and has excellent reflectivity, or may have a multi-layer structure of metal materials. Further, the conductive oxide layers CL, CL, and CLmay be formed by transparent conductive oxides other than an ITO, such as an IZO and an IGZO.

1 2 3 1 2 1 2 3 1 2 1 2 3 3 1 2 3 12 The reflective layer RF reflects the light emitted from the organic layers OR, OR, and ORupward. The conductive oxide layers CLand CLsuppress oxidation of the reflective layer RF and improve the work function of the lower electrodes LE, LE, and LE. Further, the conductive oxide layers CLand CLprotect the reflective layer RF from etching performed after the formation of the lower electrodes LE, LE, and LEin the manufacturing of the display device DSP. The conductive oxide layer CLimproves the adhesion between the lower electrodes LE, LE, and LEand the organic insulating layer.

1 1 2 2 3 3 1 2 3 1 2 3 1 2 3 4 FIG. The end portions E include an end portion Er of the reflective layer RF, an end portion Ecof the conductive oxide layer CL, an end portion Ecof the conductive oxide layer CL, and an end portion Ecof the conductive oxide layer CL. In the example shown in, the end portions Er, Ec, Ec, and Ecalign. That the end portions Er, Ec, Ec, and Ecalign includes not only cases where these end portions align to the extent that they form a single plane but also cases where they are slightly offset but align compared to the overall size of the lower electrodes LE, LE, and LE.

1 2 3 1 2 3 1 2 3 1 2 3 2 1 1 2 3 1 3 1 3 2 2 3 1 3 4 FIG. The reflective layer RF, the conductive oxide layer CL, the conductive oxide layer CL, and the conductive oxide layer CLhave respective thicknesses Tr, T, T, and T. In the example shown in, the thickness Tr is greater than each of the thicknesses T, T, and T(Tr>T, T, and T). Further, the thickness Tis greater than the thickness T(T<T). The thickness Tis, for example, equivalent to the thickness T(T=T). In this case, the thickness Tis smaller than the thickness T(T>T). The thicknesses Tand Tmay differ from each other.

1 2 1 3 2 1 2 3 For example, the thickness Tis 7 nm or more and 13 nm or less, and the thickness Tis 15 nm or more and 20 nm or less. More specifically, for example, the thickness Tr is 100 nm, the thicknesses Tand Tare 7 nm, and the thickness Tis 18 nm. However, the values of the thickness Tr, T, T, and Tare not limited to these examples.

The following describes an example of the manufacturing method of the display device DSP.

In the manufacturing of the display device DSP, a large mother substrate is fabricated. The mother substrate comprises a plurality of areas (panel portions) each corresponding to the display device DSP. The following describes a configuration applicable to this mother substrate.

5 FIG. is a schematic plan view of a mother substrate MB (a mother substrate for a display device) according to the present embodiment. The mother substrate MB comprises a plurality of panel portions PP provided in a matrix.

1 2 1 FIG. The outer shape of the panel portion PP corresponds to a cut line CTfor cutting out each panel portion PP from the mother substrate MB. In the panel portion PP, a cut line CTcorresponding to the outer shape of the display device DSP shown inis provided.

1 2 In the manufacturing of the display device DSP, the mother substrate MB is cut along the cut line CT, and each of the panel portions PP is cut out. Furthermore, the panel portions PP are cut along the cut line CT, and the portions corresponding to the display device DSP are cut out.

6 FIG. 7 FIG.A 7 FIG.E 8 FIG.A 8 FIG.I 7 FIG.A 7 FIG.E 8 FIG.A 8 FIG.I 12 is a flowchart showing an example of the manufacturing method of the display device DSP.toandtoare schematic cross-sectional views showing the manufacturing process of the display device DSP.toandtomainly focus on the display area DA and omit the components below the organic insulating layer.

11 10 1 12 11 2 2 1 2 3 3 6 FIG. 6 FIG. 6 FIG. In the formation of the panel portions PP, first, the circuit layeris formed above the substrateof the mother substrate MB (the process PRin). Further, the organic insulating layercovering the circuit layeris formed (the process PRin). After the process PR, a process for forming the lower electrodes LE, LE, and LEare performed (the process PRin).

3 3 3 12 3 3 3 1 1 3 3 1 a a a b a c a a 6 FIG. 6 FIG. 6 FIG. 7 FIG.A In the process PR, a conductive oxide layer CLto be processed into the conductive oxide layer CLis formed on the organic insulating layer(the process PRin), a reflective layer RFa to be processed into the reflective layer RF is formed on the conductive oxide layer CL(the process PRin), a conductive oxide layer CLto be processed into the conductive oxide layer CLis formed on the reflective layer RFa (the process PRin) as shown in. In the present embodiment, the conductive oxide layer CLand the conductive oxide layer CLeach are formed of an ITO, and the reflective layer RFa is formed of silver.

3 1 1 3 1 3 1 a a a a a a For example, the conductive oxide layer CL, the reflective layer RFa, and the conductive oxide layer CLcan be formed by sputtering in the same chamber CM. In this case, the sputtering targets for the conductive oxide layer CLand the conductive oxide layer CL, which are ITO, may be the same. As another example, the conductive oxide layer CL, the reflective layer RFa, and the conductive oxide layer CLmay be formed by sputtering in separate chambers.

3 1 2 2 1 3 2 2 2 1 a a a a d a a 7 FIG.B 6 FIG. After the formation of the conductive oxide layer CL, the reflective layer RFa, and the conductive oxide layer CL, a conductive oxide layer CLto be processed into the conductive oxide layer CLis formed on the conductive oxide layer CLby sputtering as shown in(the process PRin). In the present embodiment, the conductive oxide layer CLis formed of an ITO. For example, the sputtering for forming the conductive oxide layer CLmay be performed in a chamber CM, which is different from the chamber CM.

3 1 2 1 2 2 1 a a a 2 During the sputtering for forming the conductive oxide layer CL, the reflective layer RFa, the conductive oxide layer CL, and the conductive oxide layer CL, the inside of each of the chambers CMand CMis filled with an inert gas, such as argon (Ar) gas. However, water vapor (HO) is introduced into the chamber CM. On the other hand, water vapor is not introduced into the chamber CM.

1 2 1 2 a a a a In this way, although the conductive oxide layers CLand CLare both formed by an ITO, the sputtering for forming the conductive oxide layer CL(the first sputtering) is performed in an atmosphere that does not contain water vapor, and the sputtering for forming the conductive oxide layer CL(the second sputtering) is performed in an atmosphere that contains water vapor.

1 2 a a The above describes the example where the sputtering for forming the conductive oxide layers CLand CLis performed in separate chambers. As another example, these sputtering steps may be performed in the same chamber.

3 1 1 2 3 2 3 1 3 1 1 2 3 d a e f a a a 7 FIG.C 6 FIG. 6 FIG. 7 FIG.D After the process PR, a planar resist Rcorresponding to lower electrodes LE, LE, and LEis provided on the conductive oxide layer CLas shown in(the process PRin). Furthermore, etching using the resist Ras a mask is performed (the process PRin). This removes the portions exposed from the resist Rof the conductive oxide layers CL, CL, and CLand the reflective layer RFa as shown in. For example, the etching is wet etching.

3 1 3 1 2 3 3 f g a a a h 6 FIG. 6 FIG. After the process PR, the resist Ris removed (stripped) (the process PRin). Further, the conductive oxide layers CL, CL, and CLformed of an ITO are calcined (the process PRin).

1 2 3 3 1 2 7 FIG.E These steps provide the lower electrodes LE, LE, and LEin which the conductive oxide layer CL, the reflective layer RF, the conductive oxide layer CL, and the conductive oxide layer CLare stacked in this order as shown in.

1 2 3 1 1 2 3 1 2 3 1 2 3 a a a In this example, the conductive oxide layers CL, CL, and CLand the reflective layer RFa are etched using the same resist Ras a mask. Therefore, the end portions Er, Ec, Ec, and Ecof the reflective layer RF and the conductive oxide layers CL, CL, and CLalign at the end portions of the lower electrodes LE, LE, and LE.

2 3 2 3 2 1 2 3 1 1 2 3 2 a d a h a a a f a a a h a. The sputtering for forming the conductive oxide layer CLin the process PRis performed in an atmosphere containing water vapor. Thus, water is added to the conductive oxide layer CL. In this case, in the stage before calcining in the process PR, the crystallinity of the conductive oxide layer CLis lower than that of the conductive oxide layer CLformed in an atmosphere containing no water vapor. Thus, the etching rate of the conductive oxide layer CLin the etching in the process PRis greater than that of the conductive oxide layer CLin the etching. The crystallinity of each of the conductive oxide layers CLand CLis increased by the calcining in the process PR. Further, this calcining removes the water added to the conductive oxide layer CL

1 2 3 5 1 2 3 4 1 2 3 5 5 8 FIG.A 6 FIG. After the formation of the lower electrodes LE, LE, and LE, the rib layercovering the lower electrodes LE, LE, and LEis formed on the entire mother substrate MB as shown in(the process PRin). At this time, the pixel apertures AP, AP, and APare not provided in the rib layer. The rib layermay be formed by chemical vapor deposition (CVD).

5 6 5 5 1 63 2 64 3 65 4 66 2 4 2 6 1 2 3 4 6 FIG. 8 FIG.B After the formation of the rib layer, a process for forming the partitionis performed (the process PRin). In the process PR, a first layer Lto be processed into the bottom layer, a second layer Lto be processed into the stem layer, a third layer Lto be processed into the first top layer, and a fourth layer Lto be processed into the second top layerare subsequently formed on the entire mother substrate MB as shown in. Further, a resist Ris provided on the fourth layer L. The resist Rhas been patterned into the shape of the partition. The first layer L, the second layer L, the third layer L, and the fourth layer Lare formed by, for example, sputtering.

1 2 3 4 2 1 2 3 4 2 4 2 1 2 3 2 Subsequently, the first layer L, the second layer L, the third layer L, and the fourth layer Lare patterned using the resist Ras a mask. In one example, the first layer Lis formed of a titanium nitride, the second layer Lis formed of aluminum, the third layer Lis formed of titanium, and the fourth layer Lis formed of an ITO. In this case, the above patterning process may include wet etching for removing the portion exposed from the resist Rof the fourth layer L, dry etching for removing the portions exposed from the resist Rof the first, second, and third layers L, L, and L, and wet etching for reducing the width of the second layer L.

5 6 6 2 8 FIG.C The process PRcompletes the formation of the partitionin the display area DA as shown in. After the formation of the partition, the resist Ris removed (stripped).

1 2 3 6 6 3 6 5 3 1 2 3 1 2 3 5 3 1 2 3 6 6 FIG. 8 FIG.D 8 FIG.E Subsequently, a process for providing the pixel apertures AP, AP, and APis performed (the process PRin). In this process PR, a resist Rcovering the partitionis formed as shown in. Further, dry etching for the rib layeris performed using the resist Ras a mask. This dry etching forms the pixel apertures AP, AP, and APfrom which the respective lower electrodes LE, LE, and LEare exposed, in the rib layeras shown in. After the dry etching described above, the resist Ris removed (stripped). The pixel apertures AP, AP, and APmay be formed prior to the formation of the partition.

6 1 7 1 1 11 6 FIG. 8 FIG.F After the process PR, a process for forming the display element DEis performed (the process PRin). In the formation of the display element DE, first, the stacked film FLand the sealing layer SEare formed on the entire mother substrate MB as shown in.

3 FIG. 1 1 1 1 1 1 1 1 1 1 1 11 1 6 11 1 6 As shown in, the stacked film FLincludes the organic layer ORcontacting the lower electrode LEthrough the pixel aperture AP, the upper electrode UEcovering the organic layer OR, and the cap layer CPcovering the upper electrode UE. For example, the organic layer OR, the upper electrode UE, and the cap layer CPmay be formed by vapor deposition. For example, the sealing layer SEmay be formed by CVD. The stacked film FLis divided into a plurality of portions by the partitionhaving an overhang shape. The sealing layer SEcontinuously covers these portions, into which the stacked film FLhas been divided, and the partition.

1 11 4 11 4 1 6 1 8 FIG.F Subsequently, the stacked film FLand the sealing layer SEare patterned. In this patterning, a resist Ris provided on the sealing layer SEas shown in. The resist Rcovers the subpixel SPand a portion of the partitionaround the subpixel SP.

4 4 1 11 1 1 11 1 1 11 1 1 1 4 8 FIG.G Thereafter, the etching process using the resist Ras a mask is performed. This process removes the portions exposed from the resist Rof the stacked film FLand the sealing layer SEas shown in. That is, the portions overlapping the lower electrode LEof the stacked film FLand the sealing layer SEremain, and the other portions are removed. This forms the display element DEin the subpixel SP. This etching process may include wet etching and dry etching performed in order for the sealing layer SE, the cap layer CP, the upper electrode UE, and the organic layer OR. After these etching processes, the resist Ris removed (stripped).

7 2 8 2 1 2 2 12 2 2 2 2 2 2 2 2 6 FIG. 3 FIG. After the process PR, a process for forming the display element DEis performed (the process PRin). The display element DEcan be formed by the same procedure as that of the display element DE. That is, in the formation of the display element DE, the stacked film FLand the sealing layer SEare formed in the entire mother substrate MB. The stacked film FLincludes the organic layer ORcontacting the lower electrode LEthrough the pixel aperture AP, the upper electrode UEcovering the organic layer OR, and the cap layer CPcovering the upper electrode UEas shown in.

2 2 2 12 2 2 2 2 8 FIG.H The organic layer OR, the upper electrode UE, and the cap layer CPmay be formed by, for example, vapor deposition. The sealing layer SEmay be formed by, for example, CVD. Patterning these stacked film FLand sealing layer SEforms the display element DEin the subpixel SPas shown in.

8 3 9 3 1 2 3 3 13 3 3 3 3 3 3 3 3 6 FIG. 3 FIG. After the process PR, a process for forming the display element DEis performed (the process PRin). The display element DEcan be formed by the same procedures as those of the display elements DEand DE. Specifically, when the display element DEis formed, the stacked film FLand the sealing layer SEare formed in the entire mother substrate MB. The stacked film FLincludes the organic layer ORcontacting the lower electrode LEthrough the pixel aperture AP, the upper electrode UEcovering the organic layer OR, and the cap layer CPcovering the upper electrode UEas shown in.

3 3 3 13 3 13 3 3 8 FIG.I The organic layer OR, the upper electrode UE, and the cap layer CPmay be formed by, for example, vapor deposition. The sealing layer SEmay be formed by, for example, CVD. Patterning these stacked film FLand sealing layer SEforms the display element DEin the subpixel SPas shown in.

1 2 3 1 2 3 Here, the above description assumes that the display elements DE, DE, and DEare formed in this order. However, the display elements DE, DE, and DEmay be formed in another order.

1 2 3 1 10 10 2 1 11 2 2 12 6 FIG. 6 FIG. 6 FIG. After the formation of the display elements DE, DE, and DE, the resin layer RSis formed, for example, by the ink-jet method (the process PRin). After the process PR, the sealing layer SEcovering the resin layer RSis formed by, for example, CVD (the process PRin). Further, the resin layer RScovering the sealing layer SEis formed by, for example, the ink-jet method (the process PRin).

11 1 13 2 14 1 2 13 14 13 14 6 FIG. 6 FIG. After the process PR, the mother substrate MB is cut along the cut line CT(the process PRin). This cuts out each panel portion PP. Further, the panel portion PP is cut along the cut line CT(the process PRin). This completes the display device DSP. For example, laser cutting with infrared irradiation along the cut lines CTand CTmay be adopted for cutting in the processes PRand PR. The cutting in the processes PRand PRmay be performed by other methods such as scribe cutting.

1 2 1 2 3 1 2 In the above present embodiment, the conductive oxide layers CLand CLare provided on the reflective layers RF on the lower electrodes LE, LE, and LE. If a sole conductive oxide layer is formed instead of these conductive oxide layers CLand CL, the following problems may arise.

1 2 3 3 f That is, if the conductive oxide layer on the reflective layer RF has defects such as minute pinholes, the etching liquid may reach the reflective layer RF through the defects during various wet etching processes after the formation of the lower electrodes LE, LE, and LE. This may result in loss of at least part of the reflective layer RF. In contrast, forming the conductive oxide layer on the reflective layer RF to be thicker can suppress the occurrence of defects such as pinholes. However, forming the conductive oxide layer on the reflective layer RF to be thicker requires longer time for sputtering. Thus, heat generated in the sputtering easily accumulates in the conductive oxide layer. If crystallization of the conductive oxide layer proceeds due to this heat, the complete removal of the crystallized conductive oxide layer may fail during the etching in the process PR. This may result in the conductive oxide layer remaining in unintended positions.

1 2 2 2 2 2 2 1 2 1 1 2 3 a a a a a a a a a f In contrast, in the present embodiment, the conductive oxide layer on the reflective layer RF is divided into the conductive oxide layer CLand the conductive oxide layer CL. Further, as described above, the crystallinity of the conductive oxide layer CL, which serves as the base of the conductive oxide layer CL, which is its upper layer, is low due to addition of water. The crystallization start temperature of the conductive oxide layer CLis higher than that in cases not involving water addition. Thus, even when the conductive oxide layer CLis formed to be thick, the conductive oxide layer CLis not easily crystallized by the heat generated in the sputtering. Further, the heat does not easily affect the conductive oxide layer CLcovered with the conductive oxide layer CL. Thus, crystallization of the conductive oxide layer CLis suppressed as well. Thus, the conductive oxide layers CLand CLcan be sufficiently removed by etching in the process PR. This improves the yield of the display device DSP.

2 2 2 1 2 a a a a a Even if the conductive oxide layer CLis formed directly on the reflective layer RFa, the reflective layer RFa may oxidize due to water vapor during the formation of the conductive oxide layer CLor moisture contained in the conductive oxide layer CL. On the other hand, when the conductive oxide layer CLto which water is not added is provided between the reflective layer RFa and the conductive oxide layer CLas in the present embodiment, oxidation of the reflective layer RFa can be suppressed.

1 2 1 2 a a a a 9 FIG. Here, the following describes film formation conditions to be applied to the conductive oxide layers CLand CLto achieve the above effects.is a table showing an example of the film formation conditions. Here, for each of the conductive oxide layers CLand CL, the preferred ranges of thicknesses T [nm], film formation power W [KW] applied to the target during sputtering, water vapor flow rate Qi [sccm] to the atmosphere during sputtering, argon flow rate Qb [sccm] to the atmosphere during sputtering, and pressure P [Pa] of the atmosphere during sputtering are shown.

1 1 2 2 1 2 1 2 1 2 1 1 1 2 2 a a a a a a 4 FIG. The relationship between the thickness Tof the conductive oxide layer CLand the thickness Tof the conductive oxide layer CLis the same as the one described above for the conductive oxide layers CLand CLin the explanation on. That is, the thickness Tis 7 nm or more and 13 nm or less, and the thickness Tis 15 nm or more and 20 nm or less. Further, the relationship T<Tis satisfied. In this manner, decreasing the thickness Tcan suppress excessive heat accumulation and crystallization of the conductive oxide layer CLdue to that heat in the formation of the conductive oxide layer CL. Even if the conductive oxide layer CLformed under water-added conditions is formed to be thicker, this conductive oxide layer CLis difficult to crystallize as described above.

1 1 2 2 1 2 a a The film formation power Wduring the sputtering of the conductive oxide layer CLis 2.0 KW or more and 4.0 kW or less. In contrast, the film formation power Wduring the sputtering of the conductive oxide layer CLis 6.0 kW or more and 10.0 kW or less. That is, the relationship W<Wis satisfied.

1 2 a a The water vapor flow rate Qa during the sputtering of the conductive oxide layer CLis 0 sccm. In contrast, for example, the water vapor flow rate Qa during the sputtering of the conductive oxide layer CLis 5 sccm.

1 1 2 2 1 2 a a The argon flow rate Qbduring the sputtering of the conductive oxide layer CLis 180 sccm or more and 220 sccm or less. Further, the argon flow rate Qbduring the sputtering of the conductive oxide layer CLis 180 sccm or more and 220 sccm or less. That is, Qband Qbare equivalent to each other.

1 1 2 2 1 2 a a The pressure Pduring the sputtering of the conductive oxide layer CLis 0.60 Pa or more and 0.80 Pa or less. In contrast, the pressure Pduring the sputtering of the conductive oxide layer CLis 0.30 Pa or more and 0.50 Pa or less. That is, the relationship P>Pis satisfied.

1 2 2 1 The conductive oxide layers CLand CLhave these different film formation conditions. This results in differences in the transmittances. Specifically, the transmittance of the conductive oxide layer CLis lower than that of the conductive oxide layer CL. The following describes this point in detail.

10 FIG. 12 FIG. toare graphs showing the transmittances of these conductive oxide layers formed of an ITO of 7 nm, 11 nm, and 25 nm, respectively. In all graphs, the horizontal axis represents the wavelength λ of light [nm], and the vertical axis represents the transmittance TM [%]. The conductive oxide layers under measurement are formed by sputtering and then calcined to be crystallized.

10 FIG. 12 FIG. 10 FIG. 12 FIG. Into, the broken curved lines indicate the transmittance distribution of conductive oxide layers formed without water addition (Qa=0 sccm). The solid curved lines indicate the transmittance distribution of the conductive oxide layer formed with water addition (Qa=5 sccm). In all ofto, the transmittance decreases in most wavelength ranges in cases involving water addition. In particular, the decrease tends to be greater in the short-wavelength range (for example, the blue wavelength range). Further, the transmittance decreases as the thickness of the conductive oxide layer increases.

12 FIG. also shows by dashed lines the transmittance distribution of a stacked layer body composed of an ITO layer formed at a thickness of 7 nm without water addition (Qa=0 sccm) and an ITO layer formed at a thickness of 18 nm with water addition (Qa=5 sccm). The transmittance distribution of this stacked layer body is generally equivalent to that of the conductive oxide layer formed at 25 nm with water addition (shown by solid lines), but shows a slight improvement in the transmittance in the wavelength range at 400 nm or more.

10 FIG. 12 FIG. 9 FIG. 2 1 2 2 2 2 As the graphs intoshow, the transmittance of the conductive oxide layer CLformed with water addition is lower than that of the conductive oxide layer CLformed without water addition. Further, as the conductive oxide layer CLis formed to be thinner, the transmittance of the conductive oxide layer CLincreases. In light of these points and also in terms of sufficiently transmitting light reflected by the reflective layer RF, the thickness Tof the conductive oxide layer CLis desirably maintain within the range shown in the table in.

1 2 3 Next, the following describes the second embodiment. The present embodiment discloses other configurations applicable to the lower electrodes LE, LE, and LE.

13 FIG. 1 2 3 11 12 13 11 12 13 11 12 13 is a schematic cross-sectional view showing a configuration example of the lower electrodes LE, LE, and LEof the second embodiment. In the present embodiment, conductive oxide layers CL, CL, and CLare provided in order on the reflective layer RF. Each of these conductive oxide layers CL, CL, and CLis formed of an ITO. Further, the conductive oxide layers CL, CL, and CLmay be formed by transparent conductive oxides other than an ITO, such as an IZO and an IGZO.

11 12 13 1 1 11 12 13 11 12 12 13 a The conductive oxide layers CL, CL, and CLare formed by sputtering under film formation conditions without water addition as in the conductive oxide layer CL(the conductive oxide layer CL) in the first embodiment. For example, the conductive oxide layers CL, CL, and CLare formed by sputtering in the same chamber. However, after the formation of the conductive oxide layer CL, the mother substrate MB is once removed from the chamber and cooled before the formation of the conductive oxide layer CL. Similarly, after the formation of the conductive oxide layer CL, the mother substrate MB is once removed from the chamber and cooled before the formation of the conductive oxide layer CL.

11 12 13 11 12 13 Forming the conductive oxide layers CL, CL, and CLin this manner can suppress the temperature rise due to heat accumulation during sputtering than forming thick conductive oxide layers continuously on the reflective layer RF. As a result, this configuration can suppress the crystallization of the conductive oxide layers CL, CL, and CLdue to the heat generated in the sputtering such as that described above in the first embodiment.

11 12 13 11 12 13 11 12 13 11 12 13 11 12 13 The conductive oxide layers CL, CL, and CLhave respective thicknesses T, T, and T. In one example, the thicknesses T, T, and Tare 7 nm or more and 13 nm or less. More specifically, the thickness Tis 7 nm, and each of the thicknesses Tand Tis 9 nm. However, the values of the thickness T, T, and Tare not limited to these examples.

The present embodiment discloses the example where the conductive oxide layer on the reflective layer RF is divided into three layers, but the conductive oxide layer may be divided into four or more layers.

2 2 a The configurations in the first and second embodiments may be combined as appropriate. For example, when the conductive oxide layer on the reflective layer RF is divided into three layers or four layers or more as in the second embodiment, the uppermost layer may be formed under film formation conditions with water addition as in the conductive oxide layer CL(the conductive oxide layer CL) in the first embodiment.

All of the display devices and manufacturing methods thereof that can be implemented by a person of ordinary skill in the art through arbitrary design changes to the display device and manufacturing method thereof disclosed above as each embodiment of the present invention come within the scope of the present invention as long as they are in keeping with the spirit of the present invention.

Various types of the modified examples are easily conceivable within the category of the ideas of the present invention by a person of ordinary skill in the art and the modified examples are also considered to fall within the scope of the present invention. For example, additions, deletions or changes in design of the constituent elements or additions, omissions, or changes in condition of the processes arbitrarily conducted by a person of ordinary skill in the art, in the above embodiments, fall within the scope of the present invention as long as they are in keeping with the spirit of the present invention.

In addition, the other advantages of the aspects described in the embodiments, which are obvious from the descriptions of the present specification or which can be arbitrarily conceived by a person of ordinary skill in the art, are considered to be achievable by the present invention as a matter of course.