Interconnect Structure Including Vias with Different Profiles and Method for Manufacturing the Same

With rapid development of semiconductor technology, an increasing number of devices with different functions are being integrated in an integrated circuit, increasing the complexity of integrated circuit design. Since the driving voltages of the devices may be different from each other, the resistance of the wires (metal lines or metal vias) respectively connected thereto may be designed to be different. Therefore, a method for manufacturing a back-end interconnecting structure with flexibility in routing design is being continuously developed.

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “on,” “above,” “top,” “bottom,” “upper,” “lower,” “over,” “beneath,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

For the purposes of this specification and appended claims, unless otherwise indicated, all numbers expressing amounts, sizes, dimensions, proportions, shapes, formulations, parameters, percentages, quantities, characteristics, or other numerical values used in the specification and claims, are to be understood as being modified in all instances by the terms “about” and “substantially” even if the terms “about” and “substantially” are not explicitly recited with the values, amounts or ranges. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the following specification and appended claims are not and need not be exact, but may be approximations and/or larger or smaller than specified as desired, may encompass tolerances, conversion factors, rounding off, measurement error, and other factors known to those of skill in the art depending on the desired properties sought to be obtained by the presently disclosed subject matter. For example, the terms “about” and “substantially,” when used with a value, can capture variations of, in some aspects ±10%, in some aspects ±5%, in some aspects ±2.5%, in some aspects ±1%, in some aspects ±0.5%, and in some aspects ±0.1% from the specified amount, as such variations are appropriate to perform the disclosed methods or employ the disclosed compositions.

The term “source/drain portion(s)” may refer to a source or a drain, individually or collectively dependent upon the context.

In common practice, a back-end interconnecting structure includes multiple interconnect layers. Vias located in an upper one of the interconnect layers extend through the same etch stop layer so as to be connected to metal lines in a lower one of the interconnect layers. In such case, since a single type of the etch stop layer is located between the upper and lower ones of the interconnect layers, the resistance of one of the vias located in the upper one of the interconnect layer cannot be changed individually. Therefore, the present disclosure is directed to a method for manufacturing an interconnect layer which includes multiple vias in the same interconnect layer such that the multiple vias have adjustable resistances which can be independently changed.

1 FIG. 17 FIG. 19 FIG. 2 19 FIGS.to 1 2 1 1 6 1 x 0 is a flow diagram illustrating a methodfor manufacturing an interconnecting structure (e.g., an interconnecting layer Mshown inor an interconnecting layer Mshown in) in a semiconductor structurein accordance with some embodiments. The methodmay include steps Sto S.are schematic views illustrating intermediate stages of the methodin accordance with some embodiments.

2 FIG. 100 100 is a schematic sectional view illustrating a base structurein accordance with some embodiments. In some embodiments, the base structureis a device wafer including active devices (for example, transistors, diodes, or the like), passive devices (for example, capacitors, inductors, resistors, or the like), decoders, amplifiers, or combinations thereof.

100 101 102 101 101 101 101 101 101 102 102 2 FIG. In some embodiments, the base structureincludes a substrateand a plurality of semiconductor devices(one of which is exemplarily shown in) formed on the substrate. In some embodiments, the substratemay include elemental semiconductor materials (such as crystalline silicon, diamond, or germanium), compound semiconductor materials (such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide), alloy semiconductor materials (such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide), or combinations thereof. In some embodiments, the substratemay be a bulk semiconductor substrate, for example, but not limited to, a bulk substrate of silicon, germanium, silicon germanium, or other suitable semiconductor materials (such as the examples described earlier in the same paragraph). In some other embodiments not shown herein, the substratemay be configured as a semiconductor-on-insulator substrate. Other suitable materials and configurations for the substrateare within the contemplated scope of the present disclosure. In some embodiments, the substratemay be formed with trench isolations (not shown) to separate the semiconductor devicefrom an adjacent ones of the semiconductor devices. In some embodiments, the trench isolations may each be a shallow trench isolation (STI), a deep trench isolation (DTI), or other suitable structures. In some embodiments, the trench isolations may include silicon oxide, silicon nitride, silicon oxynitride, other low-k dielectric materials, or combinations thereof. In some embodiments, the semiconductor devicemay include a transistor, but is not limited thereto.

100 103 104 103 104 1041 1042 103 102 102 104 x−1 x−1 x−1 2 FIG. In some embodiments, the base structurefurther includes an interconnect layer M, where x is an integer not less than 1. The interconnect layer Mincludes a dielectric layer(which may be referred to as a lower dielectric layer) and conductive features(which may be also referred to as lower conductive features) formed in the dielectric layer. As shown in, the conductive featuresinclude a conductive featureand a conductive featurewhich are spaced apart from each other by the dielectric layer. The interconnect layer Mis formed on the semiconductor deviceso as to permit the semiconductor deviceto be electrically connected to an external circuit through the conductive features.

103 103 103 In some embodiments, the dielectric layerincludes a low-dielectric constant (low-k) material. In some embodiments, the dielectric layermay include silicon oxide, silicon oxycarbide, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), silicon oxycarbide (SiOC), spin-on-glass (SOG), fluorine-doped silicon oxide, carbon-doped silicon oxide, porous silicon oxide, porous carbon-doped silicon oxide, other suitable low dielectric constant materials, or combinations thereof. Other possible materials suitable for the dielectric layerare within the contemplated scope of the present disclosure.

104 104 105 106 105 106 103 106 103 106 105 105 106 104 104 102 19 FIG. In some embodiments, the conductive featuresare metal lines. The conductive featuresmay each includes a diffusion barrier layerand a conductive portion. The diffusion barrier layeris disposed to separate the conductive portionfrom the dielectric layerso as to prevent the metal elements in the conductive portionfrom diffusing into the dielectric layer. In some embodiments, the conductive portionincludes Co, Cu, Ni, Ru, W, Mo, Ti, Zr, Ta, Zn, or alloys thereof. In some embodiments, the diffusion barrier layerincludes titanium, titanium nitride, tantalum, tantalum nitride, or combinations thereof. Other materials suitable for the diffusion barrier layerand the conductive portionare also within the contemplated scope of the present disclosure. In some embodiments, the conductive featuresmay be formed as a single damascene structure or a dual damascene structure. In some other embodiments shown in(will be described later), the conductive featuresmay each be a gate electrode connected to the semiconductor device.

1 FIG. 5 7 FIGS.and 5 7 FIGS.and 2 FIG. 3 4 FIGS.and 5 FIG. 6 FIG. 7 FIG. 1 1 10 20 1041 1042 1 1 10 20 1 10 20 Referring toand the examples illustrated in, the methodbegins at step S, where a first etch stop layerand a second etch stop layerare respectively formed on the conductive featureand the conductive feature.are each a schematic sectional view similar to that of, but illustrating two possible structures after step Sin accordance with some embodiments.respectively illustrate two possible intermediate states in step Sin accordance with some embodiments for forming the etch stop layers,shown in, whereasillustrates a possible intermediate state in step Sin accordance with some other embodiments for forming the etch stop layers,shown in.

10 20 The first etch stop layerhas a configuration that is different from a configuration of the second etch stop layer.

5 7 FIGS.and 5 7 FIG.or 10 20 10 11 12 13 1041 10 10 1 10 2 20 In some embodiments, as shown in, the first etch stop layeris configured as a multi-layered structure, and the second etch stop layeris configured as a single layer structure. For example, the first etch stop layerincludes a first sub-layer, a second sub-layerand a third sub-layerwhich are sequentially formed on the conductive featurein such order. It is noted that the number of the sub-layers of the first etch stop layeris not limited to three as shown in. In some other embodiments not shown herein, the number of the sub-layers of the fist etch stop layermay be two, or greater than three. In some embodiments, a total thickness (T) of the first etch stop layeris greater than a total thickness (T) of the second etch stop layer.

11 12 5 11 12 13 11 12 13 11 12 13 The first sub-layeris made of a first dielectric material, the second sub-layeris made of a second dielectric material, and the third dielectric material is made of a third dielectric material. In some embodiments, the first, second and third dielectric materials are different from each other so as to permit the first, second and third dielectric materials to have different etch rates in the following etching process (e.g., in step S) using the same etchant. The first dielectric material includes or is made of silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, silicon carbon nitride, silicon oxycarbon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride. The second dielectric material includes or is made of silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, silicon carbon nitride, silicon oxycarbon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride. The third dielectric material includes or is made of silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, silicon carbon nitride, silicon oxycarbon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride. It is noted that two of the first, second and third dielectric materials may have the same atom species. For example, but not limited to, the first and second dielectric materials may each have silicon, carbon and nitrogen elements, and concentrations of the silicon, carbon and nitrogen elements in the first dielectric material are respectively different from concentrations of the silicon, carbon and nitrogen elements in the second dielectric material, so that the etch rate of the first dielectric material can be significantly different from the etch rate of the second dielectric material. In some embodiments, when the dielectric constant (k-value) of the first, second or third dielectric material is larger, the etch rate of the first, second or third dielectric material may be lower. In some embodiments, the first sub-layerhas a thickness ranging from about 10 Å to about 100 Å. In some embodiments, the second sub-layerhas a thickness ranging from about 10 Å to about 100 Å. In some embodiments, the third sub-layerhas a thickness ranging from about 10 Å to about 100 Å. In some embodiments, the thicknesses of the first, second and third sub-layers,,may be substantially equal to each other. In some alternative embodiments, the thicknesses of the first, second and third sub-layers,,may be different from each other.

20 20 20 5 FIG. 7 FIG. The second etch stop layeris made of one of the first dielectric material, the second dielectric material and the third dielectric material. In certain embodiments, as shown in, the second etch stop layeris made of the third dielectric material. In certain embodiments, as shown in, the second etch stop layeris made of the first dielectric material.

10 20 5 FIG. 3 5 FIGS.to In some embodiments, formation of the first and second etch stop layers,shown inmay include multiple sub-steps as shown in.

3 FIG. 31 32 41 32 32 1042 x−1 Firstly, as shown in, a first dielectric filmmade of the first dielectric material and a second dielectric filmmade of the second dielectric material are sequentially formed on the interconnect layer Mby atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition process (CVD), or other suitable deposition techniques. Then, a patterned photoresist layeris partially formed on the dielectric filmsby, for example, but not limited to, a spin coating, followed by an exposure process and a development process so as to expose a portion of the dielectric filmslocated above the conductive feature.

3 4 FIGS.and 5 FIG. 31 32 1042 32 31 32 11 12 10 Afterwards, as shown in, the dielectric films,are patterned to expose the conductive feature. To be specific, the exposed portion of the dielectric filmand a portion of the dielectric filmlocated beneath the exposed portion of the dielectric filmare sequentially removed by an etching process, thus obtaining the first sub-layerand the second sub-layerof the first etch stop layer(see).

4 5 FIGS.and 41 33 12 1042 33 12 13 10 33 1042 20 Next, as shown in, the photoresist layeris removed by, for example, but not limited to, an ashing process and/or a photoresist stripping process, and then a third dielectric filmmade of the third dielectric material is formed to cover the second sub-layerand the conductive featureby ALD, CVD, PVD, or other suitable deposition techniques. A first portion of the third dielectric film, which is disposed on the second sub-layer, serves as the third sub-layerof the first etch stop layer, and a second portion of the third dielectric film, which is disposed on the conductive feature, serves as the second etch stop layer

7 FIG. 5 FIG. 7 FIG. 5 FIG. 7 FIG. 6 7 FIGS.and 10 20 10 20 10 20 20 11 10 20 10 20 is a schematic sectional view similar to that of, but illustrating a variant of the configuration of the first and second etch stop layers,in accordance with some other embodiments. The first and second etch stop layers,shown inhave a configuration similar to that of the first and second etch stop layers,shown in, but the second etch stop layeris made of a material the same as that of the first sub-layerof the first etch stop layer. That is, the second etch stop layeris made of the first dielectric material. Formation of the first and second etch stop layers,shown inmay include multiple sub-steps as shown in.

6 FIG. 31 32 33 42 33 33 1042 x−1 Firstly, as shown in, the first dielectric film, the second dielectric filmand the third dielectric filmare sequentially formed on the interconnect layer Mby ALD, CVD, PVD, or other suitable deposition techniques. Then, a patterned photoresist layeris partially formed on the third dielectric filmby, for example, but not limited to, a spin coating, followed by an exposure process and a development process so as to expose a portion of the third dielectric filmlocated above the conductive feature.

6 7 FIGS.and 32 33 31 1042 33 42 32 33 33 32 31 32 33 13 12 11 10 31 20 Afterwards, as shown in, the dielectric films,are patterned to expose a first portion of the first dielectric filmlocated above the conductive feature. To be specific, the exposed portion of the third dielectric filmwhich is exposed from the patterned photoresist layer, and a portion of the second dielectric filmwhich is disposed beneath the exposed portion of the third dielectric filmare removed by an etching process. Accordingly, the patterned dielectric films,and a second portion of the first dielectric filmlocated beneath the patterned dielectric films,respectively serve as the sub-layers,,of the first etch stop layer. The first portion of the first dielectric filmserves as the second etch stop layer.

32 33 42 After the patterning of the dielectric films,, the photoresist layeris removed by, for example, but not limited to, an ashing process and/or a photoresist stripping process.

10 20 10 20 In some alternative embodiments not shown herein, the first and second etch stop layers,may be each configured as a single-layer structure, but the first and second etch stop layers,are made of different materials.

5 FIG. 7 FIG. For purposes of simplicity and clarity, in the following steps, the structures subsequent towill be illustrated, while the structures subsequent towill not be illustrated.

1 FIG. 8 FIG. 8 FIG. 5 FIG. 1 2 50 10 20 2 Referring toand the example illustrated in, the methodproceeds to step S, where a dielectric layer(which may be referred to as an upper dielectric layer) is formed to cover the first and second etch stop layers,.is a schematic sectional view similar to that of, but illustrating the structure after step Sin accordance with some embodiments.

50 103 103 50 50 2 FIG. Possible low-k dielectric materials suitable for the dielectric layerare similar to those for the dielectric layeras described above with reference to, and thus the details thereof are omitted for the sake of brevity. The dielectric materials of the dielectric layer,may be the same as or different from each other. In some embodiments, the dielectric layermay be formed by ALD, CVD, PVD, or other suitable deposition techniques.

1 FIG. 10 FIG. 10 FIG. 8 FIG. 9 10 FIGS.and 1 3 501 502 50 3 3 Referring toand the example illustrated in, the methodproceeds to step S, where a first trenchesand a second trenchare formed in an upper portion of the dielectric layer.is a schematic sectional view similar to that of, but illustrating the structure after step Sin accordance with some embodiments. In some embodiment, step Smay include multiple sub-steps as shown in.

9 FIG. 51 50 51 5101 5102 50 51 51 511 512 513 511 512 513 Firstly, as shown in, a patterned mask layeris formed on the dielectric layer. The patterned mask layeris formed with a first openingand a second openingto expose portions of the dielectric layer. In some embodiments, the patterned mask layeris formed by ALD, CVD, PVD, or other suitable deposition techniques, followed by a patterning process (for example, but not limited to, a double patterning process). In some embodiments, the patterned mask layermay be configured as a multi-layered structure which includes sub-layers,,stacked on each other. In some embodiments, the sub-layermay include silicon oxide or other suitable materials, and may serve as a lower anti-reflective coating layer. In some embodiments, the sub-layermay include a nitride-based material, such as silicon nitride, silicon oxynitride, metal nitride (e.g., aluminum nitride, tungsten nitride), or other suitable materials. In some embodiments, the sub-layermay include silicon oxide or other suitable materials, and may serve as an upper anti-reflective coating layer.

9 10 FIGS.and 9 FIG. 50 5101 5102 51 501 502 513 511 512 50 Afterwards, as shown in, a trench etching process is performed to etch an upper portion of the dielectric layerthrough the openings,of the patterned mask layer(serving as a hard mask), thereby forming the trenches,. In some embodiments, the sub-layer(see) may be consumed and removed during the trench etching process, leaving the sub-layers,on the dielectric layer.

1 FIG. 12 FIG. 10 13 FIG.or 12 FIG. 10 FIG. 11 12 FIGS.and 1 4 711 721 50 71 72 501 502 4 4 Referring toand the example illustrated in, the methodproceeds to step S, where a first holeand a second holeare formed in a lower portion of the dielectric layer. The holes,are located immediately beneath the trenches,(see), respectively.is a schematic sectional view similar to that of, but illustrating the structure after step Sin accordance with some embodiments. In some embodiment, step Smay include multiple sub-steps as shown in.

11 FIG. 10 FIG. 60 501 502 60 60 512 512 60 60 s s Firstly, as shown in, a filling layeris formed to fill the trenches,(see). In some embodiments, the filling layerhas a planar upper surfacewhich is at a level higher than that of an upper surfaceof the sub-layer. In some embodiments, the filling layermay be made of photoresist, and may be formed by a spin-on coating process, or other suitable deposition techniques. In some embodiments, the filling layermay be made of amorphous carbon or ashless carbon, and may be formed by CVD, or other suitable deposition techniques.

11 FIG. 61 60 61 611 612 60 611 612 61 61 Afterwards, as shown in, a patterned mask layeris formed on the filling layer. The patterned mask layeris formed with a first openingand a second openingto expose portions of the filling layer. The openings,are spaced apart from each other. In some embodiments, the patterned mask layeris formed by ALD, CVD, PVD, or other suitable deposition techniques, followed by a patterning process (for example, but not limited to, a double patterning process). In some embodiments, the patterned mask layerincludes a dielectric material such as silicon nitride, silicon oxide, silicon-oxynitride, or other suitable materials.

11 12 FIGS.and 12 FIG. 11 FIG. 60 50 611 612 61 611 612 60 711 721 611 612 50 711 721 50 10 20 10 711 20 50 10 20 10 20 711 721 61 Next, as shown in, a first via etching process is performed to etch the filling layerand the lower portion of the dielectric layerthrough the openings,of the patterned mask layer(serving as a hard mask). After the first via etching process, recessesA,A are formed to penetrate the filling layer, and the holes,which respectively extend downwardly from the recessesA,A, are formed in the lower portion of the dielectric layer. At least one of the holes,may penetrate the lower portion of the dielectric layerto expose a corresponding one of the etch stop layers,. In some embodiments, as shown in, the first etch stop layeris exposed from the first hole, whereas the second etch stop layeris covered by the dielectric layer. In some other embodiments not shown herein, in the case that the etch stop layers,have the same thickness, the etch stop layers,may be respectively exposed from the holes,. In some embodiments, the patterned mask layer(see) may be consumed and removed during the first via etching process.

711 711 721 721 721 711 611 612 711 712 711 721 b b b b 11 FIG. In some embodiments, a bottomof the first holeis at a level that is substantially the same as a level of a bottomof the second hole. In some other embodiments not shown herein, the level of the bottommay be slightly higher or lower than the level of the bottomdepending on the dimensions of the openings,(see). In some embodiments, whether the dimensions of the holes,are substantially the same or not, a contour or a shape of the first holeis substantially the same as that of the second hole.

60 After the first via etching process, the filling layeris removed by, for example, but not limited to, an ashing process, a photoresist stripping process, or an etching process.

1 FIG. 13 FIG. 13 FIG. 12 FIG. 1 5 712 722 712 711 10 722 721 20 5 5 71 711 712 72 721 722 Referring toand the example illustrated in, the methodproceeds to step S, where a second via etching process is performed to form a first openingand a second opening. The first openingextends downwardly from the first holeand through the first etch stop layer. The second openingextends downwardly from the second holeand through the second etch stop layer.is a schematic sectional view similar to that of, but illustrating the structure after step Sin accordance with some embodiments. After step S, a first via openingwhich includes the first holeand the first opening, and a second via openingwhich includes the second holeand the second openingare obtained.

712 722 2 x y 4 4 8 3 x y z 12 FIG. During the second via etching process, the first openingand the second openingare formed simultaneously using the same etchant. In some embodiments, the etchant used in the second via etching process include a halogen-based gas such as a chlorine-based gas, a fluorine-based gas, a bromine-based gas, or a gas mixture thereof. For example, the etchant may include chlorine (Cl), hydrogen chloride (HCl), CF(e.g., CF, CF, etc.), nitrogen fluoride (e.g, NF, etc.), hydrofluorocarbons (CHF), hydrogen bromide (HBr), other suitable etchants, or combinations thereof. In some embodiments, the second via etching process may be performed using a plasma etching process. In such case, the etchant (such as the examples described above) is ignited into a plasma remotely and then introduced into a reaction chamber in which the structure shown inis disposed for the plasma etching process.

14 FIG. 13 FIG. 15 FIG. 13 FIG. 712 722 712 7123 7122 7121 13 12 11 10 722 7222 50 7221 20 is an enlarged fragmentary view of area A shown in, andis an enlarged fragmentary view of area B shown inin accordance with some embodiments. It is worth noting that a contour or a shape of the first openingis different from that of the second opening. The first openingincludes an upper part, a middle partand a lower partwhich respectively penetrate t he sub-layers,,of the first etch stop layer. The second openinghas an upper partformed in the dielectric layerand a lower partpenetrating the second etch stop layer.

14 FIG. 13 FIG. 11 7121 12 7122 13 7123 11 12 13 11 12 13 103 12 13 13 11 11 13 13 12 Referring to, an inner surface Sof the lower parthas a first slope, an inner surface Sof the middle parthas a second slope, and an inner surface Sof the upper parthas a third slope. Since the sub-layers,,are patterned at different etch rates, the first, second and third slopes are different from each other. In other words, the inner surfaces S, S, Sare inclined with respect to an imaginary plane (P) parallel to an upper surface of the dielectric layer(see) by different angles. The second slope of the inner surface S(i.e., an infinite slope) is greater than the third slope of the inner surface S, and the third slope of the inner surface Sis greater than the first slope of the inner surface S. In some embodiments, the dielectric constant of the first dielectric material of the sub-layeris greater than the dielectric constant of the third dielectric material of the sub-layer, and the dielectric constant of the third dielectric material of the sub-layeris greater than the dielectric constant of the second dielectric material of the sub-layer.

11 12 13 1 2 3 7121 7122 7123 1 2 1 2 2 1 2 3 3 1 2 3 1 7122 7123 7123 7121 7123 7121 7123 7121 101 7121 7123 7122 7122 2 7021 71 1 7023 14 FIG. 14 FIG. 2 3 3 1 2 3 1 2 3 1 3 1 2 b To be specific, the sub-layer, the sub-layerand the sub-layerare patterned at a first etch rate (ER), a second etch rate (ER) and a third etch rate (ER), respectively. The lower, middle and upper parts,,each has an upper edge which has a first dimension (E), and a lower edge which has a second dimension (E). A dimension change (dE) is obtained by subtracting the first dimension (E) from the second dimension (E), that is, dE=E−E. For the structure shown in, the second etch rate (ER) is greater than the third etch rate (ER), and the third etch rate (ER) is greater than the first etch rate (ER). That is, ER>ER>ER. Hence, the dimension change (dE) of the middle partis greater than the dimension change (dE) of the upper part, and the dimension change (dE) of the upper partis greater than the dimension change (dE) of the lower part. That is, dE>dE>dE(or dE≈0>dE>dE). It is noted that the dimension change (dE, dE) of each of the upper and lower parts,results in a negative value, which indicates that each of the upper and lower parts,tapers in a direction toward the substrate. In the case that the dimension change (dE) results in a negative value, a tapering degree can be calculated by dividing an absolute value of the dimension change (dE) by a depth (D) of the part of the hole, i.e., tapering degree=|dE|/D. A tapering degree of the lower partis greater that of the upper part. The dimension change (dE) of the middle partis substantially equal to zero, and thus the middle partdoes not taper substantially. In some embodiments, a ratio of the second dimension (E) of the lower edge of the lower part(i.e., a bottom dimension (D) of the via openingshown in) to the first dimension (E) of the upper edge of the upper partmay less than about 1, for example, may range from about 0.3 to about 0.9, or from about 0.3 to about 0.5.

15 FIG. 21 7221 722 13 20 13 10 21 13 Referring to, an inner surface Sof the lower partof the second openinghas a slope that is substantially the same as the third slope of the inner surface S, because the second etch stop layerand the sub-layerof the first etch stop layerare made of the same dielectric material (i.e., the third dielectric material) and thus are patterned at the same etch rate (i.e., the first etch rate). In other words, the inner surfaces S, Sare inclined with respect to the imaginary plane (P) by substantially the same angle.

15 FIG. 721 7222 722 721 50 721 7222 722 0 721 22 7222 722 0 22 22 21 Still referring to, although the second holeand the upper partof the second openinglocated immediately beneath the second holeare both formed in the lower portion of the dielectric layer, the second holeis formed during the first via etching process, and the upper partof the second openingis formed during the second via etching process. In the case that the etchant used in the second via etching process is different from an etchant used in the first via etching process, an inner surface Sof the second holeand an inner surface Sof the upper partof the second openingmay be inclined with respect to the imaginary plane (P) by different angles. The slope of the inner surface Sis greater than the slope of the inner surface S, and the slope of the inner surface Sis greater than the slope of the inner surface S.

16 FIG. 14 FIG. 10 712 is a schematic sectional view similar to that of, but illustrating a variant of the configuration of the first etch stop layer, and the configuration of the first openingthus obtained in accordance with some other embodiments.

10 10 1 11 3 13 3 13 2 12 1 3 2 7121 7123 7123 7122 7123 7121 7123 7121 101 7121 7123 7122 101 2 7021 71 1 7023 12 13 13 11 16 FIG. 14 FIG. 16 FIG. 16 FIG. 1 3 3 2 1 3 2 1 3 2 3 1 b The first etch stop layershown inhas a configuration similar to that of the first etch stop layershown in, but the first etch rate (ER) of the first sub-layeris greater than the third etch rate (ER) of the third sub-layer, and the third etch rate (ER) of the third sub-layeris greater than the second etch rate (ER) of the second sub-layer. That is, ER>ER>ER. Accordingly, the dimension change (dE) of the lower partis greater than the dimension change (dE) of the upper part, and the dimension change (dE) of the upper partis greater than the dimension change (dE) of the middle part. That is, dE>dE>dE(or dE>dE>0>dE). The dimension change (dE, dE) of each of the upper and lower parts,results in a positive value, which indicates that each of the upper and lower parts,flares in the direction toward the substrate. In the case that the dimension change (dE) results in a positive value, a flaring degree can be calculated by dividing the dimension change (dE) by the depth (D) of the part of the hole, i.e., flaring degree=dE/D. A flaring degree of the lower partis greater that of the upper part. On the contrary, the middle partdoes not flare but tapers in the direction toward the substrate. In some embodiments, a ratio of the second dimension (E) of the lower edge of the lower part(i.e., a bottom dimension (D) of the via openingshown in) to the first dimension (E) of the upper edge of the upper partmay greater than about 1, for example, may range from about 1 to about 1.5. In some embodiments shown in, the dielectric constant of the second dielectric material of the sub-layeris greater than the dielectric constant of the third dielectric material of the sub-layer, and the dielectric constant of the third dielectric material of the sub-layeris greater than the dielectric constant of the first dielectric material of the sub-layer.

7121 712 10 11 712 1 2 1 2 7121 712 a In the lower partof the first opening, a bottom surface Sand the inner surface Sform an angle. When the first etch rate (ER) is greater than the second etch rate (ER), the angle 712a may be less than about 90 degrees. In some embodiments, the first etch rate (ER) is not greater than, for example, but not limited to, about ten times the second etch rate (ER), so as to permit the angle 712a to be not less than about 45 degrees. As such, poor gap filling in the lower partof the first openingmay be alleviated or eliminated.

b b b b u b b b b u 71 71 10 71 72 71 72 71 72 10 20 71 72 71 72 16 FIG. 14 FIG. 13 FIG. The bottom dimension (D) of the via openingshown inmay be larger than the bottom dimension (D) of the via openingshown indue to different configurations of the first etch stop layer. In certain embodiments, the bottom dimension (D) of the via openingmay be about 1.05 to about 1.5 times the bottom dimension (D) of the via opening, especially when the via openings,have the same upper dimension (D) (see). In some other embodiments not shown herein, the bottom dimension (D) of the via openingmay be smaller than the bottom dimension (D) of the via openingafter appropriate modification of the dielectric materials of the etch stop layers,. In certain embodiments, the bottom dimension (D) of the via openingmay be about 0.5 to 0.95 times the bottom dimension (D) of the via opening, especially when the via openings,have the same upper dimension (D).

511 512 512 511 50 12 FIG. The second via etching process is performed using the sub-layers,(see) as a hard mask. In some embodiments, the sub-layermay be consumed and removed during the second via etching process, leaving the sub-layeron the dielectric layer.

1 FIG. 13 17 FIGS.and 17 FIG. 13 FIG. 1 6 81 501 71 82 502 72 6 81 82 x Referring toand the examples illustrated in, the methodproceeds to step S, where a first conductive featureare formed to fill the first trenchand the first via opening, and a second conductive featureare formed to fill the second trenchand the second via opening, thereby obtaining the interconnecting layer M.is a schematic sectional view similar to that of, but illustrating the structure after step Sin accordance with some embodiments. The conductive features,may be also referred to as upper conductive features.

81 82 1041 1042 81 82 801 802 801 802 50 801 802 105 106 81 82 50 2 FIG. The conductive features,are respectively connected to the conductive features,. In some embodiments, the conductive features,each includes a diffusion barrier layerand a conductive portion. The diffusion barrier layeris disposed to separate the conductive portionfrom the dielectric layer. Possible materials suitable for forming the diffusion barrier layerand the conductive portionare respectively similar to those for forming the diffusion barrier layerand the conductive portionas described above with reference to, and thus the details thereof are omitted for the sake of brevity. In some embodiments, the conductive features,are formed by electrochemical plating, electroless deposition, CVD, PVD, ALD, or other suitable deposition techniques, followed by a planarization process (e.g., chemical mechanical polishing) to expose the dielectric layer.

13 17 FIGS.and 81 81 501 81 71 82 82 502 82 72 a b a b Referring to, the conductive featurehas a line portionformed in the first trenchand a via portionformed in the first via opening. The conductive featurehas a line portionformed in the second trenchand a second via portionformed in the second via opening.

81 71 82 72 71 72 81 82 b b b b. It can be observed that a contour or shape of the via portionis complied with that of the first via opening, and a contour or shape of the via portionis complied with that of the second via opening. Since the contours or shapes of the via openings,are different, the contour or shape of the via portionis different from that of the via portion

14 17 FIGS.and 81 811 711 812 712 812 13 12 11 10 812 13 12 11 7123 7122 7121 712 b Referring to, the first via portionhas an upper partformed in the first hole, and a lower partformed in the first opening. The lower parthas an upper region, a middle region and a lower region respectively extending through the sub-layers,,of the first etch stop layer. Peripheral surfaces of the upper, middle and lower regions of the lower partare respectively complied with the inner surfaces S, S, Sof the upper, middle and lower parts,,of the first opening, and thus the details thereof are omitted for the sake of brevity.

15 17 FIGS.and 82 821 721 822 722 822 50 20 822 22 21 7222 7221 722 b Referring to, the second via portionhas an upper partformed in the second hole, and a lower partformed in the second opening. The lower parthas an upper region and a lower region respectively formed in the dielectric layerand the second etch stop layer. Peripheral surfaces of the upper and lower regions of the lower partare respectively complied with the inner surfaces S, Sof the upper lower parts,of the second opening, and thus the details thereof are omitted for the sake of brevity.

17 FIG. 812 81 82 b b. In some embodiments, as shown in, the peripheral surface of the upper region of the lower partof the first via portionhas a contour or slope that is substantially the same as the contour or slope of the lower region of the lower part of the second via portion

18 FIG. 16 FIG. 18 FIG. 16 FIG. 81 71 81 71 b b is a schematic sectional view similar to that of, but further illustrating the first via portionformed in the first via opening. A contour or shape of the via portionshown inis complied with that of the first via openingshown in, and thus the details thereof are omitted for the sake of brevity.

2 x+1 x x+1 x−1 x+1 x x+1 In some embodiments, the semiconductor structuremay be further formed with an interconnect layer Mwhich is formed over the interconnect layer M. In some embodiments, the interconnect layer Mmay have a configuration similar to that of the interconnect layer M. In some other embodiments not shown herein, the interconnect layer Mmay have a configuration similar to that of the interconnect layer M. The interconnect layer Mmay be formed by a dual damascene process, a single damascene process, or other suitable back-end-of-line (BEOL) techniques.

x x 17 FIG. 81 82 81 82 81 82 50 81 82 50 81 82 a a b b b b a a b b. It is noted that the interconnect layer Mshown inis configured as a dual damascene structure which includes metal lines (i.e., the line portions,) and metal vias (i.e., the via portions,). In some other embodiments not shown herein, after appropriate modification, the interconnect layer Mmay be configured as a single damascene structure which includes the via portions,formed to penetrate the dielectric layer. In such case, the line portions,are formed in another dielectric layer which is formed over the dielectric layerafter formation of the via portions,

19 FIG. 19 FIG. 2 104 81 82 102 102 1021 1022 1021 1022 1 2 1 2 1 2 1021 1022 103 1021 1022 1021 1022 x 0 b b is a schematic sectional view illustrating the semiconductor structurein accordance with some embodiments, in which the interconnect layer Mis applied to an interconnect layer M. In such case, the conductive featuresare respectively connected to the via portions,, and are each a gate electrode of the semiconductor device. As shown in, the semiconductor deviceincludes a first transistorand a second transistor. Each of the first and second transistors,includes a channel (Ch), two source/drain portions (SD) respectively located at two opposite sides of the channel (Ch), a gate electrode (Gor G) disposed on the channel (Ch) and capable of controlling a current in the channel (Ch), a gate dielectric (not shown) disposed to separate the gate electrode (Gor G) from the channel (Ch), and two gate spacers (Sp) respectively disposed at two opposite sides of the gate electrode (Gor G). The first and second transistors,are covered by the dielectric layer. In some embodiments, a threshold voltage or other device specifications of the first and second transistors,may be different from each other. Each of the first and second transistors,may be configured as a fin-type field-effect transistor (FinFET) structure, a gate-all-around field-effect transistor (GAAFET) structure, a complementary field-effect transistor (CFET) structure which includes a lower GAAFET and an upper GAAFET sequentially formed over a substrate, a fork-sheet structure which includes two GAAFETs spaced part from each other through a wall portion which is formed on a trench isolation, or other suitable three-dimensional structures.

19 FIG. 1041 1042 1 2 1021 1022 10 20 1 2 81 82 10 20 1 2 b b As shown in, the conductive features,respectively serve as the gate electrodes (G, G) of the transistors,. The etch stop layers,are respectively formed on the gate electrodes (G, G), and each may be also referred to as a hard mask portion. The via portions,respectively extends through the etch stop layers,to be respectively connected to the gate electrodes (G, G).

0 0 0 1021 1022 50 501 502 503 81 82 81 82 103 1021 1022 10 20 1 2 1021 1022 1 10 20 1021 1022 501 103 10 20 501 103 1021 1022 502 501 81 82 501 502 10 20 1 2 4 6 502 503 502 81 82 81 82 503 81 82 503 81 82 b b a a b b b b a a b b a a. In some embodiments, the interconnect layer Mmay further include multiple metal contacts (MD) and via contacts (VD) formed to be connected to the source/drain portions (SD) of the transistors,. In some embodiments, the dielectric layermay be configured as a multi-layer structure which includes sub-layers,,stacked on each other for forming the metal contacts (MD), the via contacts (VD), the via portions,, and the line portions,therein. The interconnect layer Mare formed after formation of the dielectric layerand the transistors,. In some embodiments, formation of the interconnect layer Mmay include (i) forming the etch stop layers,respectively on the gate electrodes (G, G) of the transistors,in a manner similar to the manner as described above in step S(each of the etch stop layers,may be further patterned to have a reduced width in a direction between the two source/drain portions (SD) of a respective one of the transistors,), (ii) forming the sub-layeron the dielectric layerto cover the etch stop layers,by a suitable deposition process and/or a planarization process, (iii) forming the metal contacts (MD) which extends through the sub-layerand the dielectric layerso as to be respectively connected to the source/drain portions (SD) of the transistors,, (iv) forming the sub-layeron the sub-layerto cover the metal contacts (MD) by a suitable deposition process and/or a planarization process, (v) forming the via portions,each of which extends through the sub-layers,and a corresponding one of the etch stop layers,so as to be respectively connected to the corresponding gate electrode (Gor G) in a manner similar to the manner as described above in steps Sto S, (vi) forming the via contacts (VD) in the sub-layerso as to be respectively connected to the metal contacts (MD), (vii) forming the sub-layeron the sub-layerto cover the via portions,and the via contacts (VD) by a suitable deposition process and/or a planarization process, and (viii) forming the line portions,in the sub-layer. It is noted that, in some alternative embodiments, the via portions,may be formed after formation of the via contacts (VD), and the sub-layermay be formed after formation of the line portions,

1 2 2 x x In some embodiments, some steps in the methodmay be modified, replaced, or eliminated without departure from the spirit and scope of the present disclosure. In some alternative embodiments, the semiconductor structureand the interconnect layer Mmay further include additional features, and/or some features present in the semiconductor structureand the interconnect layer Mmay be modified, replaced, or eliminated without departure from the spirit and scope of the present disclosure.

10 20 71 72 81 82 71 72 81 1041 82 1042 10 20 71 10 11 12 13 71 10 11 12 13 81 82 b b b b b b x 0 In summary, with the provision of different configurations of the etch stop layers,, even if the layout design (e.g., size of via or contacts on a reticle or a photomask which is used in a photolithography process) is not changed, the configurations of the via openings,may be controlled to be different from each other, thereby resulting in the via portions,(respectively formed in the via openings,) having different resistances. The contact resistance between the via portionand the conductive featuremay be also different from the contact resistance between the via portionand the conductive feature. In some embodiments, the etch stop layeris configured as a multi-layered structure, and the etch stop layeris configured a single layer structure. In such case, a bottom dimension of the via openingthus formed may be adjusted by varying compositions of the etch stop layer(e.g., varying the ratios of elements or materials in each of the sub-layers,,so that during formation of the via openingin the etch stop layer, the etch rate of each of the sub-layers,,can be individually adjusted). Since the resistance of the via portions,can be changed independently, the interconnect layer Mor M) of this disclosure provides flexibility in circuit design.

In accordance with some embodiments of the present disclosure, a method for manufacturing an interconnect structure includes: forming a first etch stop layer and a second etch stop layer respectively on a first lower conductive portion and a second lower conductive portion, a configuration of the first etch stop layer being different from a configuration of the second etch stop layer, the first lower conductive portion being spaced apart from the second lower conductive portion; forming a dielectric layer to cover the first etch stop layer and the second etch stop layer; performing a first etching process to form a first hole and a second hole in the dielectric layer so as to expose at least one of the first etch stop layer and the second etch stop layer; performing a second etching process to form a first opening which extends downwardly from the first hole and through the first etch stop layer, and to form a second opening which extends downwardly from the second hole and through the second etch stop layer; and after the second etching process, forming a first upper conductive portion in the first hole and the first opening, and forming a second upper conductive portion in the second hole and the second opening.

In accordance with some embodiments of the present disclosure, the first etch stop layer is configured as a multi-layered structure, and the second etch stop layer is configured as a single layer structure.

In accordance with some embodiments of the present disclosure, the first etch stop layer includes a first sub-layer which is formed on the first lower conductive portion and which is made of a first dielectric material, and a second sub-layer which is formed on the first sub-layer opposite to the first lower conductive portion, and which is made of a second dielectric material. In the second etching process, the second dielectric material has an etch rate that is different from an etch rate of the first dielectric material.

In accordance with some embodiments of the present disclosure, the second etch stop layer is made of the second dielectric material.

In accordance with some embodiments of the present disclosure, formation of the first etch stop layer and the second etch stop layer includes forming a first film to cover the first lower conductive portion and the second conductive portion, the first film including the first dielectric material, patterning the first film to expose the second lower conductive portion such that the first film is formed into the first sub-layer of the first etch stop layer, and forming a second film which includes a first portion disposed on the first sub-layer and a second portion disposed on the second conductive portion. The first portion serves as the second sub-layer of the first etch stop layer, and the second portion serves as the second etch stop layer.

In accordance with some embodiments of the present disclosure, during the second etching process, the second sub-layer is patterned to form an upper part of the first opening, and the first sub-layer is patterned to form a lower part of the first opening. A slope of an inner surface of the upper part is different from a slope of an inner surface of the lower part.

In accordance with some embodiments of the present disclosure, a slope of an inner surface of the second opening is the same as the slope of the inner surface of the upper part.

In accordance with some embodiments of the present disclosure, during the second etching process, the first opening and the second opening are formed simultaneously using a same etchant.

In accordance with some embodiments of the present disclosure, a method for manufacturing an interconnect structure includes: forming a first etch stop layer on a first lower conductive portion; forming a second etch stop layer on a second lower conductive portion, the first lower conductive portion being spaced apart from the second lower conductive portion; forming a dielectric layer to cover the first etch stop layer and the second etch stop layer; forming a first upper conductive portion that extends through the dielectric layer and the first etch stop layer; and forming a second upper conductive portion that extends through the dielectric layer and the second etch stop layer. A configuration of the first etch stop layer is different from a configuration of the second etch stop layer so that the first upper conductive portion and the second upper conductive portion are formed to have different contours.

In accordance with some embodiments of the present disclosure, the first etch stop layer and the second etch stop layer are made of different materials.

In accordance with some embodiments of the present disclosure, a thickness of the first etch stop layer is greater than a thickness of the second etch stop layer.

In accordance with some embodiments of the present disclosure, the first etch stop layer includes a first sub-layer which is formed on the first lower conductive portion and which is made of a first dielectric material, and a second sub-layer which is formed on the first sub-layer opposite to the first lower conductive portion, and which is made of a second dielectric material that is different from the first dielectric material. The second etch stop layer is made of one of the first dielectric material and the second dielectric material.

In accordance with some embodiments of the present disclosure, the first dielectric material includes silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, silicon carbon nitride, silicon oxycarbon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride. The second dielectric material includes silicon oxide, silicon carbide, silicon nitride, silicon oxynitride, silicon carbon nitride, silicon oxycarbon nitride, aluminum oxide, aluminum nitride, or aluminum oxynitride.

In accordance with some embodiments of the present disclosure, the first lower conductive portion serves as a first gate electrode which is capable of controlling a current in a first channel disposed beneath the first gate electrode. The second lower conductive portion serves as a second gate electrode which is capable of controlling a current in a second channel disposed beneath the second gate electrode.

In accordance with some embodiments of the present disclosure, the first etch stop layer is configured as a multi-layered structure, and the second etch stop layer is configured as a single layer structure.

In accordance with some embodiments of the present disclosure, an interconnect structure includes: a first lower conductive portion and a second lower conductive portion which are formed in a lower dielectric layer and which are spaced apart from each other; a first etch stop layer and a second etch stop layer respectively formed on the first lower conductive portion and the second lower conductive portion, a configuration of the first etch stop layer being different from a configuration of the second etch stop layer; an upper dielectric layer formed to cover the first etch stop layer and the second etch stop layer; a first upper conductive portion extending through the upper dielectric layer and the first etch stop layer so as to be electrically connected to the first lower conductive portion; and a second upper conductive portion extending through the upper dielectric layer and the second etch stop layer so as to be electrically connected to the second lower conductive portion.

In accordance with some embodiments of the present disclosure, the first etch stop layer is configured as a multi-layered structure, and the second etch stop layer is configured as a single layer structure.

In accordance with some embodiments of the present disclosure, the first etch stop layer includes a first sub-layer which is formed on the first lower conductive portion and which is made of a first dielectric material, and a second sub-layer which is formed on the first sub-layer opposite to the first lower conductive portion, and which is made of a second dielectric material. The second dielectric material is different from the first dielectric material. The second etch stop layer is made of one of the first dielectric material and the second dielectric material.

In accordance with some embodiments of the present disclosure, the first upper conductive portion has an upper part extending through the upper dielectric layer, and a lower part extending through the first etch stop layer. The lower part has an upper region extending through the second sub-layer and a lower region extending through the first sub-layer. A slope of a peripheral surface of the upper region is different from a slope of a peripheral surface of the lower region.

In accordance with some embodiments of the present disclosure, the second upper conductive portion has an upper part extending through the upper dielectric layer, and a lower part extending through the second etch stop layer. The second etch stop layer is made of the second dielectric material, so that a slope of a peripheral surface of the lower part of the second upper conductive portion is the same as the slope of the peripheral surface of the upper region.

In accordance with some embodiments of the present disclosure, a method for manufacturing an interconnect structure includes: forming a first etch stop layer on a first lower conductive portion; forming a second etch stop layer on a second lower conductive portion, the first lower conductive portion being spaced apart from the second lower conductive portion; forming a dielectric layer to cover the first etch stop layer and the second etch stop layer; forming a first upper conductive portion that extends through the dielectric layer and the first etch stop layer; and forming a second upper conductive portion that extends through the dielectric layer and the second etch stop layer. A contour of an upper part of the first upper conductive portion is the same as a contour of an upper part of the second upper conductive portion, and a contour of a lower part of the first upper conductive portion is different from a contour of a lower part of the second upper conductive portion.

In accordance with some embodiments of the present disclosure, the first etch stop layer is configured as a multi-layered structure, and the second etch stop layer is configured as a single layer structure.

In accordance with some embodiments of the present disclosure, the first etch stop layer includes a first sub-layer which is formed on the first lower conductive portion and which is made of a first dielectric material, and a second sub-layer which is formed on the first sub-layer opposite to the first lower conductive portion, and which is made of a second dielectric material that is different from the first dielectric material. The second etch stop layer is made of one of the first dielectric material and the second dielectric material.

In accordance with some embodiments of the present disclosure, the dielectric layer is made of a third dielectric material that is different from the first dielectric material and the second dielectric material.

In accordance with some embodiments of the present disclosure, the lower part of the first upper conductive portion and the lower part of the second upper conductive portion respectively penetrate the first etch stop layer and the second etch stop layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes or structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.