Package for a Lateral Power Transistor

This disclosure relates generally to the technique of semiconductor packaging, and in particular to a transistor package for a lateral transistor device.

Transistor packages are widely used as electronic switches in a variety of electronic circuits. Higher efficiency, increased power density, lower switching losses, faster switching times, lower device parasitics and lower cost are among the key goals for next generation transistor package design.

Conventional approaches to reduce device parasitics (in particular drain/source inductance) for fast switching and to improve thermal behavior are to use leadless packages and/or to use clips for connecting the load electrodes of a semiconductor transistor chip to the respective terminals of the transistor package.

According to an aspect of the disclosure, a transistor package comprises a semiconductor transistor chip having a first surface and a second surface opposite the first surface. The semiconductor transistor chip comprises one or a plurality of first load electrodes, one or a plurality of second load electrodes and a control electrode on the first surface. A leadframe faces the first surface of the semiconductor transistor chip. The leadframe comprises a first terminal, a second terminal and a control terminal of the transistor package. The first terminal, the second terminal and the control terminal are exposed at a bottom of the transistor package. The first terminal is electrically coupled to the one or a plurality of first load electrodes. The second terminal is electrically coupled to the one or a plurality of second load electrodes. The control terminal is electrically coupled to the control electrode. The first terminal is aligned with a first side of the transistor package. The second terminal is aligned with a second side opposite the first side of the transistor package. The control terminal is aligned with a third side of the transistor package. The third side of the transistor package connects between the first side and the second side of the transistor package.

According to another aspect of the disclosure, an electrical circuitry comprises a circuit board. A plurality of transistor packages as described above are mounted side-by-side in a lateral direction on the circuit board. The first terminals of the transistor packages are electrically connected by a first conductor provided by the circuit board. The second terminals of the transistor packages are electrically connected by a second conductor provided by the circuit board. The control terminals of the transistor packages are electrically connected by a control conductor provided by the circuit board. The first conductor and the second conductor are spaced apart from each other by a spacing region extending along the lateral direction between the first conductor and the second conductor. The control conductor extends within the spacing region.

It is to be understood that the features of the various exemplary embodiments and examples described herein may be combined with each other unless specifically noted otherwise.

1 7 FIGS.to 1 7 FIGS.to The illustrations ofare true to scale. Therefore, dimensional relationships such as “longer than”, “shorter than” etc. may be directly taken from and are disclosed by the illustrations of, for example.

As used in this specification, the terms “electrically connected” or “electrically coupled” or similar terms are not meant to mean that the elements are directly contacted together; intervening elements may be provided between the “electrically connected” or “electrically coupled” elements, respectively. However, in accordance with the disclosure, the above-mentioned and similar terms may, optionally, also have the specific meaning that the elements are directly contacted together, i.e. that no intervening elements are provided between the “electrically connected” or “electrically coupled” elements, respectively.

Further, the words “over” or “beneath” with regard to a part, element or material layer formed or located or arranged “over” or “beneath” a surface may be used herein to mean that the part, element or material layer be located (e.g. placed, formed, arranged, deposited, etc.) “directly on” or “directly under”, e.g. in direct contact with, the implied surface. The word “over” or “beneath” used with regard to a part, element or material layer formed or located or arranged “over” or “beneath” a surface may, however, either be used herein to mean that the part, element or material layer be located (e.g. placed, formed, arranged, deposited, etc.) “indirectly on” or “indirectly under” the implied surface, with one or more additional parts, elements or layers being arranged between the implied surface and the part, element or material layer.

1 2 FIGS.and 1 FIG. 100 120 140 120 120 120 120 140 120 120 120 120 120 100 Referring to, a transistor package, according to a first example, includes a semiconductor transistor chipand a leadframe. The semiconductor transistor chiphas a first surfaceA and a second surfaceB opposite the first surfaceA. The leadframeis facing the first surfaceA of the semiconductor transistor chip. Inonly the edge of the first surfaceA is visible since the second surfaceB is the top surface of the semiconductor transistor chipwhen accommodated in the transistor package.

140 140 1 140 2 140 3 140 1 140 2 140 3 100 140 1 140 2 140 3 140 120 140 1 140 2 140 3 100 3 FIG. The leadframeincludes a first terminal_, a second terminal_and a control terminal_. The first, second and control terminals_,_,_are transistor package terminals, i.e. are configured to electrically connect the transistor packageto external circuitry such as, e.g., circuitry implemented on an application board (not shown). The first terminal_, the second terminal_and the control terminal_of the leadframeare separate from each other. They may be connected e.g. only to the semiconductor transistor chip, as will be described in more detail further below. The first terminal_, the second terminal_and the control terminal_are exposed at a bottom of the transistor package(see also).

120 120 120 160 1 160 2 160 3 140 1 140 2 140 3 140 2 FIG. The semiconductor transistor chipcomprises one or a plurality of first load electrodes, one or a plurality of second load electrodes and a control electrode on the first surfaceA of the semiconductor transistor chip.illustrates a first contact pad_, a second contact pad_and a control contact pad_, which are electrically connected (e.g. directly bonded) to the first terminal_, the second terminal_and the control terminal_of the leadframe, respectively.

160 1 160 2 160 3 120 120 140 140 1 140 2 140 3 140 The first contact pad_, the second contact pad_and the control contact pad_may, e.g., be formed by the first load electrode, the second load electrode and the control electrode of the semiconductor transistor chip, respectively. In this case, the semiconductor transistor chipis directly bonded (e.g. glued, soldered or sintered) to the leadframe(i.e. to the corresponding first, second and control terminals_,_,_of the leadframe).

160 1 160 2 160 3 160 1 160 2 120 160 3 160 1 160 2 160 3 120 1 2 FIGS.and 10 13 FIGS.to In other examples, the first contact pad_, the second contact pad_and the control contact pad_may be provided by an electrical redistribution structure (not shown in, reference is made to the examples of). The electrical redistribution structure is configured to re-route one or the plurality of first load electrodes to the first contact pad_, one or plurality of the second load electrodes to the second contact pad_and the control electrode of the semiconductor transistor chipto the control contact pad_of the electrical redistribution structure. To that end, the first contact pad_, the second contact pad_and the control contact pad_are exposed at a surface of the electrical redistribution structure facing away from the semiconductor transistor chip.

120 120 120 120 100 The semiconductor transistor chipis a lateral device, i.e. the first load electrode, the second load electrode and the control electrode are all disposed on the same (first) surfaceA of the semiconductor transistor chip. In other words, the lateral semiconductor transistor chipis implemented in the transistor packagein a flip-chip orientation.

120 The semiconductor transistor chipmay be configured as a power semiconductor chip. Power semiconductor chips are suitable, in particular, for switching high currents and/or medium or high voltages (e.g. more than 50 V or 100 V or 200 V or 300 V blocking voltage). In particular, exemplary transistor packages as disclosed herein may operate in the medium voltage (MV) range, in which the blocking voltage is equal to or greater than or less than 200 V or 150 V or 100 V or 50 V.

120 120 120 120 The semiconductor transistor chipmay be of different types. Examples described herein are, in particular, directed e.g. to HEMT (high electron mobility transistor) devices. More specifically, the semiconductor transistor chipsreferred to herein may, e.g., be III-V compound semiconductor chips having, e.g., a high band gap. The semiconductor transistor chipmay, e.g., be a GaN chip. In this case, the GaN chipmay, e.g., be a lateral GaN-on-substrate device such as a GaN-on-Si device or a GaN-on-SiC device or a GaN-on-sapphire device, for example.

140 1 140 2 160 1 120 160 2 120 Here and in all further examples, the first terminal_may be a drain (D) package terminal and the second terminal_may be a source(S) package terminal. Likewise, the first contact pad_may be or may be connected (via the redistribution structure mentioned above) to one or a plurality of (first) drain (D) electrodes of the semiconductor transistor chip, and the second contact pad_may be or may be connected (via the redistribution structure) to one or a plurality of (second) source electrodes of the semiconductor transistor chip.

1 2 FIGS.and 100 180 120 140 180 As illustrated in semi-transparent representation in, the transistor packagemay include an encapsulant. For instance, a molding process may be carried out to encapsulate the semiconductor transistor chipmounted on the leadframewith a mold material. In other words, the transistor package may include a molded encapsulantforming, e.g., the package body.

3 FIG. 100 100 180 140 1 140 2 140 3 140 140 1 140 2 140 3 100 illustrates a bottom view of the transistor package. The bottom of the transistor packagemay comprise or be composed of areas formed by a bottom surface of the encapsulantand areas formed by a bottom surface of the first and second terminals_,_and the control terminal_of the leadframe. In other words, the first terminal_, the second terminal_and the control terminal_are exposed at the bottom of the transistor package.

140 1 100 1 100 140 2 100 2 100 1 100 140 3 100 3 100 100 3 100 100 1 100 2 100 The first terminal_is aligned with a first side_of the transistor package. The second terminal_is aligned with a second side_opposite the first side_of the transistor package. The control terminal_is aligned with a third side_of the transistor package. The third side_of the transistor packageconnects between the first side_and the second side_of the transistor package.

100 140 1 140 2 140 3 100 180 140 1 140 2 140 3 100 140 1 140 2 140 3 180 100 The transistor packagemay, e.g., be a leadless package. The first terminal_, the second terminal_and/or the control terminal_may extend and terminate at the edge of the transistor packageformed, e.g., by the encapsulant. All terminals_,_,_may be flush with the bottom of the transistor package. More specifically, the bottom surfaces of the terminals_,_,_and the bottom surface of the exposed areas of the encapsulantmay all lie in the same (bottom) plane of the transistor package.

140 1 140 1 100 1 100 140 1 140 1 100 140 2 140 2 100 2 100 140 2 140 2 100 140 3 100 100 3 100 140 3 100 1 100 2 100 f f f f The first terminal_may have a plurality of fingers_which are exposed at the edge at the first side_of the transistor package. Parts of the first terminal_between these fingers_may be offset from this edge of the transistor package. The second terminal_may have a plurality of fingers_which are exposed at the edge at the second side_of the transistor package. Parts of the second terminal_between these fingers_may be offset from this edge of the transistor package. The control terminal_may, e.g., be exposed at the edge of the transistor packageat the third side_of the transistor package. Further, the control terminal_may be offset from the transistor package edge at the first side_and at the second side_of the transistor package.

140 1 140 2 140 3 100 1 100 2 100 3 100 100 100 1 100 2 100 3 A terminal_,_,_that is aligned with a specific side_,_,_of the transistor packagemay, e.g., be exposed at the edge of the transistor packageat the respective transistor package side_,_and_.

140 1 140 2 140 3 140 1 140 2 140 3 140 140 100 100 180 140 1 140 1 140 2 140 2 140 3 100 100 3 6 7 FIGS.,, 4 4 FIGS.A andB 4 4 FIGS.A andB f f The outlines of the terminals_,_,_as shown in the bottom views (e.g.) represent the lower (i.e. footprint) surface of the respective terminal. The outlines of the terminals_,_,_at their upper surface may be different. In other words, the leadframemay be a half etch type leadframe.illustrate outlines of a bottom half etch and a top half etch of the leadframeand the outline_OL of the transistor packageformed by the encapsulant. As shown in, the fingers_of the first terminal_and/or the fingers_of the second terminal_and/or the control terminal_may, e.g., protrude over the outline_OL of the transistor package.

100 140 160 1 160 2 160 3 140 140 120 120 That is, the footprint of the transistor packageis, e.g., defined by the bottom half etch BHE_OL of the leadframe. The contact area between the first contact pad_, the second contact pad_, the control contact pad_and the leadframeis defined by the top half etch THE_OL of the leadframe. The outline of the semiconductor transistor chipis indicated by the reference sign_OL.

140 140 1 140 2 140 3 160 1 160 2 160 3 120 120 140 1 140 2 140 3 100 10 13 FIGS.to In more general terms, the leadframeand hence the first, second and/or control terminals_,_,_thereof may be of a half etch type providing for top surface areas and bottom (footprint) surface areas which are different from each other in shape. This allows to “re-route” the layout of the contact pads_,_,_(which may or may not be identical with the layout of the electrodes on the first surfaceA of the semiconductor transistor chip—see e.g.) to the footprint layout of the terminals_,_,_at the bottom of the transistor package.

5 FIG. 2 FIG. 500 180 120 160 1 160 2 160 3 is a perspective top view of a second example of a transistor package. Similar tothe encapsulantand the semiconductor transistor chipare shown semi-transparent, while the first, second and control contact pads_,_,_are visible.

500 100 The transistor packageis designed largely in accordance with the features described for the transistor package. Therefore, to avoid reiteration, reference is made to the above disclosure.

500 100 140 3 140 1 140 2 140 1 140 2 500 140 3 6 FIG. The transistor packagedistinguishes from the transistor packagein that the control terminal_is arranged between the first terminal_and the second terminal_. Referring to, the first terminal_and the second terminal_are spaced apart at the bottom of the transistor packageby a gap. The control terminal_is located within this gap.

100 3 500 140 1 140 2 140 3 More specifically, there is an imaginary straight line parallel to the transistor package edge at the third side_of the transistor packagewhich intersects with the first terminal_, the second terminal_and the control terminal_.

140 2 140 1 140 3 6 FIG. The second terminal_may have a polygonal shape with a cutout corner area, see. The cutout corner area faces the first terminal_and the control terminal_is located within the cutout corner area.

140 1 500 140 2 500 For example, the first terminal_may be the drain (D) terminal of the transistor packageand the second terminal_may be the source(S) terminal of the transistor package.

140 1 140 2 140 3 100 500 100 500 180 140 1 140 2 140 3 140 2 140 3 140 1 140 2 140 1 140 3 100 500 140 3 100 3 100 500 3 6 7 FIGS.,and The layout of the first, second and control terminals_,_,_at the bottom of the transistor package,should be optimized in terms of prevention of creepage. Creepage occurs at the bottom of the transistor package,and is dependent on the mold material composition of the encapsulantand the spacings between the terminals_,_,_. Typically, creepage between the source(S) and gate (G) terminal (e.g. the second terminal_and the control terminal_) is not critical, since the source terminal is usually on common ground and the gate terminal is usually on a potential which is only a few volts offset from common ground. However, creepage between the drain (D) and source(S) terminals (e.g. the first and second terminals_and_) and creepage between the drain (D) terminal (e.g. first terminal_) and the gate (G) terminal (control terminal_) is critical since the drain (D) terminal is usually on high voltage during operation. Therefore, a sufficient creepage distance at the bottom of the transistor package,should be maintained between these terminals. Considering the package outline constraints as illustrated inthis condition is much easier to meet with the control terminal_aligned with the third side_of the transistor package,than with conventional leadframe terminal layouts.

120 100 500 120 120 100 500 Due to the face-down orientation of the semiconductor transistor chip, the transistor packages,disclosed herein allow to achieve low parasitics for fast switching and high thermal connectivity. Further, given a GaN semiconductor transistor chipis used, the face-down orientation of the GaN transistor chipallows to align the transistor package footprint with the footprints of common MOSFET (Metal Oxide Semiconductor Field Effect Transistor) packages which, however, cannot fulfill the fast switching requirements of the transistor package,described herein.

100 500 800 500 810 800 500 100 500 810 8 FIG. The transistor packages,disclosed herein further provide high suitability for footprint parallelization when mounted on a circuit board.illustrates an example of an electrical circuitrywhich comprises two exemplary transistor packagesmounted on a circuit board, e.g. a PCB (printed circuit board) or a ceramic based circuit board (e.g. a DCB (direct ceramic bonded) carrier). The electrical circuitryincludes a plurality (in this example: two) of transistor packages(or, in other examples, transistor packages). The transistor packagesare mounted side-by-side in a lateral direction on the circuit board.

820 1 820 2 810 820 1 820 2 810 500 810 A first conductor_and a second conductor_are provided by the circuit board. The first conductor_and/or the second conductor_may, e.g., be conductor tracks of the circuit boardwhich are configured to connect the transistor packagesto further circuitry (not shown) which may, e.g., also be mounted on the circuit board.

140 1 500 820 1 140 2 500 820 2 140 3 500 820 3 810 The first terminals_of the transistor packagesare electrically connected to each other by the first conductor_. The second terminals_of the transistor packagesare electrically connected to each other by the second conductor_. Further, the control terminals_of the transistor packagesare electrically connected to each other by a control conductor_provided on the circuit board.

820 1 820 2 830 820 1 820 2 820 3 830 830 140 1 140 2 500 500 810 820 1 820 2 820 3 8 FIG. The first conductor_and the second conductor_are spaced apart from each other by a spacing regionextending along the lateral direction between the first conductor_and the second conductor_. The control conductor_extends within the spacing region. The spacing regionmay align with and be of the same spacing distance as the gap between the first terminal_and the second terminal_at the bottom of the transistor package. This allows to always maintain sufficient creepage distance between drain and source and between drain and gate not only at the bottom of the transistor packagebut also at the circuit board. The first conductor_, the second conductor_and the control conductor_are shown hatched in.

800 100 500 100 500 140 3 140 3 In the electrical circuitrythe device parasitics, in particular the drain-source inductance, can be kept low. Inside the transistor package,this is largely due to the flip-chip structure mentioned above. Outside the transistor package,, the footprint layout and in particular the position of the control terminals_(gates) enable direct wiring of the control terminals_along the shortest possible path and thus with the lowest possible stray inductance.

100 500 100 500 100 500 100 500 Hence, in some examples, the transistor packages,are GaN transistor packages which may provide for footprint parallelization among neighboring GaN transistor packages,. Further, the GaN transistor packages,may, optionally, provide for footprint compatibility with common MOSFET transistor packages. In this case the transistor packages,may provide a seamless replacement option for standard MOSFETs by next generation MV GaN devices without major layout changes at circuit board level.

800 9 FIG. The footprint parallelization of the electrical circuitrymay provide distinct performance advantages for various electrical circuitries, among them, e.g., half-bridge circuitry. Half-bridge circuitry is used for buck converters, e.g. for a DC-DC buck converter as exemplarily shown in.

900 910 920 140 3 910 920 930 As known in the art, a half-bridge circuitryincludes a high-side power switchand a low side power switch. The control terminals_(e.g. gates) of the high-side power switchand/or of the low-side power switchmay be controlled by a controller.

100 500 For half-bridge circuitry, in particular for buck converters, the efficiency is one of the key performance indicators. In some cases, especially to reduce the losses at the low-side, a parallel setup of transistor packages,seems advantageous.

9 FIG. 8 FIG. 920 800 820 1 940 900 820 2 820 3 930 In the example shown in, the low-side power switchmay be implemented by a circuitryas shown in. In this case, the first conductor_may be connected to a switch nodeof the half-bridge circuitry, the second conductor_may be connected to common ground and the third conductor_may, e.g., be connected to the controller.

910 800 820 2 940 900 810 2 960 900 820 3 930 8 FIG. Optionally, the high-side power switchmay additionally or alternatively be implemented by a circuitryas shown in. In this case, the second conductor_may be connected to the switch nodeof the half-bridge circuitry, the first conductor_may be connected to an inputof the half-bridge circuitryand the third conductor_may, e.g., be connected to the controller.

940 950 900 960 900 930 The switch nodemay be connected to an outputof the half-bridge circuitry. The inputof the half-bridge circuitrymay, e.g., also be connected to the controller.

10 FIG. 120 120 120 is a top view on a conventional layout of contact pads of a semiconductor transistor chip. In this example the semiconductor transistor chipis, e.g., a lateral GaN-on-Si device. The semiconductor chipmay operate in the MV range with a blocking voltage of e.g. about 100 V.

1060 1 1060 2 1060 1 120 1060 2 120 1060 3 10 FIG. A plurality of first contact pads_and a plurality of second contact pads_may be provided. In the example shown in, the first contact pads_are drain (D) pads that are connected to drain electrode(s) (not visible) of the semiconductor transistor chip, and the second contact pads_are source(S) pads that are connected to source electrode(s) (not visible) of the semiconductor transistor chip. Further, a control contact pad_(e.g. a gate (G) pad) is provided.

1060 1 1060 2 1060 3 120 1060 1 1060 2 1060 3 The conventional layout of contact pads_,_,_of the semiconductor transistor chipmay be provided by a conventional redistribution structure configured to re-route the plurality of first and second load electrodes (not shown) and the control electrode (not shown) to the plurality of first contact pads_, the plurality of second contact pads_and the control contact pad_, respectively.

1060 1 120 1060 2 1060 1 1060 1 1060 2 1060 1 1060 2 1060 3 120 10 FIG. The plurality of first contact pads_may be arranged in a number of (horizontal) rows parallel to the longitudinal side of the semiconductor transistor chip. Likewise, the plurality of second contact pads_may be arranged in a number of (horizontal) rows parallel with the rows of the first contact pads_. In the example shown inthe rows of first contact pads_and the rows of second contact pads_are interleaved (or alternating) and the first and second contact pads_,_are offset from each other in the longitudinal direction. The control contact pad_may be arranged at a corner of the semiconductor transistor chip.

1060 1 1060 2 1060 3 100 500 1060 1 1060 2 1060 3 10 FIG. This conventional layout of contact pads_,_,_is apparently inappropriate for use in a transistor package,as described above. Therefore, an exemplary redistribution structure is described in the following which may overcome the limitations of the conventional redistribution structure forming a layout of contact pads_,_,_as shown in.

11 13 FIGS.to 2 5 13 FIGS.,, 120 120 120 illustrate an exemplary redistribution structure applied to the semiconductor transistor chipover the first surfaceA. The redistribution structure may comprise one or more structured metal layers between which structured insulating layers (not shown) are disposed. The stack of alternating structured metal layers and insulating layers allows to arrive at a contact pad layout (see e.g.) which is geometrically different from the layout of the load electrodes (not shown) of the semiconductor transistor chip.

11 FIG. 11 FIG. 1 1 120 illustrates routing in a first structured metal MET. As apparent from, routing in METmay be implemented by metal stripes oriented perpendicular to the longitudinal side of the semiconductor chipand being associated in alternating order with D and S.

12 FIG. 12 FIG. 2 1 1 2 2 120 illustrates a second structured metal METarranged over the first structured metal METwith an insulating layer (not shown) between METand MET. As apparent from, the second metal METrerouting may serve to reposition D metal and S metal to opposite longitudinal sides of the semiconductor transistor chip.

13 FIG. 10 FIG. 13 FIG. 160 1 160 2 160 3 160 1 160 2 160 3 2 2 1360 2 illustrates the layout of a first contact pad (D)_, a second contact pad(S)_and a control contact pad (G)_. The first contact pad (D)_, the second contact pad(S)_and the control contact pad (G)_may be formed by areas of metal METof the redistribution structure which may, e.g., be defined by covering the interdigitated central region of the metal METstructure by an insulating layer(e.g. a longitudinal stripe of a dielectric material applied on the second structured metal MET). Compared to the conventional contact pad layout of, the exemplary contact pad layout ofis differently designed in order to achieve an aggregation of all source contacts and drain contacts.

160 1 120 100 500 140 1 160 2 120 100 500 140 2 160 3 120 100 500 140 3 160 1 160 2 160 3 140 1 140 2 140 3 In other words, the first contact pad_is coupled to the plurality of first load electrodes (not shown) of the semiconductor transistor chipand, in the transistor package,, electrically coupled to the first terminal_. The second contact pad_is coupled to the plurality of second load electrodes (not shown) of the semiconductor transistor chipand, in the transistor package,, electrically coupled to the second terminal_. The control contact pad_is electrically coupled to the control load electrode (not shown) of the semiconductor transistor chipand, in the transistor package,, electrically coupled to the control terminal_. As mentioned before, electrical bonding between the redistribution structure (i.e. the first, second and control contact pads_,_,_) and the package terminals (i.e. the first, second and control terminals_,_,_) may be carried out by soldering or, e.g., other bonding techniques such as e.g. sintering or gluing.

The following examples pertain to further aspects of the disclosure:

Example 1 is a transistor package which comprises a semiconductor transistor chip having a first surface and a second surface opposite the first surface. The semiconductor transistor chip comprises one or a plurality of first load electrodes, one or a plurality of second load electrodes and a control electrode on the first surface. A leadframe faces the first surface of the semiconductor transistor chip. The leadframe comprises a first terminal, a second terminal and a control terminal of the transistor package. The first terminal, the second terminal and the control terminal are exposed at a bottom of the transistor package. The first terminal is electrically coupled to the one or a plurality of first load electrodes. The second terminal is electrically coupled to the one or a plurality of second load electrodes. The control terminal is electrically coupled to the control electrode. The first terminal is aligned with a first side of the transistor package. The second terminal is aligned with a second side opposite the first side of the transistor package. The control terminal is aligned with a third side of the transistor package. The third side of the transistor package connects between the first side and the second side of the transistor package.

In Example 2, the subject matter of Example 1 can optionally include wherein the control terminal is arranged between the first terminal and the second terminal.

In Example 3, the subject matter of Example 1 or 2 can optionally include wherein the first terminal and the second terminal are spaced apart at the bottom of the package by a gap, and the control terminal is located within the gap.

In Example 4, the subject matter of any preceding Example can optionally include wherein the first terminal is the drain terminal of the transistor package, the second terminal is the source terminal of the transistor package, and wherein the second terminal has a polygonal shape with a cutout corner area, the cutout corner area faces the first terminal and the control terminal is located within the cutout corner area.

In Example 5, the subject matter of any preceding Example can optionally include wherein the semiconductor transistor chip is a GaN chip.

In Example 6, the subject matter of Example 5 can optionally include wherein the GaN chip is a lateral GaN-on-Si device.

In Example 7, the subject matter of Example 5 or 6 can optionally include wherein the semiconductor transistor chip comprises a plurality of first load electrodes and a plurality of second load electrodes, the transistor package further comprising: an electrical redistribution structure configured to re-route the plurality of first load electrodes to one first contact pad and the plurality of second load electrodes to one second contact pad, wherein the first contact pad and the second contact pad are exposed at a surface of the electrical redistribution structure facing away from the semiconductor transistor chip, and wherein the first contact pad is electrically coupled to the first terminal and the second contact pad is electrically coupled to the second terminal.

In Example 8, the subject matter of Example 7 can optionally include wherein the plurality of first load electrodes and the plurality of second load electrodes are arranged in an alternating order.

In Example 9, the subject matter of Example 8 can optionally include wherein the first contact pad is soldered or sintered or glued to the first terminal and the second contact pad is soldered or sintered or glued to the second terminal.

In Example 10, the subject matter of any of the preceding Examples can optionally include wherein the transistor package comprises a molded encapsulant.

In Example 11, the subject matter of any of the preceding Examples can optionally include wherein the transistor package comprises a power switch configured to switch voltages equal to or greater than 50 V or 100 V or 150 V or 200 V.

Example 12 is an electrical circuitry comprising: a circuit board; a plurality of transistor packages of any of the preceding Examples, the transistor packages are mounted side-by-side in a lateral direction on the circuit board, wherein the first terminals of the transistor packages are electrically connected by a first conductor provided by the circuit board; the second terminals of the transistor packages are electrically connected by a second conductor provided by the circuit board; and the control terminals of the transistor packages are electrically connected by a control conductor provided by the circuit board; wherein the first conductor and the second conductor are spaced apart from each other by a spacing region extending along the lateral direction between the first conductor and the second conductor, and wherein the control conductor extends within the spacing region.

Example 13 is a half-bridge circuitry comprising a high-side power switch and a low-side power switch, wherein at least one of the high-side power switch and the low-side power switch comprises the electrical circuitry of Example 12.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.