Word Line Decoder, Control Method of Memory Device and Word Line Drive Circuit

The disclosure relates to erase operation techniques for memory devices, and more particularly, to a word line decoder, a control method of a memory device, and a word line drive circuit.

A flash memory device is consisted of a plurality of cell array blocks. These cell array blocks may share a common P-well layer in the flash memory device. For instance, the flash memory device may have 4096 bit lines and 512 word lines in a single common P-well layer of cell array blocks. Since several cell array blocks or sectors share the common P-well layer, while an erase flow algorithm of the flash memory device is performed, deselected cell array blocks/sectors may loss charge by a P-well bias voltage of the common P-well layer. For dealing with the problem with charge loss through the common P-well layer, it may perform a refresh step in the erase flow algorithm for moving the threshold voltage of the disturbed cells to original target threshold voltage area for recovering these disturbed bits. However, the refresh step may occupy not a short time, and it may create extra program disturb as well as cell degradation according to hot electron injection (HEI).

The disclosure is directed to a word line decoder and a control method of a memory device, an operation time period of an erase flow algorithm can be reduced and saved, the drain stress of a deselected cell in the memory device is reduced, and it results in better endurance for the cells in the memory device.

The disclosure provides a word line decoder. The word line decoder includes a word line drive circuit. The word line drive circuit includes a first drive transistor and a second drive transistor. A first terminal of the first drive transistor receives a first signal, and a control terminal of the first drive transistor receives a first control signal. A first terminal of the second drive transistor is coupled to a second terminal of the first drive transistor, a second terminal of the second drive transistor receives a revised global word line voltage, and a control terminal of the second drive transistor receives a global word line voltage. The first terminal of the second drive transistor and the second terminal of the first drive transistor are coupled to a gate terminal of one of a plurality of cells in a memory array. In an erase operation and the one of the plurality of cells is not selected for erase, the first control signal is enabled to enable the first transistor, the first signal is a Hi-Z state, and the first signal is coupled to the gate terminal of the one of the plurality of cells through the first drive transistor.

The disclosure provides a control method of a memory device, wherein the memory device includes a plurality of cells. The method comprising: in an erase operation, in which one of the cells as a selected cell is selected for erase, a word line voltage coupled to a gate terminal of the selected cell is a preset negative voltage; and, in which one of the cells as a deselected cell is not selected for erase, a word line voltage coupled to a gate terminal of the deselected cell is a Hi-Z state.

The disclosure provides a word line drive circuit. The word line drive circuit includes a first drive transistor and a second drive transistor. A first terminal of the first drive transistor receives a first signal, and a control terminal of the first drive transistor receives a first control signal. A first terminal of the second drive transistor is coupled to a second terminal of the first drive transistor, a second terminal of the second drive transistor receives a revised global word line voltage, and a control terminal of the second drive transistor receives a global word line voltage. The first terminal of the second drive transistor and the second terminal of the first drive transistor are coupled to a gate terminal of one of a plurality of cells in a memory array. In an erase operation and the one of the plurality of cells is not selected for erase, the first control signal is enabled to enable the first transistor, the first signal is a Hi-Z state, and the first signal is coupled to the gate terminal of the one of the plurality of cells through the first drive transistor.

Based on the above description, in a situation that the word line voltage of the deselected cell(s) is the Hi-Z state while the selected cell(s) is erased in the erase operation, it has no current or carriers flow through the corresponding deselected cell(s) in the memory device. Thus, a threshold voltage distribution of the deselected cell(s) does not been affected and also not moved in the erase operation, the refresh step in an erase flow algorithm for moving the threshold voltage of the disturbed cells is no need to be performed, and the operation time period of the erase flow algorithm can be reduced and saved. Further, the drain stress of deselected cell is reduced and it results in better endurance for the cells in the memory device.

1 FIG. 1 FIG. 110 120 130 140 illustrates a flow chart with an erase flow algorithm and threshold voltage distributions of a selected bit and a deselected bit with a common P-well layer shown in different steps of the erase flow algorithm according to a disclosure. The erase flow algorithm according to the disclosure includes four steps in: a pre-program step S, an erase step S, an over erase recovery step S, and a refresh step S. The selected cell in a flash memory device is selected for performing the erase flow algorithm, and deselected cells in the flash memory device are affected by the erase flow algorithm.

110 151 1 161 1 120 151 2 1 120 1 161 2 161 2 2 120 151 2 1 161 2 2 130 140 151 2 161 2 1 FIG. In detail, in the pre-program step S, threshold voltage distributions of the selected cell and one of the deselected cells in a flash memory device are presented on the right side of. The distribution-indicates the threshold voltage distribution of the selected cell, and the distribution-indicates the threshold voltage distribution of the deselected cell. In the erase step S, the selected cell is erased, but the un-select cells are disturbed and affected inevitably because the selected cell and the deselected cells have the common P-well layer. The threshold voltage distribution-of the selected cell is roughly moved to the target voltage area VAfor the erase step(see an arrow AR). In the other hand, the threshold voltage distribution-of the deselected cell is disturbed and moved slightly for losing some charge in the deselected cell, thus not all of the threshold voltage distributionis in an original voltage area VA(see an arrow AR). After the erase step S, the threshold voltage distribution-is not actually in the target voltage area VA, and parts of the threshold voltage distribution-is out of the original voltage area VA, thus the steps S-Sare performed for adjusting the distributions-and-.

130 151 3 1 3 161 3 140 161 4 2 4 151 4 110 140 140 140 1 FIG. In the over erase recovery step S, the threshold voltage distribution-of the selected cell is adjusted to move in to the voltage area VA(see an arrow AR) for recovery, and the threshold voltage distribution-of the deselected cell is not moved. And, in the refresh step S, the threshold voltage distribution-of the deselected cell is adjusted to move back to the original voltage area VA(see an arrow AR), and the threshold voltage distribution-of the deselected cell is not moved. Thus, the erase flow algorithm is finished inthrough the steps S-S. However, the refresh step Smay occupy not a short time, and if the erase flow algorithm for the selected cell does not affect the deselected cells based on the common P-well layer, the refresh step Sdoes not need to be implemented.

2 FIG. 0 0 210 210 0 0 0 0 is a schematic diagram of cells FC-FCN in the memory device according to an embodiment of the present invention. The cells FC-FCN are set on a common p-well layer. The common p-well layerhas a P-well bias voltage Vpwell. Each of the gate terminal of the cells FC-FCN receives a word line voltage on each of the word lines WL-WLN respectively. The movement of threshold voltage distributions with cells in the memory device is based on current Ior carriers (i.e., electronics) flow through corresponding cells. If there is no current Ior carriers flow through corresponding cells, threshold voltage distributions with these cells are not moved. Thus, if it is not desired that the threshold voltage distributions of the cell are affected for moving while the cell is deselected, no current or carriers flow through these deselected cells for erase may be implemented according to an embodiment of the present invention.

3 FIG. 3 FIG. 2 FIG. 1 FIG. 210 310 140 is a simplified signal schematic diagram for illustrating the P-well bias voltage Vpwell and the word line voltages for selected cells and deselected cells according to an embodiment of the present invention. In, the P-well bias voltage Vpwell of the common p-well layerofmay be a high voltage (for instance, 10V). In order to no current or carriers flow through the deselected cells according to the common p-well layer while the selected cell(s) is erased, in a step of the erase flow algorithm for providing the word line voltages to the cells, the word line voltage for the selected cells (i.e., a selected word line voltage VSelWL) is a fixed voltage (for instance, −10V), and the word line voltage for the deselected cells (i.e., a deselected word line voltage VdeSelWL) is a Hi-Z state (i.e., a floating state). Because of the Hi-Z state with the deselected word line voltage VdeSelWL while the selected cell(s) is erased, it has no current or carriers flow through the corresponding deselected cells in the memory device (shown as an arrow), thus the threshold voltage distributions of the deselected cells are not affected and also not moved, the refresh step Sinis no need for implementing, and the operation time period of the erase flow algorithm can be reduced and saved. Further, the drain stress of deselected cell is reduced and it results in better endurance for the cells in the memory device.

4 FIG. 400 400 is a circuit diagram for illustrating a word line decoderaccording to an embodiment of the present invention. The word line decoderis implemented in a memory device (for instance, a NOR flash memory device). The memory device has a memory array consisted of a plurality of cells and other circuits for operating the memory array (for example, a word line decoder).

400 410 1 410 400 400 420 1 420 2 400 420 1 420 2 410 1 410 410 1 0 410 1 7 1 410 1 504 410 1 511 505 410 1 410 410 1 420 1 420 2 420 1 4 FIG. 4 FIG. 4 FIG. 4 FIG. 5 FIG. 6 FIG. The word line decoderinincludes at least one word line drive circuit. For example, multiple word line drive circuits-to-N are in the word line decoderof. The word line decoderfurther includes at least one global word line decoder. For example, two global word line decoders-to-are in the word line decoderof. The global word line decoders-to-provides a global word line voltage GWL, a revised global word line voltage GWLB, and a first voltage Vpos to the word line drive circuits-to-N. For example, the word line drive circuit-inprovides a world line voltage WL[] to corresponding cell, the word line drive circuit-provides world line voltages WL[:] to corresponding cells, the word line drive circuit-N-provides world line voltage WL[] to corresponding cell, and the word line drive circuit-provides world line voltages WL[:] to corresponding cells. Circuit details of the word line drive circuits-to-N (take the word line drive circuit-as example) shown in, and circuit details of the global word line decoders-to-(take the global word line decoders-as example) shown in.

5 FIG. 4 FIG. 5 FIG. 410 1 400 410 1 410 1 1 2 1 1 2 1 2 2 2 1 2 1 410 1 0 0 is a circuit diagram for illustrating a word line drive circuit (e.g., the word line drive circuit-) in the word line decoderofaccording to an embodiment of the present invention. The word line drive circuit-is taken as example. The word line drive circuit-inincludes a first drive transistor TDand a second drive transistor TD. The first terminal (a source terminal) of the first drive transistor TDreceives a first signal Vpos, and a control terminal (a gate terminal) of the first drive transistor TDreceives a first control signal HXP. A first terminal (a drain terminal) of the second drive transistor TDis coupled to a second terminal (a drain terminal) of the first drive transistor TD, a second terminal (a source terminal) of the second drive transistor TDreceives a revised global word line voltage GWLB, and a control terminal (a gate terminal) of the second drive transistor TDreceives a global word line voltage GWL. The first terminal (the drain terminal) of the second drive transistor TDand the second terminal (the drain terminal) of the first drive transistor TDare coupled to a gate terminal of a cell FCN in the memory array. In other words, the drain terminal of the second drive transistor TDand he drain terminal) of the first drive transistor TDare coupled to an output terminal of the word line drive circuit-for providing a word line voltage (i.e., the word line voltage WL[]) to the gate terminal of the cell FC.

410 1 3 3 1 410 1 3 3 0 1 2 3 0 1 1 0 0 0 5 FIG. The word line drive circuit-infurther includes a third drive transistor TD. A first terminal (a drain terminal) of the third drive transistor TDis coupled to the second terminal (a drain terminal) of the first drive transistor TDand the output terminal of the word line drive circuit-. A control terminal (a gate terminal) of the third drive transistor TDreceives a second control signal HXN, and the second terminal (a source terminal) of the third drive transistor TDreceives a revised second control signal HXNB. The cell FCis set on the common P-well layer, and the common P-well layer has the P-well bias voltage Vpwell. The first drive transistor TDis a P-type transistor, and the second drive transistor TDand the third drive transistor TDare N-type transistors. In an erase operation and the cell FCis not selected for erase, the first control signal HXP is enabled (e.g., the first control signal HXP is 0V) to enable the first drive transistor TD, the first signal Vpos is a Hi-Z state, and the first signal Vpos is coupled to the gate terminal of the cell Vpwell through the first drive transistor TD. Thus, in the erase operation and the cell FCas a deselected cell is not selected for erase, no current flows through the cell FCwith the common P-well layer while the first signal Vpos is coupled to the gate terminal of the cell FC.

6 FIG. 4 FIG. 420 1 400 420 1 610 620 630 is a circuit diagram for illustrating a global word line decoder (e.g., the global word line decoder-) in the word line decoderofaccording to an embodiment of the present invention. The global word line decoder-includes a first inverter, a second inverter, and a voltage generator.

610 610 610 610 610 11 12 11 610 11 12 11 12 610 12 610 The input terminal of the first inverterreceives a global control signal PRED. A system voltage terminal of the first inverterreceives a system voltage VPP (e.g., the system voltage VPP may be 2V), a ground terminal of the first inverterreceives a negative voltage Vneg (e.g., the negative voltage Vneg may be −10V), and an output terminal of the first inverterprovides the global word line voltage GWL. In detail, the first inverterincludes a P-type transistor Tand a N-type transistor T. The first terminal (the source terminal) of the P-type transistor Tis the system voltage terminal of the first inverter. The control terminals (the gate terminals) of the P-type transistor Tand the N-type transistor Treceive the global control signal PRED. The second terminal (the drain terminal) of the P-type transistor Tand the first terminal (the drain terminal) of the N-type transistor Tare coupled as the output terminal of the first inverterfor providing the global word line voltage GWL. The second terminal (the source terminal) of the N-type transistor Tis the ground terminal of the first inverter.

620 620 620 620 620 21 22 21 620 21 22 21 22 620 22 620 21 21 An input terminal of the second inverterreceives the global word line voltage GWL, a system voltage terminal of the second inverterreceives the system voltage VPP, a ground terminal of the second inverterreceives the negative voltage Vneg, and an output terminal of the second inverterprovides the revised global word line voltage GWLB. In detail, the second inverterincludes a P-type transistor Tand a N-type transistor T. The first terminal (the source terminal) of the P-type transistor Tis the system voltage terminal of the second inverter. The control terminals (the gate terminals) of the P-type transistor Tand the N-type transistor Treceive the global word line voltage GWL. The second terminal (the drain terminal) of the P-type transistor Tand the first terminal (the drain terminal) of the N-type transistor Tare coupled as the output terminal of the second inverterfor providing the revised global word line voltage GWLB. The second terminal (the source terminal) of the N-type transistor Tis the ground terminal of the second inverter. The source terminal of the P-type transistor Tis the system voltage not the negative voltage Vneg, so that it can reduces a body bias effect of the P-type transistor T.

630 610 630 1 2 3 1 2 3 1 1 2 1 2 3 2 630 3 3 The voltage generatoris coupled to the first inverterfor providing the first signal Vpos according to the global word line voltage GWL, an erase enable signal EraseON, the system voltage VPP, and a ground voltage GND (e.g., the ground voltage GND may be 0V). In detail, the voltage generatoris implemented by a tri-state inverter, which includes a first voltage transistor TV, a second voltage transistor TV, and a third voltage transistor TV. The first voltage transistor TVand the second voltage transistor TVare P-type transistors, and the third voltage transistor TVis N-type transistor. A first terminal (a source terminal) of the first voltage transistor TCreceives the system voltage VPP, and a control terminal (a gate terminal) of the first voltage transistor TVreceives the erase enable signal EraseON. A first terminal (a source terminal) of the second voltage transistor TVis coupled to the second terminal (a drain terminal) of the first voltage transistor TV, and a control terminal (a gate terminal) of the second voltage transistor TVreceives the global word line voltage GWL. A first terminal (a drain terminal) of the third voltage transistor TVis coupled to the second terminal (a drain terminal) of the second voltage transistor TVas an output terminal of the voltage generator. A second terminal (a source terminal) of the third voltage transistor TVreceives the ground voltage GND, and a control terminal (a gate terminal) of the third voltage transistor TVreceives the global word line voltage GWL.

1 1 3 2 2 3 When the erase enable signal EraseON is disabled for known that the erase operation is not performed, the first voltage transistor TVis conducted to the first terminal (the source terminal) and the second terminal (the drain terminal) of the first voltage transistor TV, and the first signal Vpos is one of the system voltage VPP and the ground voltage GND according to the global word line voltage GWL. While the erase enable signal EraseON is disabled and the global word line voltage GWL is enabled (global word line voltage GWL is 2V for high voltage as the system voltage VPP), the third voltage transistor TVis conducted to it's first terminal (the drain terminal) and the second terminal (the source terminal) and the second voltage transistor TVis turned off, thus the first signal Vpos is the ground voltage GND (e.g., 0V). While the erase enable signal EraseON is disabled and the global word line voltage GWL is disabled (global word line voltage GWL is −10V for the negative voltage Vneg), the second voltage transistor TVis conducted to it's first terminal (the source terminal) and the second terminal (the drain terminal) and the third voltage transistor TVis turned off, thus the first signal Vpos is the system voltage VPP (e.g., 2V).

1 3 1 2 3 When the erase enable signal EraseON is enabled for the erase operation and the global word line voltage GWL is disabled (e.g., the global word line voltage GWL is −10V), the first voltage transistor TVand the third voltage transistor TVare turned off, and the first signal is the Hi-Z state. And, when the erase enable signal EraseON is enabled for the erase operation and the global word line voltage GWL is enabled (e.g., the global word line voltage GWL is 2V), the first voltage transistor TVand the second voltage transistor TVare turned off and the third voltage transistor TVis conducted to it's first terminal (the drain terminal) and the second terminal (the source terminal), and the first signal Vpos is coupled to the ground voltage GND (e.g., 0V).

7 FIG. 4 FIG. 6 FIG. 4 FIG. 4 FIG. 7 FIG. 0 7 1 420 1 0 7 1 410 1 410 2 410 1 410 2 is a schematic diagram illustrating signals of the word line drive circuit with the selected cell in the erase operation according to an embodiment of the present invention. It is assumed that corresponding cells of the word line voltages WL[] and WL[:] ofare selected cells, and the first signal VPP inis 0V based on the global word line decoder-in a situation of the enabled erase enable signal EraseON and the enabled global word line voltage GWL. The word line voltages WL[] and WL[:] ofare provided by the word line drive circuits-and-of. In above situation of, the first control signal HXP is 0V, the global word line voltage GWL is a high voltage HV (e.g., 2V for the system voltage VPP), the revised word line voltage GWLB is the negative voltage Vneg (e.g., −10V), the second control signal HXN is the negative voltage Vneg (e.g., −10V), and the revised second control signal HXNB is the high voltage HV (e.g., 2V for the system voltage VPP). Thus, the output terminals of the word line drive circuits-and-are the negative voltage Vneg (e.g., −10V) of the first signal Vpos as the word line voltage WL.

8 FIG. 4 FIG. 6 FIG. 4 FIG. 4 FIG. 8 FIG. 504 511 505 420 2 504 511 505 410 1 410 410 1 410 is a schematic diagram illustrating signals of the word line drive circuit with the deselected cell in the erase operation according to an embodiment of the present invention. It is assumed that corresponding cells of the word line voltages WL[] and WL[:] ofare selected cells, and the first signal VPP inis the Hi-Z state based on the global word line decoder-in a situation of the disabled erase enable signal EraseON and the enabled global word line voltage GWL. The word line voltages WL[] and WL[:] ofare provided by the word line drive circuits-N-and-N of. In above situation of, the first control signal HXP is 0V, the global word line voltage GWL is the negative voltage (e.g., −10V), the revised word line voltage GWLB is the high voltage HV (e.g., 2V for the system voltage VPP), the second control signal HXN is the negative voltage Vneg (e.g., −10V), and the revised second control signal HXNB is the high voltage HV (e.g., 2V for the system voltage VPP). Thus, the output terminals of the word line drive circuits-N-and-N are the Hi-Z state of the first signal Vpos as the word line voltage WL. Hence, it has no current or carriers flow through the corresponding deselected cell(s) in the memory device while the word line voltage WL is the Hi-Z state in the erase operation.

9 FIG. 4 FIG. 6 FIG. 4 FIG. 4 FIG. 9 FIG. 0 420 2 0 410 1 410 1 410 1 is a schematic diagram illustrating signals of the word line drive circuit with the selected cell in a read operation and a program operation according to an embodiment of the present invention. It is assumed that corresponding cell of the word line voltage WL[] ofis selected cell for the read operation or the program operation, and the first signal VPP inis the high voltage HV (e.g., 2V) based on the global word line decoder-in a situation of the disabled erase enable signal EraseON and the disabled global word line voltage GWL. The word line voltage WL[] ofis provided by the word line drive circuit-of. In above situation of, the first control signal HXP is 0V, the global word line voltage GWL is the negative voltage Vneg (−10V), the revised word line voltage GWLB is the high voltage HV (2V), the second control signal HXN is the negative voltage Vneg (−10V), and the revised second control signal HXNB is the high voltage HV (2V). Thus, the output terminal of the word line drive circuit-is the high voltage HV (2V) as the word line voltage WL. Hence, the word line drive circuit-is operated normally in the read operation or the program operation.

10 FIG. 11 FIG. 10 FIG. 4 FIG. 6 FIG. 4 FIG. 4 FIG. 10 FIG. 410 2 410 1 410 7 1 420 1 7 1 410 2 410 1 410 2 andare schematic diagrams illustrating signals of the word line drive circuit-,-N-and-N with the deselected cells in the read operation and the program operation according to an embodiment of the present invention. In, it is assumed that corresponding cells of the word line voltages WL[:] ofare deselected cells for the read operation or the program operation, and the first signal VPP inis the high voltage HV (2V) based on the global word line decoder-in a situation of the disabled erase enable signal EraseON and the disabled global word line voltage GWL. The word line voltages WL[:] ofare provided by the word line drive circuit-of. In above situation of, the first control signal HXP is the high voltage HV (2V), the global word line voltage GWL is the negative voltage Vneg (−10V), the revised word line voltage GWLB is the high voltage HV (2V), the second control signal HXN is the high voltage HV (2V), and the revised second control signal HXNB is the negative voltage Vneg (−10V). Thus, the output terminal of the word line drive circuit-is the negative voltage Vneg (−10V) as the word line voltage WL. Hence, the word line drive circuit-is operated normally in the read operation or the program operation.

11 FIG. 4 FIG. 6 FIG. 4 FIG. 4 FIG. 11 FIG. 504 511 505 420 2 504 511 505 410 1 410 410 1 410 1 410 In, it is assumed that corresponding cells of the word line voltages WL[] and WL[:] ofare deselected cells for the read operation or the program operation, and the first signal VPP inis the ground voltage GND (0V) based on the global word line decoder-in a situation of the disabled erase enable signal EraseON and the enabled global word line voltage GWL. The word line voltages WL[] and WL[:] ofare provided by the word line drive circuits-N-and-N of. In above situation of, the first control signal HXP may be in a unknown state X or is the high voltage HV (2V), the global word line voltage GWL is the high voltage HV (2V), the revised word line voltage GWLB is the negative voltage Vneg (−10V), the second control signal HXN is the negative voltage Vneg (−10V) or the high voltage HV (2V), and the revised second control signal HXNB is the high voltage HV (2V) or the negative voltage Vneg (−10V). Thus, the output terminal of the word line drive circuit-is the negative voltage Vneg (−10V) as the word line voltage WL. Hence, the word line drive circuits-N-and-N are operated normally in the read operation or the program operation.

12 FIG. 12 FIG. 4 FIG. 400 1210 1220 is a flowchart illustrating a control method of a memory device according to an embodiment of the invention. The control method inmay implemented based on the memory device and the word line decodershown in. In step S, in an erase operation, in which one of the cells as a selected cell is selected for erase, a word line voltage coupled to a gate terminal of the selected cell is a preset negative voltage. And, in step S, in which one of the cells as a deselected cell is not selected for erase in the erase operation, a word line voltage coupled to a gate terminal of the deselected cell is a Hi-Z state. Detail of the steps in the control method may be referenced for the above embodiments.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.