Flash Memory Device and Programming Method Thereof

This application claims the priority benefit of Taiwan application serial no. 113133101, filed on Sep. 2, 2024. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

The disclosure relates to a control technique of a memory device, and particularly relates to a flash memory device and a programming method thereof for reducing a programming current generated during a programming operation.

Regarding a programming operation of a NOR flash memory device, in addition to a programming time, a programming current flowing from a drain to a source of a memory cell is also an important parameter that may be used to save power consumption. When programming a specific number of memory cells, a regulator with a charge pump circuit may be used to provide a stable drain voltage (for example, 4 volts) to the memory cells to generate programming currents, thus ensuring successful programming. However, an area occupied by the charge pump circuit may be directly proportional to a peak value of the programming currents generated by all of the memory cells during programming, which may also affect manufacturing cost of product. Therefore, how to reduce the programming current generated during the programming operation of the NOR flash memory device has become one of the important issues in this field.

The disclosure is directed to a flash memory device and a programming method thereof, which are adapted to dynamically adjust a number of bits (memory cells) to be programmed simultaneously and a programming time used in a programming verification cycle, thereby reducing a programming current generated when performing a programming operation.

The disclosure provides a flash memory device including a memory array and a memory control circuit. The memory array has a plurality of bit groups. The memory control circuit is coupled to the memory array, and is configured to sequentially perform a programming operation on the bit groups. The memory control circuit performs one or more programming verification cycles on a target bit group in the bit groups when the target bit group fails a programming verification, wherein the target bit group is divided into M parts, M is a positive integer greater than 1. The memory control circuit determines whether the programming verification cycle performed on the target bit group is a first programming verification cycle. The memory control circuit sequentially programs the M parts with a first programming time when the first programming verification cycle is performed on the target bit group.

The disclosure provides a programming method of a flash memory device including following steps: sequentially performing a programming operation on a plurality of bit groups; performing one or more programming verification cycles on a target bit group in the bit groups when the target bit group fails a programming verification, wherein the target bit group is divided into M parts, M is a positive integer greater than 1; determining whether the programming verification cycle performed on the target bit group is a first programming verification cycle; and sequentially programming the M parts with a first programming time when the first programming verification cycle is performed on the target bit group.

Based on the above description, the flash memory device and the programming method thereof of the disclosure may program only one part of the bit group at a time by using less programming time than conventionally programming when performing the first programming verification cycle on the target bit group, and proceed sequentially. In this way, a peak value of the programming current generated during the programming operation may be reduced, thereby reducing an area occupied by a charge pump circuit.

To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.

1 FIG. 100 110 120 110 112 112 112 112 Referring to, a flash memory deviceaccording to an embodiment of the disclosure is, for example, a NOR type and includes a memory arrayand a memory control circuit. The memory arrayincludes a plurality of bit groups. Each bit groupis composed of a plurality of bits to be programmed into a specific data pattern. Structurally, one bit is equivalent to, for example, a memory cell with a memory tunneling oxide (ETOX) structure. It should be noted that the disclosure does not limit the number of the bit groupsand the number of bits (memory cells) that constitute one bit group.

120 110 120 112 120 114 112 110 114 1 1 1 114 2 1 114 1 The memory control circuitis coupled to the memory array. The memory control circuitmay sequentially perform a programming operation on all of the bit groups. Specifically, the memory control circuitmay select a target bit groupfrom the plurality of bit groupsin the memory arrayaccording to a received selection command CMD to perform the programming operation. In the embodiment, the target bit groupmay be divided into M parts Gto GM, where M is a positive integer greater than 1. For example, each of the parts G-GM may include 16 bits. The part Gincludes the highest 16 bits in the target bit group, the part Gincludes 16 bits immediately following the bits of the part Gin the target bit group, and so on. However, the disclosure does not limit the number of bits in each of the parts G-GM, and those skilled in the art may make appropriate adjustments according to actual needs.

120 120 100 120 100 1 FIG. The memory control circuitmay be, for example, a state machine, a central processing unit, or other programmable general-purpose or special-purpose microprocessor, digital signal processor, programmable controller, special application integrated circuit, programmable logic device, or other similar devices or combinations of these devices, and may also be a hardware circuit designed through a hardware description language or any other conventional digital circuit design method, and implemented through a field programmable logic gate array or a complex programmable logic device, etc. In addition, although the memory control circuitis shown inas being located in the flash memory device, the memory control circuitmay also be a device independent to the flash memory device.

100 130 130 120 120 130 110 120 130 110 120 1 FIG. Optionally, the flash memory devicefurther includes a flag register. The flag registeris coupled to the memory control circuit, and is configured to store a times flag FT. Each time a programming verification cycle is executed, the memory control circuitmay set an initial value of the times flag FT to a first value (for example, “0”). Moreover, although the flag registeris shown inas being independent to the memory arrayand the memory control circuit, the flag registermay also be integrated into the memory arrayor the memory control circuit.

1 FIG. 2 FIG. 1 FIG. 100 100 Referring toandat the same time, a programming method of the flash memory device of the embodiment is applicable to the flash memory deviceof, and various steps of the programming method of the embodiment of the disclosure are described below with reference of various components of the flash memory device.

200 120 112 120 112 110 114 First, in step S, the memory control circuitsequentially performs a programming operation on the plurality of bit groups. For example, the memory control circuitmay perform initialization, and set one of the bit groupsto be programmed in the memory array(for example, a first bit group) as the target bit group.

120 114 114 120 114 Then, the memory control circuitmay compare bit data (for example, 32 bits) formed by the target bit groupwith a specific data pattern (for example, 32 bits) to determine whether the target bit grouppasses programming verification. In more detail, in an example of programming verification, the memory control circuitmay determine whether a threshold voltage (Vth) of each bit (memory cell) in the target bit groupcomplies with a specified range of each bit value in the specific data pattern.

112 For example, if a bit value in a data pattern is “0”, a corresponding threshold voltage needs to be greater than a preset programming verification reference voltage, and if the bit value in the data pattern is “1”, the corresponding threshold voltage needs to be less than the preset programming verification reference voltage. The data patterns corresponding to each of the bit groupsmay be the same or different.

202 114 120 114 Therefore, in step S, if the target bit groupfails the programming verification, the memory control circuitmay perform one or more programming verification cycles on the target bit group.

204 120 114 114 206 120 1 114 120 120 114 120 120 114 Then, in step S, the memory control circuitdetermines whether the programming verification cycle executed on the target bit groupis a first programming verification cycle. When the first programming verification cycle is performed on the target bit group, in step S, the memory control circuitsequentially programs the M parts G-GM of the target bit groupwith a first programming time. For example, the memory control circuitmay set an initial value of K to 1, and the memory control circuitmay determine whether a K-th part GK of the target bit grouphas one or more failed bits. If yes, the memory control circuitapplies a programming voltage Vprg to the failed bit(s) of the K-th part GK for the first programming time, and increments K (K=K+1) to continue determination of a next part. If not, the memory control circuitdirectly increments K (K=K+1) to continue the determination of the next part. In the embodiment, the so-called “failed bit(s)” refer to bit(s) (memory cell(s)) within the target bit groupthat have failed the programming verification. The programming voltage Vprg includes voltages applied to a gate node, a drain node, a source node and a well region of the failed bit, especially the voltage applied to the drain node. For example, the voltage applied to the gate node may be 9 volts, the voltage applied to the drain node may be 4 volts, and the voltage applied to the source node and the well region may be 0 volt, but the disclosure is not limited thereto.

120 1 In addition, the memory control circuitmay repeat the above-mentioned step of determining whether the K-th part GK has one or more failed bits and the step of incrementing K, thereby continuing to determine the next part until K is greater than M (all of the parts G-GM have been determined).

114 208 120 1 114 120 1 On the other hand, when the programming verification cycle other than the first programming verification cycle (for example, the second programming verification cycle, the third programming verification cycle, etc.) is performed on the target bit group, in step S, the memory control circuitsimultaneously programs the M parts G-GM of the target bit groupwith a second programming time that is greater than the first programming time. Specifically, the memory control circuitmay simultaneously apply the programming voltage Vprg to the failed bits of all of the M parts G-GM for the second programming time. In practical applications, the first programming time is, for example, 0.2 microseconds, and the second programming time is, for example, 0.8 microseconds, which are both shorter than a conventional programming time (for example, 1 microsecond) used for the bit group of 32 bits.

120 114 By observing characteristics of the NOR flash memory device, a programming current generated by all of the bits (memory cells) during programming may decrease over time. In the embodiment, since the number of failed bits in the first programming verification cycle is the largest, the memory control circuitonly applies the programming voltage Vprg to the failed bits of one part GK of the target bit groupat a time for the first programming time in the first programming verification cycle, so as to reduce a peak value of the programming current generated by all of the failed bits that are simultaneously applied with the programming voltage Vprg.

120 1 114 Since the number of the failed bits in the programming verification cycles other than the first programming verification cycle may decrease as the number of the programming verification cycles increases, in the programming verification cycles other than the first programming verification cycle, the memory control circuitmay simultaneously apply the programming voltage Vprg to the failed bits of all of the M parts G-GM of the target bit groupat a time for the second programming time, so as to improve a speed of programming verification. In this way, the time spent in programming operations may be reduced while taking into account the programming current.

3 FIG. 1 FIG. 3 FIG. 1 FIG. 2 FIG. 100 100 114 1 2 The programming method of the disclosure will be described in more detail below with reference of the embodiment shown in. Referring toandat the same time, the programming method of the flash memory device of the embodiment is applicable to the flash memory deviceof, and various steps of the programming method of the embodiment of the disclosure are described below with reference of various components of the flash memory device. In the embodiment, the parts that are the same or similar to the description ofwill not be repeated. In addition, in order to simplify the description, in the embodiment, it is assumed that the target bit groupis divided into two parts Gand G(M equals to 2).

300 120 112 110 114 First, in step S, the memory control circuitperforms initialization and sets a first bit group among all of the bit groupsto be programmed in the memory arrayas the target bit group.

302 120 114 114 304 120 114 120 114 Then, in step S, the memory control circuitdetermines whether the target bit grouppasses the programming verification. When the target bit groupfails the programming verification, in step S, the memory control circuitdetermines whether the programming verification cycle performed on the target bit groupis the first programming verification cycle. To be specific, the memory control circuitmay determine whether the programming verification cycle performed on the current target bit groupis the first programming verification cycle according to the times flag FT.

120 114 306 120 1 114 308 120 1 310 310 306 When the times flag FT is a first value (for example, “0”), the memory control circuitmay determine that the programming verification cycle performed on the current target bit groupis the first programming verification cycle, and in step S, the memory control circuitdetermines whether a first part Gof the target bit grouphas one or more failed bits. If yes, in step S, the memory control circuitapplies the programming voltage Vprg to the failed bit(s) of the first part Gfor the first programming time, and then the method flow proceeds to S. If not, the method flow proceeds directly to Safter step S.

310 120 2 114 312 120 2 120 302 310 120 302 In step S, the memory control circuitdetermines whether a second part Gof the target bit grouphas one or more failed bits. If yes, in step S, the memory control circuitapplies the programming voltage Vprg to the failed bit(s) of the second part Gfor the first programming time, and then the memory control circuitsets the times flag FT to a second value (for example, “1”), and the method flow returns to step Sto continue the second programming verification cycle. If not, after step S, the memory control circuitsets the times flag FT to the second value, and the method flow returns to step S.

304 120 130 120 114 314 120 1 2 114 120 1 2 302 In step S, when the memory control circuitdetermines that the times flag FT stored in the flag registeris not the first value (but is the second value), the memory control circuitmay determine that the programming verification cycle performed on the current target bit groupis a programming verification cycle other than the first programming verification cycle (for example, the second programming verification cycle, the third programming verification cycle, etc.), and in step S, the memory control circuitsimultaneously programs the two parts Gand Gof the target bit groupwith the second programming time greater than the first programming time. Specifically, the memory control circuitmay simultaneously apply the programming voltage Vprg to the failed bits of all of the two parts Gand Gfor the second programming time, and then the method flow returns to step Sto continue a next programming verification cycle.

120 114 302 316 120 114 112 318 110 320 120 112 114 302 On the other hand, when the memory control circuitdetermines that the target bit grouppasses the programming verification in step S, in step S, the memory control circuitdetermines whether the target bit groupis a last bit group among all of the bit groupsto be programmed. If yes, the method flow proceeds to Sto end the programming operation of the memory array. If not, in step S, the memory control circuitsets a next bit group in the bit groupsas the target bit group, and then the method flow proceeds to Sto continue the programming operation.

1 FIG. 4 FIG. 1 FIG. 2 FIG. 3 FIG. 100 100 114 1 2 Another embodiment is provided below to illustrate the programming method of the disclosure. Referring toandat the same time, the programming method of the flash memory device of the embodiment is applicable to the flash memory deviceof, and various steps of the programming method of the embodiment of the disclosure are described below with reference of various components of the flash memory device. In the embodiment, the same or similar parts as those in the description ofandwill not be repeated. Similarly, in the embodiment, it is assumed that the target bit groupis divided into two parts Gand G(M equals to 2).

400 120 112 110 114 First, in step S, the memory control circuitperforms initialization and sets the first bit group among all of the bit groupsto be programmed in the memory arrayas the target bit group.

402 120 114 114 404 120 114 Then, in step S, the memory control circuitdetermines whether the target bit grouppasses the programming verification. When the target bit groupfails the programming verification, in step S, the memory control circuitdetermines whether the programming verification cycle performed on the target bit groupis the first programming verification cycle.

120 114 406 120 1 114 408 120 1 410 410 406 When the memory control circuitdetermines that the programming verification cycle performed on the current target bit groupis the first programming verification cycle, in step S, the memory control circuitdetermines whether the first part Gof the target bit grouphas one or more failed bits. If yes, in step S, the memory control circuitapplies the programming voltage Vprg to the failed bit(s) of the first part Gfor the first programming time, and then the method flow proceeds to S. If not, the method flow proceeds directly to Safter step S.

410 120 2 114 412 120 2 414 414 410 In step S, the memory control circuitdetermines whether the second part Gof the target bit grouphas one or more failed bits. If yes, in step S, the memory control circuitapplies the programming voltage Vprg to the failed bit(s) of the second part Gfor the first programming time, and then the method flow proceeds to S. If not, the method flow proceeds directly to Safter step S.

2 114 414 120 1 2 114 120 1 2 402 Different from the previous embodiment, after determining whether the second part Gof the target bit grouphas one or more failed bits, in step S, the memory control circuitsimultaneously programs the two parts Gand Gof the target bit groupwith a third programming time. The third programming time in the embodiment is, for example, greater than the first programming time and less than or equal to the second programming time. Specifically, the memory control circuitmay simultaneously apply the programming voltage Vprg to the failed bits of all of the two parts Gand Gfor the third programming time. Then, the method flow returns to step Sto continue a next programming verification cycle.

404 120 114 416 120 1 2 114 In step S, when the memory control circuitdetermines that the programming verification cycle performed on the current target bit groupis a programming verification cycle other than the first programming verification cycle (such as the second programming verification cycle, the third programming verification cycle, etc.), in step S, the memory control circuitsimultaneously programs the two parts Gand Gof the target bit groupwith the second programming time that is greater than the first programming time.

120 114 402 418 120 114 112 420 110 422 120 112 114 402 On the other hand, when the memory control circuitdetermines that the target bit grouppasses the programming verification in step S, in step S, the memory control circuitdetermines whether the target bit groupis the last bit group among all of the bit groupsto be programmed. If yes, the method flow then proceeds to Sto end the programming operation of the memory array. If not, in step S, the memory control circuitsets a next bit group in the bit groupsas the target bit group, and then the method flow proceeds to Sto continue the programming operation.

In summary, the flash memory device and the programming method thereof of the disclosure may reduce the programming currents generated during programming operations. Even though the total programming time may increase a little, the peak value of the generated programming currents will be greatly reduced, which may greatly reduce the area occupied by the charge pump circuit and reduce the manufacturing cost of product, which is beneficial to applications of the Internet of Things (IOT) and batteries. Therefore, the disclosure provides a green semiconductor technology.