Thin Film Transistor, Method for Manufacturing the Same and Display Apparatus Comprising the Same

This application claims the benefit of priority of the Republic of Korea Patent Application No. 10-2024-0115768 filed on Aug. 28, 2024, which is hereby incorporated by reference in its entirety.

The present disclosure relates to a thin film transistor having a seed layer, a method for manufacturing the thin film transistor, and a display apparatus including the thin film transistor.

The transistors are widely used as switching devices or driving devices in the field of electronic devices. In particular, thin film transistors are widely used as switching devices in display apparatuses such as liquid crystal display apparatuses or organic light emitting devices because they may be manufactured on glass or plastic substrates.

Thin film transistors may be classified into amorphous silicon thin film transistors in which amorphous silicon is used as the active layer, polycrystalline silicon thin film transistors in which polycrystalline silicon is used as the active layer, and oxide semiconductor thin film transistors in which oxide semiconductor is used as the active layer, based on the material constituting the active layer.

Since amorphous silicon may be deposited in a short period of time to form an active layer, amorphous silicon thin film transistors (a-Si TFT) have the advantages of a short manufacturing process time and low production costs. On the other hand, amorphous silicon thin film transistors have the disadvantages of limited use in active matrix organic light emitting diode (AMOLED) because of low mobility, poor current driving capability, and changes in threshold voltage.

Polycrystalline silicon thin film transistors (poly-Si TFT) are made by crystallizing amorphous silicon after amorphous silicon has been deposited. Polycrystalline silicon thin film transistors have the advantages of high electron mobility, excellent stability, thinness, high resolution, and high power efficiency. Examples of such polycrystalline silicon thin film transistors include low temperature poly-silicon (LTPS) thin film transistors, or polysilicon thin film transistors. Since the manufacturing process of polycrystalline silicon thin film transistors requires a process in which amorphous silicon is crystallized, the number of processes increases, which increases the manufacturing cost, and crystallization must be performed at a high process temperature.

Oxide semiconductor thin film transistors that have high mobility and a large resistance variation depending on the oxygen content have the advantage of being able to easily obtain desired property. In addition, since the oxide constituting the active layer may be formed at a relatively low temperature during the manufacturing process of oxide semiconductor thin film transistors, the manufacturing cost is low. Since oxide semiconductors are transparent due to the nature of oxides, they are also advantageous in implementing transparent displays.

However, the performance of oxide semiconductor thin film transistors may be degraded and the turn-on voltage may become unstable due to hydrogen. In particular, when the oxide semiconductor thin film transistor is used in an environment containing a large amount of hydrogen or at a high temperature, the performance deterioration or performance instability due to hydrogen may become severe. Therefore, in order to prevent deterioration of the oxide semiconductor thin film transistor and improve stability, it is necessary to protect the oxide semiconductor thin film transistor from hydrogen.

In addition, electronic products have become more highly integrated recently. In addition, the demand for high-resolution display apparatuses is increasing. For high integration and high resolution, the size and area of thin film transistors need to be reduced. Therefore, it is required to manufacture thin film transistors in a narrow area.

The disclosed thin film transistor structure features a vertical configuration that employs a seed layer with an inclined surface to enable selective crystallization of the active layer. This results in a crystalline channel region while maintaining amorphous regions at the source and drain contacts. The structure supports high carrier mobility and enhanced resistance to hydrogen degradation, making it suitable for applications requiring high resolution and component density. The seed layer, formed from oxide semiconductor materials with low carrier concentration, facilitates controlled crystallization during thermal treatment at temperatures between 300 and 500 degrees Celsius. The active layer may include specific dopants to manage crystallization behavior and improve electrical conductivity.

The design also includes configurations where the seed layer has a concave geometry, allowing the channel length to be extended without increasing the surface area. This approach improves space utilization and supports integration into compact electronic devices. The described thin film transistors are compatible with display panels, including those using organic light emitting diodes, and can be implemented in gate driver circuits on the panel substrate. These features contribute to improved reliability, electrical stability, and manufacturing efficiency.

For example, one embodiment of the present disclosure provides a thin film transistor including a seed layer having an inclined surface, and a gate electrode disposed to face the inclined surface of the seed layer. One embodiment of the present disclosure provides a thin film transistor having a vertical structure including a channel part disposed on the inclined surface of the seed layer.

One embodiment of the present disclosure is to provide a thin film transistor having a vertical structure capable of securing a channel length even within a limited area.

One embodiment of the present disclosure is to provide a thin film transistor having a narrow area.

One embodiment of the present disclosure is to provide a thin film transistor having a crystallized channel part and excellent resistance to hydrogen.

Another embodiment of the present disclosure provides a manufacturing method of a thin film transistor having a vertical structure by using an oxide semiconductor material having conductor property and a seed layer.

Another embodiment of the present disclosure is to provide a display apparatus having excellent reliability, including a thin film transistor as described above.

One embodiment of the present disclosure for achieving the above described technical subject provides a thin film transistor including a seed layer having an inclined surface, an active layer contacting the seed layer and including a channel part, and a gate electrode overlapping at least a portion of the active layer, wherein the channel part has a crystalline structure, wherein the channel part is disposed on the inclined surface and contacts the inclined surface, and wherein at least a portion of the gate electrode is disposed to face the inclined surface with the active layer interposed therebetween.

The active layer may further include a first connection part connected to one side of the channel part and a second connection part connected to the other side of the channel part, and the first connection part and the second connection part may each have an amorphous structure.

The first connection part and the second connection part do not contact the seed layer.

In a plan view, in a portion where the gate electrode is disposed, a width of the seed layer is greater than a width of the active layer. Here, the width of the seed layer and the width of the active layer are measured in a direction perpendicular to a line connecting the first connection part and the second connection part.

The above seed layer may have an amorphous structure.

The seed layer is an amorphous layer in which a ratio of a sum of areas of the crystals having a grain size of 1 nm or more is 10% or less to an entire cross-sectional area in a cross-section of the seed layer.

The seed layer may have a lower carrier concentration than the channel part.

16 3 The seed layer may have a carrier concentration of 1.0×10ea/cmor less.

The seed layer may include at least one oxide semiconductor material of an IZO (InZnO) based oxide semiconductor material, an IGZO (InGaZnO) based oxide semiconductor material, an IGZTO (InGaZnSnO) based oxide semiconductor material, a GZTO (GaZnSnO) based oxide semiconductor material, a GZO (GaZnO) based oxide semiconductor material, and a GO (GaO) based oxide semiconductor material.

The active layer may include at least one of an IGZO (InGaZnO) based, IGO (InGaO) based, IGZTO (InGaZnSnO) based, GZTO (GaZnSnO) based, GZO (GaZnO) based, GO (GaO) based, TO (SnO) based, ITO (InSnO) based, ITZO (InSnZnO) based, IZO (InZnO) based, ZO (ZnO) based, InO (InO) based, and FIZO (FeInZnO) based oxide semiconductor material.

The active layer may further include at least one of beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y), and zirconium (Zr).

The seed layer and the active layer may include at least one common metal element.

In a cross-section the channel part, a ratio of sum of areas of crystals having a grain size of 1 nm or more is 50% or more to an entire cross-sectional area.

The channel part may include at least one of ta (400) crystal plane, a (222) crystal plane, a (220) crystal plane, a (311) crystal plane, and a (001) crystal plane.

The thin film transistor further includes a source electrode and a drain electrode spaced apart from each other, wherein the source electrode may contact the seed layer and the first connection part, and wherein the drain electrode may contact the seed layer and the second connection part.

The seed layer may have a concave part, wherein the concave part may be defined by the inclined surface and the bottom surface, and wherein the active layer may be disposed on the inclined surface and the bottom surface of the concave part.

The bottom surface may be a part of the seed layer, and the channel part may be extended form on the inclined surface to on the bottom surface.

The thin film transistor may further include a metal layer disposed on the bottom surface of the concave part, and wherein the active layer may further include a third connection part contacting the metal layer.

The third connection part may have an amorphous structure.

Another embodiment of the present disclosure provides a display apparatus including the thin film transistor described above.

Another embodiment of the present disclosure provides a manufacturing method of a thin film transistor comprising forming a seed material layer on a substrate, forming a seed layer having an inclined surface by patterning the seed material layer, forming an active layer contacting the inclined surface of the seed layer, heat treating the active layer to crystallize a portion of the active layer contacting the inclined surface, and forming a gate electrode on the active layer, wherein at least a portion of the gate electrode may be disposed to face the inclined surface with the active layer interposed therebetween

Before the heat treating, the active layer may have an amorphous structure.

A temperature of the heat treating may be in the range of 300 to 500° C.

The advantages and features of the present disclosure, and the method for achieving them, will become clear with reference to the embodiments described in detail below together with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below, and may be implemented in various other forms. These embodiments are provided to ensure that the disclosure of the present disclosure is complete, and to enable those skilled in the art to easily understand the disclosure.

The shapes, sizes, dimensions (e.g., length, width, height, thickness, radius, diameter, area, etc.), ratios, angles, number of elements, and the like illustrated in the accompanying drawings for describing the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto.

A dimension including size and a thickness of each component illustrated in the drawing are illustrated for convenience of description, and the present disclosure is not limited to the size and the thickness of the component illustrated, but it is to be noted that the relative dimensions including the relative size, location, and thickness of the components illustrated in various drawings submitted herewith are part of the present disclosure.

The same components may be referred to by the same reference numerals throughout the specification. In addition, in explaining the present disclosure, if it is determined that a detailed description of a related known technology may unnecessarily obscure the gist of the present disclosure, the detailed description is omitted.

In this specification, when the words “includes,” “has,” and “consists of,” are used, other parts may be added unless the expression “only” is used. When a component is expressed in the singular, the plural is included unless otherwise explicitly stated.

When interpreting a component, it is interpreted as including the error range even though there is no separate explicit description.

As used herein, the term “connected” is intended to have the broadest possible meaning. Specifically, the phrase “A is connected to B” encompasses both a direct connection—where no intervening components or elements are present—and an indirect connection, where one or more intermediate components or elements exist between A and B. In other words, “A is connected to B” includes both direct physical or electrical coupling and indirect coupling through one or more intervening components. Unless explicitly stated otherwise, these terms do not require direct physical or electrical contact. The term “coupled” and “in contact” should be interpreted in the same manner.

When describing a positional relationship, for example, when the positional relationship between two parts is described as ‘on’, ‘above’, ‘below’, ‘next to’, or the like, one or more other parts may be located between the two parts, unless the expression ‘right’ or ‘directly’ is used.

The spatially relative terms “below,” “beneath,” “lower,” “above,” “upper,” and the like may be used to easily describe the relationship of one element or component to another element or component, as illustrated in the drawings. The spatially relative terms should be understood to include different orientations of the elements during use or operation in addition to the orientations depicted in the drawings. For example, if an element illustrated in the drawings is flipped over, an element described as “below” or “beneath” another element may end up being placed “above” the other element. Thus, the exemplary term “below” can include both the above and below directions. Likewise, the exemplary term “above” or “above” can include both the above and below directions.

When describing a temporal relationship, for example, when describing a temporal relationship such as ‘after’, ‘following’, ‘next to’, or ‘before’, it can also include cases where there is no continuity, as long as the expression ‘right away’ or ‘directly’ is not used.

Although the terms first, second, or the like. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, a first component referred to below may also be a second component within the technical concept of the present disclosure.

At least one term should be understood to include all combinations that may be presented from one or more of the associated items. For example, the meaning of “at least one of the first, second, and third items” can mean not only each of the first, second, or third items, but also all combinations of items that may be presented from two or more of the first, second, and third items.

The individual features of the various embodiments of the present disclosure may be partially or wholly combined or combined with each other, and may be technically linked and driven in various ways, and each embodiment may be implemented independently of each other or may be implemented together in a related relationship.

Hereinafter, a thin film transistor and a display apparatus including the same according to an embodiment of the present disclosure will be described in detail with reference to the attached drawings. When adding reference symbols to components in each drawing, the same components may have the same symbols as much as possible even though they are shown in different drawings.

In embodiments of the present disclosure, the source electrode and the drain electrode are distinct, but the source electrode and the drain electrode may be interchanged. For example, the source electrode according to one embodiment may become the drain electrode in another embodiment, and the drain electrode according to one embodiment may become the source electrode in another embodiment.

In the embodiments of the present disclosure, for the convenience of explanation, the source region and the source electrode are distinguished, and the drain region and the drain electrode are distinguished, but the embodiments of the present disclosure are not limited thereto. The source region may be the source electrode, and the drain region may be the drain electrode. In addition, the source region may be the drain electrode, and the drain region may be the source electrode.

1 FIG. 2 FIG. 1 FIG. 3 FIG. 1 FIG. 100 is a plan view of a thin film transistoraccording to one embodiment of the present disclosure,is a cross-sectional view taken along line I-I′ of, andis a cross-sectional view taken along line II-II′ of.

100 120 120 130 120 150 130 130 130 130 s n n The thin film transistoraccording to one embodiment of the present disclosure includes a seed layerhaving an inclined surface, an active layercontacting the seed layer, and a gate electrodeat least partially overlapping the active layer. The active layerincludes a channel part. The channel parthas a crystalline structure.

130 120 120 120 150 120 120 130 n s s s The channel partis disposed on the inclined surfaceof the seed layerand contacts the inclined surface. At least a portion of the gate electrodeis arranged facing the inclined surfaceof the seed layerwith the active layerinterposed therebetween.

2 3 FIGS.and 100 110 100 110 Referring to, a thin film transistormay be disposed on a substrate. Anything that supports the thin film transistormay be referred to as a substratewithout limitation.

110 110 110 110 The Glass or plastic may be used as the substrate. A transparent plastic having flexible property may be used as the substrate. Among the plastics, for example, when polyimide is used as the substrate, considering that a high-temperature deposition process is performed on the substrate, a heat-resistant polyimide that can withstand high temperatures may be used.

115 110 115 115 115 115 130 110 115 A buffer layermay be disposed on the substrate. The buffer layermay be made of an insulating material. For example, the buffer layermay include at least one of an insulating material such as silicon oxide, silicon nitride, and a metal oxide. The buffer layermay have a single-film structure or a multi-film structure. The buffer layermay protect the active layerby blocking air and moisture. The surface of the upper portion of the substratemay be made uniform by the buffer layer.

115 The buffer layermay be omitted.

161 115 161 110 161 120 A source electrodemay be disposed on the buffer layer. The source electrodemay also be placed directly on the substrate. However, one embodiment of the present disclosure is not limited thereto, and the source electrodemay also be disposed on the seed layer.

120 161 120 110 120 115 The seed layermay be disposed on the source electrode. However, one embodiment of the present disclosure is not limited thereto, and the seed layermay be placed directly on the substrate. The seed layermay also be disposed on the buffer layer.

120 130 120 120 130 120 130 The seed layerselectively crystallizes a portion of the active layerthat comes into contact with the seed layer. The seed layeracts as a seed for crystal growth. A selected portion of the active layermay be crystallized by the seed layer. As a result, a portion of the active layermay have crystallinity.

120 According to one embodiment of the present disclosure, the seed layermay include an oxide semiconductor material.

120 For example, the seed layermay include at least one of an IZO (InZnO) based oxide semiconductor material, an IGZO (InGaZnO) based oxide semiconductor material, an IGZTO (InGaZnSnO) based oxide semiconductor material, a GZTO (GaZnSnO) based oxide semiconductor material, a GZO (GaZnO) based oxide semiconductor material, and a GO (GaO) based oxide semiconductor material.

120 120 120 130 130 According to one embodiment of the present disclosure, the seed layermay have a basic composition made of an oxide semiconductor material, but includes a large amount of oxygen. As a result, the seed layermay have the characteristic of an insulating layer in terms of electrical property. The seed layeronly selectively crystallizes the active layer, and does not affect the electrical characteristic of the active layer.

120 120 120 130 120 130 130 n In detail, the seed layermay be formed by an oxide semiconductor material having a low carrier concentration and a high oxygen concentration. The seed layeraccording to one embodiment of the present disclosure may have a high resistivity. The seed layerhaving a high resistivity has electrical characteristic similar to an insulator and does not participate in the carrier movement of the active layer. According to one embodiment of the present disclosure, the seed layermay have a lower carrier concentration than the channel partof the active layer.

120 120 120 16 3 16 3 According to one embodiment of the present disclosure, the seed layermay have a carrier concentration of 1.0×10ea/cmor less. When the carrier concentration of the seed layeris 1.0×10ea/cmor less, the seed layermay have electrical characteristic close to an insulating layer.

120 120 100 16 3 According to one embodiment of the present disclosure, the seed layermay have a low carrier concentration of 1.0×10ea/cmor less and thus has insulating property. Accordingly, the seed layermay not affect the on-current characteristic of the thin film transistor.

120 120 The seed layermay have an amorphous structure. According to one embodiment of the present disclosure, the seed layermay be an amorphous layer.

According to one embodiment of the present disclosure, when a ratio of a sum of areas of crystals having a grain size of 1 nm or more is 10% or less to an entire cross-sectional area based on a cross-section of a layer, the layer is called an amorphous layer. In detail, based on a transmission electron microscope (TEM) image of a cross-section of a layer to be measured, when the ratio of a sum of areas of crystals having a grain size of 1 nm or more is 10% or less to an entire area of the cross-sectional area, the layer is called an amorphous layer.

120 According to one embodiment of the present disclosure, the seed layermay be an amorphous layer in which the proportion of a sum of areas of crystals having a grain size of 1 nm or more is 10% or less to an entire cross-sectional area based on a cross-section.

On the other hand, if a ratio of a sum of areas of crystals having a grain size of 1 nm or more is 50% or more to an entire cross-sectional area based on a cross-section of a layer, the layer is called a crystalline layer. In detail, based on a transmission electron microscope (TEM) image of a cross-section of a layer to be measured, if the ratio of a sum of areas of crystals having a grain size of 1 nm or more is 50% or more to an entire cross-sectional area, the layer is called a crystalline layer.

2 FIG. 120 120 120 120 120 s s Referring to, the seed layermay have an inclined surface. After a seed material layer may be formed by a material for forming the seed layer, the seed material layer may be patterned so that a seed layerhaving an inclined surfacemay be formed.

120 120 110 110 120 120 161 110 161 120 120 s s s 2 FIG. The inclined surfaceof the seed layermay have a predetermined inclination angle θ based on the upper surface of the substrate. According to one embodiment of the present disclosure, the angle between the upper surface of the substrateand the inclined surfaceof the seed layeris referred to as the inclination angle θ. When the upper surface of the source electrodeand the upper surface of the substrateare parallel to each other, as illustrated in, the angle between the upper surface of the source electrodeand the inclined surfaceof the seed layermay be referred to as the inclination angle θ.

162 120 161 162 161 162 161 162 2 FIG. 2 FIG. The drain electrodemay be disposed on the seed layer. In one embodiment of the present disclosure, the source electrodeand the drain electrodeare distinguished only for convenience of explanation, and the source electrodeand the drain electrodeare not limited to. In, the positions of the source electrodeand the drain electrodemay be exchanged.

161 162 161 162 The source electrodeand the drain electrodemay each include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. The source electrodeand the drain electrodemay each be formed of a single layer made of a metal or an alloy of metals, or may be formed of a multilayer of two or more layers.

130 120 130 120 According to one embodiment of the present disclosure, an active layermay be disposed on a seed layer. At least a portion of the active layermay contact the seed layer.

2 FIG. 3 FIG. 130 161 162 120 130 120 120 130 120 120 s s Referring toand, an active layermay be disposed on the source electrode, the drain electrode, and the seed layer. The active layeris disposed on the inclined surfaceof the seed layer. At least a portion of the active layermay contact the inclined surfaceof the seed layer.

130 130 130 130 130 130 130 n a n b n. According to one embodiment of the present disclosure, the active layerincludes a channel part. In addition, the active layerincludes a first connection partconnected to one side of the channel partand a second connection partconnected to the other side of the channel part

130 130 130 n a b According to one embodiment of the present disclosure, the channel partmay have a crystalline structure. The first connection partand the second connection parteach may have an amorphous structure.

130 130 130 According to one embodiment of the present disclosure, the active layermay be formed of a semiconductor material. The active layermay include an oxide semiconductor material. The active layermay include, for example, an oxide semiconductor layer.

1 3 FIGS.to 100 130 In, a thin film transistorin which the active layeris an oxide semiconductor layer is illustrated as an example.

130 130 120 130 19 3 According to one embodiment of the present disclosure, the active layermay be formed by an oxide semiconductor material having a high mobility similar to that of a conductor. For example, the active layermay be formed by an amorphous oxide semiconductor material having a carrier concentration of 1.0×10ea/cmor more. On the other hand, the seed layermay be formed by an amorphous oxide semiconductor material having a lower carrier concentration than that of the active layer.

130 130 The active layermay include, for example, at least one of an IGZO (InGaZnO) based oxide semiconductor material, an IGO (InGaO) based oxide semiconductor material, an IGZTO (InGaZnSnO) based oxide semiconductor material, a GZTO (GaZnSnO) based oxide semiconductor material, a GZO (GaZnO) based oxide semiconductor material, a GO (GaO) based oxide semiconductor material, a TO (SnO) based oxide semiconductor material, an ITO (InSnO) based oxide semiconductor material, an ITZO (InSnZnO) based oxide semiconductor material, an IZO (InZnO) based oxide semiconductor material, a ZO (ZnO) based oxide semiconductor material, an InO (InO) based oxide semiconductor material, and a FIZO (FeInZnO) based oxide semiconductor material. However, one embodiment of the present disclosure is not limited thereto, and other known oxide semiconductor materials having high mobility may be applied to the active layeraccording to one embodiment of the present disclosure.

130 130 According to one embodiment of the present disclosure, an indium based oxide semiconductor material having an indium (In) content of 50 atom % (at %) or more based on the number of atoms among all metal elements may be used as an oxide semiconductor material for forming an active layer. The active layermay include, for example, at least one of an IZO (InZnO) based oxide semiconductor material, an IGO (InGaO) based oxide semiconductor material, an IGZO (InGaZnO) based oxide semiconductor material, an ITO (InSnO) based oxide semiconductor material, and an IGZTO (InGaZnSnO) based oxide semiconductor material having an indium (In) content of 50 atom % (at %) or more based on the number of atoms among all metal elements.

130 In detail, the active layermay include an IZO based oxide semiconductor material having an indium (In) content of 50 at % or more relative to the total content of indium (In) and zinc (Zn), an IGO based oxide semiconductor material having an indium (In) content of 70 at % or more relative to the total content of indium (In) and gallium (Ga), an IGZO based oxide semiconductor material having an indium (In) content of 50 at % or more relative to the total content of indium (In), gallium (Ga), and zinc (Zn), an ITO based oxide semiconductor material having an indium (In) content of 80 at % or more relative to the total content of indium (In) and tin (Sn), and an IGZTO based oxide semiconductor material having a mixed content of indium (In) and tin (Sn) of 50 at % or more relative to the total content of indium (In), gallium (Ga), zinc (Zn), and tin (Sn).

130 130 130 According to one embodiment of the present disclosure, the active layermay have a low oxygen concentration. When the active layerincludes a high concentration of indium (In) and a low concentration of oxygen, the active layermay have high mobility characteristic and excellent electrical conductivity.

130 According to one embodiment of the present disclosure, the active layermay include at least one of beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y), and zirconium (Zr). The above elements may be dispersed in the oxide semiconductor material.

According to one embodiment of the present disclosure, beryllium (Be), boron (B), carbon (C), aluminum (Al), silicon (Si), iron (Fe), calcium (Ca), tin (Sn), titanium (Ti), tantalum (Ta), vanadium (V), yttrium (Y), and zirconium (Zr) may be referred to as crystallization controlling elements.

130 130 130 130 The crystallization control element is an element that has a strong bonding force with oxygen and can delay the crystallization speed of the active layer. The active layermay be formed by deposition and patterning, and the crystallization control element prevents crystallization of the active layerduring the deposition process, thereby preventing the patterning property of the active layerfrom deteriorating.

130 130 120 130 120 On the other hand, crystallization control does not completely prevent crystallization of the active layer. As a result, if heat treatment is performed while the active layermay contact the seed layer, a portion of the active layercontacting the seed layermay be crystallized.

130 130 130 According to one embodiment of the present disclosure, the crystallization control element may have a content of 0.1 to 6 atomic % (at %) with respect to the total atoms of the active layerexcluding oxygen. When the content of the crystallization control element is less than 0.1 atomic % (at %) with respect to the total atoms of the active layerexcluding oxygen, the crystallization prevention effect may not be sufficiently exerted during the deposition process. As a result, difficulties may occur during the patterning process after deposition of the oxide semiconductor material for forming the active layer.

130 130 On the other hand, if the content of the crystallization control element exceeds 6 atom % at % with respect to the total atoms of the active layerexcluding oxygen, a selected portion of the active layermay not be crystallized or the crystallization rate may be reduced due to the excessive amount of the crystallization control element.

130 120 130 120 130 120 According to one embodiment of the present disclosure, the active layerand the seed layermay include at least one common metal element. When the active layerand the seed layerinclude the same element, the bonding strength between the active layerand the seed layermay be improved.

130 130 120 130 n. According to one embodiment of the present disclosure, after an active layermay be formed by an amorphous oxide semiconductor material, a region of the active layerthat contacts the seed layeris crystallized, thereby forming a channel part

130 According to one embodiment of the present disclosure, the change of a portion having an amorphous structure into a crystalline structure is called “crystallization.” In addition, the crystallization of only a specific portion of the active layeris called “selective crystallization.”

130 130 120 130 120 n n According to one embodiment of the present disclosure, the channel partmay be a portion of the active layerthat is crystallized by the seed layer. Alternatively, the channel partmay be a portion that is selectively crystallized by the seed layer.

130 120 130 120 120 120 130 120 For example, selective crystallization of the active layermay occur when oxygen contained in the seed layerdiffuses to the active layerin contact with the seed layer. The seed layeracts as a seed for crystallization. Using the seed layeras a seed, crystallization may proceed from a portion of the active layerthat contacts the seed layer.

130 120 130 120 130 130 130 130 130 120 n n n a b n In the process of crystallizing the active layercontacting the seed layerand forming the channel part, movement of oxygen O may occur. Oxygen O may move from the seed layerto the channel part. As a result, the channel partmay have a higher oxygen concentration than the first connection partand the second connection part. However, the oxygen concentration of the channel partdoes not become higher than the oxygen concentration of the seed layer.

130 120 n According to one embodiment of the present disclosure, the channel partmay have a lower oxygen concentration than the seed layer. The oxygen concentration may be expressed in atomic percent at %.

130 130 n n According to one embodiment of the present disclosure, in a cross-section of the channel part, a ratio of a sum of areas of crystals having a crystal grain size of 1 nm or more may be 50% or more to an entire area of the cross-section. In detail, based on a transmission electron microscope (TEM) image of a cross-section of the channel part, a ratio of a sum of areas of crystals having a grain size of 1 nm or more may be 50% or more to an entire area of the cross-section.

130 n According to one embodiment of the present disclosure, the channel partmay include at least one crystal structure among, for example, a cubic crystal structure, a bixbyite crystal structure, a Cubic Bixbyite crystal structure, a spinel crystal structure, a hexagonal crystal structure, and a wurtzite crystal structure.

130 130 130 130 n n n According to one embodiment of the present disclosure, the channel partmay have a crystal plane. The channel partmay include, for example, at least one of a (400) crystal plane, a (222) crystal plane, a (220) crystal plane, a (311) crystal plane, and a (001) crystal plane. The nodal plane may be identified or measured from X-ray diffraction analysis (XRD) of the channel partof the active layer.

130 130 130 100 130 130 130 100 n n n n n n The channel parthaving a crystalline structure may have excellent physical and chemical stability. As a result, damage to the channel partor deformation of the physical property of the channel partduring the manufacturing process and use process of the thin film transistormay be suppressed or prevented. In addition, since the channel parthas a crystalline structure, it may have excellent resistance to hydrogen. As a result, the channel partmay have excellent stability. According to one embodiment of the present disclosure, since the channel parthas excellent stability, the thin film transistormay have excellent operating stability.

130 130 130 130 a b a b According to one embodiment of the present disclosure, the first connection partand the second connection partare non-crystallized portions. The first connection partand the second connection partmay have excellent electrical conductivity similar to that of metal.

130 130 130 130 130 130 n a b n a b. The channel parthas a lower carrier concentration than the first connection partand the second connection part. In addition, the channel partmay have a lower mobility than the first connection partand the second connection part

2 FIG. 130 130 120 130 120 130 120 130 130 130 130 130 a b n a b a b. Referring to, the first connection partand the second connection partdo not contact the seed layer. The portion of the active layerthat contacts the seed layerand its surroundings may be crystallized to become a channel part, and the portion that does not contact the seed layermay become the first connection partand the second connection part. The amorphous portion of the active layermay become the first connection partand the second connection part

130 130 130 130 130 130 a b a b a b 19 3 21 3 The first connection partand the second connection part, which are not crystallized and exist in an amorphous state, may have excellent electrical conductivity. According to one embodiment of the present disclosure, the first connection partand the second connection partmay each have a carrier concentration of 1.0×10ea/cmor more. In detail, the first connection partand the second connection partmay each have a carrier concentration of 1.0×10ea/cmor more.

130 130 130 130 a b a b 3 2 In addition, the first connection partand the second connection partmay each have a sheet resistance of 10Ω/□ or less. In detail, the first connection partand the second connection partmay each have a sheet resistance of 10Ω/□ or less.

130 130 a b The first connection partand the second connection parthaving high carrier concentration and low surface resistance may have electrical characteristic similar to those of a conductor without going through a separate conductorization process.

130 130 130 130 300 a b n According to one embodiment of the present disclosure, the first connection partand the second connection partmay be formed without performing a conductorization process on the active layer. As a result, diffusion of a conductorized region into the channel partduring the conductorization process may be prevented. In one embodiment of the present disclosure, the conductorization process may be referred to as a process of providing conductivity or improving conductivity to a selected part of a semiconductor layer or a selected part of the active layer.

130 161 161 130 130 162 161 130 162 130 130 a a b b According to one embodiment of the present disclosure, the first connection partmay contact the source electrode. The source electrodeis electrically connected to the first connection partof the active layer. The drain electrodeis spaced apart from the source electrodeand contacts the second connection part. The drain electrodeis electrically connected to the second connection partof the active layer.

130 130 130 130 130 130 a b a b a b According to one embodiment of the present disclosure, the first connection partmay be a source region, and the second connection partmay be a drain region. According to one embodiment of the present disclosure, the first connection partmay serve as a source electrode, and the second connection partmay serve as a drain electrode. The first connection partand the second connection partmay be interchanged.

130 130 130 In addition, according to one embodiment of the present disclosure, the active layermay have a multilayer structure. For example, the active layermay include a first oxide semiconductor layer and a second oxide semiconductor layer disposed on the first oxide semiconductor layer. In addition, the active layermay further include a third oxide semiconductor layer on the second oxide semiconductor layer.

1 FIG. 2 FIG. 161 162 161 120 130 162 120 130 a b. As illustrated inand, a thin film transistor according to one embodiment of the present disclosure may include a source electrodeand a drain electrodethat are spaced apart from each other. The source electrodemay contact the seed layerand the first connection part. The drain electrodemay contact the seed layerand the second connection part

2 FIG. 3 FIG. 140 130 140 140 140 130 n. Referring toand, a gate insulating layermay be disposed on an active layer. The gate insulating layermay include at least one of silicon oxide, silicon nitride, and metal oxide. The gate insulating layermay have a single layer or a multilayer structure. The gate insulating layermay protect the channel part

2 FIG. 140 130 120 120 130 130 150 140 n s n Referring to, the gate insulating layermay be disposed on the channel partdisposed on the inclined surfaceof the seed layer. The channel partof the active layerand the gate electrodemay be spaced apart from each other by the gate insulating layer.

140 110 140 130 130 130 n a b Additionally, the gate insulating layermay be formed over the entire upper portion of the substrate. For example, the gate insulating layermay cover all of the channel part, the first connection part, and the second connection partexcept for the contact region.

140 140 150 However, one embodiment of the present disclosure is not limited thereto, and the gate insulating layermay be patterned. For example, the gate insulating layermay be patterned into a shape corresponding to the gate electrode.

150 140 The gate electrodemay be disposed on the gate insulating layer.

150 150 The gate electrodemay include at least one of an aluminum series metal such as aluminum (Al) or an aluminum alloy, a silver series metal such as silver (Ag) or a silver alloy, a copper series metal such as copper (Cu) or a copper alloy, a molybdenum series metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrodemay also have a multilayer structure including at least two conductive layers having different physical property.

150 130 130 120 150 n The gate electrodemay overlap with the channel partof the active layer. In addition, the seed layermay overlap with the gate electrode.

130 120 150 130 120 150 n According to one embodiment of the present disclosure, the active layeris disposed between the seed layerand the gate electrode. In addition, the channel partmay be disposed between the seed layerand the gate electrode.

130 130 150 100 130 150 130 130 150 n n n The channel partof the active layermay have semiconductor characteristic and may have electrical conductivity when voltage is applied to the gate electrode. In order for the thin film transistorto be driven, the channel partmust be disposed within an area to which an electric field generated by the gate electrodeis applied. According to one embodiment of the present disclosure, the channel part, which is a crystallized portion of the active layer, may be disposed within an area defined by the gate electrode.

1 FIG. 3 FIG. 150 1 120 2 130 130 a b. Referring toand, in a region overlapping the gate electrodein a planar manner, the width wof the seed layeris larger than the width of the active layer w. According to one embodiment of the present disclosure, the width is measured in a direction perpendicular to a line connecting the first connection partand the second connection part

130 120 130 120 130 120 130 130 1 2 100 130 130 100 a b a b If a part of the active layerdoes not overlap with the seed layerin the width direction, an electric short may occur. In detail, a part of the active layerthat does not overlap with the seed layerwill not be crystallized and will have a high carrier concentration, low electrical resistance, and high electrical conductivity. Therefore, if a part of the active layerthat does not overlap with the seed layerextends from the first connection partto the second connection partalong the width direction w, wdirection to form a connection part, current will flow through the connection part regardless of the on-off of the thin film transistor. As a result, a short or leakage current may occur between the first connection partand the second connection part, and the thin film transistormay not be able to perform a switching function.

1 120 150 2 To prevent such short or leakage current, according to one embodiment of the present disclosure, the width wof the seed layerin the area overlapping the gate electrodein a plane is designed to be larger than the width of the active layer w.

100 130 120 120 100 130 100 100 n s n In addition, the thin film transistoraccording to one embodiment of the present disclosure may have a vertical structure including a channel partdisposed on an inclined surfaceof a seed layer. According to one embodiment of the present disclosure, since the thin film transistormay have a vertical structure, the length of the channel partmay be secured even in a narrow area. In addition, the area occupied by the thin film transistoris small, and the thin film transistormay be formed within a narrow area.

4 FIG. 5 FIG. 4 FIG. 200 is a plan view of a thin film transistoraccording to another embodiment of the present disclosure, andis a cross-sectional view taken along line III-III′ of.

4 FIG. 5 FIG. 120 125 125 120 120 120 125 120 120 120 120 125 s b s b s b Referring toand, the seed layermay have a concave part. The concave partof the seed layermay have an inclined surfaceand a bottom surface. The concave partmay be defined by the inclined surfaceand the bottom surface. According to another embodiment of the present disclosure, a space surrounded by the inclined surfaceand the bottom surfacemay be referred to as a concave part.

5 FIG. 120 125 120 120 125 120 120 125 120 b b s Referring to, the bottom surfaceof the concave partmay be a part of the seed layer. In detail, according to another embodiment of the present disclosure, the bottom surfaceof the concave partmay be a part of the surface of the seed layer. In addition, the inclined surfaceof the concave partmay be also another part of the surface of the seed layer.

130 120 120 125 130 120 120 125 s b s b The active layermay be disposed on the inclined surfaceand the bottom surfaceof the concave part. The active layermay be disposed across the inclined surfaceand the bottom surfaceof the concave part.

130 120 120 125 130 120 120 125 130 120 120 125 130 130 120 120 130 120 130 120 s b s b n n s b n s n b The active layermay contact the seed layeron the inclined surfaceof the concave part. In addition, the active layermay contact the seed layeron the bottom surfaceof the concave part. A portion of the active layerthat contacts the inclined surfaceand the bottom surfaceof the concave partmay be crystallized to become a channel part. According to another embodiment of the present disclosure, the channel partmay be extended from on the inclined surfaceto on the bottom surface. In detail, a portion of the channel parton the inclined surfaceand a portion of the channel parton the bottom surfacemay be connected each other.

150 130 150 120 130 150 120 130 s b The gate electrodemay overlap the active layer. The gate electrodemay be disposed facing the inclined surfacewith the active layerinterposed therebetween. In addition, the gate electrodemay be disposed facing the bottom surfacewith the active layerinterposed therebetween.

120 125 130 130 130 130 130 130 130 n n n n n a b. When the seed layermay have a concave part, the channel partmay have a curved shape. Accordingly, the length of the channel partmay be increased. In detail, when the channel partmay have a curve formed along the longitudinal direction, compared to the case where the channel partdoes not have a curve based on the same plane, the effect of the length of the channel partbeing increased may occur. Here, the longitudinal direction is the direction connecting the first connection partand the second connection part

200 161 162 161 162 130 161 162 120 A thin film transistoraccording to another embodiment of the present disclosure includes a source electrodeand a drain electrode. The source electrodeand the drain electrodeare spaced apart from each other and each contacts the active layer. The source electrodeand the drain electrodemay be disposed on a seed layer.

5 FIG. 161 162 120 130 161 162 130 161 162 130 161 130 130 162 130 a b. Referring to, the source electrodeand the drain electrodeare disposed on the upper surface of the seed layer, and the active layermay be disposed on the upper surface of the source electrodeand the upper surface of the drain electrode. The portion of the active layerdisposed on the source electrodeand the portion disposed on the drain electrodemay not be crystallized and may have excellent electrical conductivity. The portion of the active layerdisposed on the source electrodemay become a first connection part, and the portion of the active layerdisposed on the drain electrodemay become a second connection part

125 120 3 3 125 2 3 2 3 125 2 130 130 130 n n n. The concave partof the seed layermay have a predetermined width w. The width wof the concave partmay be greater than the width wof the active layer w>w. When the width wof the concave partis greater than the width wof the active layer, the channel partmay have a curve over the entire width direction. As a result, the effect of the length of the channel partbecoming longer may occur over the entire width direction of the channel part

3 125 1 120 3 1 3 125 1 120 3 1 3 125 2 3 2 The width wof the concave partmay be smaller than the width wof the seed layer, w<w, or the width wof the concave partmay be equal to the width wof the seed layer, w=w. In addition, the width wof the concave partmay be smaller than the width wof the active layer, w<w.

6 FIG. 7 FIG. 6 FIG. 300 is a plan view of a thin film transistoraccording to another embodiment of the present disclosure, andis a cross-sectional view taken along line IV-IV′ of.

300 163 120 125 6 FIG. 7 FIG. b The thin film transistorhaving the structure ofandfurther includes a metal layerdisposed on the bottom surfaceof the concave part.

1500 163 110 120 163 120 125 163 125 In detail, a thin film transistoraccording to another embodiment of the present disclosure includes a metal layeron a substrate, and a seed layermay be disposed on the metal layer. The seed layermay have a concave part, and the metal layerbecomes a bottom surface of the concave part.

130 163 130 130 163 120 125 7 FIG. c b According to another embodiment of the present disclosure, the active layermay contact the metal layer. Referring to, the active layermay include a third connection partthat contacts the metal layerdisposed on the bottom surfaceof the concave part.

130 120 125 130 130 130 c b c c The third connection partthat comes into contact with the bottom surfaceof the concave partof the active layeris not crystallized. Therefore, the third connection partmay have an amorphous structure and may have excellent electrical conductivity. The third connection partmay not function as a channel part, but can function as a wiring portion.

130 120 125 120 125 120 130 130 1 130 2 s s b n n n 7 FIG. The portion of the active layerthat comes into contact with the inclined surfaceof the concave partmay be crystallized and serve as a channel part. Referring to, the inclined surfacesof the concave partmay be separated by the bottom surfaceand divided into two regions. Accordingly, the channel partmay be divided into a first channel partand a second channel part.

300 130 1 130 2 300 1301 1302 150 1301 1302 7 FIG. 7 FIG. n n The thin film transistorofmay have a structure in which two channel parts,are connected in series. The thin film transistorofcorresponds to a structure in which two sub thin film transistors,are connected in series. The gate electrodesof the two sub thin film transistors,are common.

130 130 1301 130 1 1301 130 130 1 1301 a al n c b For example, the first connection partmay become the source electrodeof the first sub-thin film transistor, the first channel partmay become the channel part of the first sub-thin film transistor, and the third connection partmay become the drain electrodeof the first sub-thin film transistor.

130 130 2 1302 130 2 1302 130 130 2 1302 b b n c a Additionally, the second connection partmay become the drain electrodeof the second sub-thin film transistor, the second channel partmay become the channel part of the second sub-thin film transistor, and the third connection partmay become the source electrodeof the second sub-thin film transistor.

7 FIG. 140 140 150 Also, referring to, the gate insulating layermay be patterned. The gate insulating layermay be patterned, for example, in a shape corresponding to the gate electrode.

8 FIG. 9 FIG. 8 FIG. 400 is a plan view of a thin film transistoraccording to another embodiment of the present disclosure, andis a cross-sectional view taken along line V-V′ of.

125 According to another embodiment of the present disclosure, the concave partmay have various shapes.

8 FIG. 125 125 Referring to, the concave partmay have an elliptical shape in plan-view. However, another embodiment of the present disclosure is not limited thereto, and the concave partmay have a circular or polygonal shape in plan-view.

8 FIG. 9 FIG. 120 125 120 125 130 b b c In addition, referring toand, the bottom surfaceof the concave partmay have a circle shape in a plan view. As the bottom surfaceof the concave partmay have a circle shape, the third connection partmay also have a circle shape in a plan view.

163 400 400 Additionally, the metal layermay be an input terminal that inputs a signal to the thin film transistorand may also be an output terminal that receives a signal from the thin film transistor.

Hereinafter, a manufacturing method of a thin film transistor according to one embodiment of the present disclosure will be described.

10 10 FIGS.A toI 101 are cross-sectional views illustrating a manufacturing method of a thin film transistoraccording to one embodiment of the present disclosure.

101 120 110 120 120 120 130 120 120 120 120 120 130 m s m s s The manufacturing method of a thin film transistoraccording to one embodiment of the present disclosure includes forming a seed material layeron a substrate, forming a seed layerhaving an inclined surfaceby patterning the seed material layer, forming an active layercontacting the inclined surfaceof the seed layer, heat treating the active layerto crystallize a portion of the active layercontacting the inclined surface, and forming a gate electrode on the active layer,

120 110 m The seed material layermay be formed on a substrate.

10 FIG.A 161 110 In detail, referring to, a source electrodemay be formed on a substrate.

10 FIG.B 120 162 161 m m And, referring to, a seed material layerand a drain material layermay be formed on the source electrode.

10 FIG.C 510 162 m. Referring to, a photoresist patternmay be formed on a drain material layer

10 FIG.D 162 510 162 m Referring to, a drain material layermay be patterned by etching using the photoresist patternas a mask. As a result, a drain electrodemay be formed.

10 FIG.E 120 510 120 120 120 120 m s m. Referring to, the seed material layeris patterned by additional etching process using the photoresist patternas a mask. As a result, the seed layermay be formed. According to one embodiment of the present disclosure, the seed layerhaving an inclined surfacemay be formed by patterning the seed material layer

10 FIG.F 510 510 Referring to, the photoresist patternis removed. The photoresist patternmay be removed by an ashing process.

10 g FIG. 130 120 130 120 130 120 120 s Referring to, an active layermay be formed on a seed layer. At least a portion of the active layermay contact the seed layer. The active layermay contact an inclined surfaceof the seed layer.

130 130 130 The active layermay have an amorphous structure. For example, the active layermay be made of an amorphous oxide semiconductor material. The active layermay have a high carrier concentration and may have electrical conductivity similar to that of a metal or conductor.

130 130 130 120 120 s Next, the active layeris heat treated. As the active layeris heat treated, a portion of the active layerthat contacts the inclined surfaceof the seed layermay be crystallized.

130 130 120 According to one embodiment of the present disclosure, the active layermay have an amorphous structure before heat treating, and through heat treating, a portion of the active layerthat contacts the seed layeris crystallized.

120 The heat treating temperature may be 300 to 500° C. The heat treating temperature may vary depending on the thickness of the seed layer. The heat treating temperature may be referred to as a temperature of the heat treating.

10 FIG.H 130 Referring to, as a result of heat treating, an active layerincluding a crystalline portion and an amorphous portion may be formed.

130 130 130 130 130 n a b. The crystalline portion of the active layerbecomes the channel part. The amorphous portion of the active layerbecomes the first connection partand the second connection part

10 FIG.I 140 130 150 140 150 130 150 130 n. Referring toa gate insulating layermay be formed on the active layer, and a gate electrodemay be formed on the gate insulating layer. The gate electrodemay overlap at least partially with the active layer. In detail, the gate electrodemay be formed to overlap with a channel part

150 120 130 s According to one embodiment of the present disclosure, at least a portion of the gate electrodemay be disposed facing the inclined surfacewith the active layerinterposed therebetween.

101 As a result, a thin film transistoraccording to one embodiment of the present disclosure may be manufactured as described above.

Hereinafter, a display apparatus including at least one of the thin film transistors described above will be described in detail.

11 FIG. 500 is a schematic diagram of a display apparatusaccording to another embodiment of the present disclosure.

500 310 320 330 340 A display apparatusaccording to another embodiment of the present disclosure may include a display panel, a gate driver, a data driver, and a control unit.

310 The Gate lines GL and data lines DL are disposed on the display panel, and pixels P are disposed in the intersection area of the gate lines GL and data lines DL. An image is displayed by driving the pixels P.

340 320 330 The control unitcontrols the gate driverand the data driver.

340 320 330 340 330 The control unitoutputs a gate control signal GCS for controlling the gate driverand a data control signal DCS for controlling the data driverusing a signal supplied from an external system. In addition, the control unitsamples input image data input from an external system, rearranges it, and supplies the redisposed image data RGB to the data driver.

The gate control signal GCS may include a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a start signal Vst, a gate clock GCLK, or the like. In addition, the gate control signal GCS may include control signals for controlling a shift register.

The data control signal DCS may include a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, a polarity control signal POL, or the like.

330 310 330 340 The data driversupplies data voltage to the data lines DL of the display panel. In detail, the data drivercan convert image data RGB input from the control unitinto analog data voltage and supply the data voltage to the data lines DL.

320 320 The gate driversequentially supplies gate pulses GP to the gate lines GL during one frame. Here, one frame refers to a period during which one image is output through the display panel. In addition, the gate driversupplies a gate off signal Goff capable of turning off the switching element to the gate lines GL during the remaining period during which the gate pulse GP is not supplied during one frame. Hereinafter, the gate pulse GP and the gate off signal Goff are collectively referred to as a scan signal SS.

320 110 320 110 According to one embodiment of the present disclosure, the gate drivermay be mounted on the substrate. In this way, a structure in which the gate driveris directly mounted on the substrateis called a Gate In Panel (GIP) structure.

12 FIG. 11 FIG. 13 FIG. 12 FIG. 14 FIG. 13 FIG. is a circuit diagram for one pixel P of,is a plan view for the pixel P of, andis a cross-sectional view taken along line VI-VI′ of.

12 FIG. 500 710 The circuit diagram ofis an equivalent circuit diagram for a pixel P of a display apparatusincluding an organic light emitting diode OLED as a display element.

710 710 The pixel P includes a display elementand a pixel driver PDC that drives the display element.

1 The first thin film transistor TRis connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS supplied through the gate line GL.

1 The data line DL provides a data voltage Vdata to the pixel driver PDC, and the first thin film transistor TRcontrols the application of the data voltage Vdata.

710 2 710 The driving power line PL provides a driving voltage Vdd to the display element, and the second thin film transistor TRcontrols the driving voltage Vdd. The driving voltage Vdd is a pixel driving voltage for driving the organic light emitting diode OLED, which is the display element.

1 320 2 710 1 2 1 When the first thin film transistor TRis turned on by a scan signal SS applied through the gate line GL from the gate driver, the data voltage Vdata supplied through the data line DL is supplied to the gate electrode of the second thin film transistor TRconnected to the display element. The data voltage Vdata is charged in the first capacitor Cformed between the gate electrode and the source electrode of the second thin film transistor TR. The first capacitor Cis a storage capacitor Cst.

710 2 710 The amount of current supplied to the organic light emitting diode OLED, which is a display element, through the second thin film transistor TRis controlled according to the data voltage Vdata, and accordingly, the gradation of light output from the display elementmay be controlled.

13 FIG. 14 FIG. 1 2 110 Referring toand, a first thin film transistor TRand a second thin film transistor TRare disposed on a substrate.

110 110 The substratemay be made of glass or plastic. As the substrate, a plastic having flexible property, for example, polyimide PI, may be used.

110 1 1 2 2 110 A data line DL and a driving power line PL are disposed on a substrate. In addition, a source electrode Sof a first thin film transistor TRand a drain electrode Dof a second thin film transistor TRare disposed on the substrate.

1 1 2 2 The source electrode Sof the first thin film transistor TRmay be formed integrally with the data line DL. The drain electrode Dof the second thin film transistor TRmay be formed integrally with the driving power line PL.

121 1 1 122 2 2 A seed layermay be disposed on the source electrode Sof the first thin film transistor TR. Additionally, a seed layermay be disposed on the drain electrode Dof the second thin film transistor TR.

1 1 121 2 2 122 A drain electrode Dof a first thin film transistor TRmay be disposed on a seed layer. Additionally, a source electrode Sof a second thin film transistor TRmay be disposed on a seed layer.

1 2 1 2 1 2 1 2 The source electrodes S, Sand the drain electrodes D, Dare distinguished only for convenience of explanation, and the source electrodes S, Sand the drain electrodes D, Dmay be interchanged.

13 FIG. 14 FIG. 2 2 110 1 Referring toand, the source electrode Sof the second thin film transistor TRmay extend onto the substrateso that a portion thereof may become the first capacitor electrode CE.

1 2 121 122 Active layers A, Amay be disposed on the seed layers,.

14 FIG. 1 1 1 121 1 1 121 Referring to, an active layer Amay be disposed on the source electrode S, the drain electrode D, and the seed layerof the first thin film transistor TR. The active layer Amay contact the inclined surface of the seed layer.

2 2 2 122 1 2 122 Additionally, an active layer Amay be disposed on the source electrode S, the drain electrode Dand the seed layerof the second thin film transistor TR. The active layer Amay contact the inclined surface of the seed layer.

1 2 1 2 1 2 1 2 1 2 120 The active layers A, Amay include, for example, an oxide semiconductor material. The active layers A, Amay be formed of an oxide semiconductor layer made of an oxide semiconductor material. The active layers A, Amay include a crystalline portion and an amorphous portion. The channel part of the active layers A, Amay have a crystalline structure. A portion of the active layers A, Athat comes into contact with the seed layermay be crystallized and have a crystalline structure.

140 1 2 140 1 2 1 2 140 1 2 A gate insulating layermay be disposed on the active layers A, A. The gate insulating layermay have insulating property and separates the active layers A, Afrom the gate electrodes G, G. The gate insulating layercan cover the entire surface of the active layers A, A.

1 1 2 2 140 A gate electrode Gof a first thin film transistor TRand a gate electrode Gof a second thin film transistor TRare disposed on a gate insulating layer.

1 1 1 1 2 2 2 2 The gate electrode Gof the first thin film transistor TRoverlaps at least partly with the active layer Aof the first thin film transistor TR. The gate electrode Gof the second thin film transistor TRoverlaps at least partly with the active layer Aof the second thin film transistor TR.

13 FIG. 14 FIG. 2 1 2 2 1 1 1 2 1 2 2 2 Referring toand, a second capacitor electrode CEmay be disposed on the same layer as the gate electrodes G, G. The second capacitor electrode CEmay be connected to the drain electrode Dof the first thin film transistor TRthrough a contact hole H. In addition, a part of the second capacitor electrode CEmay extend to an upper portion of the active layer Aof the second thin film transistor TRto become the gate electrode Gof the second thin film transistor TR.

2 2 140 2 Alternatively, it may be the gate electrode Gof the second thin film transistor TRextends over the gate insulating layerand functions as a second capacitor electrode CE.

2 1 1 2 1 The second capacitor electrode CEoverlaps the first capacitor electrode CE. The first capacitor electrode CEand the second capacitor electrode CEoverlap to form a first capacitor C.

180 1 2 2 180 A planarization layermay be disposed on the gate electrodes G, Gand the second capacitor electrode CE. An interlayer insulating film may be further disposed under the planarization layer.

180 1 2 1 2 The planarization layerplanarizes the upper portions of the first thin film transistor TRand the second thin film transistor TRand protects the first thin film transistor TRand the second thin film transistor TR.

711 710 180 711 710 2 2 2 180 A first electrodeof a display elementmay be disposed on a planarization layer. The first electrodeof the display elementmay be connected to a source electrode Sof a second thin film transistor TRthrough a contact hole Hformed in the planarization layer.

750 711 750 710 A bank layermay be disposed at the edge of the first electrode. The bank layerdefines a light emitting area of the display element.

712 711 713 712 710 710 100 14 FIG. An organic light emitting layermay be disposed on a first electrode, and a second electrodemay be disposed on the organic light emitting layer. Accordingly, a display elementis completed. The display elementillustrated inis an organic light emitting diode OLED. Therefore, a display apparatusaccording to an embodiment of the present disclosure is an organic light emitting display apparatus.

A pixel driver PDC according to another embodiment of the present disclosure may be formed in various structures other than the structures described above. The pixel driver PDC may include, for example, three or more thin film transistors and two or more capacitors.

The present disclosure described above is not limited to the above-described embodiments and the attached drawings, and it will be apparent to a person skilled in the art to which the present disclosure pertains that various substitutions, modifications, and changes are possible within a scope that does not depart from the technical details of the present disclosure.

The thin film transistor according to one embodiment of the present disclosure may have a vertical structure including a channel part disposed on an inclined surface of a seed layer. Since the channel part may have a vertical structure, the length of the channel part may be secured even in a narrow area. Accordingly, the area occupied by the thin film transistor according to one embodiment of the present disclosure is small. In addition, when the thin film transistor according to one embodiment of the present disclosure is used, integration of elements is possible.

The thin film transistor according to one embodiment of the present disclosure includes a seed layer and an active layer contacting the seed layer, and a portion of the active layer contacting the seed layer may have a crystalline structure. A portion of the active layer having the crystalline structure may be a channel part. According to one embodiment of the present disclosure, the channel part of the thin film transistor may have a crystalline structure and thus may have excellent resistance to hydrogen, and the channel part may have excellent electrical stability. Therefore, the thin film transistor according to one embodiment of the present disclosure may have excellent electrical stability.

According to one embodiment of the present disclosure, a thin film transistor may be manufactured without going through a conductorization process.

110 120 110 130 120 120 130 130 120 In one embodiment, a thin film transistor includes a substrate, a seed layerdisposed on the substrate, and an active layerformed adjacent to at least one inclined surface of the seed layer. The seed layermay be formed from an oxide semiconductor material and patterned to exhibit a sloped or angled profile, which enables the formation of a vertical or slanted channel in the active layer. The active layerincludes a crystalline channel part that is disposed on the inclined surface of the seed layer, and amorphous connection parts located on opposing sides of the channel part. The channel part may be selectively crystallized by thermal treatment, while the surrounding amorphous regions retain high conductivity characteristics.

140 130 150 140 150 A gate insulating layeris formed over the active layer, and a gate electrodeis disposed to face at least the channel part with the gate insulating layerinterposed therebetween. In some embodiments, the gate electrodeincludes a non-planar segment shaped to follow the contour or profile of the inclined surface, thereby ensuring close alignment with the crystallized channel part. This configuration allows for strong electrostatic coupling and effective modulation of the channel, even in geometrically compact structures.

161 162 The thin film transistor may further include source and drain electrodes formed in electrical contact with the amorphous connection parts of the active layer. In one example, the source electrodeis in contact with a first amorphous connection part located on one end of the channel part, and the drain electrodeis in contact with a second amorphous connection part on the opposite side of the channel. These regions may be sufficiently conductive to facilitate charge injection and collection without requiring additional doping or conductorization steps.

120 130 In another embodiment, the seed layerincludes a concave part defined by two opposing inclined surfaces and a bottom surface that connects the inclined surfaces. The active layermay be formed to extend continuously and contiguously along the two inclined surfaces and the bottom surface, thereby forming a curved or U-shaped channel profile. The portions of the active layer contacting the inclined surfaces may form first and second crystalline channel parts, while the portion disposed along the bottom surface may remain amorphous and serve as a connection part.

163 Optionally, a conductive layermay be disposed at the bottom of the concave part and positioned in contact with the amorphous connection part of the active layer. This metal layer may act as a contact node or signal routing line, providing a low-resistance path to or from the central portion of the active layer. The structure allows two crystalline regions to be connected in series, while still maintaining spatial compactness and vertical integration.

120 130 150 120 In a plan view, the seed layermay be wider than the active layerin the region of overlap with the gate electrode. This arrangement ensures that the channel region of the active layer is completely formed on the seed layerand avoids unintended conductive paths through the amorphous connection regions. By maintaining proper overlap, electrical isolation and reliable switching behavior are preserved.

In a further embodiment, the above-described thin film transistors may be incorporated into each pixel of a display apparatus, such as an organic light emitting diode (OLED) display panel. Each pixel may include a thin film transistor in which the seed layer defines a concave part with a first inclined surface, a second inclined surface, and a bottom surface. The active layer is formed along these surfaces to create first and second crystalline channel parts on the inclined surfaces and an amorphous connection part bridging them at the bottom.

163 The gate electrode in such configurations may be disposed to overlap at least the two crystalline channel parts with a gate insulating layer in between. A metal layermay optionally be provided in contact with the amorphous connection part at the bottom surface of the seed layer, providing an electrical interface for driving signals. In addition, the first and second crystalline channel parts may each extend to respective amorphous connection regions outside the concave part, which are contacted by source and drain electrodes.

The seed layer and the semiconductor active layer may share at least one common metal element, such as indium or gallium, to enhance lattice compatibility and interfacial adhesion. Furthermore, in some embodiments, the use of a concave seed structure enables an increased effective channel length without expanding the lateral footprint of the pixel. This architecture is particularly beneficial for enhancing switching performance and achieving high resolution in compact display panels.

In addition to the effects mentioned above, other features and advantages of the present disclosure are described below or may be clearly understood by those skilled in the art to which the present disclosure pertains from such description and explanation.

The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.