Detection of Structural Defects in an Integrated Circuit

This application claims the benefit of French Application No. FR 2409177, filed on Aug. 28, 2024, which application is hereby incorporated herein by reference.

Embodiments and implementations relate to integrated circuits, in particular the detection of structural defects in these integrated circuits, for example cracks and/or delaminations.

An integrated circuit conventionally includes a part known to a person skilled in the art by the acronym “FEOL” (“Front End Of Line” or more simply “front end”) including the various components, such as transistors, implemented in and on the semiconductor substrate of the integrated circuit, and an interconnection portion known to a person skilled in the art by the acronym “BEOL” (“Back End Of Line” or more simply “back end”) including a network of metal tracks, of vias between the different metal levels and of contacts between the first metal level and the active areas of the substrate and/or of the different components (gate, source and drain portions of the transistors for example) buried in a dielectric material and ensuring in particular an interconnection between the components of the integrated circuit.

Integrated circuits are manufactured simultaneously on locations on a silicon wafer separated by cutting lines.

Then, once manufactured, the integrated circuits are individualized by cutting the wafer, typically by sawing, along the cutting lines.

During the operation of sawing the aforementioned wafer, cracks and/or a phenomenon of delamination (i.e. a decohesion of the layers) may occur in the BEOL part, in particular at the periphery of the integrated circuit.

French Patent Application No. 2406877 filed by the Applicant describes a device including in particular an annular wall located at the periphery of the integrated circuit allowing detecting cracks and/or delaminations resulting from the aforementioned sawing operation.

However, there is a constant need to further improve the detection of structural defects in an integrated circuit, in particular cracks and/or delaminations, which could allow moisture to penetrate into the integrated circuit, which is detrimental to the proper operation thereof.

In this respect, the Inventor has observed that such structural defects could also result from the manufacturing process of the integrated circuit itself, and in particular during the steps of soldering connecting wires (“wire bonding”) or of forming soldering balls on the contact pads (“pads”) located at the last metal level of the interconnection portion (BEOL).

Indeed, the Inventor has observed that these steps at these contact pads might locally create cracks and/or peeling of the structure.

According to one aspect, an electronic system is provided comprising an integrated circuit, including a semiconductor substrate, an interconnection portion located above the substrate and having metal levels and vias and contact levels embedded in an electrically-insulating region as well as contact pads located at the last metal level of the interconnection portion, and a detection system configured to detect the possible presence of at least one type of structural defects, for example a crack and/or a delamination, within at least one area of the interconnection portion located at least beneath a contact pad.

According to one embodiment, the detection system comprises an electrically-conductive region located at least in the area and a detection device configured to detect at least one electrical discontinuity of the region.

The detection device may be located within the integrated circuit.

In this respect, it may include, for example, inverters associated with a processing unit, for example an electronic chip present in the integrated circuit.

Alternatively, the detection device may include a module external to the integrated circuit, for example a tester.

According to one variant, it is possible to arrange, beneath the corresponding contact pad, an electrically-conductive track which does not contact the contact pad, which allows, if one wishes so, continuously detecting the apparition of a structural defect beneath the contact pad, even when the integrated circuit is in its application operation.

More specifically, according to an embodiment of this variant, in the case where the interconnection portion includes N metal levels with N greater than or equal to 2, the rank 1 metal level being the metal level the closest to the substrate, the contact pads being located at the rank N metal level, the electrically-conductive region may include an electrically-conductive track having a first end and a second end located at the rank 1 metal level and able to be electrically coupled to the detection device, a first branch extending from the first end up to the rank N−1 metal level, and a second branch extending from the rank N−1 metal level up to the second end, the two branches being mutually connected at the rank N−1 metal level.

For example, each branch may include a stack of metal portions, respectively located at the rank 1 to N−1 metal levels, and of vias between these metal portions, and a connection metal portion located at the rank N−1 metal level connecting the two metal portions of the two branches located at the rank N−1 metal level.

According to another embodiment of this variant, wherein the interconnection portion includes, herein again, N metal levels with N greater than or equal to 2, the rank 1 metal level being the metal level the closest to the substrate, the contact pads being located at the rank N metal level, the electrically-conductive region includes a first active area and a second active area located in the semiconductor substrate as well as an electrically-conductive track.

This electrically-conductive track has a first end and a second end located at the rank 1 metal level and able to be electrically coupled to the detection device, a first contact connected between the first end and the first active area, a first branch extending from the first active area up to the rank N−1 metal level, a second branch extending from the rank N−1 metal level up to the second active area, and a second contact connected between the second active area and the second end, the two branches being mutually connected at the rank N−1 metal level.

Such an embodiment wherein the electrically-conductive track that does not contact the contact pad but which extends up to the active areas of the substrate, allows, if one wishes so, continuously detecting the apparition of a structural defect beneath the contact pad, even when the integrated circuit is in the application operation thereof, and that being so between the rank N−1 metal level and the semiconductor substrate.

For example, each branch may include a stack of metal portions, respectively located at the rank 1 to N−1 metal levels, of vias between these metal portions and of a contact between the corresponding active area and the metal portion located at the rank 1 metal level, and a connection metal portion located at the rank N−1 metal level connecting the two metal portions of the two branches located at the rank N−1 metal level.

The electrically-conductive region may include several electrically-conductive tracks.

These tracks may be individualized and each connected to a respective processing unit, or respectively connected at four input ports of one single processing unit, or connected in a multiplexed manner at one single input port of the processing unit, or connected in series at one single input port of the processing unit.

According to another variant, the electrically-conductive track located beneath the contact pad could contact the latter. This allows also detecting a defect located at the contact pad or just below. However, it is not possible to perform this detection during the application operation of the integrated circuit.

More specifically, in this other variant, the at least one area of the interconnection portion (in which it is possible to detect the possible presence of a structural defect) also incorporates the contact pad.

According to an embodiment of this other variant, wherein the interconnection portion includes N metal levels, the rank 1 metal level being the metal level the closest to the substrate, the contact pads being located at the rank N metal level, the electrically-conductive region includes an electrically-conductive track having a first end located at the contact pad and a second end located at the rank 1 metal level, the two ends being able to be electrically coupled to the detection device, and a branch extending between the first end and the second end.

For example, this branch includes a stack of metal portions, respectively located at the rank 1 to N−1 metal levels, of vias between these metal portions, and of a via between the metal portions located at the N−1 metal level and the contact pad.

According to another embodiment of this other variant, wherein the interconnection portion includes N metal levels, the rank 1 metal level being the metal level the closest to the substrate, the contact pads being located at the rank N metal level, and the electrically-conductive region includes a third active area located in the semiconductor substrate and an electrically-conductive track.

This electrically-conductive track has a first end located at the contact pad and a second end located at the rank 1 metal level, the two ends being able to be electrically coupled to the detection device, a branch extending between the first end and the third active area, and a third contact connected between the third active area and the second end.

This other embodiment allows detecting a defect located at the contact pad or just below or between this contact pad and the substrate. However, herein again, it is possible to perform this detection during the application operation of the integrated circuit

For example, the branch may include a stack of metal portions, respectively located at the 1 to N−1 rank metal levels, of vias between these metal portions, of a via between the metal portion located at the N−1 metal level and the contact pad and of a contact between the third active area and the metal portion located at the rank 1 metal level.

The detection system may include a pull-up resistor having a first terminal able to be coupled to a supply voltage and a second terminal coupled to the second end of the electrically-conductive track.

The detection system may also include a pull-down resistor having a first terminal able to be coupled to a power supply ground point, for example the ground, and a second terminal coupled to the second end of the electrically-conductive track.

The electrically-conductive region may include several star-connected electrically-conductive tracks, the contact pad incorporating the first ends of all tracks.

According to another aspect, an integrated circuit belonging to the electronic system as defined hereinbefore is provided.

According to another aspect, a method is provided, comprising providing an integrated circuit, including a semiconductor substrate, an interconnection portion located above the substrate and having metal levels and vias and contacts levels embedded in an electrically-insulating region as well as contact pads located at the last metal level of the interconnection portion, and detecting the possible presence of at least one type of structural defects, for example a crack and/or a delamination, within at least one area of the interconnection portion located at least beneath a contact pad.

According to one implementation, the detection comprises detecting at least one electrical discontinuity of an electrically-conductive region located at least in the area.

The areas may also incorporate the contact pad.

The electrically-conductive region may include at least one active located in the semiconductor substrate.

1 FIG. In, the reference SYS designates an electronic system comprising an integrated circuit IC and a detection system MDET.

As it will be seen in more detail hereinafter, the detection system MDET may be located entirely in the integrated circuit IC or partially outside the integrated circuit IC.

This integrated circuit IC includes a ring PDF of contact pads PD (“pads” in English) as well as a peripheral sealing ring SR.

In this example, the integrated circuit IC also includes a processing unit UT, for example an electronic chip which, in some cases, may be part of the detection system MDET.

2 FIG. As illustrated in, the integrated circuit comprises a semiconductor substrate SB as well as an interconnection portion INT (known to a person skilled in the art by the acronym “BEOL”: “Back End Of Lines”) located above the substrate SB.

This interconnection portion has metal levels, herein 5 metal levels M1-M5 and vias levels V embedded in an electrically-insulating region DL, generally a dielectric material.

The interconnection portion also has the contact pads PD located at the last metal level of the interconnection portion.

To simplify the figure, only one contact pad PD is shown.

The interconnection portion INT also has a contacts level between the rank 1 metal level M1 and active regions of the substrate and/or components such as transistors.

2 FIG. + In, for simplicity, only one contact CT is shown between an active region ZA of the substrate (for example an Ndoped region) and a track of the metal level M1.

Still to simplify the figure, the insulating regions, for example of the “shallow trench” type (known to a person skilled in the art by the acronym “STI”: Shallow Trench Isolation”) isolating the active region from the rest of the substrate SB, are not shown.

The interconnection portion INT is conventionally covered with a passivation layer CP having open areas ZB so as to uncover the contact pads PD.

These contact pads are intended to receive, by soldering, connecting wires (“wire bonding”) or solder balls.

These operations of soldering the wires or the balls may cause the apparition of defects DFT in an area ZD located at least beneath the contact pad PD and possibly at this contact pad PD.

These structural defects may include cracks and/or delaminations.

The aforementioned detection system MDET is configured to detect the possible presence of at least one type of structural defects DFT within at least one area ZD of the interconnection portion INT, this area ZD being located at least beneath a contact pad PD and which could incorporate the contact pad itself.

1 FIG. As illustrated in, the detection system MDET comprises an electrically-conductive region RGC located in the area ZD at least beneath a contact pad, this electrically-conductive region RGC could also incorporate the contact pad itself as will be seen in more detail hereinafter.

The detection system MDET also includes a detection device configured to detect at least one electrical discontinuity of the region RGC.

1 FIG. In the example of, the detection device may comprise the processing unit UT.

It will be seen hereinafter that the detection system may also include a module external to the integrated circuit, for example a tester.

10 FIG. schematically illustrates steps of a mode of implementation of a method according to an embodiment.

10 More particularly, in a step S, an integrated circuit IC is provided including a semiconductor substrate, and an interconnection portion located above the substrate and having metal levels and vias levels embedded in an electrically-insulating region, the interconnection portion also having contact pads located at the last metal level of this interconnection portion.

11 Then, in a step S, the possible presence of at least one type of structural defects within at least one area ZD of the interconnection portion is detected, the area being located at least beneath a contact pad.

11 110 More particularly, this detection Scomprises detecting Sat least one electrical discontinuity of an electrically-conductive region RGC located in the area ZD.

110 If such an electrical discontinuity is detected in step S, then one could conclude on the presence of a defect DFT in the area ZD.

110 Conversely, if in step S, no electrical discontinuity of the region RG is detected, then one could conclude that no defect is detected in this area ZD;

3 FIG. Reference is not made more particularly toto describe an embodiment.

In this embodiment, the interconnection portion INT includes N=5 metal levels, the rank 1 metal level referenced M1, being the metal level the closest to the substrate SB.

The contact pads PD are located at the rank N metal level, referenced M5.

The metal levels M2, M3 and M4 are intermediate metal levels between the metal level M1 and the metal level M5.

The electrically-conductive region RGC includes an electrically-conductive track CH.

1 2 This electrically-conductive track CH has a first end EXlocated at the rank 1 metal level M1 and a second end EXalso located at the rank 1 metal level M1.

1 2 These two ends EXand EXare able to be electrically coupled to the detection device of the detection system MDET.

1 1 2 2 1 2 In this embodiment, this detection device includes a first inverter INVwhose output is connected to the first end EX, a second inverter INVwhose input is connected to the second end EX, and the processing unit UT connected, on the one hand, to the input of the first inverter INVand, on the other hand, to the output of the second inverter INV.

1 1 The electrically-conductive track CH also includes a first branch BRextending from the first end EXup to the rank N−1 metal level, herein the rank 4 metal level M4.

2 2 The electrically-conductive track CH also includes a second branch BRextending from the rank N−1 metal level M4 up to the second end EX.

1 2 The two branches BRand BRare mutually connected at the rank N−1 metal level M4.

1 11 21 31 4 11 21 31 More specifically, the first branch BRincludes a stack of metal portions PM, PM, PM, PMrespectively located at the rank 1 to 4 metal levels M1-M4 and of vias V, V, Vbetween these metal portions.

11 1 The metal portion PMforms the first end EXof the electrically-conductive track CH.

2 21 22 32 4 12 22 32 The second branch BRincludes a stack of metal portions PM, PM, PM, PMrespectively located at the metal level M1-M4 and of vias V, V, Vbetween these metal portions.

21 2 The metal portion PMforms the second end EXof the electrically-conductive track CH.

4 4 The metal portion PMalso forms a connection metal portion connecting the two metal portions PMof the two branches located at the metal level M4.

3 FIG. As illustrated in, in this embodiment, it is possible to detect a structural defect DFT, of the cracks and/or delamination type, located between the metal level M1 and the metal level M4 by detecting an electrical discontinuity DISC of the electrically-conductive track CH.

3 FIG. 22 For example, in the example of, the defect DFT causes an electrical discontinuity DISC located at the via V.

However, this embodiment does not allow detecting defect DFT that would be located between the metal level M4 and the contact pad PD.

In return, this embodiment allows performing a detection of a defect DFT in the area ZD between the metal levels M1 and M4, including these levels M1 and M4, whether during a test of the integrated circuit or even during an application operation of the integrated circuit.

1 To perform this detection, the processing unit UT delivers, for example, at the input of the inverter INVa voltage corresponding to a 1 logic level.

1 2 2 If there is no discontinuity DISC, a 0 logic level is obtained at the output of the inverter INV, which is found at the input of the inverter INV. Hence, the logic level is found at the output of the inverter INV.

1 2 If the logic level at the input of the inverter INVis shifted, in the absence of any discontinuity, we should find the same logic level at the output of the inverter INV.

1 2 Conversely, if, upon a modification of the logic level at the input of the inverter INV, we do not find this same modification at the output of the inverter INV, this means that there is an electrical discontinuity in the electrically-conductive track CH, which is synonymous of the presence of a defect DFT.

4 FIG. 1 4 In order to further improve the detection of defects, as schematically illustrated inwhich illustrates a top view of the contact pad PD, it is possible to provide within the electrically-conductive region RGC for several star-connected electrically-conductive tracks, herein four electrically-conductive tracks CH-CH.

In this schematic figure, these tracks are illustrated at random positions of the contact pad.

In practice, they may, for example, be arranged respectively beneath the four corners of the contact pads PD.

10 1 20 4 A first inverter INVhas its output connected to the first end of the track CHand a second inverter INVhas its input connected to the second end of the track CH.

3 FIG. These two inverters are connected to the processing unit UT in a way similar to what has been described with reference to.

1 4 It is then possible to detect one or more discontinuit(y/ies) in one or more of the tracks CH-CH.

Of course, it is possible to provide for more than four tracks.

Thus, a fifth track could also be arranged beneath the center of the contact pad.

5 FIG. Reference is now made more particularly toto describe another embodiment.

In this embodiment, the area ZD in which it is possible to detect any structural defects also incorporates the contact pad PD located at the rank N metal level, herein the metal level M5.

1 2 More specifically, it is possible, for example, to detect a defect DFTlocated between the metal level M2 and M3 or a defect DFTlocated between the metal level M4 and the metal level M5 or still possibly a structural defect in the contact pad itself.

5 In this respect, herein again, the electrically-conductive region RGC includes an electrically-conductive track CH.

5 1 2 1 2 This track CHhas a first end EXlocated at the contact pad PD and a second end EXlocated at the rank 1 metal level M1. Herein again, the two ends EXand EXare able to be electrically coupled to the detection device which, in this embodiment, includes an external module such as a tester, TST.

1 2 The tester is looped back between the first end EXand the second end EX, for example via another contact pad which is not shown herein.

1 2 1 2 For example, the tester may apply a voltage difference between the two ends EXand EXand verify the presence, or not, of a current flowing between these two ends EXand EX.

5 1 2 The presence of a current is synonymous of an absence of electrical discontinuity of the track CHand therefore an absence of detection of a defect DFTor DFT.

1 2 Conversely, the absence of a current between these two ends is synonymous of the presence of at least one electrical discontinuity of this track and therefore the presence of at least one defect DFTor DFT.

5 5 1 2 In this respect, the track CHincludes a branch BRextending between the first end EXand the second end EX.

51 52 53 54 51 52 53 54 54 This branch includes a stack of metal portions PM, PM, PM, PMrespectively located at the metal level M1-M4, of vias V, V, Vbetween these metal portions and a via Vbetween the metal portion PMlocated at the metal level M4 and the contact pad PD.

A defect(s) detection is performed during a test of the integrated circuit but is not be performed during the application operation of the integrated circuit.

6 FIG. 100 200 As illustrated in, herein again, to detect the possible presence of a defect, it is possible to use, instead of an external tester TST, the processing unit UT present within the integrated circuit in combination with two inverters INVand INV.

100 The inverter INVhas its output connected to the contact pad PD and its input is connected to the processing unit UT.

200 2 5 The second inverter INVhas its input connected to the second end EXof the track CHand its output connected to the processing unit UT.

3 FIG. 200 100 5 By analogy with what has been described with reference to, a detection of a logic level chattering at the output of the second inverter INVin response to a logic level chattering at the input of the inverter INVis synonymous of the absence of any electrical discontinuity in the track CHand therefore of the absence of detection of a defect.

200 100 5 Conversely, failure to detect a logic level chattering at the output of the second inverter INVin response to a chattering at the input of the inverter INVis synonymous of at least one electrical discontinuity in the track CHand therefore of the presence of at least one structural defect in the area ZD.

When using the processing unit UT for the detection of the electrical discontinuity, the latter should be powered between the supply voltage VDD and the ground GND.

7 FIG. 2 6 However, it is possible to also detect a defect DFT beneath a contact pad PDGND intended to be connected to the ground by placing, as illustrated in, a pull-up resistor RPP (Pull-up) connected, on the one hand, to the supply voltage VDD and, on the other hand, to the second end EXof the electrically-conductive track CHa first end of which is located at the contact pad PDGND.

6 1 2 6 Indeed, in the absence of any electrical discontinuity of the track CH, the node NDconnected at the second end EXof the track CH, remains grounded which enables the processing unit to detect an absence of defects.

6 1 Conversely, in the presence of at least one electrical discontinuity of the track CH, the node NDis floating but will be pulled towards the supply VDD via the resistor RPP.

1 6 An increase in the voltage at the node ND, detected by the processing unit UT, is then synonymous of an electrical discontinuity in the track CHand therefore of the presence of a defect.

8 FIG. 2 2 7 In the case where the processing unit UT is intended to detect the possible presence of a defect beneath a contact pad PDVDD intended to be powered with the supply voltage VDD, then it is provided, as illustrated in, to connect a pull-down resistor (pull-down) RPD between the node NDconnected to the second end EXof the track CHand the ground GND.

7 2 7 2 In the absence of any electrical discontinuity of the track CH, the voltage VDD is present at the node NDwhereas in the presence of an electrical discontinuity in the track CH, the voltage at the node NDwill be grounded via the resistor RPD.

7 This voltage decrease, detected by the processing unit UT is also synonymous of the presence of at least one electrical discontinuity of the track CHand therefore of the presence of at least one structural defect beneath the contact pad PD VDD.

9 FIG. 50 51 52 53 As illustrated in, in order to further improve the defect detection, it is also possible to provide for several star-connected electrically-conductive tracks, herein four tracks CH, CH, CH, CH, beneath the contact pad PD.

150 151 152 153 50 51 52 53 More specifically, the contact pad PD forms the respective first ends EX, EX, EX, EXof the four tracks CH, CH, CH, CH.

250 251 252 253 The respective second ends EX, EX, EXand EXof these tracks are connected separately, for example at four input ports of the processing unit UT or in a multiplexed manner at one input port of the processing unit.

In the example described herein, the four tracks are connected at the middle of the four edges of the contact pad PD.

Of course, they could be located differently for example at the four corners.

11 12 FIGS.and Other embodiments are also possible as it will be now described with reference to.

11 FIG. 3 FIG. 3 FIG. In, elements that are similar or having functions that are similar to those ofbear the same references as those of.

Only the differences between these two figures are described.

1 2 The electrically-conductive region RGC includes a first active area ZAand a second active area ZAlocated in the semiconductor substrate SB.

+ The substrate herein typically is a substrate with a P conductivity type and the active areas herein are Ndoped areas. They are isolated from each other and isolated from the rest of the substrate SB by insulating regions RIS for example of the “shallow trench” type.

7 The region RGC also includes an electrically-conductive track CH.

7 1 2 1 2 3 FIG. This electrically-conductive track CHhas a first end EXand a second end EXlocated at the rank 1 metal level and able to be electrically coupled to the detection device, including, like in, inverters INVand INVconnected to the processing unit UT.

7 27 The first end of the track CHis herein formed by a metal portion PM.

7 28 The second end of the track CHis herein formed by another metal portion PM.

7 10 1 27 1 The track CHalso has a first contact CTconnected between the first end EX(metal portion PM) and the first active area ZA.

7 7 1 8 2 The track CHalso includes a first branch BRextending from the first active area ZAup to the rank N−1 metal level M4 (N=5 herein), and a second branch BRextending from the rank N−1 metal level M4 up to the second active area ZA.

7 21 2 2 28 The electrically-conductive track CHalso includes a second contact CTconnected between the second active area ZAand the second end EX(metal portion PM).

7 8 11 20 1 2 17 18 Each branch BR, BRherein includes a stack of metal portions, respectively located at the rank 1 to N−1 metal levels M1 to M4, of vias between these metal portions and of a contact CT, CTbetween the corresponding active area ZA, ZAand the corresponding metal portion PM, PMlocated at the rank 1 metal level M1.

4 A connection metal portion PMlocated at the rank n−1 metal level connects the two metal portions of the two branches located at the rank N−1 metal level.

7 1 2 6 7 7 Such an embodiment wherein the electrically-conductive track CHthat does not contact the contact pad but extends up to the active areas ZA, ZAof the substrate, allows, if one wishes so, continuously detecting the apparition of a structural defect DFT, DFTbeneath the contact pad, even when the integrated circuit is in its application operation, and that being so between the rank N−1 metal level and the semiconductor substrate. In particular, it is possible to detect a defect DFTsuch as a delamination, the closest to the substrate SB.

12 FIG. 5 FIG. 5 FIG. In, elements that are similar or having functions that are similar to those ofbear the same references as those of.

Only the differences between these two figures are described.

3 The electrically-conductive region RGC includes a third active area ZAlocated in the semiconductor substrate SB.

3 + The substrate herein typically is a substrate with a P conductivity type and the active area ZAherein is an Ndoped area. It is isolated from the rest of the substrate SB by insulating regions RIS for example of the “shallow trench” type.

9 The region RGC also includes an electrically-conductive track CH.

9 1 2 This electrically-conductive track CHhas a first end EXlocated at the contact pad PD and a second end EXlocated at the rank 1 metal level, the two ends being able to be electrically coupled to the detection device TST.

2 29 The second end EXis herein formed by a metal portion PMlocated at the rank 1 metal level M1.

9 1 3 The track CHP also includes a branch BRextending between the first end EXand the third active area ZA.

9 91 3 2 29 The track CHalso includes a third contact CTconnected between the third active area ZAand the second end EX(metal portion PM).

9 94 90 3 19 The branch BRherein includes a stack of metal portions, respectively located at the rank 1 to N−1 metal levels M1 to M4, of vias between these metal portions, of a via Vbetween the metal portion located at the metal level M4 and the contact pad PD and of a contact CTbetween the third active area ZAand the metal portion PMlocated at the rank 1 metal level M1.

2 1 2 0 This other embodiment allows detecting a defect DFTlocated at the contact pad or just beneath or a defect located between this contact pad and the substrate, for example a defect DFTlocated at the middle of the branch BRor a defect DFTlocated in the vicinity of the substrate SB.

2 7 8 FIGS.and As the case may be, it is also possible to connect a pull-up resistor or a pull-down resistor on the second end EXas described with reference to.

Of course, what has been described hereinabove for one single contact pad could apply in practice for all of the contact pads, irrespective of the considered embodiment.

In other words, the detection system MDET may be configured to detect the possible presence of at least one type of structural defects within areas ZD of the interconnection portion respectively located at least beneath each contact pad.

Thus, in this respect, it is provided to arrange electrically-conductive regions RGC respectively at least in each area and to provide for at least one detection device UT, TST configured to detect at least one electrical discontinuity DISC of each region RGC. It should also be noted that the present embodiments are compatible with the embodiments described in the aforementioned French patent application number 2406877, providing for the presence of an annular wall inside, or on either or both sides of, the sealing ring.