Memory System and Power Control Circuit

120 387 This application is a continuation of and claims benefit under 35 U.S.C. §to U.S. Application No. 18/358,, filed July 25, 2023, which is based upon and claims the benefit of priority from Japanese Patent Application No. 2022-147204, filed September 15, 2022, the entire contents of each of which are incorporated herein by reference.

Embodiments described herein relate generally to a memory system including a nonvolatile memory, and a power control circuit of the memory system.

In recent years, memory systems that include a nonvolatile memory are widely used. As one of such memory systems, a solid state drive (SSD) that includes a NAND flash memory is known. The SSD is used as a main storage for various computing devices.

A memory system includes a power control circuit. The power control circuit is a circuit that controls power to be supplied to each unit of the memory system.

The memory system may be set in a low power consumption mode. The low power consumption mode is a mode in which power consumption is lower than that in a normal operation mode.

When the memory system has exit from the low power mode to the normal operation mode, initialization of at least part of the memory system is performed. Power supplied from the power control circuit to each unit of the memory system immediately after the exit may have large variations in voltage. Such variations in supply voltage may cause a failure of the initialization in the memory system.

In general, according to one embodiment, a memory system connectable to a host includes a nonvolatile memory, a controller, and a power control circuit. The controller controls the nonvolatile memory. The power control circuit controls power to be supplied to the controller and the nonvolatile memory and includes one or more DC/DC converters. The nonvolatile memory and the controller include one or more circuit blocks. Each of the one or more DC/DC converters supplies an internal power supply voltage to one of the one or more circuit blocks. A first DC/DC converter of the one or more DC/DC converters transitions to a forced pulse width modulation mode in response to the memory system that has transitioned from a low power consumption mode to a normal operation mode.

Various embodiments will be described hereinafter with reference to the accompanying drawings.

1 1 2 3 1 FIG. First, an example of a configuration of an information processing systemthat includes a memory system according to an embodiment will be described with reference to. The information processing systemincludes a host deviceand a memory system.

2 3 3 2 2 The host deviceis capable of storing data in the memory systemand reading data from the memory system, and it is, for example, a storage server and a personal computer. Hereinafter, the host devicewill also be referred to as a host.

3 5 5 3 3 The memory systemis, for example, a storage device configured to write data to a nonvolatile memory, such as a NAND flash memory, and read data from the nonvolatile memory. Note that the nonvolatile memory is not limited to the NAND flash memory. The memory systemis also referred to as a storage device. The memory systemis realized as, for example, a solid state drive (SSD).

3 2 3 2 The memory systemmay be used as a storage of the host. The memory systemis connected to the hostvia a cable, for example.

2 3 An interface for connecting the hostand the memory systemconforms to standards such as PCI ExpressTM (PCIeTM) or NVM ExpressTM (NVMeTM).

3 3 3 3 3 The memory systemoperates, for example, in either a normal operation mode or a low power consumption mode. The low power consumption mode is an operation mode in which power consumption is lower than that in the normal operation mode. The low power consumption mode may include an off mode in which power supply to at least part of units of the memory systemis stopped, and a low power mode (LPM) in which the operation and performance are restricted to lower power consumption than that in the normal operation mode. The low power mode includes, for example, a mode called a sleep mode. In a case where the memory systemhas multiple low power consumption modes such as the off mode and the sleep mode, a decrease in power consumption of the memory systemcan be controlled more effectively. Note that the low power consumption modes may include two or more modes. Thus, multiple power states that are different in power consumption may be provided as the low power consumption modes of the memory systemof the present embodiment.

3 4 5 6 7 The memory systemincludes, for example, a dynamic random access memory (DRAM), a NAND flash memory, a power control circuit, and a controller.

4 51 The DRAMis a volatile RAM and includes, for example, a storage area of firmware (FW).

51 7 51 5 4 3 The FWis a program for controlling the operation of the controller. The FWis loaded from the NAND flash memoryto the DRAMwhen the memory systemis boot up, for example.

5 The NAND flash memoryincludes multiple blocks (not illustrated). Each of the blocks includes multiple pages. The blocks each function as the minimum unit of a data erase operation. The block may also be referred to as an erasure block or a physical block. Each of the pages includes memory cells connected to a single word line. The pages each function as a unit of a data write operation and a data read operation. Note that the word line may function as a unit of a data write operation and a data read operation.

6 4 5 7 3 6 6 3 6 3 6 The power control circuitcontrols power to be supplied to each unit (for example, the DRAM, the NAND flash memory, and the controller) of the memory system. The power control circuitis implemented as a power management IC (PMIC), for example. The power control circuittransitions to a sleep mode in response to the memory systemthat has transitioned from the normal operation mode to the low power consumption mode. The power control circuitexits from the sleep mode in response to the memory systemthat has transitioned from the low power consumption mode to the normal operation mode. The sleep mode is a mode in which at least part of circuit blocks in the power control circuitare turned off to reduce power consumption.

6 7 6 7 6 7 6 6 2 FIG. The power control circuitis capable of communicating with the controller. Communications between the power control circuitand the controllerconforms to a serial communication standard such as Inter-Integrated Circuit (I2C) (not illustrated). The power control circuitreceives, for example, a command from the controllervia the communications. This command is, for example, a command for controlling the operation of the power control circuit. The specific configuration of the power control circuitwill be described later with reference to.

7 4 5 6 7 7 4 7 The controlleris a controller configured to control the DRAM, the NAND flash memory, and the power control circuit. The controlleris implemented by a circuit such as a system-on-a-chip (SoC). The controllermay include a static random access memory (SRAM) or a DRAM. In this case, the DRAMoutside the controllerneed not be provided.

7 11 12 13 14 11 12 13 14 10 The controllerincludes, for example, a host interface (host I/F), a NAND interface (NAND I/F), a DRAM interface (DRAM I/F), and a CPU. The host I/F, the NAND I/F, the DRAM I/F, and the CPUare connected via a bus, for example.

11 2 11 2 11 15 The host I/Ffunctions as a circuit that receives various commands, for example, I/O commands and various control commands, and data from the host. The host I/Falso functions as a circuit that transmits a response to a command and data to the host. The host I/Fincludes a PCIe PHY.

15 2 2 3 15 15 15 The PCIe PHYis a circuit that is connected to the hostvia a serial interface. The serial interface includes a link capable of interconnecting the hostand the memory system. The PCIe PHYcorresponds to a physical layer defined by the PCIe standard. The PCIe PHYhas, for example, a physical connection form that conforms to the PCIe standard. The PCIe PHYperforms an interface operation for physically transmitting and receiving data via the link.

12 7 5 12 The NAND I/Felectrically connects the controllerand the NAND flash memory. The NAND I/Fconforms to an interface standard such as Toggle DDR or Open NAND Flash Interface (ONFI).

12 5 12 5 7 5 The NAND I/Ffunctions as a NAND control circuit configured to control access to the NAND flash memory. The NAND I/Fmay be connected to the respective memory chips in the NAND flash memoryvia multiple channels (Ch). By operating the memory chips in parallel, it is possible to broaden an access bandwidth between the controllerand the NAND flash memory.

13 4 The DRAM I/Ffunctions as a DRAM control circuit configured to control access to the DRAM.

14 11 12 13 14 51 5 4 51 14 14 2 14 51 14 The CPUis a processor configured to control the host I/F, the NAND I/F, and the DRAM I/F. The CPUperforms various processes by executing the FWloaded from the NAND flash memoryonto the DRAM. The FWis a control program including instructions for causing the CPUto execute the various processes. The CPUmay perform command processes to execute various commands from the host. The operation of the CPUis controlled by the FWexecuted by the CPU.

7 7 14 51 The function of each unit in the controllermay be realized by dedicated hardware in the controlleror may be realized by the CPUexecuting the FW.

6 6 2 FIG. Next, the configuration of the power control circuitwill be described.is a circuit diagram illustrating an example of the configuration of the power control circuit.

6 61 62 63 64 64 1 64 2 64 3 64 4 The power control circuitincludes, for example, control logic, a load switch, a low dropout (LDO) regulator, and one or more DC/DC converters(-,-,-,-, ...).

61 6 61 6 61 6 7 5 7 5 5 15 6 The control logicis a circuit that controls each unit in the power control circuit. The control logicsends, for example, a control signal to control the operation of each unit in the power control circuit. Also, the control logicmay monitor a value related to a current that is passed through each of one or more circuit blocks to which power is supplied from the power control circuit. The value related to a current to be monitored may be a value of the current itself or may be an index or a signal that represents the value of the current. Each of the circuit blocks is included, for example, in either the controlleror the NAND flash memory. More specifically, each of the circuit blocks is, for example, a core part of the SoC that is the controller, a core part of the NAND flash memory, an input/output (I/O) part of the NAND flash memory, or the PCIe PHY. From the point of view of the power control circuit, each circuit block to which power is supplied is also called a load. The current that is passed through the load is also called a load current.

62 6 62 62 61 62 The load switchis a switch circuit that switches between the supply (on) and stop (off) of power to each unit in the power control circuit. The load switchis supplied with a power supply voltage VIN from an external power supply. The load switchswitches between the on and off of power supply in response to a control signal from the control logic. The load switchoutputs a power supply voltage VOUT while it is turned on.

6 6 6 6 63 64 The power supply voltage VOUT is output to the outside of the power control circuitthrough a pin of the power control circuit. The power supply voltage VOUT is taken in the power control circuitthrough another pin of the power control circuit. More specifically, the power supply voltage VOUT is input as an input power supply voltage LDO_IN of the LDO regulator. The power supply voltage VOUT is also input as an input power supply voltage PVIN of each of the one or more DC/DC converters.

63 63 62 63 61 63 The LDO regulatoris a linear regulator that is capable of operating with a small input/output potential difference. The LDO regulatoradjusts the input power supply voltage LDO_IN by voltage control and outputs an internal power supply voltage LDO_OUT. Instead of the output voltage VOUT of the load switch, another voltage may be used for the input power supply voltage LDO_IN. The LDO regulatoroperates (turns on) or stops (turns off) in response to a control signal from the control logic. While the LDO regulatorturns on, it outputs the internal power supply voltage LDO_OUT.

6 6 7 The internal power supply voltage LDO_OUT is output to the outside of the power control circuitthrough a pin of the power control circuit. The internal power supply voltage LDO_OUT is, for example, 1.8 volts (V). The internal power supply voltage LDO_OUT is used, for example, for an analog power supply to the SoC that is the controller.

64 64 7 5 64 6 3 6 64 64 64 64 1 64 2 64 3 64 4 Each of the one or more DC/DC convertersis a converter that converts a voltage in direct current. Each of the one or more DC/DC convertersgenerates an internal power supply voltage to be supplied to a circuit block that is included in either the controlleror the NAND flash memory. The number of the DC/DC convertersprovided in the power control circuitis based on the number of components (for example, circuit blocks) in the memory systemto be supplied with power from the power control circuit. Note that in the following descriptions, any unspecified one of the one or more DC/DC convertersmay be referred to simply as a DC/DC converter. Here, a case where the one or more DC/DC convertersinclude four DC/DC converters-,-,-, and-will be explained as illustrated in the figure.

64 1 62 64 1 1 62 1 64 1 61 64 1 1 The first DC/DC converter-is supplied with the power supply voltage VOUT from the load switchas an input power supply voltage PVIN1. The first DC/DC converter-adjusts the input power supply voltage PVIN1 by voltage control and outputs an internal power supply voltage DC/DC_OUT. Instead of the output voltage VOUT of the load switch, another voltage may be used for the input power supply voltage PVIN. The first DC/DC converter-operates (turns on) or stops (turns off) in response to a control signal from the control logic. While the first DC/DC converter-turns on, it outputs the internal power supply voltage DC/DC_OUT.

1 6 6 1 1 5 1 5 64 1 5 1 1 64 The internal power supply voltage DC/DC_OUT is output to the outside of the power control circuitthrough a pin of the power control circuit. The internal power supply voltage DC/DC_OUT is, for example, 2.5 V. The internal power supply voltage DC/DC_OUT is used, for example, for a power supply for the core part of the NAND flash memory. That is, the internal power supply voltage DC/DC_OUT is supplied to a circuit block of the core part of the NAND flash memory. A power supply channel from the first DC/DC converter-to the core part of the NAND flash memorywith the internal power supply voltage DC/DC_OUT is referred to as a DC/DC channel CH. A DC/DC channel that is a power supply channel is assigned information (for example, number) by which the corresponding DC/DC converteris identifiable.

64 2 62 2 64 2 2 62 2 64 2 61 64 2 2 The second DC/DC converter-is supplied with the power supply voltage VOUT from the load switchas an input power supply voltage PVIN. The second DC/DC converter-adjusts the input power supply voltage PVINby voltage control and outputs an internal power supply voltage DC/DC2_OUT. Instead of the output voltage VOUT of the load switch, another voltage may be used for the input power supply voltage PVIN. The second DC/DC converter-operates (turns on) or stops (turns off) in response to a control signal from the control logic. While the second DC/DC converter-turns on, it outputs the internal power supply voltage DC/DC_OUT.

2 6 6 2 2 5 2 5 64 2 5 2 2 The internal power supply voltage DC/DC_OUT is output to the outside of the power control circuitthrough a pin of the power control circuit. The internal power supply voltage DC/DC_OUT is, for example, 1.2 V. The internal power supply voltage DC/DC_OUT is used, for example, for a power supply for the I/O part of the NAND flash memory. That is, the internal power supply voltage DC/DC_OUT is supplied to a circuit block of the I/O part of the NAND flash memory. A power supply channel from the second DC/DC converter-to the I/O part of the NAND flash memorywith the internal power supply voltage DC/DC_OUT is referred to as a DC/DC channel CH.

64 3 62 3 64 3 3 3 62 64 3 61 64 3 3 The third DC/DC converter-is supplied with the power supply voltage VOUT from the load switchas an input power supply voltage PVIN. The third DC/DC converter-adjusts the input power supply voltage PVINby voltage control and outputs an internal power supply voltage DC/DC_OUT. Instead of the output voltage VOUT of the load switch, another voltage may be used for the input power supply voltage PVIN3. The third DC/DC converter-operates (turns on) or stops (turns off) in response to a control signal from the control logic. While the third DC/DC converter-turns on, it outputs the internal power supply voltage DC/DC_OUT.

3 6 6 3 3 15 7 3 15 64 3 15 3 3 The internal power supply voltage DC/DC_OUT is output to the outside of the power control circuitthrough a pin of the power control circuit. The internal power supply voltage DC/DC_OUT is, for example, 1.2 V. The internal power supply voltage DC/DC_OUT is used, for example, for a power supply for the PCIe PHYincluded in the SoC that is the controller. That is, the internal power supply voltage DC/DC_OUT is supplied to a circuit block of the PCIe PHY. A power supply channel from the third DC/DC converter-to the PCIe PHYwith the internal power supply voltage DC/DC_OUT is referred to as a DC/DC channel CH.

64 4 62 4 64 4 4 4 62 64 4 61 64 4 4 The fourth DC/DC converter-is supplied with the power supply voltage VOUT from the load switchas an input power supply voltage PVIN. The fourth DC/DC converter-adjusts the input power supply voltage PVINby voltage control and outputs an internal power supply voltage DC/DC_OUT. Instead of the output voltage VOUT of the load switch, another voltage may be used for the input power supply voltage PVIN4. The fourth DC/DC converter-operates (turns on) or stops (turns off) in response to a control signal from the control logic. While the fourth DC/DC converter-turns on, it outputs the internal power supply voltage DC/DC_OUT.

4 6 6 4 4 7 4 The internal power supply voltage DC/DC_OUT is output to the outside of the power control circuitthrough a pin of the power control circuit. The internal power supply voltage DC/DC_OUT is, for example, 0.8 V. The internal power supply voltage DC/DC_OUT is used, for example, for a core part of the SoC that is the controller. That is, the internal power supply voltage DC/DC_OUT is supplied to a circuit block of the core part of the SoC.

64 6 4 1 FIG. As the DC/DC convertersof the power control circuit, another DC/DC converter that outputs a power supply voltage to the DRAMillustrated inmay be included.

61 65 In addition, the control logicincludes one or more registers, for example.

65 6 7 14 51 65 65 1 65 2 Each of the registersis a memory element. The memory element may store, for example, a value that specifies an operation of at least part of the configuration of the power control circuit. The value stored in the memory element is set or updated in response to a request issued by the controller, for example. This request is implemented as, for example, a command issued by the CPUexecuting the FW. The registersinclude, for example, a DC/DC mode setting register-and a sleep mode control register-.

65 1 64 64 64 2 64 3 64 65 1 3 FIG. The DC/DC mode setting register-is a register for setting related to an operation mode of each of the DC/DC converters(-1,-,-,-4, ...). A specific example of a configuration of the DC/DC mode setting register-will be described later with reference to.

64 65-1 3 64 65-1 Each of the DC/DC convertersmay operate in an operation mode based on a value set in the DC/DC mode setting registerwhile the memory systemis set in the normal operation mode, for example. Each of the DC/DC convertersincludes, for example, a circuit such as a switch that operates on the basis of the value set in the DC/DC mode setting register.

65-2 1 6 2 63 64 6 65-2 6 FIG. The sleep mode control registeris a register for () setting of the power control circuitrelated to transition to the sleep mode and exit from the sleep mode and () setting related to an operation mode of the LDO regulatorand an operation mode of the DC/DC converterwhile the power control circuitis in the sleep mode. A specific example of a configuration of the sleep mode control registerwill be described later with reference to.

6 63 64 65-2 3 3 63 64 65-2 The power control circuit(more specifically, the LDO regulatorand the DC/DC converter) may operate on the basis of a value set in the sleep mode control register, for example, when the memory systemtransitions from the normal operation mode to the low power consumption mode and when the memory systemtransitions from the low power consumption mode to the normal operation mode. Each of the LDO regulatorand DC/DC converterincludes a circuit such as a switch that operates on the basis of the value set in the sleep mode control register, for example.

64 The operation mode of the DC/DC converterwill be described below.

64 64 The operation mode of the DC/DC converteris, for example, one of a pulse frequency modulation (PFM) mode, a pulse width modulation (PWM) mode, an auto mode, and an off mode. Each of the PFM and PWM modes is a voltage control scheme used by the DC/DC converterto generate an output voltage.

In the PFM mode, a voltage control scheme in which the frequency is variable and the pulse width is constant is used. In the PFM mode, power consumption is small, but variations in output voltage are large.

In the PWM mode, a voltage control scheme in which the frequency is constant and the pulse width is variable is used. In the PWM mode, the power consumption is large, but variations in output voltage are small.

64 64 The auto mode is a mode in which the PFM mode and the PWM mode are automatically switched depending on a load current. In the auto mode, when the load current has exceeded a boundary while the DC/DC converteris operating in the PFM mode, the PFM mode is switched to the PWM mode. Further, when the load current has become not larger than the boundary while the DC/DC converteris operating in the PWM mode, the PWM mode is switched to the PFM mode. Note that the boundary has hysteresis to prevent frequent switching between the PFM mode and the PWM mode near the boundary. The hysteresis may cause, for example, the boundary to be set more greatly in a case where the PFM mode is switched to the PWM mode than in a case where the PWM mode is switched to the PFM mode.

3 FIG. 65-1 3 65-1 8 8 is a diagram illustrating an example of a configuration of the DC/DC mode setting registerused in the memory system. The DC/DC mode setting registerincludes, for example, an-bit memory area. Hereinafter, memory areas ofbits of a register will be referred to as a zeroth bit memory area, a first bit memory area, ..., and a seventh bit memory area in order from the least significant bit.

64-1 1 3 0 64-1 1 64-1 64 The seventh bit memory area stores a value indicative of an operation mode of the first DC/DC converter(that is, the DC/DC channel CH) while the memory systemis in the normal operation mode. When the stored value is, the first DC/DC converteroperates in the auto mode. When the stored value is, the first DC/DC converteroperates in a forced PWM mode. Unlike in the auto mode, in the forced PWM mode, automatic switching does not occur. While the forced PWM mode is set, the operation mode of the DC/DC converteris fixed in the PWM mode.

64-2 3 0 64-2 1 64-2 The sixth bit memory area stores a value indicative of an operation mode of the second DC/DC converter(that is, the DC/DC channel CH2) while the memory systemis in the normal operation mode. When the stored value is, the second DC/DC converteroperates in the auto mode. When the stored value is, the second DC/DC converteroperates in the forced PWM mode.

64-3 3 0 64-3 1 64-3 The fifth bit memory area stores a value indicative of an operation mode of the third DC/DC converter(that is, the DC/DC channel CH3) while the memory systemis in the normal operation mode. When the stored value is, the third DC/DC converteroperates in the auto mode. When the stored value is, the third DC/DC converteroperates in the forced PWM mode.

The fourth to zeroth bit memory areas are reserved areas.

65-1 64 Note that the DC/DC mode setting registermay further store values indicative of operation modes of the other DC/DC converters.

64 65-1 3 65-1 64 3 65-1 6 14 51 Each of the DC/DC convertersmay operate based on the value set in the DC/DC mode setting registerwhile the memory systemis in the normal operation mode, for example. Therefore, the setting of a value in the DC/DC mode setting registerenables setting the operation mode of each of the DC/DC convertersto either the auto mode or the forced PWM mode while the memory systemis in the normal operation mode. Note that the setting of a value in the DC/DC mode setting registeris performed, for example, on the basis of a command issued to the power control circuitfrom the CPUexecuting the FW.

3 Here, an operation of a memory system according to a comparative example in a case where the memory system exits from a low power consumption mode to a normal operation mode. The memory system according to the comparative example has a configuration similar to that of the memory systemaccording to the present embodiment, except for the configuration related to control of operation modes of DC/DC converters.

4 FIG. 8 8 81 82 83 84 8 is a time chartillustrating transitions of operations and voltages in the case where the memory system according to the comparative example exits from the low power consumption mode to the normal operation mode. More specifically, the time chartillustrates the transitions of an internal power supply voltagesupplied to a NAND flash memory, operation modesof DC/DC converters, an internal power supply voltagesupplied to a PCIe PHY, and an operationof the PCIe PHY as time passes. The horizontal axis of the time chartindicates time.

4 FIG. 11 11 82 81 84 In, time tis time at which the memory system is requested to exit from the low power consumption mode to the normal operation mode. At time t, the memory system is in the low power consumption mode and the power control circuit is in the sleep mode. Thus, the operation modeof each of the DC/DC converters in the power control circuit is in an off state or is in a PFM mode with low power consumption. The internal power supply voltagesupplied to the NAND flash memory is off, and a DC/DC converter in an on state with low voltage is set in the PFM mode. In addition, the operationof the PCIe PHY is disabled.

11 12 81 The period from time tto time tis a period in which the memory system transitions from the low power consumption mode to the normal operation mode. Within this period, the internal power supply voltagesupplied to the NAND flash memory gradually rises and heightens.

12 12 82 Time tis time at which the memory system exits from the low power consumption mode to the normal operation mode. At time t, the operation modeof each DC/DC converter transitions to the auto mode. Since the load current is small at that time, the PFM mode is set based on automatic switching in the auto mode.

12 14 84 82 82 83 Then, in a period from time tto time t, the operationof the PCIe PHY transitions from being disabled to activation and then to initialization. The initialization includes calibration, for example. The calibration is, for example, an operation of passing a current through resistors provided in the PCIe PHY to adjust variations of chips (ICs). The load current of the PCIe PHY during the activation and initialization is small. Thus, the operation modeof each DC/DC converter is maintained in the PFM mode. While the operation modeis in the PFM mode, the internal power supply voltagesupplied to the PCIe PHY varies greatly.

12 14 13 14 83 83 83 Of the period from time tto time t, a period from time tto time tis a period in which the internal power supply voltagesupplied to the PCIe PHY varies greatly. In this period, the PCIe PHY starts the initialization. For example, in the calibration, the variations in voltage need to be small because current is passed through the resistors in the PCIe PHY to adjust the variations of the chips. That is, the calibration is an operation sensitive to the variations in voltage. Since, however, the variations in the internal power supply voltageare large, the PCIe PHY may perform the calibration incorrectly. Under the variations in the internal power supply voltage, therefore, the initialization in the PCIe PHY may fail.

14 84 82 Time tis time at which the operationof the PCIe PHY transitions from the end of the initialization to the normal operation. At this time, the operation modeof each DC/DC converter is maintained in the PFM mode.

15 82 Then, at time t, the operation modeof each DC/DC converter transitions to the PWM mode based on automatic switching in the auto mode. The timing when the automatic switching is triggered is, for example, the timing when a load current corresponding to any one of the DC/DC converters has exceeded a predetermined boundary.

As in the comparative example described above, the initialization of the PCIe PHY may fail because of the operation performed when the memory system exits from the low power consumption mode.

12 For example, at time tafter the memory system exits from the low power consumption mode to the normal operation mode, the setting of the DC/DC mode setting register may cause the operation mode of each DC/DC converter to transition to the forced PWM mode. This transition manner enables the PCIe PHY to perform the initialization while each DC/DC converter is operating in the forced PWM mode with small variations in voltage. In this case, however, it is desirable to transition each DC/DC converter to the forced PWM mode immediately after the memory system exits from the low power consumption mode to the normal operation mode. This is because the power consumption increases in the period of transition from the low power consumption mode to the forced PWM mode. On the other hand, in the transition method of the DC/DC converter to the forced PWM mode immediately after the memory system exits from the low power consumption mode to the normal operation mode, it needs to issue a command for each DC/DC converter to set in the forced PWM mode after the memory system exits to the normal operation mode and to cause each DC/DC converter to transition to the PWM mode. The time for performing the operation of issuing the command delays timing of starting access to the NAND flash memory. If, furthermore, the DC/DC converter continues to be in the forced PWM mode thereafter, its power consumption may increase compared to a case where the DC/DC converter is set in the auto mode.

5 FIG. 8 is a diagram illustrating an example of a configuration of a sleep mode control register that is used in the memory system according to the comparative example. The sleep mode control register of the comparative example includes, for example, an-bit memory area.

1 The seventh bit memory area stores a value indicative of an operation of a DC/DC channel CHwhile the power control circuit is in the sleep mode.

0 When the stored value is, the DC/DC channel CH1 is turned off. That is, a first DC/DC converter is in an off mode.

1 1 1 When the stored value is, then the DC/DC channel CHis alive and enters into the low power mode (LPM). While the DC/DC channel CHis in the LPM, the first DC/DC converter is fixed to the PFM mode. In the first DC/DC converter fixed to the PFM mode, a circuit block that is used only when the first DC/DC converter is in the PWM mode is turned off. That is, the circuit block that is used only when the first DC/DC converter is in the PWM mode, is not supplied with power. Accordingly, the DC/DC channel set in the LPM can reduce power consumption.

The sixth bit memory area stores a value indicative of an operation of a DC/DC channel CH2 while the power control circuit is in the sleep mode.

0 2 When the stored value is, the DC/DC channel CHis turned off. That is, a second DC/DC converter is in the off mode.

1 2 When the stored value is, the DC/DC channel CHis alive and enters into the LPM. In this case, the second DC/DC converter is fixed to the PFM mode.

3 The fifth bit memory area stores a value indicative of an operation of a DC/DC channel CHwhile the power control circuit is in the sleep mode.

0 3 When the stored value is, the DC/DC channel CHis turned off. That is, a third DC/DC converter is in the off mode.

1 3 When the stored value is, the DC/DC channel CHis alive and enters into the LPM. In this case, the third DC/DC converter is fixed to the PFM mode.

The fourth bit memory area stores a value indicative of an operation of a LDO regulator while the power control circuit is in the sleep mode.

0 When the stored value is, a power supply channel from the LDO regulator is turned off. That is, the LDO regulator is in the off mode.

1 When the stored value is, the power supply channel from the LDO regulator is alive and enters into the LPM. In this case, the LDO regulator decreases the current for control.

The third bit to first bit memory areas are reserved areas.

0 1 The zeroth bit memory area stores a value related to enter and exit of the sleep mode of the power control circuit. When the stored value is, the power control circuit exits from the sleep mode. When the stored value is, the power control circuit enters into the sleep mode.

As described above, in the memory system according to the comparative example, each of the first to third DC/DC converters and LDO regulator is set to the off mode or the LPM while the power control circuit is in the sleep mode, in accordance with a setting using the sleep mode control register. This reduces power consumption in the power supply control circuit. Whether each of the first to third DC/DC converters and LDO regulator is set in the off mode or the LPM is determined based on the power state of the low power consumption mode in which the memory system is set.

In the sleep mode control register of the memory system according to the comparative example, the operation mode of each DC/DC converter is not specified when the memory system exits from the low power consumption mode to the normal operation mode (that is, when the power control circuit exits from the sleep mode). In this case, therefore, the operation mode of each DC/DC converter typically transitions to the auto mode, for example, and is set to the PFM mode based on automatic switching in the auto mode because the load current is small. In this PFM mode, for example, the initialization of the PCIe PHY may fail due to large variations in voltage.

3 3 64 3 15 In contrast, in the memory systemaccording to the present embodiment, when the memory systemhas exit from the low power consumption mode to the normal operation mode, the operation mode of the DC/DC converteris caused to transition to the forced PWM mode. The forced PWM mode is a PWM mode in which automatic switching is not made unlike in the auto mode. In the forced PWM mode, variations in voltage are small. Therefore, a failure of initialization in the memory system(for example, in the PCIe PHY) can be prevented.

65-2 64 3 More specifically, by using the sleep mode control register, the operation mode of the DC/DC converteris caused to transition to the forced PWM mode when the memory systemhas exit from the low power consumption mode to the normal operation mode.

6 FIG. 5 FIG. 65-2 3 65-2 is a diagram illustrating an example of a configuration of the sleep mode control registerthat is used in the memory system. The sleep mode control registerdiffers from the sleep mode control register of the comparative example described above with reference toin the contents regarding the zeroth bit memory area. The values stored in the seventh bit to first bit memory areas may be similar to those stored in the seventh bit to first bit memory areas of the sleep mode control register of the comparative example.

65-2 6 0 6 1 4 64-1 64-4 1 6 The zeroth bit memory area of the sleep mode control registerstores a value related to enter and exit of the sleep mode of the power supply control circuit. When the stored value is, the power control circuitexits from the sleep mode and causes all the DC/DC channels CHto CH(that is, DC/DC convertersto) to transition to the forced PWM mode. When the stored value is, the power control circuitenters into the sleep mode.

65-2 64-1 64-4 6 3 15 64-3 15 3 3 15 By using the sleep mode control register, the DC/DC converterstotransition to the forced PWM mode when the power control circuitexits from the sleep mode in response to the memory systemthat has exit from the low power consumption mode to the normal operation mode. This enables, for example, the PCIe PHYto perform the initialization while the third DC/DC converteris operating in the forced PWM mode. In other words, the PCIe PHYcan perform the initialization while variations in voltage are small. Thus, a failure of the initialization in the memory systemcan be prevented. Note that in the memory system, a circuit block (load) that is a target to prevent a failure of initialization is not limited to the PCIe PHY, but may be another circuit block that is sensitive to variations in voltage.

3 An example of an operation performed in a case where the memory systemexits from the low power consumption mode will be described specifically.

7 FIG. 7 FIG. 3 61 64-3 15 64-1 64-2 64-4 64-3 64-3 3 is a sequence diagram illustrating an operation example in the case where the memory systemexits from the low power consumption mode to the normal operation mode.illustrates an operation of the control logic, the third DC/DC converter, and the PCIe PHY. Note that the other DC/DC converters,andmay operate in a similar manner to the third DC/DC converter. It is assumed that the third DC/DC converteris set in the PFM mode while the memory systemis set in the low power consumption mode.

61 65-2 64 64-3 3 11 65-2 6 0 First, the control logicsends the value stored in the sleep mode control registerto all the DC/DC converters, which includes the third DC/DC converter, in response to the memory systemthat has exit from the low power consumption mode to the normal operation mode (A). In the zeroth bit of the sleep mode control register, the value indicating that the power control circuitexits from the sleep mode and every DC/DC channel is set in the forced PWM mode (i.e.,) is set.

64-3 65-2 12) 64-3 3 64-3 65-2 64-3 3 15 13 The third DC/DC convertertransitions from the PFM mode to the forced PWM mode on the basis of the value stored in the sleep mode control register(A. Note that the third DC/DC convertermay be set in the off mode while the memory systemis set in the low power consumption mode. In that case, the third DC/DC convertertransitions from the off mode to the forced PWM mode on the basis of the value stored in the sleep mode control register. Therefore, the third DC/DC convertersupplies the internal power supply voltage DC/DC_OUT to the PCIe PHYin the forced PWM mode (A).

3 64-3 15 14 15 15 2 3 While the power supply voltage DC/DC_OUT is supplied from the third DC/DC converterin the forced PWM mode, the PCIe PHYperforms initialization (A). The initialization of the PCIe PHYincludes, for example, calibration and a link training process. The calibration is an operation of passing a current through resistors in the PCIe PHYto adjust variations among chips (ICs). The link training process is a process of making a link available, such as synchronization of clock signals between the hostand the memory system.

61 64 15 61 64 64-3 16 In addition, the control logicdetects that the load current of any of the one or more circuit blocks that corresponds to the one or more DC/DC converters, respectively, has exceeded a boundary (A). Then, the control logicinstructs all the DC/DC converters, which includes the third DC/DC converter, to transition to the auto mode (A).

61 15 64-3 61 64-3 Note that the control logicmay detect that the load current of the PCIe PHYcorresponding to the third DC/DC converterhas exceeded the boundary. In this case, the control logicinstructs, for example, the third DC/DC converterto transition to the auto mode.

64-3 61 17 64-3 3 15 18 Then, the third DC/DC convertertransitions from the forced PWM mode to the auto mode in response to the instruction from the control logic(A). The third DC/DC convertersupplies the internal power supply voltage DC/DC_OUT to the PCIe PHYin the auto mode (A).

64-3 64-3 3 15 In the auto mode, the operation mode of the third DC/DC converteris automatically switched between the PFM mode and the PWM mode in accordance with the load current. Therefore, the third DC/DC convertercan supply the internal power supply voltage DC/DC_OUT to the PCIe PHYin either the PFM mode or the PWM mode which is selected in accordance with the load current.

15 64-3 15 3 As described above, the PCIe PHYperforms the initialization while the internal power supply voltage DC/DC3_OUT is supplied from the third DC/DC converterin the forced PWM mode. That is, the PCIe PHYperforms the initialization while variations in voltage are small. This can prevent a failure of the initialization in the memory system.

64 64 The DC/DC converteralso transitions from the forced PWM mode to the auto mode in response to the load current that has exceeded the boundary. This also prevents the DC/DC converterfrom being fixed in a high power consumption state (i.e. from being maintained in the forced PWM mode).

65 61 65-3 65-3 64 6 65-3 6 Note that the registersprovided in the control logicmay further include a channel designation register. The channel designation registerdesignates a DC/DC channel (i.e., a DC/DC converter) to be transitioned to the forced PWM mode in response to the power control circuitthat has exit from the sleep mode. Specifically, the channel designation registerincludes a plurality of memory areas, for example. Each of the memory areas stores information indicative of a DC/DC channel to be transitioned to the forced PWM mode in response to the power control circuitthat has exit from the sleep mode.

11 61 65-2 65-3 64 3 65-2 6 0 65-3 In this case, in A, the control logicmay send the value stored in the sleep mode control registerand the information stored in the channel designation registerto the DC/DC convertersin response to the memory systemthat has exit from the low power consumption mode to the normal operation mode. The zeroth bit of the sleep mode control registerstores, for example, a value indicating that the power control circuitexits from the sleep mode and causes the designated DC/DC channel to transition to the forced PWM mode (i.e.,). In addition, the channel designation registerstores information that designates a DC/DC channel to be transitioned to the forced PWM mode.

12 64 65-3 64 65-1 64 17 In this case, in A, the DC/DC convertercorresponding to the designated DC/DC channel, which is based on the value stored in the channel designation register, transitions from the PFM mode (or off mode) to the forced PWM mode. Note that the DC/DC convertercorresponding to an undesignated DC/DC channel transitions from the PFM mode (or off mode) to the auto mode, based on the value stored in the DC/DC mode setting register, for example. In addition, the DC/DC converterthat has transitioned to the forced PWM mode transitions to the auto mode in Ain response to the load current that has exceeded the boundary.

65-3 64 3 64 In a case where the channel designation registeris further used as described above, only a specific DC/DC convertercan be caused to transition to the forced PWM mode when the memory systemhas exit from the low power consumption mode to the normal operation mode. In addition, the specific DC/DC converterthat has transitioned to the forced PWM mode can be caused to transition to the auto mode in response to the load current that has exceeded the boundary.

8 FIG. 9 3 9 91 5 92 64 93 3 15 94 15 95 15 9 is a time chartillustrating an example of transitions of operations, voltages, and a current in the case where the memory systemexits from the low power consumption mode to the normal operation mode. Specifically, the time chartrepresents the transitions of an internal power supply voltage(i.e., DC/DC1_OUT) supplied to the NAND flash memory, an operation modeof each DC/DC converter, an internal power supply voltage(i.e., DC/DC_OUT) supplied to the PCIe PHY, an operationof the PCIe PHY, and a load currentof the PCIe PHYas time passes. The horizontal axis of the time chartindicates time.

95 64 95 95 64 95 95 64 95 64 A boundaryA is a value of a current for determination to switch between the PFM mode and the PWM mode while each DC/DC converteris in the auto mode. More specifically, when the load currenthas exceeded the boundaryA, each DC/DC converterin the auto mode is switched from the PFM mode to the PWM mode. When the load currenthas become not larger than the boundaryA, each DC/DC converterin the auto mode is switched from the PWM mode to the PFM mode. The boundaryA is also used for determination to switch each DC/DC converterfrom the forced PWM mode to the auto mode.

21 3 21 3 6 92 64 6 81 5 64 94 95 Time tis time at which the memory systemis requested to exit from the low power consumption mode to the normal operation mode. At time t, the memory systemis in the low power consumption mode and the power control circuitis in the sleep mode. Thus, the operation modeof each DC/DC converterin the power control circuitis the off mode or the PFM mode with low power consumption. The internal power supply voltagesupplied to the NAND flash memoryis off, and the DC/DC converterin an on state with low voltage is set in the PFM mode. The operationof the PCIe PHY is disabled. The load currentis low.

21 22 3 91 5 The period from time tto time tis a period in which the memory systemtransitions from the low power consumption mode to the normal operation mode. Within this period, the internal power supply voltagesupplied to the NAND flash memorygradually rises and heightens.

22 3 2 92 64 Time tis time at which the memory systemhas exit from the low power consumption mode to the normal operation mode. At time t2, the operation modeof each DC/DC convertertransitions to the forced PWM mode.

22 23 94 95 15 95 93 15 64 In a period from time tto time t, the operationof the PCIe PHY transitions from being disabled to activation. The load currentof the PCIe PHYis smaller than the boundaryA during the activation, but the variations in the internal power supply voltagesupplied to the PCIe PHYare small because the DC/DC converteris in the forced PWM mode.

23 94 Time tis time at which the operationof the PCIe PHY transitions from the activation to initialization (for example, calibration).

23 24 15 95 15 95 93 15 64 93 15 15 In a period from time tto time t, the PCIe PHYstarts to perform the initialization. The load currentof the PCIe PHYis smaller than the boundaryA during the initialization, but the variations in the internal power supply voltagesupplied to the PCIe PHYare small while the DC/DC converteris in the forced PWM mode. The small variations in the internal power supply voltageprevent a failure of the initialization in the PCIe PHY. For example, in the PCIe PHY, the risk that incorrect calibration is performed is reduced.

94 92 64 94 95 15 Time t24 is time at which the operationof the PCIe PHY transitions from the end of the initialization to the normal operation. At this time, the operation modeof each DC/DC converteris maintained in the forced PWM mode. After the operationof the PCIe PHY transitions to the normal operation, the load currentof the PCIe PHYmay increase.

92 64 61 95 15 95 61 95 6 14 51 92 64 6 92 64 Then, at time t25, the operation modeof each DC/DC convertertransitions from the forced PWM mode to the auto mode on the basis of, for example, an instruction from the control logicin response to the load currentof the PCIe PHYthat has exceeded the boundaryA. The timing of transition to the auto mode is instructed by the control logic, based on the load current. It is therefore unnecessary for a configuration outside the power control circuit, such as the CPUexecuting the FW, to control the operation modeof each DC/DC converter. Note that the configuration outside the power supply control circuitmay perform control so that the operation modeof each DC/DC convertertransitions from the forced PWM mode to the auto mode at a certain timing.

92 64 95 15 95 92 64 64 92 64 64 The foregoing example describes that the operation modeof each DC/DC convertertransitions to the auto mode in response to the load currentof the PCIe PHYthat has exceeded the boundaryA. However, the operation modeof each DC/DC convertermay transition to the auto mode in response to the load current corresponding to any one of the DC/DC convertersthat has exceeded the boundary. Alternatively, the operation modeof each DC/DC convertermay transition to the auto mode when the load current corresponding to any one of the DC/DC convertersthat are set in the forced PWM mode has exceeded the boundary.

92 64 64 After that, the operation modeof each DC/DC converteris set to either the PFM mode or the PWM mode according to automatic switching in the auto mode. This can prevent the DC/DC convertersfrom being fixed in a high power consumption state (i.e., from being kept in the PWM mode).

64 3 As described above, the present embodiment can prevent a failure of initialization due to variations in supply voltage. The DC/DC convertertransitions to the forced PWM mode in response to the memory systemthat has transitioned from the low power consumption mode to the normal operation mode.

64-3 3 15 15 64-3 15 64-3 For example, the third DC/DC convertersupplies the internal power supply voltage DC/DC_OUT to the PCIe PHY. The PCIe PHYperforms initialization while the third DC/DC converteris in the forced PWM mode. In the forced PWM mode, the variations in voltage are small. Thus, the possibility of failure of the initialization in the PCIe PHYcan be decreased more than that in a case where the initialization is performed while the third DC/DC converteris in the PFM mode (that is, in a mode in which variations in voltage are large).

Each of the various functions described in the embodiment may be realized by a circuit (e.g., processing circuit). An exemplary processing circuit may be a programmed processor such as a central processing unit (CPU). The processor executes computer programs (instructions) stored in a memory thereby performs the described functions. The processor may be a microprocessor including an electric circuit. An exemplary processing circuit may be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a microcontroller, a controller, or other electric circuit components. The components other than the CPU described according to the embodiment may be realized in a processing circuit.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel devices and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modification as would fall within the scope and spirit of the inventions.