Receiver Circuit of Interface Circuit and Operating Method Thereof

This application claims priority to Korean Patent Application No. 10-2024-0123374, filed on Sep. 10, 2024 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein its entirety.

The present disclosure relates to a receiver circuit of an interface circuit, and an operating method of the receiver circuit.

In order to sample and process an input signal without distortion, a sample and hold circuit (S/H circuit) is used at an input terminal of an analog-digital converter. The S/H circuit samples the input analog voltage, holds a sampled value for a certain period of time, and transmits it to an analog-to-digital converter.

The S/H circuit may include a buffer circuit to drive the input capacity of the analog-to-digital converter. As data processing speed increases, a sampled value may be distorted by a parasitic capacitor in the buffer circuit.

Some embodiments may provide a receiver circuit for sampling an input voltage without distortion, and an operating method thereof.

According to an aspect of an embodiment, a receiver circuit includes: a first sampling circuit comprising a first capacitor connected to a first node, the receiver circuit being configured to receive a first input voltage, and store a first charge corresponding to the first input voltage in the first capacitor during a first period; and a buffer circuit comprising a first transistor including a gate terminal connected to the first node, a source terminal connected to a first output node which is configured to output a first output voltage corresponding to the first input voltage, and a drain terminal connected to a second node that is AC grounded during the first period.

According to an aspect of an embodiment, a receiver circuit includes: a first capacitor that is connected to a first node and configured to store a first charge corresponding to a first input voltage during a first period; a first transistor including a first gate terminal connected to the first node, a drain terminal connected to a second node, and a source terminal connected to a first output node configured to output a first output voltage corresponding to the first input voltage; and a first reset switch including a first end connected to the second node and a second end that is AC grounded, the first reset switch being turned on during the first period.

According to an aspect of an embodiment, an operating method of a receiver circuit, includes: receiving a first input voltage and performing a sampling operation for sampling a first charge corresponding to the first input voltage to a first capacitor connected to a first node; and performing a holding operation for generating a first output voltage corresponding to the first input voltage through a first output node by a first transistor including a gate terminal connected to the first node, a drain terminal connected to a second node, and a source terminal connected to the first output node, wherein the performing the sampling operation includes turning on of a first reset switch including a first end connected to the second node and a second end that is AC grounded.

In the following detailed description, certain example embodiments are shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, without departing from the spirit or scope of the present disclosure.

Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification. In the flowchart described with reference to the drawing, the order of operations may be changed, several operations may be merged, some operations may be split, and certain operations may not be performed.

In the present specification, expressions described in the singular may be construed in the singular or plural unless an explicit expression such as “one” or “single” is used. In the present specification, the terms including ordinal numbers such as first, second, etc. may be used to describe various elements, but the elements are not limited by the terms. The terms are used only for the purpose of distinguishing one element from another element.

1 FIG. shows an interface circuit according to one or more embodiments.

1 FIG. 10 11 20 10 20 11 11 Referring to, an interface circuitmay include a channeland a receiver circuit. In some embodiments, the interface circuitmay be an interface used for input/output of a memory device. The receiver circuitmay be connected with a transmitter circuit through the channel. In some embodiments, the channelmay be a through-silicon via (TSV).

10 10 In some embodiments, the interface circuitmay be a circuit for transmitting data to a memory device, for example, a non-volatile memory device. For example, the interface circuitmay be a circuit for various interfaces such as a universal serial bus (USB), a multimedia card (MMC), a PCIExpress (PCI-E), AT attachment (ATA), a serial AT attachment (SATA), parallel AT attachment (PATA), a small computer system interface (SCSI), a serial attached SCSI (SAS), an enhanced small disk interface (ESDI), integrated drive electronics (IDE), non-volatile memory express (NVMe), and the like.

20 11 20 100 110 The receiver circuitmay receive a transmission signal TX via the channel, sequentially determine a bit value of the transmission signal TX, and output a bit value D[0: n] of an input signal. The transmission signal TX may be an analog voltage signal. In some embodiments, the receiver circuitmay include a sample and hold (S/H) circuitand an analog digital converter.

100 100 110 100 The S/H circuitmay generate a plurality of output voltages Vout based on the transmission signal TX. The S/H circuitmay alternately perform a sampling operation and a holding operation on the transmission signal TX (i.e., input voltage). The sampling operation may be an operation that samples the input voltage. The holding operation may be an operation of holding a sampled input voltage, generating an output voltage corresponding to the input voltage, and transmitting the output voltage to an analog-to-digital converterin synchronization with a clock signal. In some embodiments, the S/H circuitmay include a sampling circuit and a flipped voltage follower (FVF) buffer. For example, the FVF buffer may include a feedback loop that includes a feedback capacitor and may have low output impedance. In addition, the FVF buffer may operate with increased bandwidth compared to a source follower.

100 100 100 100 100 5 FIG. 8 FIG. 12 FIG. 14 FIG. 9 FIG. 11 FIG. In some embodiments, the S/H circuitmay operate as a single input buffer or a differential input buffer. For example, when the S/H circuitis a differential input buffer, the S/H circuitmay include a first sampling circuit that receives a non-inverted input signal corresponding to the transmission signal TX and a second sampling circuit that receives an inverted input signal. Hereinafter, the sample hold bufferoperating as a single input buffer will be described with reference totoandto, and the S/H circuitoperating as a differential input buffer will be described with reference toto.

The sampling circuit may include at least one sample switch. The sampling circuit may perform a sampling operation based on a sample switch control signal for controlling at least one sample switch.

In some embodiments, the FVF buffer may include at least one reset switch. At least one reset switch may be a switch to remove distortion of sampling values caused by a parasitic capacitor during the sampling operation. For example, at least one reset switch may be connected to AC ground. In some embodiments, the FVF buffer may respond to a plurality of reset switch control signals during the sampling operation to control at least one reset switch such that each of the reset switches is connected to the AC ground. As used in the present specification, the term “AC ground” refers to a node voltage condition in which a DC component is allowed to pass, while an AC component is connected to ground and thereby removed. That is, in such a configuration, high-frequency components or varying AC signals at a given node in the circuit are filtered out, and only a stable DC voltage is maintained.

110 100 110 110 110 1 110 110 1 110 110 1 110 110 1 110 110 1 110 m m m m m The analog digital convertermay generate the bit value D[0: n] of the input signal based on each of the plurality of output voltages Vout received from the S/H circuit. In some embodiments, the analog digital convertermay be a time-interleaved analog digital converter. The analog-digital convertermay include a plurality of analog-digital converters_to_(where m is an integer greater than or equal to 2) that receive inputs in common (or time-divisionally). Each of the plurality of analog-digital converters_to_may sample the input at different points in time. The plurality of analog-digital converters_to_each may output a digital signal corresponding to the magnitude of the output voltage VOUT. Each of the plurality of analog-digital converters_to_may be synchronized to a clock signal, and the plurality of clock signals supplied to the plurality of analog-digital converters_to_may have different phases.

2 FIG. 3 FIG. 4 FIG. 3 FIG. andare circuit diagrams of the S/H circuit according to one or more embodiments.is a timing diagram of an operation of the S/H circuit ofaccording to one or more embodiments.

2 FIG. 3 FIG. 1000 1000 is a circuit diagram of a case that the S/H circuitperforms the sampling operation, andis a circuit diagram of a case that the S/H circuitperforming the holding operation.

2 FIG. 3 FIG. 1000 1001 1003 As shown inand, the S/H circuitmay include a sampling circuitand a FVF buffer circuit.

1001 1 The sampling circuitmay include a first switch SWand a sampling capacitor Cs.

1001 1 3 1 1 1 3 The sampling circuitmay receive an input voltage Vin through an input terminal. One end of the first switch SWmay be connected to the input terminal and the other end may be connected to a third node N. The first switch SWmay be controlled by a first sample switch control signal S. When the first switch SWis turned on, the input voltage Vin input through the input terminal may be transmitted to the third node N.

3 3 1 3 The sampling capacitor Cs may be connected between the third node Nand a ground voltage. The sampling capacitor Cs may store a charge based on a voltage of the third node N. When the first switch SWis turned on, the charge stored in the sampling capacitor Cs may increase as the input voltage Vin is transmitted to the third node N.

1003 1 2 The FVF buffer circuitmay include a plurality of transistors Tand T, a feedback capacitor Cc, and a resistor Rb.

1 1 1 3 1003 A plurality of capacitors Cgs and Cgd may be parasitic capacitors between a gate terminal and a source terminal of the transistor Tand between the gate terminal and a drain terminal of the transistor T. Due to the parasitic capacitor, a voltage at the first node Nand a voltage at the third node Nmay affect the charge stored in the sampling capacitor Cs. Accordingly, the FVF buffer circuitmay output a voltage of a different magnitude than the input voltage.

1 3 1 1 1 2 1003 3 1 1 3 2 The gate terminal of the first transistor Tmay be connected to the third node N. The source terminal of the first transistor Tmay be connected to the first node N. A drain terminal of the first transistor Tmay be connected to a second node N. When the FVF buffer circuitoperates at high frequency, a gate-source capacitor Cgs between the third node N, which is the gate terminal of the first transistor T, and the first node N, and a gate-drain capacitor Cgd between the third node Nand the second node Nmay affect the output voltage.

2 2 2 1 2 1 A gate terminal of the second transistor Tmay be connected to one end of the feedback capacitor Cc. A source terminal of the second transistor Tmay be connected to a power source voltage VDD. A drain terminal of the second transistor Tmay be connected to the first node N. The second transistor Tmay perform a function that compensates for the operation of the first transistor T.

1 2 1 2 In some embodiments, the first transistor Tand the second transistor Tmay include P-type transistors. However, the present disclosure is not limited thereto, and the first transistor Tand the second transistor Tmay be formed of N-type transistors.

2 2 The feedback capacitor Cc may be connected between the gate terminal of the second transistor Tand the second node N. In some embodiments, the feedback capacitor Cc may have a capacitance value that is larger than capacitance values of the parasitic capacitors Cgs and Cgd.

2 1003 One end of the resistor Rb may be connected to the second node N, and the other end may be connected to a ground power. The resistor Rb may control the intensity of the current flowing to the FVF buffer circuit.

1003 1 The FVF buffer circuitmay output the output voltage Vout through an output terminal. The output terminal may be connected to the first node N.

4 FIG. 1000 1 401 407 3 407 409 1 401 407 3 407 409 Referring to, the S/H circuitmay perform the sampling operation and the holding operation alternately. The S/H circuit may perform the sampling operation during a first period P(tto t) and the holding operation during a second period P(tto t). The S/H circuit may perform the sampling operation during the first period P(tto t) and the holding operation during the second period P(tto t).

401 1 1 1 At t, the first switch SWmay be turned on by the first sample switch control signal Sof high level H. During the first period P, charges may be stored in the sampling capacitor Cs based on the input voltage Vin.

403 1 1 1 in in in in At t, the input voltage Vin may transition from a first level (V(n-)) to a second level (V(n)). Here, a difference between the first level (V(n-)) and the second level (V(n)) may be ΔV.

in in in 1 3 1 As the input voltage Vtransitions from the first level (V(n-)) to the second level (V(n)), a voltage at the third node Nmay be lowered by ΔV.

1000 1 1 2 1 3 in in While the S/H circuitoperates at low frequency, the voltage of the first node N, which is connected to the source terminal of the first transistor T, and the second node N, which is connected to the drain terminal of the first transistor T, may be determined based on the input voltage Vtransmitted to the third node N. Accordingly, the output voltage Vout may be generated based on the input voltage V.

1000 1 2 3 1 3 However, when the S/H circuitoperates at high frequency, a delay may occur until the voltages of the first node Nand second node Nchange due to the voltage of the third node N. Accordingly, the first node voltageV(N) may transition at a later time than the time at which the voltage of the third node Ntransitions.

405 407 3 1 1 2 1 2 2 2 2 2 1 At tto t, as the voltage of the third node Nis applied to the gate terminal of the first transistor T, the current flowing through the first transistor Tmay increase. The voltage of the second node Nmay increase due to the current flowing through the first transistor T. A voltage applied to the gate terminal of the second transistor Tmay increase due to the increased voltage of the second node N. Since the second transistor Tis a P type transistor, the current flowing to the second transistor Tmay decrease as the voltage applied to the gate terminal increases. Accordingly, the voltages of the second node Nand the first node Nmay decrease.

1 3 1 3 3 1 3 2 For example, the first node voltageV(N) may be lowered by AV. Changes in the first node voltageV(N) may affect the third node voltageV(N) through parasitic capacitors Cgs and Cgd. Specifically, to preserve the charge of the capacitor, a voltage difference between the two terminals of the gate-source capacitor Cgs and the gate-drain capacitor Cgd may need to be maintained. Accordingly, the third node voltageV(N) may be affected by changes in the magnitude of the first node voltageV(N), which is one end of the gate-source capacitor Cgs. Similarly, the third node voltageV(N) may be affected by changes in the magnitude of the second node voltageV(N), which is one end of the gate-drain capacitor Cgd.

3 1 2 That is, the third node voltageV(N) may be affected by the first node voltageV(N) and the second node voltageV(N) through a gate-source capacitor Cgs and the gate-drain capacitor Cgd.

407 61 1 3 3 1 405 409 2 2 403 405 in in After t, the first node voltageV(N) may output a voltage, which is a value obtained by subtracting the sum of the change ΔVin the magnitude of the input voltage Vand AV, as the output voltage Vout. In this case, the third node voltageV(N) may have a voltage that changes to a different extent than the input voltage Vdue to the influence of the change in the first node voltageV(N). In addition, at tto t, the second node voltageV(N) may have a value smaller than a peak value of the second node voltageV(N) at tto t.

3 1000 in After the second section P, the S/H circuitmay transmit the output voltage Vout to an analog-to-digital converter (ADC) circuit. The ADC circuit may determine a bit value corresponding to the input voltage Vbased on the output voltage Vout.

1 1000 in The first node voltageV(N) may have a different voltage from the input voltage Vdue to the influence of parasitic capacitors Cgs and Cgd. Accordingly, the ADC circuit connected to the rear end of the S/H circuitmay determine a bit value corresponding to a voltage different from the input voltage as data.

5 FIG. is a circuit diagram of the S/H circuit according to one or more embodiments.

5 FIG. 300 301 303 As shown in, the S/H circuitmay include a sampling circuitand an FVF buffer circuit.

301 31 3 The sampling circuitmay include a first switch SWand a sampling capacitor Cs.

301 31 33 31 31 31 33 The sampling circuitmay receive the input voltage Vin through an input terminal. One end of the first switch SWmay be connected to the input terminal and the other end may be connected to the third node N. The first switch SWmay be controlled by the first sample switch control signal S. When the first switch SWis turned on, the input voltage Vin input through the input terminal may be transmitted to the third node N.

3 33 1 1 3 33 31 3 33 The sampling capacitor Csmay be connected between the third node Nand the ground voltage GND. The first ground GNDmay be a ground power. The sampling capacitor Csmay store charges based on the voltage of the third node N. When the first switch SWis turned on, the charge stored in the sampling capacitor Csmay increase as the input voltage Vin is transmitted to the third node N.

303 31 32 3 3 32 33 The FVF buffer circuitmay include a plurality of transistors Tand T, a feedback capacitor Cc, a resistor Rb, a first reset switch SW, and a second reset switch SW.

3 3 31 A plurality of capacitors Cgsand Cgdmay be parasitic capacitors between a gate terminal and a source terminal, and between the gate terminal and a drain terminal of a first transistor T.

31 33 31 31 31 32 303 3 33 31 31 3 33 32 5 FIG. The gate terminal of the first transistor Tmay be connected to the third node N. The source terminal of the first transistor Tmay be connected to the first node N. The drain terminal of the first transistor Tmay be connected to the second node N. When the FVF buffer circuitoperates at high frequency, a gate-source capacitor Cgsbetween the third node N, which is the gate terminal of the first transistor T, and the first node N, and a gate-drain capacitor Cgdbetween the third node Nand the second node Nare shown in.

32 3 32 32 31 32 31 A gate terminal of a second transistor Tmay be connected to one end of the feedback capacitor Cc. A source terminal of the second transistor Tmay be connected to the power source voltage VDD. A drain terminal of the second transistor Tmay be connected to the first node N. The second transistor Tmay perform a function that compensates for the operation of the first transistor T.

31 32 31 32 In some embodiments, the first transistor Tand the second transistor Tmay include P-type transistors. However, the present disclosure is not limited to this, and the first transistor Tand the second transistor Tmay be N-type transistors.

3 32 32 The feedback capacitor Ccmay be connected between a gate terminal of the second transistor Tand the second node N.

32 1 3 303 One end of the resistor Rb may be connected to the second node Nand the other end may be connected to the first ground GND. The resistor Rbmay control the intensity of the current flowing to the FVF buffer circuit.

32 32 2 2 32 32 32 32 2 32 405 405 31 32 405 303 6 FIG. 6 FIG. One end of the first reset switch SWmay be connected to the second node N, and the other end may be connected to the second ground GND. The second ground GNDmay be an AC ground. The first reset switch SWmay be controlled by the first reset switch control signal S. When the first reset switch SWis turned on, the second node Nmay be AC biased through the second ground GND. Accordingly, in the second node N, an AC component is removed and only a DC component voltage may exist. For example, as will be described later,illustrates an example of an AC ground implemented using a replica circuit. In, the replica circuitis configured with the same FVF structure as the main buffer and includes a low-pass filter. Through this configuration, the first node Nand the second node Ncan be maintained at a constant DC voltage. That is, the replica circuitcan replicate the operating environment of the FVF buffersuch that it is not affected by AC components.

33 31 3 3 33 33 33 31 3 31 One end of the second reset switch SWmay be connected to the first node N, and the other end may be connected to the third ground GND. The third ground GNDmay be an AC ground. The second reset switch SWmay be controlled by the second reset switch control signal S. When the second reset switch SWis turned on, the first node Nmay be AC biased through the third ground GND. Accordingly, at the first node N, the AC component is removed and only the DC component voltage exist.

32 33 6 FIG. 8 FIG. Specific examples of the AC grounds that can be connected to the first reset switch SWand the second reset switch SWwill be described with reference toto.

303 31 The FVF buffer circuitmay output the output voltage Vout through the output terminal. The output terminal may be connected to the first node N.

300 300 2 3 32 33 300 31 32 33 31 32 3 3 31 3 31 The S/H circuitperforms the sampling operation and the holding operation alternately. The S/H circuitmay be connected to the AC ground GNDand GNDby turning on the first reset switch SWand the second reset switch SWwhile performing the sampling operation. The S/H circuitmay have no changes in the first node Nand the second node Nwhile performing the sampling operation. Accordingly, the third node Nmay not be affected by the changes in first node Nand the second node N. That is, the charge stored in the sampling capacitor Csthrough the parasitic capacitor Cgsbetween the gate terminal and source terminal of the first transistor Tand the parasitic capacitor Cgdbetween the gate terminal and drain terminal of the first transistor Tmay not be distorted.

6 FIG. 7 FIG. 8 FIG. 6 FIG. 7 FIG. andare circuit diagrams of an S/H circuit according to one or more embodiments.is a timing diagram of the operation of the S/H circuit ofand.

6 FIG. 7 FIG. 400 400 is a circuit diagram of a case that an S/H circuitperforms the sampling operation, andis a circuit diagram of a case that the S/H circuitperforms the holding operation.

6 FIG. 7 FIG. 5 FIG. 300 In some embodiments,andare circuit diagrams of a case where a replica circuit is used as an example for implementing the AC ground in the S/H circuitin.

6 FIG. 7 FIG. 400 401 403 405 As shown inand, the S/H circuitmay include a sampling circuit, a FVF buffer circuit, and a replica circuit.

401 41 4 The sampling circuitmay include a first switch SWand a sampling capacitor Cs.

401 41 43 41 41 41 43 The sampling circuitmay receive the input voltage Vin through an input terminal. One end of the first switch SWmay be connected to an input terminal, and the other end may be connected to a third node N. The first switch SWmay be controlled by a first sample switch control signal S. When the first switch SWis turned on, the input voltage Vin input through the input terminal may be transmitted to the third node N.

4 43 4 43 41 4 43 The sampling capacitor Csmay be connected between the third node Nand a ground voltage. The sampling capacitor Csmay store charge based on a voltage of the third node N. When the first switch SWis turned on, the charge stored in the sampling capacitor Csmay increase as the input voltage Vin is transmitted to the third node N.

403 411 412 41 41 42 43 The FVF buffer circuitmay include a plurality of transistors Tand T, a feedback capacitor Cc, a resistor Rb, a first reset switch SW, and a second reset switch SW.

41 41 411 A plurality of capacitors Cgsand Cgdmay be parasitic capacitors between a gate terminal and a source terminal, and between the gate terminal and a drain terminal of a first transistor T, respectively.

411 43 411 41 411 42 The gate terminal of the first transistor Tmay be connected to the third node N. The source terminal of the first transistor Tmay be connected to a first node N. A drain terminal of the first transistor Tmay be connected to a second node N

41 43 411 41 41 43 42 403 6 FIG. A gate-source capacitor Cgsbetween the third node N, which is the gate terminal of the first transistor T, and the first node N, and a gate-drain capacitor Cgdbetween the third node Nand the second node Nare shown in, these are important when the FVF buffer circuitoperates at high frequency.

412 41 412 412 41 412 411 A gate terminal of a second transistor Tmay be connected to one end of the feedback capacitor Cc. A source terminal of the second transistor Tmay be connected to the power source voltage VDD. A drain terminal of the second transistor Tmay be connected to the first node N. The second transistor Tmay perform a function that compensates for the operation of the first transistor T.

411 412 411 412 In some embodiments, the first transistor Tand the second transistor Tmay include P-type transistors. However, the present disclosure is not limited thereto, and the first transistor Tand the second transistor Tmay include N-type transistors.

41 412 42 The feedback capacitor Ccmay be connected between a gate terminal of the second transistor Tand the second node N.

41 42 41 403 One end of the resistor Rbmay be connected to the second node N, and the other end may be connected to the ground power. The resistor Rbmay control the intensity of the current flowing to the FVF buffer circuit.

403 44 41 43 The FVF buffer circuitmay output the output voltage Vout through an output terminal. The output terminal may be connected to a fourth node N, which is connected via the first node Nand the second reset switch SW.

42 42 45 405 42 42 42 42 45 One end of the first reset switch SWmay be connected to the second node N, and the other end may be connected to a fifth node Nof the replica circuit. The first reset switch SWmay be controlled by the first reset switch control signal S. When the first reset switch SWis turned on, the second node Nand the fifth node Nmay be connected.

43 41 44 43 43 43 31 41 One end of the second reset switch SWmay be connected to the first node N, and the other end may be connected to the fourth node N. The second reset switch SWmay be controlled by the second reset switch control signal S. When the second reset switch SWis turned on, the first node Nmay be AC biased. Accordingly, at the first node N, the AC component is removed and only the DC component voltage may exist.

405 403 405 403 The replica circuitmay be a circuit for providing the AC ground of the FVF buffer circuit. The replica circuitmay be implemented with components identical to at least some of the components of the FVF buffer circuit.

405 3051 421 422 42 42 In some embodiments, the replica circuitmay include a low pass filter, a plurality of transistors Tand T, a feedback capacitor Cc, and a resistor Rb.

3051 3051 3051 3051 The low pass filtermay only pass a low frequency signal. That is, the low pass filtermay filter out a high frequency component. For example, the low pass filtermay block bands with frequencies greater than a predetermined cutoff frequency. Here, the cutoff frequency may be set based on the size of the resistor and the capacitance of the capacitor that make up the low pass filter.

41 41 421 A plurality of capacitors Cgsand Cgdeach may be a parasitic capacitor between a gate terminal and a source terminal, and between the gate terminal and a drain terminal of a third transistor T, respectively.

421 46 421 44 421 45 The gate terminal of the third transistor Tmay be connected to a sixth node N. The source terminal of the third transistor Tmay be connected to the fourth node N. The drain terminal of the third transistor Tmay be connected to the fifth node N.

422 42 422 422 44 A gate terminal of a fourth transistor Tmay be connected to one end of the feedback capacitor Cc. A source terminal of the fourth transistor Tmay be connected to the power source voltage VDD. A drain terminal of fourth transistor Tmay be connected to the fourth node N.

421 422 421 422 In some embodiments, the third transistor Tand the fourth transistor Tmay include P-type transistors. However, the present disclosure is not limited to this, and the third transistor Tand the fourth transistor Tmay be N-type transistors.

42 422 45 The feedback capacitor Ccmay be connected between the gate terminal of the fourth transistor Tand the fifth node N.

42 45 42 405 One end of the resistor Rbmay be connected to the fifth node N, and the other end may be connected to the ground power. The resistor Rbmay control the intensity of the current flowing to the replica circuit.

421 422 42 42 411 412 41 41 42 41 42 41 The plurality of transistors Tand T, the feedback capacitor Cc, and the resistor Rbmay each have the same characteristics as the plurality of transistors Tand T, the feedback capacitor Cc, and the resistor Rb, respectively. For example, a capacitance value of the feedback capacitor Ccmay be the same as the capacitance value of the feedback capacitor Cc, and a value of the resistor Rgmay be the same as the value of the resistor Rb.

405 403 405 403 In some embodiments, the replica circuitmay be placed in the same region as the buffer circuit. For example, an active region of the replica circuitand an active region of the buffer circuitmay be identical.

8 FIG. 400 400 41 801 805 43 805 809 Referring to, the S/H circuitmay alternately perform the sampling operation and the holding operation. The S/H circuitmay perform the sampling operation during a first period P(tto t) and the holding operation during a second period P(tto t).

6 FIG. 8 FIG. 41 41 41 42 42 43 43 Referring toandtogether, in the first period P, the first switch SWmay be turned on by the first sample switch control signal Sof a high level H. The first reset switch SWmay be turned on by the first reset switch control signal Sof the high level H. The second reset switch SWmay be turned on by the second reset switch control signal Sof the high level H.

41 4 During the first period P, charges may be stored in the sampling capacitor Csbased on the input voltage Vin.

803 1 1 1 in in in in in At t, the input voltage Vmay transition from a first level (V(n-)) to a second level (V(n)). Here, a difference between the first level (V(n-)) and the second level (V(n)) may be ΔV.

in in in 1 43 1 42 43 41 44 42 45 14 44 42 45 1003 503 405 603 1 31 41 44 42 45 2 303 FIG., 5 FIG. 9 FIG. 6 FIG. 12 FIG. As the input voltage Vtransitions from the first level (V(n-)) to the second level (V(n)), the third node voltage Vmay be lowered by ΔV. Since the first reset switch SWand the second reset switch SWare turned on, a voltage of the first node Nand a voltage of the fourth node Nmay be the same, and a voltage of the second node Nand a voltage of the fifth node Nmay be the same. That is, a common mode voltage (Vcm, N) and a common mode voltage (Vcm, N) are the same, and a common mode voltage (Vcm, N) and a common mode voltage (Vcm, N) may be the same. The common mode voltage Vom may be a reference potential of each node in a steady-state condition of a circuit employing a Flipped Voltage Follower (FVF) or Super Source Follower (SSF) structure, before an external input voltage is applied. For example, as described below, the common mode voltage Vcm may be set as an initial potential formed at output nodes and feedback nodes of an FVF buffer (e.g.,inin, orin), a replica circuit (in), or a buffer (in), prior to the initiation of a sampling operation. In the present specification, for example, the initial voltages of the output nodes N, N, N, Nand the feedback nodes N, Nare regarded as the common mode voltage Vcm, which may serve as a reference potential maintained while the circuit is in a pre-sampling state or during sampling when reset switches are turned on and the corresponding nodes are AC grounded.

42 43 41 42 44 45 41 41 4 Since the first reset switch SWand the second reset switch SWare turned on, there may be no voltage change in the first node N, the second node N, the fourth node N, and the fifth node N. Accordingly, the parasitic capacitors Cgsand Cgdmay not affect the charge stored in the sampling capacitor Cs.

7 FIG. 8 FIG. 43 41 41 42 42 43 43 Referring toandtogether, in the second period P, the first switch SWmay be turned off by the first sample switch control signal Sof a low level L. The first reset switch SWmay be turned off by the first reset switch control signal Sof the low level L. The second reset switch SWmay be turned off by the second reset switch control signal Sof the low level L.

41 43 Since the first switch SWis turned off, the input voltage Vin may not be transmitted to the third node N.

805 807 411 43 411 42 411 412 42 412 412 42 41 At tto t, the current flowing through the first transistor Tmay increase as the voltage of the third node Nis applied to the gate terminal of the first transistor T. The voltage of the second node Nmay increase due to the current flowing through the first transistor T. The voltage applied to the gate terminal of the second transistor Tmay increase due to the increased voltage of the second node N. Since the second transistor Tis a P type transistor, as the voltage applied to the gate terminal increases, the current flowing to the second transistor Tmay decrease. Accordingly, the voltage of the second node Nand the first node Nmay decrease.

41 411 411 1 1 421 1 110 1 1 1 8 FIG. 1 FIG. The voltage of the first node Nmay decrease by the amount of the sum of a change amount in the input voltage Vin and a voltage difference between the gate terminal and the source terminal of the first transistor T. In, a voltage difference between the gate terminal and source terminal of the first transistor Tis shown as a first offset G. The first offset Gmay be based on a difference between an input voltage Vin and an output voltage Vout. In addition, the difference between the input voltage Vin and the output voltage Vout may be based on a gate-to-source voltage difference of a transistor T. Information regarding the magnitude of the first offset Gmay be pre-stored, for example, in the form of a look-up table (LUT). The ADC circuit (of) may compensate for the first offset Gby adding or subtracting a bit value corresponding to the first offset Gto or from a bit value corresponding to the input voltage Vin, based on the pre-stored first offset G.

807 41 1 41 110 1 FIG. After t, a first node voltageV(N) may be output a voltage obtained by subtracting the sum of the magnitude change in the input voltage Vin and the first offset Gfrom the common voltage (Vcm, N) as an output voltage Vout. Therefore, the output voltage Vout may be determined based on the charge stored in the sampling capacitor Cs by the input voltage Vin. Afterwards, it may be transmitted to the analog digital converter (of).

9 FIG. 10 FIG. 11 FIG. 9 FIG. 10 FIG. andare circuit diagrams of an S/H circuit according to one or more embodiments.is a timing diagram of the operation of the S/H circuit ofand.

9 FIG. 500 500 500 p n. As shown in, an S/H circuitmay include a first S/H circuitand a second S/H circuit

500 501 501 503 p p n The first S/H circuitmay include a first sampling circuit, a second sampling circuit, and a FVF buffer circuit.

501 511 51 p The first sampling circuitmay include a first switch SWand a first sampling capacitor Cs.

501 511 513 511 51 511 513 p The first sampling circuitmay receive a non-inverted input voltage Vinp through an input terminal. One end of the first switch SWmay be connected to the input terminal, and the other end may be connected to a third node N. The first switch SWmay be controlled by a first sample switch control signal S. When the first switch SWis turned on, the non-inverted input voltage Vinp input through the input terminal may be transmitted to the third node N.

51 513 51 513 511 51 513 The sampling capacitor Csmay be connected between the third node Nand the ground voltage. The sampling capacitor Csmay store charges based on a voltage of the third node N. When the first switch SWis turned on, the charge stored in the sampling capacitor Csmay increase as the non-inverting input voltage Vinp is transmitted to the third node N.

501 512 52 n The second sampling circuitmay include a second switch SWand a sampling capacitor Cs.

501 512 523 512 51 512 523 n The second sampling circuitmay receive an inverted input voltage Vinn through an input terminal. One end of the second switch SWmay be connected to the input terminal, and the other end may be connected to a third node N. The second switch SWmay be controlled by the first sample switch control signal S. When the second switch SWis turned on, the inverted input voltage Vinn input through the input terminal may be transmitted to the third node N.

52 523 52 523 512 52 523 The sampling capacitor Csmay be connected between the third node Nand the ground voltage. The sampling capacitor Csmay store charges based on a voltage of the third node N. When the second switch SWis turned on, the charge stored in the sampling capacitor Csmay increase as the inverted input voltage Vinn is transmitted to the third node N.

503 511 512 521 522 51 52 51 52 52 53 The FVF buffer circuitmay include a plurality of transistors T, T, T, and T, feedback capacitors Ccand Cc, resistors Rband Rb, a first reset switch SW, and a second reset switch SW.

9 FIG. 51 51 511 52 52 521 In, a plurality of capacitors Cgsand Cgdmay be parasitic capacitors between a gate terminal and a source terminal, and between the gate terminal and a drain terminal of a first transistor T. In addition, a plurality of capacitors Cgsand Cgdmay be parasitic capacitors between a gate terminal and a source terminal, and between the gate terminal and a drain terminal of a second transistor T.

511 513 511 511 511 512 51 513 511 511 51 513 512 503 9 FIG. The gate terminal of the first transistor Tmay be connected to a thirteenth node N. The source terminal of the first transistor Tmay be connected to an eleventh node N. The drain terminal of the first transistor Tmay be connected to a twelfth node N. A gate-source capacitor Cgsbetween the thirteenth node N, which is the gate terminal of the first transistor T, and the eleventh node N, and a gate-drain capacitor Cgdbetween the thirteenth node Nand the twelfth node Nare shown in, these are important when the FVF buffer circuitoperates at high frequency.

512 51 512 512 511 512 511 The gate terminal of the second transistor Tmay be connected to one end of the feedback capacitor Cc. The source terminal of the second transistor Tmay be connected to the power source voltage VDD. The drain terminal of the second transistor Tmay be connected to the eleventh node N. The second transistor Tmay perform a function that compensates for the operation of the first transistor T.

521 523 521 521 521 522 52 523 521 521 52 523 522 503 10 FIG. A gate terminal of a third transistor Tmay be connected to a twenty-third node N. A source terminal of the third transistor Tmay be connected to a twenty-first node N. A drain terminal of the third transistor Tmay be connected to a twenty-second node N. A gate-source capacitor Cgsbetween the twenty-third node N, which is a gate terminal of the third transistor T, and the twenty-first node N, and a gate-drain capacitor Cgdbetween the twenty-third node Nand the twenty-second node Nare shown in, these are important when the FVF buffer circuitoperates at high frequency.

522 52 522 522 521 522 521 A gate terminal of a fourth transistor Tmay be connected to one end of the feedback capacitor Cc. A source terminal of the fourth transistor Tmay be connected to the power source voltage VDD. A drain terminal of the fourth transistor Tmay be connected to the twenty-first node N. The fourth transistor Tmay perform a function that compensates for the operation of the third transistor T.

511 512 521 522 511 512 521 522 In some embodiments, the first transistor T, the second transistor T, the third transistor T, and the fourth transistor Tmay include P-type transistors. However, the present disclosure is not limited thereto, and the first transistor T, the second transistor T, the third transistor T, and the fourth transistor Tmay be N-type transistors.

51 512 512 The feedback capacitor Ccmay be connected between the gate terminal of the second transistor Tand the twelfth node N.

52 522 522 The feedback capacitor Ccmay be connected between the gate terminal of the fourth transistor Tand the twenty-second node N.

51 512 One end of the resistor Rbmay connected to the twelfth node N, and the other end may be connected to the ground power.

52 522 51 52 503 One end of the resistor Rbmay be connected to the twenty-second node N, and the other end may be connected to the ground power. The resistors Rband Rbmay control the intensity of the current flowing to the FVF buffer circuit.

52 512 522 52 52 52 512 522 One end of the first reset switch SWmay be connected to the twelfth node N, and the other end may be connected to the twenty-second node N. The first reset switch SWmay be controlled by a first reset switch control signal S. When the first reset switch SWis turned on, the twelfth node Nand the twenty-second node Nmay be connected.

53 511 521 53 53 53 511 521 One end of the second reset switch SWmay be connected to the eleventh node N, and the other end may be connected to the twenty-first node N. The second reset switch SWmay be controlled by a second reset switch control signal S. When the second reset switch SWis turned on, the eleventh node Nand the twenty-first node Nmay be connected.

503 511 503 503 The FVF buffer circuitmay output an output voltage through a plurality of output terminals. The first output terminal may be connected to the eleventh node N. The FVF buffer circuitmay output a non-inverted output voltage Voutp through a first output terminal. The FVF buffer circuitmay output an inverted output voltage Voutn through a second output terminal.

11 FIG. 500 500 51 1101 1105 53 1105 1109 Referring to, the S/H circuitmay alternately perform the sampling operation and the holding operation. The S/H circuitmay perform the sampling operation for a first period P(tto t) and may perform the holding operation for a second period P(tto t).

9 FIG. 11 FIG. 51 511 512 51 52 52 53 53 Referring toandtogether, in the first period P, the first switch SWand the second switch SWmay be turned on by the first sample switch control signal Sof a high level H. The first reset switch SWmay be turned on by the first reset switch control signal Sof the high level H. The second reset switch SWmay be turned on by the second reset switch control signal Sof the high level H.

51 51 52 During the first period P, charges may be stored in the sampling capacitors Csand Csbased on the corresponding input voltages Vinp and Vinn.

1103 1 1 1 1 inp inp inp inn inp inp inn inn At t, the non-inverting input voltage Vinp may transition from a first level (V(n-)) to a second level (V(n)). In addition, the inverted input voltage Vinn may transition from a third level (V(n-)) to a fourth level (V(n)). Here, a difference between the first level (V(n-)) and the second level (V(n)) and a difference between the third level (V(n-)) and the fourth level (V(n)) may be V.

inp inp inp inn inn inn 1 513 1 523 As the non-inverting input voltage Vtransitions from the first level first level (V(n-)) to the second level (V(n)), a voltage of the thirteenth node Nmay be lowered by V. As the inverted input voltage Vtransitions from the third level (V(n-)) to the fourth level (V(n)), a voltage of the twenty-third node Nmay increase by V.

52 512 522 53 511 521 511 521 512 522 Since the first reset switch SWis turned on, the voltage of the twelfth node Nand the voltage of the twenty-second node Nmay be maintained the same. In addition, since the second reset switch SWis turned on, the voltage of the eleventh node Nand the voltage of the twenty-first node Nmay be maintained the same. That is, a common mode voltage (Vcm, N) and a common mode voltage (Vcm, N) may be the same, and a common mode voltage (Vcm, N) and a common mode voltage (Vcm, N) may be the same.

52 53 511 512 521 522 Since the first reset switch SWand the second reset switch SWare turned on, the non-inverting input voltage Vinp and the inverting input voltage Vinn may not change due to changes in the eleventh node N, the twelfth node N, the twenty-first node N, and the twenty-second node N.

10 FIG. 11 FIG. 53 511 512 51 52 52 53 53 Referring toandtogether, in the second period P, the first switch SWand the second switch SWmay be turned off by the first sample switch control signal Sof a low level L. The first reset switch SWmay be turned off by the first reset switch control signal Sof the low level L. The second reset switch SWmay be turned off by the second reset switch control signal Sof the low level L.

511 512 513 523 Since the first switch SWand the second switch SWare turned off, the non-inverting input voltage Vinp may not be transmitted to the thirteenth node N, and the inverting input voltage Vinn may not be transmitted to the twenty-third node N.

1105 1107 513 511 511 512 511 512 512 512 512 512 511 At tto t, as the voltage of the thirteenth node Nis applied to the gate terminal of the first transistor T, the current flowing through the first transistor Tmay increase. The voltage of the twelfth node Nmay increase due to the current flowing through the first transistor T. The voltage applied to the gate terminal of the second transistor Tmay increase due to the increased voltage of the twelfth node N. Since the second transistor Tis a P type transistor, as the voltage applied to the gate terminal increases, the current flowing to the second transistor Tmay decrease. Accordingly, the voltage of the twelfth node Nand the eleventh node Nmay decrease.

511 511 511 51 11 FIG. The voltage of the eleventh node Nmay decrease by the sum of the amount of changed in the non-inverted input voltage Vinp and a voltage difference between the gate terminal and the source terminal of the first transistor T. In, a voltage difference between the gate terminal and the source terminal of the first transistor Tis shown as a first offset G.

523 521 521 522 521 522 522 522 522 522 521 Similarly, as the voltage of the twenty-third node Nis applied to the gate terminal of the third transistor T, the current flowing through the third transistor Tmay decrease. The voltage of the twenty-second node Nmay be reduced by the current flowing through the third transistor T. The voltage applied to the gate terminal of the fourth transistor Tmay decrease by the reduced voltage of the twenty-second node N. Since the fourth transistor Tis a P type transistor, the current flowing through the fourth transistor Tmay increase as the voltage applied to the gate terminal decreases. Accordingly, the voltage of the twenty-second node Nand the twenty-first node Nmay increase.

521 521 521 52 51 52 11 FIG. The voltage of the twenty-first node Nmay increase by the sum of the amount of change in the inverted input voltage Vinn and a voltage difference between the gate terminal and the source terminal of the third transistor T. In, a voltage difference between the gate terminal and the source terminal of the third transistor Tis shown as a second offset G. Here, the first offset Gand the second offset Gmay have the same value.

1107 511 51 511 521 52 521 After t, an eleventh node voltageV(N) may output a voltage, which is a voltage obtained by subtracting the sum of the change V in the magnitude of the non-inverting output voltage Vinp and the first offset Gfrom the common voltage (Vcm, N) as the non-inverted output voltage Voutp. The twenty-first node voltageV(N) may output a voltage obtained by adding the sum of the change V in the magnitude of the inverted input voltage Vinn and the second offset Gto the common voltage (Vcm, N) as the inverted output voltage Voutn.

53 500 110 110 1 FIG. 1 FIG. After the second period P, the S/H circuitmay transmit the non-inverted output voltage Voutp and the inverted output voltage Voutn to the ADC circuit (in). The ADC circuit (in) may determine a bit value corresponding to the input voltages Vinp and Vinn based on the non-inverted output voltage Voutp and the inverted output voltage Voutn.

500 511 51 513 511 521 511 521 512 522 512 522 511 521 51 51 511 52 52 521 The S/H circuitmay perform the sampling operation by connecting the source terminal and the drain terminal of the first transistor T, which receives the non-inverted input voltage Vinp in the first period P, and the source terminal and the drain terminal of the third transistor T, which receives the inverted input voltage Vinn. That is, the eleventh node Nand the twenty-first node Nmay have common voltages (Vcm, Nand Vcm, N), and the twelfth node Nand the twenty-second node Ncan have common voltages (Vcm, Nand Vcm, N). Accordingly, the voltage change occurring at the source terminal and the drain terminal of the first transistor Tdue to the non-inverting input voltage Vinp and the voltage change occurring at the source terminal and the drain terminal of the third transistor Tdue to the inverting input voltage Vinn may not occur. Therefore, there may be no distortion of the sampling capacitor Cs due to the parasitic capacitors Cgsand Cgdof the first transistor Tand the parasitic capacitors Cgsand Cgdof the third transistor T.

12 FIG. 13 FIG. 14 FIG. 12 FIG. 13 FIG. andare circuit diagrams of an S/H circuit according to one or more embodiments.is a timing diagram of the operation of the S/H circuit ofand.

12 FIG. 13 FIG. 600 600 is a circuit diagram of a case that an S/H circuitperforms the sampling operation, andis a circuit diagram of a case that the S/H circuitperforms the holding operation.

12 FIG. 13 FIG. 600 601 603 As shown inand, the S/H circuitmay include a sampling circuitand a buffer circuit.

601 61 6 The sampling circuitmay include a first switch SWand a sampling capacitor Cs.

601 61 63 61 61 61 63 The sampling circuitmay receive an input voltage Vin through an input terminal. One end of the first switch SWmay be connected to the input terminal, and the other end may be connected to a third node N. The first switch SWmay be controlled by a first sample switch control signal S. When the first switch SWis turned on, the input voltage Vin input through the input terminal may be transmitted to the third node N.

6 63 6 63 61 6 63 The sampling capacitor Csmay be connected between the third node Nand the ground voltage. The sampling capacitor Csmay store charges based on a voltage of the third node N. When the first switch SWis turned on, the charge stored in the sampling capacitor Csmay increase as the input voltage Vin is transmitted to the third node N.

603 The buffer circuitmay include a super source follower (SSF). The super source follower has a large input resistance and a low output resistance, and thus it may output the received input signal as an output signal with almost no loss.

603 61 62 62 63 1601 1603 The buffer circuitmay include a plurality of transistors Tand T, a first reset switch SW, a second reset switch SW, a first current source, and a second current source.

6 6 61 A plurality of capacitors Cgsand Cgdmay be parasitic capacitors between a gate terminal and a source terminal, and between the gate terminal and a drain terminal of a first transistor T.

61 3 61 61 61 62 603 6 63 61 61 6 63 62 603 12 FIG. The gate terminal of the first transistor Tmay be connected to the third node N. The source terminal of the first transistor Tmay be connected to a first node N. The drain terminal of the first transistor Tmay be connected to a second node N. While the buffer circuitoperates at high frequency, a gate-source capacitor Cgsbetween the third node N, which is the gate terminal of the first transistor T, and the first node N, and a gate-drain capacitor Cgdbetween the third node Nand the second node Nare shown in, these are important when the buffer circuitoperates at high frequency.

62 62 62 61 64 62 61 A gate terminal of the second transistor Tmay be connected to the second node N. A source terminal of the second transistor Tmay be connected to a first ground GND(i.e., fourth node N). A drain terminal of the second transistor Tmay be connected to the first node N.

61 62 1 2 In some embodiments, the first transistor Tmay be a P-type transistor and the second transistor Tmay include an N-type transistor. However, the present disclosure is not limited thereto, and the first transistor Tand the second transistor Tmay be N-type transistors or P-type transistors.

1601 61 1601 1 61 A first current sourcemay control a current input to the first node N. The first currentmay provide a first current lbto the first node N.

1603 62 64 1603 2 64 A second current sourcemay be connected between the second node Nand the fourth node N. The second currentmay provide a second current lbto the fourth node N.

61 1601 61 62 1603 62 2 1 1 2 The source terminal of the first transistor Tis driven by the first current source, and the drain terminal of the first transistor Tand the gate terminal of the second transistor Tmay be driven by the second current source. The current flowing into the drain terminal of the second transistor Tmay be a value obtained by subtracting the second current lbfrom the first current lb. The first current lbmay be greater than the second current Ib.

601 62 A drain voltage of the first transistor Tmay be set by a gate-source voltage of the second transistor T.

62 62 62 62 62 62 62 62 62 62 One end of the first reset switch SWmay be connected to the second node N, and the other end may be connected to a second ground GND. The second ground GNDmay be an AC ground. The first reset switch SWmay be controlled by a first reset switch control signal S. When the first reset switch SWis turned on, the second node Nmay be AC biased through the second ground GND. Accordingly, in the second node N, an AC component is removed and only a DC component voltage may exist.

63 61 63 63 63 63 63 61 3 61 One end of the second reset switch SWmay be connected to the first node N, and the other end may be connected to a third ground GND. Third ground GNDmay be the AC ground. The second reset switch SWmay be controlled by a second reset switch control signal S. When the second reset switch SWis turned on, the first node Nmay be AC biased through the third ground GND. Accordingly, at the first node N, the AC component is removed and only the DC component voltage may exist.

603 61 The buffer circuitmay output an output voltage Vout through an output terminal. The output terminal may be connected to the first node N.

14 FIG. 600 600 61 1401 1405 63 1405 1409 Referring to, the S/H circuitmay alternately perform the sampling operation and the holding operation. The S/H circuitmay perform the sampling operation during a first period P(tto t) and the holding operation during a second period P(tto t).

1401 61 61 62 62 63 63 At t, the first switch SWmay be turned on by the first sample switch control signal Sof a high level H. The first reset switch SWmay be turned on by the first reset switch control signal Sof the high level H. The second reset switch SWmay be turned on by the second reset switch control signal Sof the high level H.

12 FIG. 61 6 Referring to, during the first period P, charges may be stored in the sampling capacitor Csbased on the input voltage Vin.

1403 1 1 in in in in At t, the input voltage Vin may transition from a first level (V(n-)) to a second level (V(n)). Here, a difference between the first level (V(n-)) and the second level (V(n)) may be V.

in in 1 63 As the input voltage Vin transitions from the first level (V(n-)) to the second level (V(n)), a voltage of the third node Nmay be lowered by ΔV.

62 63 62 63 Since the first reset switch SWis turned on, the third node Nmay be AC grounded. Accordingly, the voltage of the second node Nmay not be changed by the voltage of the third node N.

63 61 61 63 61 61 62 62 In addition, since the second reset switch SWis turned on, the first node Nmay be AC grounded. Accordingly, the voltage of the first node Nmay not be changed by the voltage of the third node N. That is, the first node Nmay be maintained at a common mode voltage (Vcm, N), and the second node Nmay be maintained at a common mode voltage (Vcm, N).

13 FIG. 14 FIG. 63 61 61 62 62 63 63 Referring toandtogether, in the second period P, the first switch SWmay be turned off by the first sample switch control signal Sof the low level L. The first reset switch SWmay be turned off by the first reset switch control signal Sof the low level L. The second reset switch SWmay be turned off by the second reset switch control signal Sof the low level L.

61 63 Since the first switch SWis turned off, the input voltage Vin may not be transmitted to the third node N.

1405 1407 61 63 61 At tto t, the current flowing through the first transistor Tmay increase as the voltage of the third node Nis applied to the gate terminal of the first transistor T.

1603 62 61 62 The current flowing through the second current sourcemay be maintained constantly. The voltage of the first node Nmay decrease due to the current flowing through the first transistor T. In addition, the voltage of the second node Nmay be increased.

1601 62 62 However, the entire current flowing through the first current sourcemay be the same. The voltage of the second node Nmay again be maintained at the common mode voltage (Vcm, N).

61 61 61 61 14 FIG. The voltage of the first node Nmay decrease by a value obtained by adding the voltage difference between the gate terminal and the source terminal of the first transistor Tto the amount of change in the input voltage Vin. In, the voltage difference between the gate terminal and the source terminal of the first transistor Tis illustrated as a first offset G.

1407 61 61 61 After t, the first node voltageV(N) may output a voltage obtained by subtracting the sum of the change V in the magnitude of the input voltage Vin and the first offset Gfrom the common voltage (Vcm, N), as the output voltage Vout.

63 600 110 110 1 FIG. After the second section P, the S/H circuitmay transmit the output voltage Vout to the ADC circuit (in). The ADC circuitmay determine a bit value corresponding to the input voltage Vin based on the output voltage Vout.

6 6 61 600 61 61 61 62 6 6 61 62 6 6 6 61 The parasitic capacitors Cgsand Cgdmay exist between the gate terminal and the source terminal, and between the gate terminal and the drain terminal of the first transistor T. The S/H circuitmay connect the source terminal and the drain terminal of the first transistor T, which receives the input voltage Vin in the first period P, to the AC ground. Accordingly, the voltages of the first node Nand the second node Nmay not change due to changes in the input voltage Vin through the parasitic capacitors Cgsand Cgd. Therefore, the voltage of the first node Nand the second node Nmay not have any influence on the sampling capacitor Csby the parasitic capacitor Cgsand Cgdof the first transistor T.

15 FIG. is a block diagram of a communication apparatus according to one or more embodiments.

1500 1500 1500 1500 1500 1500 A communication apparatusmay refer to any device that communicates with another communication apparatus through a communication channel CH. For example, the communication apparatusmay be a portable device or a component included in a portable device, such as a laptop computer, a mobile phone, a wearable device, and the like. In addition, the communication apparatusmay be a fixed device or a component included in a fixed device, such as a desktop computer, a server, a kiosk, and the like. In addition, the communication apparatusmay also be used as a component of a means of transportation such as a vehicle or a ship. In some embodiments, the communication channel CH may include a wired channel, and the communication apparatusmay perform communication based on any wired communication, for example, optical communication, Ethernet, peripheral component interconnect (PCI), PCI express (PCIe), universal serial bus (USB), serial ATA (SATA), and the like. In some embodiments, the communication channel CH may include a radio channel, and the communication apparatusmay perform communication based on any wireless communication, a wireless local area network (WLAN), Bluetooth, long-term evolution (LTE), 5th generation (5G), and the like.

15 FIG. 1500 152 154 156 1500 152 154 152 154 As shown in, the communication apparatusmay include a transmitter, a receiver, and a processing circuit. When the communication channel CH includes a radio channel, the communication apparatusmay further include at least one antenna connected to the transmitterand the receiver. In some embodiments, the transmitterand the receivermay be implemented as a single component and collectively referred to as a transceiver.

152 156 152 152 1 152 2 152 2 156 152 1 152 1 15 FIG. The transmittermay receive transmission data TXD from the processing circuitand output a transmission signal TX to the communication channel CH based on the transmission data TXD. As shown in, the transmittermay include a transmitter circuit_and a digital-to-analog converter (DAC)_. The DAC_may convert the transmission data TXD received from the processing circuitinto an analog signal, and the transmitter circuit_may process the analog signal to generate a transmission signal TX. The transmitter circuit_may include circuits for processing analog signals, for example, an amplifier, a filter, or a mixer.

154 156 154 154 1 154 2 154 1 15 FIG. The receivermay receive a received signal RX from the communication channel CH and provide received data RXD to the processing circuitbased on the received signal RX. As shown in, the receivermay include a receiver circuit_and an analog-to-digital converter (ADC)_. The receiver circuit_may process the received signal RX and may include circuits for processing the received signal RX, for example, an amplifier, a filter, or a mixer.

154 1 154 1 154 2 154 1 2 FIG. 14 FIG. In some embodiments, the receiver circuit_may include the S/H circuit as described with reference toto. In some embodiments, the S/H circuit may include a feedback loop to which a feedback capacitor is connected. The receiver circuit_may receive the received signal RX, and may AC ground an output node and the feedback loop connected to the ADC_while sampling the received signal RX. Since the output node and feedback loop are AC grounded, only DC components may exist in the output node and the feedback loop during sampling. Accordingly, a sampling value may not be changed by a parasitic capacitor between an input terminal (i.e., gate terminal) of the S/H circuit and the output node and between the input terminal and the feedback loop. That is, the receiver circuit_may control the S/H circuit such that the sampling value corresponding to the received signal RX is not distorted by a voltage change of the output node and the feedback loop.

154 2 154 1 154 2 The ADC_may generate received data RXD by converting the signal received from the receiver circuit_. For high-speed communications, the ADC_may be a time-interleaved ADC including a plurality of sub analog-digital converters.

156 152 156 152 The processing circuitmay generate transmission data TXD based on information to be transmitted to another communication apparatus through the communication channel CH in a transmission mode, and provide the transmission data TXD to the transmitter. In addition, the processing circuitmay receive received data RXD from the transmitterin a receiving mode, and may obtain information transmitted by another communication apparatus through the communication channel CH by processing the received data RXD.

156 The processing circuitmay include programmable components, components providing fixed functions, and/or reconfigurable components.

While certain example embodiments have been described, it is to be understood that embodiments of the present disclosure is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.