Receiver with Pre-Cursor Intersymbol Interference Mitigation

This application is a continuation of U.S. patent application Ser. No. 18/309,587, filed Apr. 28, 2023, which claims priority from U.S. Provisional Application No. 63/417,341, titled “Pre-Cursor ISI Mitigation using Clock Shifting”, filed on Oct. 19, 2022, which applications are hereby incorporated herein by reference.

In high-speed wireline systems with lossy media (e.g., cables), pre-cursor and post-cursor intersymbol interference (ISI) degrades signal integrity. While continuous-time linear equalizer (CTLE) and decision-feedback equalizer (DFE) techniques can reduce or cancel post-cursor ISI, these techniques are not effective against pre-cursor ISI. A transmitter-side finite impulse response (FIR) is one option to mitigate pre-cursor ISI, but some communication standards do not permit this option. Another option to mitigate pre-cursor ISI is a receiver-side feed-forward equalizer (FFE), but this option results in an undesirable noise penalty.

In an example, a receiver includes: equalizer circuitry; clock and data recovery (CDR) circuitry; sampler circuitry; adaptation circuitry; and clock adjustment circuitry. The equalizer circuitry has a first input, a second input, and an output. The CDR circuitry has a first input, a second input, and a clock output. The sampler circuitry has a first input, a second input, and an output. The adaptation circuitry has a first input, a second input, a third input, a first output, a second output, and a third output. The first input of the adaptation circuitry is coupled to the output of the CDR circuitry. The second input of the adaptation circuitry is coupled to the output of the sampler circuitry. The third input of the adaptation circuitry is coupled to the output of the equalizer circuitry. The first output of the adaptation circuitry is coupled to the second input of the equalizer circuitry. The second output of the adaptation circuitry is coupled to the first input of the CDR circuitry and the first input of the sampler circuitry. The clock adjustment circuitry has a first input, a second input, and an output. The first input of the clock adjustment circuitry is coupled to the third output of the adaptation circuitry. The second input of the clock adjustment circuitry is coupled to the clock output of the CDR circuitry. The output of the clock adjustment circuitry is coupled to the second input of the CDR circuitry or the second input of the sampler circuitry.

In another example, a system includes: a transmitter; and a receiver in communication with the transmitter via a channel. The receiver includes: equalizer circuitry; CDR circuitry; sampler circuitry; adaptation circuitry; and clock adjustment circuitry. The equalizer circuitry has a first input, a second input, and an output. The CDR circuitry has a first input, a second input, and a clock output. The sampler circuitry has a first input, a second input, and an output. The adaptation circuitry has a first input, a second input, a third input, a first output, a second output, and a third output. The first input of the adaptation circuitry is coupled to the output of the CDR circuitry. The second input of the adaptation circuitry is coupled to the output of the sampler circuitry. The third input of the adaptation circuitry is coupled to the output of the equalizer circuitry. The first output of the adaptation circuitry is coupled to the second input of the equalizer circuitry. The second output of the adaptation circuitry is coupled to the first input of the CDR circuitry and the first input of the sampler circuitry. The clock adjustment circuitry has a first input, a second input, and an output. The first input of the clock adjustment circuitry is coupled to the third output of the adaptation circuitry. The second input of the clock adjustment circuitry is coupled to the clock output of the CDR circuitry. The output of the clock adjustment circuitry is coupled to the second input of the CDR circuitry or the second input of the sampler circuitry.

In yet another example, a method includes: receiving data via a channel; performing equalization operations on received data, the equalization operations resulting in first equalized data; performing sampling operations responsive to the first equalized data and second equalized data, the sampling operations resulting in data samples and error samples; performing adaptation operations responsive to the first equalized data, the data samples, and the error samples, the adaptation operations resulting in a clock adjustment control signal and the second equalized data; providing a CDR clock signal responsive to the second equalized data; and adjusting a sampling clock signal relative to the CDR clock signal responsive to the clock adjustment control signal.

The same reference numbers or other reference designators are used in the drawings to designate the same or similar features. Such features may be the same or similar either by function and/or structure.

Described herein are receivers with clock adjustment circuitry and related circuits and systems. The clock adjustment circuitry adjusts a clock and data recovery (CDR) clock signal relative to a sampling clock signal. In some examples, the operations of the clock adjustment circuitry delay the CDR clock signal so that the CDR clock signal is delayed related to the sampling clock signal. As another option, the operations of the clock adjustment circuitry delay both the CDR clock signal and the sampling clock signal, where the CDR clock signal is delayed more than the sampling clock signal. As another option, a voltage level of the sampling clock signal is adjusted to shift the phase of the sampling clock signal relative to the phase of the CDR clock signal. As desired, the operations of the clock adjustment circuitry may combine clock signal delay options and clock signal voltage adjustment options to adjust a CDR clock signal relative to a sampling clock signal. In some examples, the operations of the clock adjustment circuitry adjust a CDR clock signal relative to a sampling clock signal to mitigate pre-cursor inter-symbol interference (ISI).

1 FIG. 100 100 102 106 112 102 104 106 108 110 106 112 113 is a diagram showing an example system. As shown, the systemincludes a transmitter, a channel, and a receiver. The transmitterhas an output. The channelhas an inputand an output. In some examples, the channelis a wired channel. The receiverhas an input.

1 FIG. 114 140 150 128 162 114 116 118 120 122 124 126 140 142 144 146 148 150 152 154 156 158 160 156 128 130 132 134 136 138 162 164 166 168 170 172 170 172 170 172 In the example of, the receiver includes equalizer circuitry, CDR circuitry, sampler circuitry, adaptation circuitry, and clock adjustment circuitry. The equalizer circuitryhas a first input, a second input, a third input, a fourth input, a fifth input, and an output. The CDR circuitryhas a first input, a second input, a first output, and a second output. The sampler circuitryhas a first input, a second input, a third input, a first output, and a second output. In some examples, the third inputis omitted. The adaptation circuitryhas a first input, a second input, a first output, a second output, and a third output. The clock adjustment circuitryhas a first input, a second input, a third input, a first outputand a second output. In some examples, the first outputis omitted and the second outputis included. In other examples, the first outputis included and the second outputis omitted.

1 FIG. 116 114 113 112 118 114 148 140 120 114 160 150 122 114 134 128 124 114 136 128 126 114 142 140 152 150 114 In the example of, the first inputof the equalizer circuitryis coupled to the inputof the receiver. The second inputof the equalizer circuitryis coupled to the second outputof the CDR circuitry. The third inputof the equalizer circuitryis coupled to the second outputof the sampler circuitry. The fourth inputof the equalizer circuitryis coupled to the first outputof the adaptation circuitry. The fifth inputof the equalizer circuitryis coupled to the second outputof the adaptation circuitry. The outputof the of the equalizer circuitryis coupled to the first inputof the CDR circuitryand to the first inputof the sampler circuitry. Without limitation, the equalizer circuitrymay include continuous-time linear equalizer (CTLE) circuitry, decision feedback equalizer (DFE) circuitry, combine circuitry, and/or other equalizer circuitry.

144 140 170 162 146 140 166 162 148 140 168 162 The second inputof the CDR circuitryis coupled to the first outputof the clock adjustment circuitry. The first outputof the CDR circuitryis coupled to the second inputof the clock adjustment circuitry. The second outputof the CDR circuitryis coupled to the third inputof the clock adjustment circuitry.

156 150 162 158 150 130 128 160 150 132 128 138 128 164 162 The third inputof the sampler circuitryis coupled to the second output of the clock adjustment circuitry. The first outputof the sampler circuitryis coupled to the first inputof the adaptation circuitry. The second outputof the sampler circuitryis coupled to the second inputof the adaptation circuitry. The third outputof the adaptation circuitryis coupled to the first inputof the clock adjustment circuitry.

114 116 140 118 150 120 128 122 128 124 126 In some examples, the equalizer circuitryoperates to: receive data from the channel at its first input; receive a sampling clock signal from the CDR circuitryat its second input; receive data samples from the sampler circuitryat its third input; receive CTLE index results from the adaptation circuitryat its fourth input; receive DFE coefficient(s) from the adaptation circuitryat its fifth input; and provide equalization results at its outputresponsive to the received data, the sampling clock signal, the data samples, the CTLE index results, and the DFE coefficient(s).

140 114 142 162 144 146 148 In some examples, the CDR circuitryoperates to: receive equalization results from the equalizer circuitryat its first input; receive an adjusted clock signal, e.g., an adjusted CDR clock signal, from the clock adjustment circuitryat its second input; generate first and second (CDR) clock signals responsive to the equalization results and, in some instances, according to the adjusted clock signal; provide the first CDR clock signal at its first output; and provide the second CDR clock signal at its second output.

150 114 152 140 154 162 156 158 160 In some examples, the sampler circuitryoperates to: receive equalization results from the equalizer circuitryat its first input; receive a CDR clock signal from the CDR circuitryat its second inputor receive the adjusted clock signal from the clock adjustment circuitryat its third input; provide error samples at its first outputresponsive to the equalization results and responsive to the CDR clock signal or the adjusted clock signal; and provide data samples at its second outputresponsive to the equalization results and responsive to the CDR clock signal or the adjusted clock signal.

128 150 130 150 132 134 136 138 In some examples, the adaptation circuitryoperates to: receive error samples from the sampler circuitryat its first input; receive data samples from the sampler circuitryat its second input; provide CTLE index results at its first outputresponsive to the error samples and the data samples; provide DFE coefficient(s) at its second outputresponsive to the error samples and the data samples; and provide a clock adjustment control signal at its third outputresponsive to the error samples and the data samples.

162 128 164 166 168 170 162 172 170 172 In some examples, the clock adjustment circuitryoperates to: receive a clock adjustment control signal from the adaptation circuitryat its first input; receive a first CDR clock signal at its second input; receive a second CDR clock signal at its third input; provide an adjusted CDR clock signal at its first outputresponsive to the clock adjustment control signal and the first and/or second CDR clock signals. In some examples, the adjusted clock signal is a first adjusted clock signal, and the clock adjustment circuitryoperates to provide a second adjusted clock signal at its second outputresponsive to the clock adjustment control signal and the first and/or second CDR clock signals. In some examples, the first adjusted clock signal at the first outputand/or the second adjusted clock signal at the second outputare used to mitigate pre-cursor ISI.

100 102 112 In some examples, the systemuses a 2-level modulation scheme or a multi-level modulation scheme for communications between the transmitterand the receiver. An example 2-level modulation scheme is a non-return-to-zero (NRZ) modulation scheme. An example multi-level modulation scheme is a pulse-amplitude modulation (PAM-N) modulation scheme.

2 a FIG. 200 200 is an example graphshowing a single-bit pulse response of a receiver, in which a CDR clock (also referred to herein as a CDR clock signal) is aligned with a sampling clock (also referred to herein as a sampling clock signal). The CDR clock signal is generated by CDR circuity. The sampling clock signal is provided by the CDR circuitry to sampler circuitry. The example receiver includes equalizer circuitry that includes both CTLE circuitry and DFE circuitry. Accordingly, in the graph, the receiver signals include a CTLE output signal (pulse) and a DFE output signal (pulse) as a function of time.

200 200 −1 0 1 0 −1 1 2 3 0 The graphalso shows a CDR clock position and voltage c, c, and c(sometimes referred to as “terms” herein) at respective sampling points. The voltage cis called the main cursor and is the desired voltage caused by the current but at the current sample point. The voltage cis an undesired voltage caused by the current bit at the previous sample point due to pre-cursor ISI between bit N and bit N−1. The voltage cis an undesired voltage caused by the current bit at the next sample point due to post-cursor ISI between bit N and bit N+1. In some examples, DFE is used to zero additional post-cursor terms (e.g., c, c, and so on). For error-free reception of the data signal, the sum of all the pre-cursor and post-cursor ISI terms is much lower than the main cursor. In the graph, the current sampling point for the voltage cis aligned with the CDR clock signal. As shown, the CTLE output signal and the DFE output signal are the same before the current sampling point, indicating that the pre-cursor ISI is not mitigated by the DFE. After the current sampling point, the DFE output signal drops quickly compared to the CTLE output signal, thus forcing the post-cursor ISI term to zero and, thereby, canceling the post-cursor ISI term.

2 b FIG. 210 210 200 is a graphshowing receiver signals in which the CDR clock signal and the sampling clock signal are not aligned, in that there is a relative delay between the clock signals. For example, the CDR clock signal is delayed relative to the sampling clock signal, which is represented as the sampling clock signal being shifted to the left of the CDR clock signal. In the graph, the receiver signals again include the CTLE output signal and the DFE output signal described for the graph.

210 210 200 −1 0 1 0 1 −1 −1 0 1 −1 0 1 0 0 −1 −1 1 1 1 The graphalso shows a CDR clock position and voltages c′, c′, and c′at respective sampling points. The voltage c′is the main cursor and is the desired voltage caused by the current but at the current sample point. The voltage c′is an undesired voltage caused by the current bit at the next sample point due to post-cursor ISI between bit N and bit N+1. The voltage c′is an undesired voltage caused by the current bit at the previous sample point due to pre-cursor ISI between bit N and bit N−1. In the graph, the sampling points for the voltages c′, c′, and c′are shifted to the left relative to the sampling points represented in graph. With the sampling points for the voltages c′, c′, and c′shifted to the left, the voltage c′relative to the voltage cis reduced slightly, the voltage c′relative to the voltage cis greatly reduced, and the voltage c′relative to the voltage cis slightly increased. As shown, the voltage c′for the DFE output is forced to zero, thus canceling post-cursor ISI. By selectively adjusting the position of the sampling clock signal and/or the position of the CDR clock as described herein, the sampled voltage values can reduce pre-cursor ISI without significantly affecting post-cursor ISI handling.

200 210 1 2 3 0 2 2 a b FIGS.and 2 2 a b FIGS.and In some examples, the CTLE output shown in graphsandis the same as the DFE input. The DFE tap works on post-cursor ISI term cas well as additional post-cursor ISI term cand c(not specifically shown in). DFE taps are adjusted such that the post-cursor ISI terms are forced to zero in the pulse response at the DFE output. As shown in, DFE does not affect the pre-cursor ISI term c or the main cursor term c.

3 6 FIGS.- 3 FIG. 300 400 500 600 300 114 140 150 128 162 114 114 140 140 150 150 128 128 162 162 are block diagrams respectively illustrating example receivers,,, and. In the example of, the receiverincludes equalizer circuitryA, CDR circuitryA, sampler circuitryA, adaptation circuitryA, and clock adjustment circuitryA. The equalizer circuitryA is an example of the equalizer circuitry. The CDR circuitryA is an example of the CDR circuitry. The sampler circuitryA is an example of the sampler circuitry. The adaptation circuitryA is an example of the adaptation circuitry. The clock adjustment circuitryA is an example of the clock adjustment circuitry.

114 116 118 120 122 124 126 140 142 146 148 140 144 144 144 150 152 154 158 160 128 130 132 134 136 138 162 164 166 168 162 170 170 170 170 170 1 FIG. 1 FIG. 1 FIG. 1 FIG. 1 FIG. 1 FIG. 3 FIG. 1 FIG. The equalizer circuitryA has the first input, the second input, the third input, the fourth input, the fifth input, and the outputdescribed in. The CDR circuitryA has the first input, the first output, and the second outputdescribed in. The CDR circuitryA also has a second inputA and a third inputB, which are examples of the second inputin. The sampler circuitryA has the first input, the second input, the first output, and the second outputdescribed in. The adaptation circuitryA has the first input, the second input, the first output, the second output, and the third outputdescribed in. The clock adjustment circuitryA has the first input, the second input, and the third inputdescribed in. In the example of, the clock adjustment circuitryA has a first outputA and a second outputB. The first outputA and the second outputB are examples of the first outputin.

114 302 306 310 303 304 305 306 307 308 309 310 312 314 316 317 310 1 2 3 As illustrated, the equalizer circuitryA includes a combine circuit, a CTLE circuit, and a DFE circuit. The combine circuit has a first input, a second input, and an output. The CTLE circuithas a first input, a second input, and an output. The DFE circuithas a first input, a second input, a third input, and an output. In some examples, the DFE circuitis 3-tap DFE circuit used to cancel three post-cursor ISI terms (e.g., terms c, cand c).

140 338 344 348 352 360 368 370 338 339 339 340 341 342 344 345 346 348 349 350 352 354 356 358 360 362 363 364 366 368 369 370 371 372 3 FIG. As illustrated, the CDR circuitryA includes a phase and frequency detector (PFD), a frequency detector charge pump (FD CP), a phase detector charge pump (PD CP), a loop filter, a voltage-controlled oscillator (VCO), a VCO regulator, and a divider. In the example of, the PFDhas a first inputA, a second inputB, a third input, first outputs, and second outputs. The frequency detector charge pumphas inputsand an output. The phase detector charge pumphas inputsand an output. The loop filterhas a first input, a second input, and an output. The VCOhas a first input, a second input, a first output, and a second output. The VCO regulatorhas an output. The dividerhas includes inputsand outputs.

150 374 378 374 375 376 377 378 379 380 381 3 FIG. As illustrated, the sampler circuitryA includes an error samplerand a data sampler. In the example of, the error samplerhas a first input, a second input, and an output. The data samplerhas a first input, a second input, and an output.

128 318 322 326 334 318 319 320 318 322 323 324 322 326 328 330 331 332 334 335 336 As illustrated, the adaptation circuitryA includes a first deserializer, a second deserializer, a digital equalizer adaptation circuit, and a clock adjustment controller. Although logically shown as part of the adaptation circuitry, the clock adjustment controller can be logically part of the clock adjustment circuitry. The first deserializerhas an inputand outputs. In some examples, the first deserializeris a 1:32 (one input to 32 parallel outputs) deserializer. The second deserializerhas an inputand outputs. In some examples, the second deserializeris a 1:32 deserializer. The digital equalizer adaptation circuithas first inputs, second inputs, a first output, and a second output. The clock adjustment controllerhas an inputand an output.

162 382 388 382 384 385 386 388 390 391 392 As illustrated, the clock adjustment circuitryA includes a first delay circuitand a second delay circuit. The first delay circuithas a first input, a second input, and an output. The second delay circuithas a first input, a second input, and an output.

3 FIG. 307 306 116 114 306 122 114 309 306 303 302 312 310 120 114 314 310 124 114 316 310 118 114 317 310 304 302 305 302 126 114 In the example of, the first inputof the CTLE circuitis coupled to the first inputof the equalizer circuitryA. The second input of the CTLE circuitis coupled to the fourth inputof the equalizer circuitryA. The outputof the CTLE circuitis coupled to the first inputof the combine circuit. The first inputof the DFE circuitis coupled to the third inputof the equalizer circuitryA. The second inputof the DFE circuitis coupled to the fifth inputof the equalizer circuitryA. The third inputof the DFE circuitis coupled to the second inputof the equalizer circuitryA. The outputof the DFE circuitis coupled to the second inputof the combine circuit. The outputof the combine circuitis coupled to the outputof the equalizer circuitryA.

3 FIG. 339 338 144 140 339 338 144 140 340 338 142 140 341 338 345 344 342 338 349 348 346 344 354 352 350 348 356 352 352 362 360 363 369 368 364 360 371 370 366 360 371 370 372 370 146 140 372 370 146 148 140 In the example of, the first inputA of the PFDis coupled to the second inputA of the CDR circuitryA. The second inputB of the PFDis coupled to the third inputB of the CDR circuitryA. The third inputof the PFDis coupled to the first inputof the CDR circuitryA. The first outputsof the PFDare coupled to the inputsof the frequency detector charge pump. The second outputsof the PFDare coupled to the inputsof the phase detector charge pump. The outputof the frequency detector charge pumpis coupled to the first inputof the loop filter. The outputof the phase detector charge pumpis coupled to the second inputof the loop filter. The output of the loop filteris coupled to the first inputof the VCO. The second inputis coupled to the outputof the VCO regulator. The first outputof the VCOis coupled to the inputsof the divider. The second outputof the VCOis also coupled to the inputsof the divider. The outputsof the dividerare coupled to the first outputof the CDR circuitryA. The outputsof the dividerare coupled to the first outputand the second outputof the CDR circuitryA.

375 374 152 150 376 374 154 150 377 374 158 150 379 378 152 150 380 378 154 150 381 378 160 150 As illustrated, the first inputof the error sampleris coupled to the first inputof the sampler circuitryA. The second inputof the error sampleris coupled to the second inputof the sampler circuitryA. The outputof the error sampleris coupled to the first outputof the sampler circuitryA. The first inputof the data sampleris coupled to the first inputof the sampler circuitryA. The second inputof the data sampleris coupled to the second inputof the sampler circuitryA. The outputof the data sampleris coupled to the second outputof the sampler circuitryA.

319 318 130 128 320 318 328 326 323 322 132 128 324 322 330 326 331 326 134 128 332 326 136 128 331 326 335 334 336 334 138 128 The inputof the first deserializeris coupled to the first inputof the adaptation circuitryA. The outputsof the first deserializerare coupled to the first inputsof the digital equalizer adaptation circuit. The inputof the second deserializeris coupled to the second inputof the adaptation circuitryA. The outputsof the second deserializerare coupled to the second inputsof the digital equalizer adaptation circuit. The first outputof the digital equalizer adaptation circuitis coupled to the first outputof the adaptation circuitryA. The second outputof the digital equalizer adaptation circuitis coupled to the second outputof the adaptation circuitryA. The first outputof the digital equalizer adaptation circuitis also coupled to the inputof the clock adjustment controller. The outputof the clock adjustment controlleris coupled to the third outputof the adaptation circuitryA.

384 382 166 162 385 382 164 162 386 382 170 162 390 388 168 162 391 388 164 162 392 388 170 162 The first inputof the first delay circuitis coupled to the second inputof the clock adjustment circuitryA. The second inputof the first delay circuitis coupled to the first inputof the clock adjustment circuitryA. The outputof the first delay circuitis coupled to the first outputA of the clock adjustment circuitryA. The first inputof the second delay circuitis coupled to the third inputof the clock adjustment circuitryA. The second inputof the second delay circuitis coupled to the first inputof the clock adjustment circuitryA. The outputof the second delay circuitis coupled to the second outputB of the clock adjustment circuitryA.

300 106 1 FIG. In some examples, the receiveroperates to: receive data via a channel such as the channelin; perform equalization operations on the received data, the equalization operations resulting in equalized data; perform sampling operations responsive to or on the equalized data, the sampling operations resulting in error samples and data samples; perform adaptation operations responsive to the error samples and the data samples, the adaptation operations resulting in a clock adjustment control signal, CTLE index results, and DFE coefficient(s); provide a CDR clock signal and a sampling clock signal responsive to the equalized data and input clock signal(s); and adjust the CDR clock signal and/or the sampling clock signal responsive to the clock adjustment control signal.

114 116 140 118 150 120 128 122 128 124 126 More specifically, the equalizer circuitryA operates to: receive data from the channel at its first input; receive a sampling clock signal from the CDR circuitryA at its second input; receive data samples from the sampler circuitryA at its third input; receive CTLE index results from the adaptation circuitryA at its fourth input; receive DFE coefficient(s) from the adaptation circuitryA at its fifth input; and provide equalization results at its outputresponsive to the received data from the channel; the sampling clock signal; the data samples; the CTLE index results; and DFE coefficient(s). In this example, the equalization results include equalized or filtered data with mitigated pre-cursor and post-cursor ISI resulting from implementing the described teachings.

140 114 142 162 144 144 146 148 140 372 370 162 The CDR circuitryA operates to: receive the equalization results from the equalizer circuitryA at its first input; receive adjusted clock signals from the clock adjustment circuitryA at its second inputA and third inputB; provide a first CDR clock signal at its first outputresponsive to the equalization results and the adjusted clock signal; and provide a second CDR clock signal at its second outputresponsive to the equalization results (e.g., the equalized data) and the adjusted clock signal. For example, the CDR circuitryA performs clock recovery from the equalized data, resulting in recovered CDR clock signals (e.g., the I and Q clock signals herein)at the outputsof the divider. The recovered CDR clock signals are time shifted by the clock adjustment circuitryA based on the described teachings.

150 114 152 140 154 158 160 The sampler circuitryA operates to: receive equalization results (e.g., the equalized data) from the equalizer circuitryA at its first input; receive a sampling clock signal from the CDR circuitryA at its second input; provide error samples at its first outputresponsive to the equalization results and the CDR clock signal; and provide data samples at its second outputresponsive to the equalization results and the sampling clock signal.

128 150 130 150 132 134 136 138 The adaptation circuitryA operates to: receive error samples from the sampler circuitryA at its first input; receive data samples from the sampler circuitryA at its second input; provide CTLE index results at its first outputresponsive to the error samples and the data samples; provide DFE coefficient(s) at its second outputresponsive to the error samples and the data samples; provide a clock adjustment control signal at its third outputresponsive to the error samples and the data samples.

162 122 164 166 168 170 170 170 170 300 The clock adjustment circuitryA operates to: receive a clock adjustment control signal from the adaptation circuitryA at its first input; receive a first CDR clock signal at its second input; receive a second CDR clock signal at its third input; provide an first adjusted clock signal at its first outputA responsive to the first CDR clock signal and the clock adjustment control signal; and provide a second adjusted clock signal at its second outputB responsive to the second CDR clock signal and the clock adjustment control signal. With the first adjusted clock signal at the first outputA and/or the second adjusted clock signal at the second outputB, the receivercan mitigate pre-cursor ISI using the described teachings.

338 140 339 339 341 342 344 338 345 346 348 338 349 350 352 344 354 348 356 358 In some examples, the PFDof the CDR circuitryA operates to: receive a Q clock signal received at its first inputA; receive an I clock signal at its second inputB; provide frequency information of the equalized data at the first outputsresponsive to the received Q and I clock signals; and provide phase information of the equalized data at the second outputsresponsive to the received Q and I clock signals. The frequency detector charge pumpoperates to: receive frequency information from the PFDat its inputs; and provide a charge at its outputresponsive to the received frequency information. The phase detector charge pumpoperates to: receive phase information from the PFDat its inputs; and provide a charge at its outputresponsive to the received phase information. The loop filteroperates to: receive charge from the frequency detector charge pumpat its first input; receive charge from the phase detector charge pumpat its second input; and provide a control voltage at its outputresponsive to the received charges. In an example, the control voltage is representative of the phase and frequency information of the equalized data.

360 352 362 368 363 364 366 370 371 372 370 360 370 370 372 372 150 372 370 162 The VCOoperates to: receive the control voltage from the loop filterat its first input; receive a supply voltage from the VCO regulatorat its second input; provide a Q clock signal at its first outputresponsive to the control voltage and the supply voltage; and provide an I clock signal at its second outputresponsive to the control voltage and the supply voltage. The divideroperates to: receive the Q and I clock signals at its inputs; and provide divider results at its outputsresponsive received Q and I clock signals and a divider integer setting N of the divider. In different examples, the value of N varies. In some examples, the VCOmay provide a single clock signal to the divider. In such examples the dividermay generate I and Q clock phases. Moreover, the divider results at the outputsrepresent a CDR clock signal derived from the equalized data. In the present examples, the clock signal from one of the outputsis provided to the sampling circuitryA as the sampling clock signal. Additionally, in the present example, the CDR clock signal at outputsof the divideris delayed by the clock adjustment circuitryA relative to the sampling clock signal.

140 150 3 FIG. The CDR circuitryA inis an example of a full-rate CDR that uses I and Q clocks. The I clock or in-phase clock is usually aligned to the middle of the data bit. Accordingly, the I clock may be used to sample data for the sampler circuitryA (perhaps with some clock shifting as described herein). The I clock is also used to generate phase information for the CDR clock signal (e.g., the I clock is used for phase acquisition/detection). The Q clock on the other hand is 90 degree out of phase when compared to the I clock and is used in conjunction with the I clock to determine frequency information for the CDR clock signal (e.g., the I and Q clocks are used for frequency acquisition/detection).

306 307 308 309 310 312 314 316 317 302 303 304 305 In some examples, the CTLE circuitoperates to: receive an analog data signal at its first input; receive a CTLE index at its second input; and provide CTLE results at its outputresponsive to the analog data signal and the CTLE index. The DFE circuitoperates to: receive data samples at its first input; receive DFE coefficient(s) at its second input; receive a sampling clock signal at its third input; and provide DFE results at its outputresponsive to the data samples, the DFE results, and the sampling clock signal. The combine circuitoperates to: receive CTLE results at its first input; receive DFE results at its second input; and provide equalization results at its outputresponsive to the CTLE results and the DFE results.

374 375 376 377 378 379 380 381 318 374 320 322 378 324 The error sampleroperates to: receive the equalization results at its first input; receive the sampling clock signal at its second input; and provide error samples at its outputresponsive to the equalization signal and the first CDR clock signal. The data sampleroperates to: receive the equalization signal at its first input; receive the sampling clock signal at its second input; and provide data sample results at its outputresponsive to the equalization signal and the sampling clock signal. The first deserializeroperates to: receive the error samples from the error sampler; and provide deserialized error samples at its outputresponsive to the received error samples. The second deserializeroperates to: receive data samples from the data sampler; and provide deserialized data sample at its outputresponsive to the received data samples.

326 318 322 331 332 The digital equalizer adaptation circuitoperates to: receive deserialized error samples from the first deserializer; receive deserialized data samples from the second deserializer; provide CTLE index results at the first outputresponsive to the deserialized error samples and the deserialized data samples; and provide one or more DFE coefficients at the second outputresponsive to the deserialized error samples and the deserialized data samples.

334 326 335 336 334 334 334 6 FIG. 3 5 FIGS.- In some examples, the clock adjustment controlleroperates to: receive the CTLE index results from the digital equalizer adaptation circuitat its input; and provide a clock adjustment control signal at its outputresponsive to the CTLE index results. In some examples, the clock adjustment controllerincludes a processor and a memory. In such examples, the memory may include a look-up table (LUT) to provide a delay code as the clock adjustment control signal responsive to the CTLE index results. In some examples, the clock adjustment controllermaps the delay code to the CTLE index which could be directly outputted in analog domain using an analog adaptation scheme. As another option, the clock adjustment controlleruses a phase-interpolator (PI). This options lends itself to PI-based CDR circuitry as ininstead of VCO-based CDR circuitry as in.

326 318 322 In some examples, the digital equalizer adaptation circuitand the deserializersandmay be replaced by analog equalizer adaptation circuitry using filters and rectifiers. In such examples, the CTLE input and DFE coefficients could be controlled through a control voltage or current instead of digital coefficients. As an option, analog equalizer adaptation circuitry can be followed by an analog-to-digital conversion (ADC) if digital control signals are desired.

382 384 385 386 388 390 391 392 382 388 382 388 3 4 FIGS.and The first delay circuitoperates to: receive the first CDR clock signal at its first input; receive the clock adjustment control signal at its second input; and provide a delayed version of the first CDR clock signal at its outputresponsive to the first CDR clock signal and the clock adjustment control signal. The second delay circuitoperates to: receive the second CDR clock signal at its first input; receive the clock adjustment control signal at its second input; and provide a delayed version of the second CDR clock signal at its outputresponsive to the second CDR clock signal and the clock adjustment control signal. In different examples, delay circuits such as the first delay circuitand the second delay circuitmay be a digital controlled delay circuit or an analog controlled delay circuit.implement the first delay circuitand the second delay circuitas digital controlled delay circuits. For analog controlled delay circuits, a control voltage or current may be used to adjust the delay.

334 162 In some examples, the clock adjustment controllermay include a LUT, a digital-to-analog converter (DAC), a current source, and/or other circuitry to provide a clock adjustment control signal for digital controlled delay circuits or analog controlled delay circuits of clock adjustment circuitry such as the clock adjustment circuitryA.

334 334 0 0 −1 −1 −1 0 In some examples, the clock adjustment controlleradjusts clock(s) such that the sampling clock signal is shifted to the left relative to the CDR clock. This results in an insignificant change in the main cursor term (i.e., c′≈c) due the flat region in the pulse response around the peak. The offset between the sampling clock signal and the CDR clock results in a significant change in the pre-cursor ISI term (i.e., c′<<c) and lowers the pre-cursor ISI between the current bit and previous bit. In some examples, the clock adjustment controllerused CTLE index results to control the offset between the sampling clock signal and the CDR clock signal as the CTLE index provides an indication of the channel loss and hence the shape of the pulse response. As the length of the channel increases, the pre-cursor ISI ratio c/cincreases. Accordingly, in some examples, the amount of offset between the sampling clock signal and the CDR clock signal is increased as the channel length increases. Without limitation, the relationship between the CTLE index and offset between the sampling clock signal and the CDR clock signal may be defined using an LUT.

4 FIG. 3 FIG. 4 FIG. 3 FIG. 4 FIG. 3 FIG. 4 FIG. 4 FIG. 400 306 302 310 374 378 318 322 326 334 338 344 348 352 360 368 370 400 400 300 162 334 416 162 In the example of, the receiverincludes the CTLE circuit, the combine circuit, the DFE circuit, the error sampler, the data sampler, the first deserializer, the second deserializer, the digital equalizer adaptation circuit, the clock adjustment controller, the PFD, the frequency detector charge pump, the phase detector charge pump, the loop filter, the VCO, the VCO regulator, and the dividerdescribed in. While not specifically shown in, respective components of the receivermay be part of equalizer circuitry, CDR circuitry, sampler circuitry, adaptation circuitry, and clock adjustment circuitry as described in. The difference between the receiverofand the receiverofis that the clock adjustment circuitryB inincludes delay circuits for the CDR clock signals and for the sampling clock signal. In other words, both the CDR clock signals and the sample clock signal may be delayed. To support flexible delay options, the clock adjustment controllerinmay have a second outputto provide a second clock adjustment control signal for the clock adjustment circuitryB.

4 FIG. 3 FIG. 1 FIG. 3 FIG. 162 164 166 168 170 170 162 404 172 172 172 162 382 388 408 408 410 412 414 410 408 166 162 412 408 404 162 414 162 172 162 404 416 334 As shown in, the clock adjustment circuitryB has the first input, the second input, the third input, the first outputA, and the second outputB described in. In addition, the clock adjustment circuitryB has a fourth inputand a third outputA. The third outputA is an example of the second outputin. In some examples, the clock adjustment circuitryB includes the first delay circuitand the second delay circuitdescribed inas well as a third delay circuit. The third delay circuithas a first input, a second input, and an output. The first inputof the third delay circuitis coupled to the second inputof the clock adjustment circuitryB. The second inputof the third delay circuitis coupled to the fourth inputof the clock adjustment circuitryB. The outputof the clock adjustment circuitryB is coupled to the third outputA of the clock adjustment circuitryB. In some examples, the fourth inputis coupled to the second outputof the clock adjustment controller.

382 388 338 408 410 412 414 382 388 408 408 408 162 3 FIG. 3 FIG. In some examples, the first delay circuitand the second delay circuitprovide delayed first and second CDR clock signals to the PFDas in. However, the third delay circuitoperates to: receive the first CDR clock signal at its first input; receive the second clock adjustment control signal at its second input; and provide a sampling clock signal at its outputresponsive to the first CDR clock signal and the second clock adjustment control signal. To mitigate pre-cursor ISI as described herein, the delay of the first delay circuitand the second delay circuitis greater than the delay of the third delay circuit. In some examples, the delay of the third delay circuitis fixed. In some examples, the delay of the third delay circuitis set to a minimum delay option. With the clock adjustment circuitryB and related control options, the offset between the CDR clock signal and the sampling clock signal can be smaller or more fine-tuned compared to an offset based only on CTLE index results as in. As needed, the offset between the CDR clock signal and the sampling clock signal can be reduced to zero.

5 FIG. 3 FIG. 5 FIG. 3 FIG. 5 FIG. 3 FIG. 5 FIG. 500 306 302 310 374 378 318 322 326 334 338 344 348 352 360 368 370 500 500 300 162 500 510 336 334 162 In the example of, the receiverincludes the CTLE circuit, the combine circuit, the DFE circuit, the error sampler, the data sampler, the first deserializer, the second deserializer, the digital equalizer adaptation circuit, the clock adjustment controller, the PFD, the frequency detector charge pump, the phase detector charge pump, the loop filter, the VCO, the VCO regulator, and the dividerdescribed in. While not specifically shown in, respective components of the receivermay be part of equalizer circuitry, CDR circuitry, sampler circuitry, adaptation circuitry, and clock adjustment circuitry as described in. The difference between the receiverofand the receiverofis that the clock adjustment circuitryC inadjusts a phase of the sampling clock signal so that CDR clock signal is delayed relative to the sampling clock signal. Also, the receiverincludes a DACbetween the outputof the clock adjustment controllerand the clock adjustment circuitryC.

5 FIG. 510 512 514 162 501 502 509 162 503 504 506 508 As shown in, the DAChas an inputand an output. The clock adjustment circuitryC has a first input, a second input, and an output. The clock adjustment circuitryC includes a combine circuithaving a first input, a second input, and an output.

512 510 336 334 514 510 502 162 501 162 372 370 504 503 501 162 506 503 502 162 508 503 509 162 509 162 374 378 310 In some examples, the inputof the DACis coupled to the outputof the clock adjustment controller. The outputof the DACis coupled to the second inputof the clock adjustment circuitryC. The first inputof the clock adjustment circuitryC is coupled to one of the outputsof the divider. The first inputof the combine circuitis coupled to the first inputof the clock adjustment circuitryC. The second inputof the combine circuitis coupled to the second inputof the clock adjustment circuitryC. The outputof the combine circuitis coupled to the outputof the clock adjustment circuitryC. As shown, the outputof the clock adjustment circuitryC is coupled to respective inputs of the error sampler, the data sampler, and the DFE circuit.

510 334 512 514 503 504 506 508 162 OS CK OS CK OS CK OS CK CK OS CK CK OS CK 3 4 FIGS.and In some examples, the DACoperates to: receive a control signal from the clock adjustment controllerat its input; and provide an offset voltage (V) at its outputresponsive to the control signal. In some examples, the combine circuitoperates to: receive a second CDR clock signal (V) at its first input; receive Vat its second input; and provide V+Vat its outputresponsive to Vand V. Relative to the phase of V, the phase of V+Vis shifted to the left such that the on-time of Vis delayed relative to the on-time of V+V. In some examples, Vis the same as I clock in. With the clock adjustment circuitryC, pre-cursor ISI is mitigated as described herein.

334 334 0 0 −1 −1 −1 0 In some examples, the clock adjustment controlleradjusts clock(s) such that the sampling clock signal is shifted to the left relative to the CDR clock signal. This results in an insignificant change in the main cursor term (i.e., c′≈c) due the flat region in the pulse response around the peak. The offset between the sampling clock signal and the CDR clock signal results in a significant change in the pre-cursor ISI term (i.e., c′<<c) and lowers the pre-cursor ISI between the current bit and previous bit. In some examples, the clock adjustment controllerused CTLE index results to control the offset between the sampling clock signal and the CDR clock signal as the CTLE index provides an indication of the channel loss and hence the shape of the pulse response. As the length of the channel increases, the pre-cursor ISI ratio c/cincreases. Accordingly, in some examples, the amount of offset between the sampling clock signal and the CDR clock signal is increased as the channel length increases. Without limitation, the relationship between the CTLE index and offset between the sampling clock signal and the CDR clock signal is defined using an LUT.

6 FIG. 3 FIG. 6 FIG. 3 FIG. 6 FIG. 3 FIG. 600 306 302 310 374 378 318 322 326 334 338 344 348 352 360 370 600 600 300 600 602 612 162 In the example of, the receiverincludes the CTLE circuit, the combine circuit, the DFE circuit, the error sampler, the data sampler, the first deserializer, the second deserializer, the digital equalizer adaptation circuit, the clock adjustment controller, the PFD, the charge pumpsand, the loop filter, the VCO, and the dividerdescribed in. While not specifically shown in, respective components of the receivermay be part of equalizer circuitry, CDR circuitry, sampler circuitry, adaptation circuitry, and clock adjustment circuitry as described in. The difference between the receiverofand the receiverofis that the receiveralso uses a reference clock source, PI-based CDR circuitry, and PI-based clock adjustment circuitryD.

602 338 602 600 612 606 In some examples, the reference clock sourceprovides a reference clock signal to the PFD circuit. For example, the reference clock sourceis a crystal oscillator or a microelectromechanical system (MEMS)-based oscillator that operates to provide the reference clock signal. The reference clock signal may have a frequency of 25 MHz, 100 MHz, or another frequency. For receivers with a reference clock source such as the receiver, the CDR circuitry may include PI-based CDR circuitryand a phase-locked loop (PLL).

6 FIG. 338 344 348 352 360 370 606 612 618 626 634 374 378 310 606 600 162 In the example of, the PFD circuit, the charge pumpsand, the loop filter, the VCO, and the dividerare components of the PLL. The PI-based CDR circuitryincludes a phase detector circuit, a finite state machine (FSM), and a first PI circuit. To adjust the sampling clock signal provided to the error sampler, the data sampler, and the DFE circuitrelative to the CDR clock signal provided from the PLL, the receiveruses the PI-based clock adjustment circuitryD.

6 FIG. 602 604 606 608 610 612 614 615 616 618 620 622 624 626 628 630 632 634 636 637 638 In the example of, the reference clock sourcehas an output. The PLLhas an inputand an output. The PI-based CDR circuitryhas a first input, a second input, and an output. The phase detector circuithas a first input, a second input, and an output. The FSMhas a first input, a second input, and an output. The first PI circuithas a first input, a second input, and an output.

6 FIG. 162 640 642 644 162 648 656 656 648 650 652 654 656 658 660 662 162 162 In the example of, the PI-based clock adjustment circuitryD has a first input, a second input, a third input, and an output. The PI-based clock adjustment circuitryD includes a second PI circuitand a combine circuit. In some examples, the combine circuitis a digital adder. The second PI circuithas a first input, a second input, and an output. The combine circuithas a first input, a second input, and an output. The clock adjustment circuitryD is an example of the clock adjustment circuitry.

604 602 608 606 339 338 608 606 610 606 615 612 610 606 360 360 614 612 305 302 616 612 642 162 640 162 610 606 644 162 336 334 646 162 374 378 310 6 FIG. As illustrated, the outputof the reference clock sourceis coupled to the inputof the PLL. A first input (e.g., the first inputA) of the PFD circuitis coupled to the inputof the PLL. The outputof the PLLis coupled to the second inputof the PI-based CDR circuitry. As shown, the outputof the PLLis coupled to the output of the VCO. In some examples, the output of the VCOrepresented inis a Q clock signal output. The first inputof the PI-based CDR circuitryis coupled to the outputof the combine circuit. The outputof the PI-based CDR circuitryis coupled to the second inputof the PI-based clock adjustment circuitryD. The first inputof the PI-based clock adjustment circuitryD is coupled to the outputof the PLL. The third inputof the PI-based clock adjustment circuitryD is coupled to the outputof the clock adjustment controller. The outputof the PI-based clock adjustment circuitryD is coupled to and provides an adjusted clock signal to the error sampler, the data sampler, and the DFE circuit.

650 648 662 656 652 648 640 162 654 646 162 658 642 162 660 656 644 162 In some examples, the first inputof the second PI circuitis coupled to the outputof the combine circuit. The second inputof the second PI circuitis coupled to the first inputof the PI-based clock adjustment circuitryD. The output of the second PI circuitis coupled to the outputof the PI-based clock adjustment circuitryD. The first inputof the combine circuit is coupled to the second inputof the PI-based clock adjustment circuitryD. The second inputof the combine circuitis coupled to the third inputof the PI-based clock adjustment circuitryD.

620 618 614 612 622 618 638 634 618 628 626 630 626 638 634 632 626 636 634 616 612 637 634 615 612 As illustrated, the first inputof the phase detector circuitis coupled first inputof the PI-based CDR circuitry. The second inputof the phase detector circuitis coupled to the outputof the first PI circuit. The output of the phase detector circuitis coupled to is coupled to the first inputof the FSM. The second inputof the FSMis coupled to the outputof the first PI circuit. The outputof the FSMis coupled to the first inputof the first PI circuitand to the outputof the PI-based CDR circuitry. The second inputof the first PI circuitis coupled to the second inputof the PI-based CDR circuitry.

606 648 302 612 618 618 626 634 626 606 In operation, the CDR clock signal at the output of the PLLis provided to the second PI circuitto adjust the phase of the sampling clock signal to align with the equalization results (e.g., the equalized data) provided by the combine circuit. The PI-based CDR circuitryoperates to: compare the phases of the equalization results and a PI-based clock signal using the phase detector circuit; process the output of the phase detector circuitand provide a resulting control code using the FSM; and provide the PI-based clock signal using the first PI circuitresponsive to the control code from the FSMand the CDR clock signal from the PLL. In this example, the CDR clock signal is a PLL-based clock signal.

618 620 634 622 624 626 618 628 634 630 632 634 626 636 606 637 638 The phase detector circuitoperates to: receive the equalization results at its first input; receive the PI-based clock signal from the first PI circuitat its second input; and provide comparison results at its outputresponsive to the equalization results and the PI-based clock signal. The FSMoperates to: receive the comparison results from the phase detector circuitat its first input; receive the PI-based clock signal from the first PI circuitat its second input; and provide the control code at its outputresponsive to the comparison results and the PI-based clock signal. The first PI circuitoperates to: receive the control code from the FSMat its first input; receive a PLL-based clock signal from the PLLat its second input; and provide the PI-based clock signal at its outputresponsive to the control code and the PLL-based clock signal.

6 FIG. 634 648 656 634 648 In the example of, the phase shift between CDR clock signal and sampling clock signal is controlled by offsetting the control codes used for the first PI circuitand the second PI circuit. For example, if the LUT delay code is k, and the first PI circuit code is M, then the combine circuitprovides the second PI circuit code (M-k). The offset control codes for the first PI circuitand the second PI circuitresult in the sampler clock signal phase being shifted to the left relative to the CDR clock signal phase corresponding to the delay offset code of -k.

334 334 0 0 −1 −1 −1 0 In some examples, the clock adjustment controlleradjusts clock(s) such that the sampling clock signal is shifted to the left relative to the CDR clock signal. This results in an insignificant change in the main cursor term (i.e., c′≈c) due the flat region in the pulse response around the peak. The offset between the sampling clock signal and the CDR clock signal results in a significant change in the pre-cursor ISI term (i.e., c′<<c) and lowers the pre-cursor ISI between the current bit and previous bit. In some examples, the clock adjustment controllerused CTLE index results to control the offset between the sampling clock signal and the CDR clock signal as the CTLE index provides an indication of the channel loss and hence the shape of the pulse response. As the length of the channel increases, the pre-cursor ISI ratio c/cincreases. Accordingly, in some examples, the amount of offset between the sampling clock signal and the CDR clock signal is increased as the channel length increases. Without limitation, the relationship between the CTLE index and offset between the sampling clock signal and the CDR clock signal may be defined using an LUT.

7 FIG. 5 FIG. 5 FIG. 3 4 FIGS.and 6 FIG. 700 700 704 702 702 704 702 704 702 500 700 CK CK OS CK OS CK OS CK OS CK CK OS CK is a graphshowing an example sampling clock signal adjustment. In graph, a Vsignaland a V+Vsignalare represented. As shown, V+Vsignalhas a similar shape compared to the Vsignalbut has a higher voltage level due to V. Accordingly, the phase of V+Vsignalis shifted to the left compared to Vsignal. In other words, the V+Vsignalcrosses zero before the Vsignal crosses zero. The receiverofuses the sampling clock signal adjustment strategy represented in graphto delay the CDR clock signal relative to the sampling clock signal and mitigate pre-cursor ISI. As desired, adding a voltage offset to a CDR clock signal (as in) may be combined with delay circuitry (as in), and/or phase interpolator adjustment (as in).

8 a FIG. 8 8 b c FIGS.and 800 810 820 shows an example eye diagramwithout clock adjustment of a signal output from a DFE summation node (e.g., the output from a combine circuit, which is coupled to a DFE circuit). Without clock adjustment, the eye size may be smaller than desired indicating higher likelihood of ISI issues such as pre-cursor ISI. By contrast,show example eye diagramsandin which the CDR clock signal is delayed relative to the sampling clock signal consistent with described examples.

8 b FIG. 8 b FIG. 8 a FIG. 302 310 810 800 In the example of, the signal is output from a DFE summation node (e.g. output from the combine circuit, which is coupled to the DFE circuit), and the sampling clock signal is offset from the CDR clock signal by 5 ps. As shown, the eye size in the eye diagramofis larger than the eye size in the eye diagramof. The increase in eye size indicates the mitigation of ISI issues such as pre-cursor ISI.

8 c FIG. 8 c FIG. 820 In the example of, the eye diagram is of a signal at the input of the sampler circuit, and the sampling clock signal is offset from the CDR clock signal by about 0.1 unit interval (UI). In different examples, the amount of offset between the sampling clock signal and the CDR clock signal may vary. With the offset, the sampling clock signal is better aligned with the center of the eye in the eye diagramof. Adjusting the sampling clock signal relative to the CDR clock signal mitigates ISI issues such as pre-cursor ISI.

9 FIG. 3 4 FIGS.and 3 4 FIGS.and 4 FIG. 9 FIG. 900 900 382 388 408 900 902 924 926 928 930 932 900 1 6 1 6 904 910 918 1 6 1 6 904 906 908 910 912 916 914 918 920 922 DD in in out out is a schematic diagram showing an example delay circuit. The delay circuitis an example of the first delay circuitin, the second delay circuitin, or the third delay circuitin. As shown, the delay circuithas a power supply (V) terminal, a first input voltage (V) terminal, a second Vterminal, a first output voltage (V) terminal, a second Vterminal, and a ground terminal. The delay circuitincludes resistors Rto R, transistors Tto T, a first current source, a second current source, and a third current sourcein the arrangement shown. In the example of, each of the resistors Rto Rhas a first terminal and second terminal. Each of transistors Tto Thas a first terminal, a second terminal, and a control terminal. The first current sourcehas a first terminaland a second terminal. The second current sourcehas a first terminal, a second terminal, and a control terminal. The third current sourcehas a first terminaland a second terminal.

1 902 1 1 3 4 5 5 1 924 1 906 904 908 904 932 2 902 2 2 4 3 6 6 2 926 2 906 904 3 4 912 910 916 910 932 914 910 DD in DD in In some examples, the first terminal of resistor Ris coupled to the Vterminal. The second terminal of the resistor Ris coupled to the first terminals of the transistors Tand T, the control terminals of the transistors Tand T, and the first terminal of resistor R. The control terminal of the transistor Tis coupled to the first Vterminal. The second terminal of transistor Tis coupled to the first terminalof the first current source. The second terminalof the first current sourceis coupled to the ground terminal. The first terminal of the resistor Ris coupled to the Vterminal. The second terminal of the resistor Ris coupled to the first terminals of the transistors Tand T, the control terminals of the transistors Tand T, and the first terminal of the resistor R. The control terminal of the transistor Tis coupled to the second Vterminal. The second terminal of transistor Tis coupled to the first terminalof the first current source. The second terminals of the transistors Tand Tare coupled to the first terminalof the second current source. The second terminalof the second current sourceis coupled to the ground terminal. The control terminalof the second current sourcereceive a delay control signal such as the clock adjustment control signal described herein.

3 902 3 5 5 928 5 920 918 922 918 932 4 902 4 6 6 930 6 920 918 DD out DD out The first terminal of the resistor Ris coupled to the Vterminal. The second terminal of the resistor Ris coupled to the second terminal of the resistor R, the first terminal of the transistor T, and the first Vterminal. The second terminal of the transistor Tis coupled to the first terminalof the third current source. The second terminalof the third current sourceis coupled to the ground terminal. The first terminal of the resistor Ris coupled to the Vterminal. The second terminal of the resistor Ris coupled to the second terminal of the resistor R, the first terminal of the transistor T, and the second Vterminal. The second terminal of the transistor Tis coupled to the first terminalof the third current source.

900 924 926 914 910 928 930 900 1 6 900 900 in in out out in out in out in The delay circuitoperates to: receive Vas the voltage across the first and second Vterminalsand; receive the delay control signal at the control terminalof the second current source; and provide Vas the voltage across the first and second Vterminalsandresponsive to Vand the delay control signal. With the delay circuit, Vfollows Vwith some delay. In some examples, Vmay have a different current level relative to V. In some examples, the transistors T-Tof the delay circuitmay be implemented as NPN bipolar transistors as shown or as n-channel metal-oxide semiconductor (NMOS) transistors. In other examples, a delay circuit may use PNP bipolar transistors or p-channel metal-oxide semiconductor (PMOS) transistors and a flipped topology relative to the delay circuit.

10 FIG. 1 FIG. 1000 1000 112 1000 1002 1004 1006 1008 1010 is a flowchart showing an example method. The methodis performed, for example, by a receiver such as receiverof. As shown, the methodincludes receiving data via a channel at block. At block, equalization operations are performed on the received data, the equalization operations resulting in equalization results. At block, sampling operations are performed responsive to the equalization results, the sampling operations resulting in data samples and error samples. At block, adaptation operations are performed responsive to the data samples and the error samples, the adaptation operations resulting in a clock adjustment control signal. At block, a sampling clock signal is adjusted relative to a CDR clock signal responsive to the clock adjustment control signal.

1010 1010 1010 In some examples, adjusting the sampling clock signal relative to the CDR clock signal responsive to the clock adjustment control signal in blockincludes delaying the CDR clock signal relative to the sampling clock signal responsive to the clock adjustment control signal. In some examples, adjusting the sampling clock signal relative to the CDR clock signal responsive to the clock adjustment control signal in blockincludes adjusting a voltage of the sampling clock signal relative to a voltage of the CDR clock signal responsive to the clock adjustment control signal. In some examples, adjusting the sampling clock signal relative to the CDR clock signal responsive to the clock adjustment control signal in blockincludes adjusting a phase of the sampling clock signal relative to a phase the CDR clock signal responsive to the clock adjustment control signal.

112 114 116 118 120 122 124 126 140 142 144 146 148 372 370 610 606 142 126 150 152 154 156 158 160 152 126 154 156 148 128 130 132 134 136 138 130 132 158 160 134 122 136 124 162 166 168 164 170 172 166 168 146 148 164 138 In some examples, a receiver (e.g., the receiveror variants herein) includes equalizer circuitry (e.g., the equalizer circuitryor variants herein) having a first input (e.g., the first inputor variants herein), a second input (e.g., the second inputor variants herein), a third input (e.g., the third inputor variants herein), a fourth input (e.g., the fourth inputor variants herein), a fifth input (e.g., the fifth inputor variants herein), and an output (e.g., the outputor variants herein). The receiver also includes CDR circuitry (e.g., the CDR circuitryor variants herein) having a first input (e.g., the first inputor variants herein), a second input (e.g., the second inputor variants herein), and a clock output (e.g., the first output, the second output, the outputsof the divider, the outputof the PLL, or variants herein). The first input (e.g., the first inputor variants herein) of the CDR circuitry is coupled to the output (e.g., the outputor variants herein) of the equalizer circuitry. The receiver also includes sampler circuitry (e.g., the sampler circuitryor variants herein) having a first input (e.g., the first inputor variants herein), a second input (e.g., the second input, the third input, or variants herein), and an output (e.g., the first output, the second output, or variants herein). The first input (e.g., the first inputor variants herein) of the sampler circuitry is coupled to the output (e.g., the outputor variants herein) of the equalizer circuitry. The second input (e.g., the second input, the third input, or variants herein) of the sampler circuitry coupled to the clock output (e.g., the clock outputor variants herein) of the CDR circuitry. The receiver also includes adaptation circuitry (e.g., the adaptation circuitor variants herein) having an input (e.g., the first input, the second input, or variants herein), a first output (e.g., the first outputor variants herein), a second output (the second outputor variants herein), and a third output (e.g., the third outputor variants herein). The input (e.g., the first input, the second input, or variants herein) of the adaptation circuitry is coupled to the output (e.g., the first output, the second output, or variants herein) of the sampler circuitry. The first output (e.g., the first outputor variants herein) of the adaptation circuitry is coupled to the fourth input (e.g., the fourth inputor variants herein) of the equalizer circuitry. The second output (e.g., the second outputor variants herein) of the adaptation circuitry is coupled to the fifth input (e.g., the fifth inputor variants herein) of the equalizer circuitry. The receiver also includes clock adjustment circuitry (e.g., the clock adjustment circuitryor variants herein) having a first input (e.g., the second input, the third input, or variants herein), a second input (e.g., the first inputor variants herein), and an output (e.g., the first output, the second output, or variants herein). The first input (e.g., the second input, the third input, or variants herein) of the clock adjustment circuitry is coupled to the clock output (e.g., the first output, the second output, or variants herein) of the CDR circuitry. The second input (e.g., the first inputor variants herein) of the clock adjustment circuitry is coupled to the third output (e.g., the third outputor variants herein) of the adaptation circuitry.

170 144 382 388 384 390 385 391 386 392 384 390 166 168 385 391 164 386 392 170 In some examples, the output (e.g., the first outputor variants herein) of the clock adjustment circuitry is coupled to the second input (e.g., the second inputor variants herein) of the CDR circuitry. In some examples, the clock adjustment circuitry includes a delay circuit (e.g., the first delay circuitor the second delay circuitherein) having an input (e.g., the inputor the inputherein), a control input (the control inputor the control inputherein), and an output (e.g., the outputor the outputherein). The input (e.g., the inputor the inputherein) of the delay circuit is coupled to the first input (e.g., the second input, the third input, or variants herein) of the clock adjustment circuitry. The control input (e.g., the control inputor the control inputherein) of the delay circuit is coupled to the second input (e.g., the first inputor variants herein) of the clock adjustment circuitry. The output (e.g., the outputor the outputherein) of the delay circuit is coupled to the output (e.g., the first outputor variants herein) of the clock adjustment circuitry.

170 172 156 382 388 408 410 412 414 410 168 414 172 In some examples, the output (e.g., the first outputor variants herein) of the clock adjustment circuitry is a first output of clock adjustment circuitry, the clock adjustment circuitry has a second output (e.g., the second outputor variants herein) coupled to the second input (e.g., the third inputor variants herein) of the sampler circuitry, the delay circuit (e.g., the first delay circuitor the second delay circuitherein) is a first delay circuit, and the clock adjustment circuitry includes a second delay circuit (e.g., the delay circuitherein) having an input (e.g., the inputherein), a control input (e.g., the control inputherein), and an output (e.g., the outputherein). The input (e.g., the inputherein) of the second delay circuit is coupled to the first input (e.g., the third inputherein) of the clock adjustment circuitry. The output (e.g., the outputherein) of the second delay circuit is coupled to the second output (e.g., the second outputor variants herein) of the clock adjustment circuitry.

172 154 156 382 388 388 146 148 408 148 In some examples, the output (e.g., the second outputor variants herein) of the clock adjustment circuitry is coupled to the second input (e.g., the second input, the third input, variants herein) of the sampler circuitry. In some examples, the clock adjustment circuitry includes a first delay circuit (e.g., the first delay circuitor the second delay circuitherein) and a second delay circuit (e.g., the third delay circuitherein). The first delay circuit is configured to provide a CDR clock signal (e.g., delayed versions of the I or Q clocks herein) based on a clock signal (e.g., the I or Q clocks herein) at the clock output (e.g., the first outputor the second outputherein). The second delay circuit (e.g., the third delay circuitherein) is configured to provide a sampling clock signal (e.g., a delayed version of the I clock herein) based on the clock signal (e.g., the I clock herein) at the clock output (e.g., the second outputherein). The CDR clock signal is delayed more than the sampling clock signal relative to the clock signal at the clock output.

503 504 506 508 503 148 CK OS CK OS In some examples, the clock adjustment circuitry includes a combine circuit (e.g., the combine circuitherein) having a first input (e.g., the first inputherein), a second input (e.g., the second inputherein), and an output (e.g., the outputherein). The combine circuit (e.g., the combine circuitherein) is configured to: receive a clock signal (e.g., the I clock or Vherein) from the clock output (e.g., the second outputherein) at its first input; receive an offset voltage (e.g., Vherein) at its second input; and provide a sampling clock signal (e.g., V+V) at its output responsive to the clock signal and the offset voltage.

648 652 650 654 648 610 606 652 650 654 In some examples, the clock adjustment circuitry includes a PI circuit (e.g., the second PI circuitherein) having a first input (e.g., the second inputherein), a second input (e.g., the first inputherein), and an output (e.g., the outputherein). The PI circuit (e.g., the second PI circuitherein) is configured to: receive a clock signal from the clock output (e.g., the clock signal at the outputof the PLLherein) at its first input (e.g., the second inputherein); receive a control code at its second input (e.g., the first inputherein); and provide a sampling clock signal at its output (e.g., the outputherein) responsive to the clock signal and the control code.

634 648 656 658 660 662 658 660 662 In some examples, the CDR circuitry includes a first PI circuit (e.g., the first PI circuitherein), the PI circuit of the clock adjustment circuitry is a second PI circuitry (e.g., the second PI circuitherein), and the clock adjustment circuitry includes a combine circuit (e.g., the combine circuitherein) having a first input (e.g., the first inputherein), a second input (e.g., the second inputherein), and an output (e.g., the outputherein). The combine circuit is configured to: receive a first control code related to the first PI circuit at its first input (e.g., the first inputherein); receive an offset at its second input (e.g., the second inputherein); and provide the control code for the second PI circuitry at its output (e.g., the outputherein) responsive to the first control code and the offset.

128 334 335 336 416 334 334 510 In some examples, the adaptation circuitry (e.g., the adaptation circuitryor variants herein) includes a clock adjustment controller (e.g., the clock adjustment controllerherein) having an input (e.g., the inputherein) and an output (e.g., the outputor the outputherein). The clock adjustment controller (e.g., the clock adjustment controllerherein) is configured to: receive a CTLE index result; and provide a clock adjustment control signal to the clock adjustment circuitry responsive to the CTLE index result. In some examples, the clock adjustment controller (e.g., the clock adjustment controllerherein) uses an LUT to provide the clock adjustment control signal responsive to the CTLE index result. In some examples, the clock adjustment controller uses a DAC (e.g., the DACherein) to provide the clock adjustment control signal responsive to the CTLE index result.

102 112 106 114 116 118 120 122 124 126 140 142 144 146 148 372 370 610 606 142 126 150 152 154 156 158 160 152 126 154 156 148 128 130 132 134 136 138 130 132 158 160 134 122 136 124 162 166 168 164 170 172 166 168 146 148 164 138 In some examples, a system includes: a transmitter (e.g., the transmitterherein); and a receiver (e.g., the receiveror variants herein) in communication with the transmitter via a channel (e.g., the channelherein). The receiver includes equalizer circuitry (e.g., the equalizer circuitryor variants herein) having a first input (e.g., the first inputor variants herein), a second input (e.g., the second inputor variants herein), a third input (e.g., the third inputor variants herein), a fourth input (e.g., the fourth inputor variants herein), a fifth input (e.g., the fifth inputor variants herein), and an output (e.g., the outputor variants herein). The receiver also includes CDR circuitry (e.g., the CDR circuitryor variants herein) having a first input (e.g., the first inputor variants herein), a second input (e.g., the second inputor variants herein), and a clock output (e.g., the first output, the second output, the outputsof the divider, the outputof the PLL, or variants herein). The first input (e.g., the first inputor variants herein) of the CDR circuitry is coupled to the output (e.g., the outputor variants herein) of the equalizer circuitry. The receiver also includes sampler circuitry (e.g., the sampler circuitryor variants herein) having a first input (e.g., the first inputor variants herein), a second input (e.g., the second input, the third input, or variants herein), and an output (e.g., the first output, the second output, or variants herein). The first input (e.g., the first inputor variants herein) of the sampler circuitry is coupled to the output (e.g., the outputor variants herein) of the equalizer circuitry. The second input (e.g., the second input, the third input, or variants herein) of the sampler circuitry coupled to the clock output (e.g., the clock outputor variants herein) of the CDR circuitry. The receiver also includes adaptation circuitry (e.g., the adaptation circuitor variants herein) having an input (e.g., the first input, the second input, or variants herein), a first output (e.g., the first outputor variants herein), a second output (the second outputor variants herein), and a third output (e.g., the third outputor variants herein). The input (e.g., the first input, the second input, or variants herein) of the adaptation circuitry is coupled to the output (e.g., the first output, the second output, or variants herein) of the sampler circuitry. The first output (e.g., the first outputor variants herein) of the adaptation circuitry is coupled to the fourth input (e.g., the fourth inputor variants herein) of the equalizer circuitry. The second output (e.g., the second outputor variants herein) of the adaptation circuitry is coupled to the fifth input (e.g., the fifth inputor variants herein) of the equalizer circuitry. The receiver also includes clock adjustment circuitry (e.g., the clock adjustment circuitryor variants herein) having a first input (e.g., the second input, the third input, or variants herein), a second input (e.g., the first inputor variants herein), and an output (e.g., the first output, the second output, or variants herein). The first input (e.g., the second input, the third input, or variants herein) of the clock adjustment circuitry is coupled to the clock output (e.g., the first output, the second output, or variants herein) of the CDR circuitry. The second input (e.g., the first inputor variants herein) of the clock adjustment circuitry is coupled to the third output (e.g., the third outputor variants herein) of the adaptation circuitry.

162 146 148 166 168 164 170 148 501 502 509 610 606 640 642 644 646 CK OS CK OS In some examples, the clock adjustment circuitry (e.g., the clock adjustment circuitor variants herein) is configured to: receive a clock signal (e.g., the I or Q clocks herein) from the clock output (e.g., the first outputor the second outputherein) at its first input (e.g., the second input, the third input, or variants herein); receive a clock adjustment control signal at its second input (e.g., the first inputor variants herein); and provide a delayed version of the clock signal at its output (e.g., the first outputor variants herein) responsive to the clock signal and the clock adjustment control signal. In some examples, the clock adjustment circuitry is configured to: receive a clock signal e.g., the I clock or Vherein) from the clock output (e.g., the second outputherein) at its first input (e.g., the first inputherein); receive a clock adjustment control signal (e.g., Vherein) at its second input (e.g., the second inputherein); and provide a voltage offset version (e.g., V+Vherein) of the clock signal at its output (e.g., the outputherein) responsive to the clock signal and the clock adjustment control signal. In some examples, the clock adjustment circuitry is configured to: receive a clock signal (e.g., the clock signal at the outputof the PLLherein) from the clock output at its first input (e.g., the first inputherein); receive a clock adjustment control signal at its second input (e.g., the second inputor the third inputherein); and provide a phase-shifted version of the clock signal at its output (e.g., the outputherein) responsive to the clock signal and the clock adjustment control signal.

In this description, the term “couple” may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct connection; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

Also, in this description, the recitation “based on” means “based at least in part on.” Therefore, if X is based on Y, then X may be a function of Y and any number of other factors.

A device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or reconfigurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof.

As used herein, the terms “terminal”, “node”, “interconnection”, “pin” and “lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device or other electronics or semiconductor component.

A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by an end-user and/or a third-party.

While the use of particular transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no change to the remaining circuitry. For example, a field effect transistor (“FET”) such as an NFET or a PFET, a bipolar junction transistor (BJT—e.g., NPN transistor or PNP transistor), an insulated gate bipolar transistor (IGBT), and/or a junction field effect transistor (JFET) may be used in place of or in conjunction with the devices described herein. The transistors may be depletion mode devices, drain-extended devices, enhancement mode devices, natural transistors or other types of device structure transistors. Furthermore, the devices may be implemented in/over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN) or a gallium arsenide substrate (GaAs).

References may be made in the claims to a transistor's control terminal and its first and second terminals. In the context of a FET, the control terminal is the gate, and the first and second terminals are the drain and source. In the context of a BJT, the control terminal is the base, and the first and second terminals are the collector and emitter.

References herein to a FET being “ON” means that the conduction channel of the FET is present and drain current may flow through the FET. References herein to a FET being “OFF” means that the conduction channel is not present so drain current does not flow through the FET. An “OFF” FET, however, may have current flowing through the transistor's body-diode.

Circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.

While certain elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit and/or some features illustrated as being internal to the integrated circuit may be incorporated outside of the integrated circuit. As used herein, the term “integrated circuit” means one or more circuits that are: (i) incorporated in/over a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and/or (iv) incorporated in/on the same printed circuit board.

Uses of the phrase “ground” in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. In this description, unless otherwise stated, “about,” “approximately” or “substantially” preceding a parameter means being within +/−10 percent of that parameter or, if the parameter is zero, a reasonable range of values around zero.

Modifications are possible in the described examples, and other examples are possible, within the scope of the claims.