Bonded Structure, Semiconductor Device, and Bonding Method

The present disclosure relates to a bonding structure, a semiconductor device, and a bonding method.

Various configurations have been proposed for a semiconductor device incorporating a semiconductor element. WO2020/085377 discloses an example of a conventional semiconductor device. The semiconductor device disclosed in WO2020/085377 includes a semiconductor element, a conductive member, a support member, and a sealing resin. The semiconductor element is bonded to the obverse surface of the conductive member. A second metal layer containing Ag (silver) is disposed on the reverse surface of the conductive member. A first metal layer containing Ag (silver) is disposed on the support surface of the support member. The conductive member and the support member are bonded together by solid-phase diffusion bonding of the first metal layer and the second metal layer.

The following describes preferred embodiments of the present disclosure in detail with reference to the drawings.

In the present disclosure, the terms such as “first”, “second”, and “third” are used merely as labels and are not intended to impose ordinal requirements on the items to which these terms refer.

In the description of the present disclosure, the expression “An object A is formed in an object B”, and “An object A is formed on an object B” imply the situation where, unless otherwise specifically noted, “the object A is formed directly in or on the object B”, and “the object A is formed in or on the object B, with something else interposed between the object A and the object B”. Likewise, the expression “An object A is disposed in an object B”, and “An object A is disposed on an object B” imply the situation where, unless otherwise specifically noted, “the object A is disposed directly in or on the object B”, and “the object A is disposed in or on the object B, with something else interposed between the object A and the object B”. Further, the expression “An object A is located on an object B” implies the situation where, unless otherwise specifically noted, “the object A is located on the object B, in contact with the object B”, and “the object A is located on the object B, with something else interposed between the object A and the object B”. Still further, the expression “An object A overlaps with an object B as viewed in a certain direction” implies the situation where, unless otherwise specifically noted, “the object A overlaps with the entirety of the object B”, and “the object A overlaps with a part of the object B”. Furthermore, in the description of the present disclosure, the expression “A surface A faces (a first side or a second side) in a direction B” is not limited to the situation where the angle of the surface A to the direction B is 90°and includes the situation where the surface A is inclined with respect to the direction B.

1 16 FIGS.to 1 10 10 2 3 19 29 41 42 43 44 45 48 5 6 8 show a semiconductor device according to a first embodiment of the present disclosure. The semiconductor device Aof the present embodiment includes a plurality of first semiconductor elementsA, a plurality of second semiconductor elementsB, a conductive substrate, a support substrate, bonding membersand, a first terminal, a second terminal, a plurality of third terminals, a fourth terminal, a plurality of control terminals, a control terminal support, a first conductive member, a second conductive member, and a sealing resin.

1 FIG. 2 FIG. 1 FIG. 3 FIG. 2 FIG. 4 FIG. 5 FIG. 4 FIG. 6 FIG. 5 FIG. 7 FIG. 5 FIG. 8 FIG. 9 FIG. 5 FIG. 10 FIG. 5 FIG. 11 12 FIGS.and 10 FIG. 13 FIG. 5 FIG. 14 FIG. 5 FIG. 15 FIG. 5 FIG. 16 FIG. 1 15 FIGS.to 1 8 5 1 8 8 8 5 6 1 8 is a perspective view of a semiconductor device A.is a perspective view corresponding to, from which the sealing resinis omitted.is a perspective view corresponding to, from which the first conductive memberis omitted.is a plan view of the semiconductor device A.is a plan view corresponding to, in which the sealing resinis indicated by imaginary lines.is a partially enlarged view in which a portion ofis enlarged and the sealing resinis omitted.is a plan view corresponding tofrom which the sealing resinand the first conductive memberare omitted and in which the second conductive memberis indicated by imaginary lines.is a bottom view of the semiconductor device A.is a sectional view taken along line IX-IX in.is a sectional view taken along line X-X in.are partially enlarged views in which a portion ofis enlarged.is a sectional view taken along line XIII-XIII in.is a sectional view taken along line XIV-XIV in.is a sectional view taken along line XV-XV in.is a schematic front view for describing the bonding structure of the semiconductor device shown in, in which the sealing resinand the like are omitted.

1 In these figures, the thickness direction of the semiconductor device Ais referred to as the “thickness direction z”. A direction orthogonal to the thickness direction z is referred to as the “first direction x”. The direction orthogonal to the thickness direction z and the first direction x is referred to as the “second direction y”. In the description below, “in plan view” means as viewed in the thickness direction z. The z1 side in the thickness direction z may be referred to as “upper”, and the z2 side in the thickness direction z may be referred to as “lower”.

10 10 1 10 10 10 10 10 10 10 10 10 10 Each of the first semiconductor elementsA and the second semiconductor elementsB is an electronic component as a core for the function of the semiconductor device A, and an example of the “semiconductor element” of the present disclosure. The constituent material of the first semiconductor elementsA and the second semiconductor elementsB is, for example, a semiconductor material mainly composed of SiC (silicon carbide). The semiconductor material is not limited to SiC and may be Si (silicon), GaN (gallium nitride) or C (diamond), for example. Each of the first semiconductor elementsA and the second semiconductor elementsB is a power semiconductor chip having a switching function, such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The first semiconductor elementsA and the second semiconductor elementsB are MOSFETs in the present embodiment, but are not limited to these and may be other transistors such as IGBTs (Insulated Gate Bipolar Transistors). The first semiconductor elementsA and the second semiconductor elementsB are all identical with each other. Each of the first semiconductor elementsA and the second semiconductor elementsB is, for example, an n-channel MOSFET, but may be a p-channel MOSFET.

11 12 FIGS.and 10 10 101 102 10 10 101 102 101 102 As shown in, each of the first semiconductor elementsA and the second semiconductor elementsB has an element obverse surfaceand an element reverse surface. In each of the first semiconductor elementsA and the second semiconductor elementsB, the element obverse surfaceand the element reverse surfaceare spaced apart from each other in the thickness direction z. The element obverse surfacefaces the z1 side in the thickness direction z, and the element reverse surfacefaces the z2 side in the thickness direction z.

1 10 10 10 10 1 10 10 10 10 10 10 10 10 1 7 FIG. In the present embodiment, the semiconductor device Aincludes four first semiconductor elementsA and four second semiconductor elementsB. The number of first semiconductor elementsA and the number of second semiconductor elementsB are not limited to this, and may be changed as appropriate in accordance with the performance required of the semiconductor device A. In the example shown in, four each of the first semiconductor elementsA and the second semiconductor elementsB are provided. The number of first semiconductor elementsA and the number of second semiconductor elementsB may be two, three, or five or more. The number of first semiconductor elementsA and the number of second semiconductor elementsB may be the same or may be different. The number of first semiconductor elementsA and the number of second semiconductor elementsB are determined based on the current capacity of the semiconductor device A.

1 1 10 10 10 10 10 10 The semiconductor device Amay be configured as a half-bridge type switching circuit. In this case, in the semiconductor device A, the second semiconductor elementsB form the upper arm circuit, and the first semiconductor elementsA form the lower arm circuit. In the upper arm circuit, the second semiconductor elementsB are connected in parallel with each other. In the lower arm circuit, the first semiconductor elementsA are connected in parallel with each other. Each second semiconductor elementB and a relevant one of the first semiconductor elementsA are connected in series to form a bridge layer.

7 14 FIGS.and 7 FIG. 10 2 10 10 2 2 19 10 2 102 2 As shown inin particular, each of the first semiconductor elementsA is mounted on the conductive substrate. In the example shown in, the first semiconductor elementsA may be aligned in the second direction y and are spaced apart from each other. Each of the first semiconductor elementsA is conductively bonded to the conductive substrate(the first conductive portionA, described later) via a bonding member. When the first semiconductor elementsA are bonded to the first conductive portionA, the element reverse surfacesface the first conductive portionA.

7 15 FIGS.and 7 FIG. 7 FIG. 10 2 10 10 2 2 19 10 2 102 2 10 10 As shown inin particular, each of the second semiconductor elementsB is mounted on the conductive substrate. In the example shown in, the second semiconductor elementsB may be aligned in the second direction y and are spaced apart from each other. Each of the second semiconductor elementsB is conductively bonded to the conductive substrate(the second conductive portionB, described later) via a bonding member. When the second semiconductor elementsB are bonded to the second conductive portionB, the element reverse surfacesface the second conductive portionB. As understood from, the first semiconductor elementsA and the second semiconductor elementsB overlap with each other as viewed in the first direction x, but these may not overlap with each other.

10 10 11 12 13 15 11 12 13 15 10 10 11 12 13 101 11 12 13 15 102 Each of the first semiconductor elementsA and the second semiconductor elementsB has a first obverse surface electrode, a second obverse surface electrode, a third obverse surface electrode, and a reverse surface electrode. The configurations of the first obverse surface electrode, the second obverse surface electrode, the third obverse surface electrodeand the reverse surface electrodedescribed below are common to the first semiconductor elementsA and the second semiconductor elementsB. The first obverse surface electrode, the second obverse surface electrode, and the third obverse surface electrodeare provided on the element obverse surface. The first obverse surface electrode, the second obverse surface electrode, and the third obverse surface electrodeare insulated from each other by an insulating film, not shown. The reverse surface electrodeis provided on the element reverse surface.

11 10 10 10 10 12 13 15 15 102 15 15 The first obverse surface electrodeis, for example, a gate electrode, through which a drive signal (e.g., gate voltage) for driving the first semiconductor elementA (the second semiconductor elementB) is inputted. In each first semiconductor elementA (each second semiconductor elementB), the second obverse surface electrodeis, for example, a source electrode, through which a source current flows. The third obverse surface electrodeis, for example, a source sense electrode, through which a source current flows. The reverse surface electrodeis, for example, a drain electrode, through which a drain current flows. The reverse surface electrodecovers the entire (or almost entire) element reverse surface. The reverse surface electrodeis formed by Ag (silver) sputtering. The reverse surface electrodemay be formed by Au (gold) sputtering.

10 10 11 15 12 10 10 1 10 10 44 41 42 43 Each of the first semiconductor elementsA (the second semiconductor elementsB) switches between a conducting state and a disconnected state in response to a drive signal (gate voltage) inputted to the first obverse surface electrode(the gate electrode). In the conducting state, a current flows from the reverse surface electrode(the drain electrode) to the second obverse surface electrode(the source electrode). In the disconnected state, this current does not flow. That is, each first semiconductor elementA (each second semiconductor elementB) performs a switching operation. The semiconductor device Auses the switching function of the first semiconductor elementsA and the second semiconductor elementsB to convert the DC voltage inputted between the single fourth terminaland the two, i.e., the first and the second terminalsandinto e.g. AC voltage and outputs the AC voltage from the third terminal.

5 10 FIG.and 1 17 17 As shown inin particular, the semiconductor device Aincludes thermistors. The thermistorsare used as a temperature detection sensor.

2 10 10 2 3 29 2 2 2 2 2 2 2 2 2 2 41 42 43 44 5 6 10 10 2 2 3 29 10 2 19 10 2 19 2 2 2 2 2 2 2 2 9 15 FIGS.to 3 7 9 10 FIGS.,,and The conductive substratesupports the first semiconductor elementsA and the second semiconductor elementsB. The conductive substrateis bonded on the support substratevia the bonding members. The constituent material of the conductive substrateis mainly composed of Cu (copper), for example. The phrase “is mainly composed of” includes the case where components other than the mentioned main component are not contained. Thus, the constituent material of the conductive substratemay be Cu that does not contain other elements, or may be a Cu alloy. The constituent material of the conductive substrateis not limited, and may be mainly composed of other metals. The conductive substrateincludes a first conductive portionA and a second conductive portionB. Each of the first conductive portionA and the second conductive portionB is a plate that is rectangular in plan view. The first conductive portionA and the second conductive portionB, together with the first terminal, the second terminal, the third terminals, the fourth terminal, the first conductive memberand the second conductive memberform a conduction path of a main circuit current to the first semiconductor elementsA and the second semiconductor elementsB. As shown in, each of the first conductive portionA and the second conductive portionB is bonded on the support substratevia a bonding member. Each of the first semiconductor elementsA is bonded to the first conductive portionA via a bonding member. Each of the second semiconductor elementsB is bonded to the second conductive portionB via a bonding member. As shown in, the first conductive portionA and the second conductive portionB are spaced apart from each other in the first direction x. In the example shown in these figures, the first conductive portionA is located on the x1 side in the first direction x from the second conductive portionB. The first conductive portionA and the second conductive portionB overlap with each other as viewed in the first direction x. Each of the first conductive portionA and the second conductive portionB has dimensions of, for example, 15 mm to 25 mm in the first direction x, 30 mm to 40 mm in the second direction y, and 1.0 mm to 5.0 mm (preferably, about 2.0 mm) in the thickness direction z.

2 201 202 201 202 201 202 201 2 2 10 10 201 19 202 2 2 202 3 29 3 201 202 2 9 10 13 15 16 FIGS.,,to, and The conductive substratehas an obverse surfaceand a reverse surface. As shown in, the obverse surfaceand the reverse surfaceare spaced apart from each other in the thickness direction z. The obverse surfacefaces the z1 side in the thickness direction z, and the reverse surfacefaces the z2 side in the thickness direction z. The obverse surfaceis constituted of the upper surface of the first conductive portionA and the upper surface of the second conductive portionB. The fist semiconductor elementsA and the second semiconductor elementsB are bonded to the obverse surfacevia the bonding members. The reverse surfaceis constituted of the lower surface of the first conductive portionA and the lower surface of the second conductive portionB. The reverse surfaceis conductively bonded to the support substratevia the bonding memberssuch that it faces the support substrate. The obverse surfaceand the reverse surfaceof the conductive substrateare not provided with a metal layer such as Ag (silver) plating.

3 2 3 3 31 32 33 The support substratesupports the conductive substrate. The support substratemay be provided by an AMB (Active Metal Brazing) substrate. The support substrateincludes an insulating layer, a first metal layer, and a second metal layer.

31 31 31 The insulating layermay be a ceramic material having excellent thermal conductivity, for example. Examples of such a ceramic material include SiN (silicon nitride). The insulating layeris not limited to a ceramic material and may be a sheet of insulating resin, for example. The insulating layeris, for example, rectangular in plan view.

33 31 33 33 33 33 33 33 33 33 33 2 33 29 33 2 33 29 33 33 32 The second metal layeris formed on the upper surface (the surface facing the z1 side in the thickness direction z) of the insulating layer. The constituent material of the second metal layeris mainly composed of, for example, Cu (copper), and may be Cur or a Cu alloy. The constituent material of the second metal layeris not limited, may be mainly composed of other metals such as Al (aluminum). The second metal layerincludes a first portionA and a second portionB. The first portionA and the second portionB are spaced apart from each other in the first direction x. The first portionA is located on the x1 side in the first direction x from the second portionB. The first conductive portionA is conductively bonded to the first portionA via a bonding memberand supported by the first portionA. The second conductive portionB is conductively bonded to the second portionB via a bonding memberand supported by the second portionB. Each of the first portionA and the second portionB is, for example, rectangular in plan view.

32 31 32 33 302 32 8 32 33 33 3 301 302 301 302 301 302 302 8 33 301 32 302 301 33 33 33 301 2 2 301 29 302 32 302 301 302 3 3 301 302 8 FIG. 9 15 16 FIGS.toand 8 FIG. The first metal layeris formed on the lower surface (the surface facing the z2 side in the thickness direction z) of the insulating layer. The constituent material of the first metal layeris the same as that of the second metal layer. As shown in, the lower surface (the bottom surface, described later) of the first metal layeris exposed from the sealing resin. The first metal layeroverlaps with both the first portionA and the second portionB in plan view. As shown in, the support substratehas a support surfaceand a bottom surface. The support surfaceand the bottom surfaceare spaced apart from each other in the thickness direction z. The support surfacefaces the z1 side in the thickness direction z, and the bottom surfacefaces the z2 side in the thickness direction z. As shown in, the bottom surfaceis exposed from the sealing resin. More specifically, the second metal layerhas the support surface, and the first metal layerhas the bottom surface. The support surfaceis the upper surface of the second metal layerand constituted of the upper surface of the first portionA and the upper surface of the second portionB. The support surfacefaces the conductive substrate, and the conductive substrateis conductively bonded to the support surfacevia the bonding member. The bottom surfaceis the lower surface of the first metal layer. A heat dissipation member such as a heat sink, not shown, can be attached to the bottom surface. The support surfaceand the bottom surfaceof the support substrateare not provided with a metal layer such as Ag (silver) plating. The dimension of the support substratein the thickness direction z (the distance from the support surfaceto the bottom surfacealong the thickness direction z) is, for example, 0.7 mm to 2.0 mm.

19 10 10 2 2 2 10 10 2 2 19 10 10 19 2 2 29 2 2 2 33 33 33 3 2 2 33 33 29 2 2 29 33 33 19 29 The bonding memberis interposed between a semiconductor elementA (a second semiconductor elementB) and the first conductive portionA (the second conductive portionB) of the conductive substrateto conductively bond the first semiconductor elementA (the second semiconductor elementB) and the first conductive portionA (the second conductive portionB). The bonding memberand the first semiconductor elementA (the second semiconductor elementB) are solid-phase bonded, and the bonding memberand the first conductive portionA (the second conductive portionB) are solid-phase bonded. The bonding memberis interposed between the first conductive portionA (the second conductive portionB) of the first conductive substrateand the first portionA (the second portionB) of the second metal layerof the support substrateto conductively bond the first conductive portionA (the second conductive portionB) and the first portionA (the second portionB). The bonding memberand the first conductive portionA (the second conductive portionB) are solid-phase bonded, and the bonding memberand the first portionA (the second conductive portionB) are solid-phase bonded. In the present embodiment, the bonding memberand the bonding memberare metal foils with a thickness dimension (the dimension in the thickness direction z) of about 100 μm.

17 FIG. 19 29 191 192 193 194 195 191 19 29 194 191 194 194 191 194 194 192 194 19 29 192 195 191 195 195 191 195 195 193 195 19 29 193 192 193 19 29 194 195 191 192 194 193 195 19 29 191 192 193 194 195 192 193 a b a a b a As shown in, the bonding memberand the bonding membereach include a body layer, an obverse layer, a reverse layer, and intermediate layersand. The body layeris the main part of the bonding member,, and the constituent material is, for example, Al (aluminum) or an Al alloy. The intermediate layeris disposed in contact with the surface of the body layerthat faces the z1 side in the thickness direction z. The intermediate layerincludes an Ni layerin contact with the body layer, and a Cu layerin contact with the Ni layer. The obverse layeris disposed in contact with the surface of the intermediate layerthat faces the z1 side in the thickness direction z, and is located furthest to the z1 side of the bonding member,. The constituent material of the obverse layeris Ag. The intermediate layeris disposed in contact with the surface of the body layerthat faces the z2 side in the thickness direction z. The intermediate layerincludes an Ni layerin contact with the body layer, and a Cu layerin contact with the Ni layer. The reverse layeris disposed in contact with the surface of the intermediate layerthat faces the z2 side in the thickness direction z, and is located furthest to the z2 side of the bonding member,. The constituent material of the reverse layeris Ag. Thus, the obverse layerand the reverse layer, which are made of Ag, are disposed on opposite ends in the thickness direction z of the bonding member,. The intermediate layersandare formed by plating the body layer, for example. The obverse layeris formed by plating the intermediate layer, for example. The reverse layeris formed by plating the intermediate layer, for example. The method for forming the bonding member,is not limited. The constituent materials of the body layer, the obverse layer, the reverse layer, and the intermediate layersandare not limited. For example, the constituent material of the obverse layerand the reverse layermay be an alloy containing Ag or mainly composed of Au.

19 19 19 19 19 19 19 19 192 10 10 19 193 2 29 29 29 29 29 29 29 29 192 2 29 193 3 a b a b a b a b a b a b a b a b 16 FIG. 16 FIG. The bonding memberhas an obverse surfaceand a reverse surface. As shown in, the obverse surfaceand the reverse surfaceare spaced apart from each other in the thickness direction z. The obverse surfacefaces the z1 side in the thickness direction z, and the reverse surfacefaces the z2 side in the thickness direction z. The obverse surfaceis the surface of the obverse layerthat faces the z1 side in the thickness direction z, and faces the first semiconductor elementA (the second semiconductor elementB). The reverse surfaceis the surface of the reverse layerthat faces the z2 side in the thickness direction z, and faces the conductive substrate. The bonding memberhas an obverse surfaceand a reverse surface. As shown in, the obverse surfaceand the reverse surfaceare spaced apart from each other in the thickness direction z. The obverse surfacefaces the z1 side in the thickness direction z, and the reverse surfacefaces the z2 side in the thickness direction z. The obverse surfaceis the surface of the obverse layerthat faces the z1 side in the thickness direction z, and faces the conductive substrate. The reverse surfaceis the surface of the reverse layerthat faces the z2 side in the thickness direction z, and faces the support substrate.

192 19 19 15 10 10 193 19 19 201 2 2 2 192 29 29 202 2 2 2 193 29 29 33 301 3 3 29 2 19 10 10 a b a b The obverse layer(the obverse surface) of the bonding memberis solid-phase bonded to the reverse surface electrodeof the first semiconductor elementA (the second semiconductor elementB). The reverse layer(the reverse surface) of the bonding memberis solid-phase bonded to the obverse surfaceof the first conductive portionA (the second conductive portionB) of the conductive substrate. The obverse layer(the obverse surface) of the bonding memberis solid-phase bonded to the reverse surfaceof the first conductive portionA (the second conductive portionB) of the conductive substrate. The reverse layer(the reverse surface) of the bonding memberis solid-phase bonded to the second metal layer(the support surface) of the support substrate. The support substrate, the bonding member, the conductive substrate, the bonding member, and the first semiconductor elementA (the second second semiconductor elementB) are placed in this order in the thickness direction z and transported to a pressurizing device for performing solid-phase bonding, where solid-phase bonding of these components is performed in a single pressurization process.

17 FIG. 17 FIG. 29 3 193 29 29 33 301 3 b is an image of the bonding area between the bonding memberand the support substratetaken using a scanning electron microscope (SEM). The image shows the state after 100 cycles of temperature cycling testing. As shown in, the bonding interface between the reverse layer(the reverse surface) of the bonding memberand the second metal layer(the support surface) of the support substrateexhibits a properly bonded state.

41 42 43 44 1 41 42 44 43 1 5 7 8 FIGS.to,and Each of the first terminal, the second terminal, the third terminals, and the fourth terminalis provided by a plate made of a metal. The constituent material of the metal plate is, for example, Cu or a Cu alloy. In the example shown in, the semiconductor device Ahas one each of the first terminal, the second terminaland the fourth terminal, and two third terminals.

41 42 44 44 41 42 10 10 43 41 42 43 44 8 8 The DC voltage to be converted is inputted to the first terminal, the second terminal, and the fourth terminal. The fourth terminalis a positive electrode (P terminal), and each of the first terminaland the second terminalis a negative electrode (N terminal). The AC voltage converted by the first semiconductor elementsA and the second semiconductor elementsB is outputted from the third terminals. Each of the first terminal, the second terminal, the third terminalsand the fourth terminalincludes a portion covered with the sealing resinand a portion exposed from the sealing resin.

10 FIG. 7 FIG. 44 2 44 2 2 44 10 2 2 44 2 15 10 2 As shown in, the fourth terminalis formed integrally with the second conductive portionB. Unlike this configuration, the fourth terminalmay be provided separately from the second conductive portionB and conductively bonded to the second conductive portionB. As shown inin particular, the fourth terminalis located on the x2 side in the first direction x with respect to the second semiconductor elementsB and the second conductive portionB (the conductive substrate). The fourth terminalis electrically connected to the second conductive portionB and also electrically connected to the reverse surface electrode(the drain electrode) of each second semiconductor elementB via the second conductive portionB.

7 FIG. 5 6 FIGS.and 5 7 FIGS.and 1 5 8 FIGS.toand 41 42 2 5 41 42 41 42 10 2 2 41 42 5 12 10 5 1 41 42 44 8 41 42 44 41 42 44 41 44 42 44 41 42 44 As shown in, the first terminaland the second terminalare spaced apart from the second conductive portionB. As shown in, the first conductive memberis bonded to the first terminaland the second terminal. As shown inin particular, the first terminaland the second terminalare located on the x2 side in the first direction x with respect to the second semiconductor elementsB and the second conductive portionB (the conductive substrate). The first terminaland the second terminalare electrically connected to the first conductive memberand also electrically connected to the second obverse electrode(the source electrode) of each first semiconductor elementA via the first conductive member. As shown inin particular, in the semiconductor device A, the first terminal, the second terminaland the fourth terminalprotrude from the sealing resinto the x2 side in the first direction x. The first terminal, the second terminal, and the fourth terminalare spaced apart from each other. The first terminaland the second terminalare located opposite to each other across the fourth terminalin the second direction y. The first terminalis located on the y2 side in the second direction y of the fourth terminal, and the second terminalis located on the y1 side in the second direction y of the fourth terminal. The first terminal, the second terminal, and the fourth terminaloverlap with each other as viewed in the second direction y.

7 9 FIGS.and 7 FIG. 43 2 43 2 2 43 10 2 2 43 2 15 10 2 43 43 43 2 As understood from, the two third terminalsare integrally formed with the first conductive portionA. Unlike this configuration, the third terminalsmay be provided separately from the first conductive portionA and conductively bonded to the first conductive portionA. As shown inin particular, the two third terminalsare located on the x1 side in the first direction x with respect to the first semiconductor elementsA and the first conductive portionA (the conductive substrate). Each third terminalis electrically connected to the first conductive portionA and also electrically connected to the reverse surface electrode(the drain electrode) of each first semiconductor elementA via the first conductive portionA. The number of third terminalsis not limited to two, and may be one, or three or more. When only one third terminalis provided, the third terminalis preferably connected to the middle part in the second direction y of the first conductive portionA.

45 10 10 45 46 46 47 47 46 46 10 47 47 10 The control terminalsare pin-shaped terminals for controlling the first semiconductor elementsA and the second semiconductor elementsB. The control terminalsinclude a plurality of first control terminalsA toD and a plurality of second control terminalsA toE. The first control terminalsA toD are used to control the first semiconductor elementsA, for example. The second control terminalsA toE are used to control the second semiconductor elementsB, for example.

46 46 46 46 2 48 48 46 46 10 43 7 10 FIGS.and 5 7 FIGS.and The first control terminalsA toD are spaced apart from each other in the second direction y. As shown inin particular, the first control terminalsA toD are supported on the first conductive portionA via the control terminal support(the first support portionA, described later). As shown in, the first control terminalsA toD are located between the first semiconductor elementsA and the two third terminalsin the first direction x.

46 10 10 46 The first control terminalA is a terminal (a gate terminal) for inputting a drive signal for the first semiconductor elementsA. A drive signal for driving the first semiconductor elementsA is inputted (e.g., a gate voltage is applied) to the first control terminalA.

46 10 12 10 46 The first control terminalB is a terminal (a source sense terminal) for detecting a source signal of the first semiconductor elementsA. The voltage applied to the second obverse surface electrode(the source electrode) of each first semiconductor elementA (the voltage corresponding to the source current) is detected from the first control terminalB.

46 46 17 The first control terminalC and the first control terminalD are terminals electrically connected to a thermistor.

47 47 47 47 2 48 48 47 47 10 41 42 44 7 10 FIGS.and 5 7 FIGS.and The second control terminalsA toE are spaced apart from each other in the second direction y. As shown inin particular, the second control terminalsA toE are supported on the second conductive portionB via the control terminal support(the second support portionB, described later). As shown in, the second control terminalsA toE are located between the second semiconductor elementsB and the first, the second and the fourth terminals,andin the first direction x.

47 10 10 47 47 10 12 10 47 47 47 17 47 10 15 10 47 The second control terminalA is a terminal (a gate terminal) for inputting a drive signal for the second semiconductor elementsB. A drive signal for driving the second semiconductor elementsB is inputted (e.g., a gate voltage is applied) to the second control terminalA. The second control terminalB is a terminal (a source sense terminal) for detecting a source signal of the second semiconductor elementsB. The voltage applied to the second obverse surface electrode(the source electrode) of each second semiconductor elementB (the voltage corresponding to the source current) is detected from the second control terminalB. The second control terminalC and the second control terminalD are terminals electrically connected to a thermistor. The second control terminalE is a terminal (a drain sense terminal) for detecting a drain signal of the second semiconductor elementsB. The voltage applied to the reverse surface electrode(the drain electrode) of each second semiconductor elementB (the voltage corresponding to the drain current) is detected from the second control terminalE.

45 46 46 47 47 451 452 Each of the control terminals(the first control terminalsA toD and the second control terminalsA toE) includes a holderand a metal pin.

451 451 48 482 459 459 451 452 451 451 8 451 8 11 12 FIGS.and The holdersare made of an electrically conductive material. As shown in, the holdersare bonded to the control terminal support(the first metal layer, described later) via a conductive bonding material. The constituent material of the conductive bonding materialis not limited and may be solder, metal paste, or sintered metal, for example. Each holderincludes a cylindrical portion, an upper flange portion, and a lower flange portion. The upper flange portion is connected to the upper part of the cylindrical portion, and the lower flange portion is connected to the lower part of the cylindrical portion. A metal pinis inserted in at least the upper flange portion and the cylindrical portion of each holder. The holderis mostly covered with the sealing resin. In the illustrated example, only the upper end surface of each holderis exposed from the sealing resin.

452 452 451 452 48 482 451 452 459 451 452 48 459 452 11 12 FIGS.and The metal pinsare bar-shaped members extending in the thickness direction z. The metal pinsare supported by being press-fitted into the holders. The metal pinsare electrically connected to the control terminal support(the first metal layer, described later) at least via the holders. When the lower ends (the ends on the z2 side in the thickness direction z) of the metal pinsare in contact with the conductive bonding materialwithin the through-holes of the holdersas in the example shown in, the metal pinsare electrically connected to the control terminal supportvia the conductive bonding material. The length of the metal pinin the thickness direction z is not limited to the example shown in the figure and can be selected as appropriate.

48 45 48 201 2 45 The control terminal supportsupports the plurality of control terminals. The control terminal supportis interposed between the obverse surface(the conductive substrate) and the control terminalsin the thickness direction z.

48 48 48 48 2 2 46 46 45 48 2 49 49 48 2 2 47 47 45 48 2 49 11 FIG. 12 FIG. The control terminal supportincludes a first support portionA and a second support portionB. The first support portionA is disposed on the first conductive portionA of the conductive substrateand supports the first control terminalsA toD of the control terminals. As shown in, the first support portionA is bonded to the first conductive portionA via a bonding material. The bonding materialmay be electrically conductive or insulating, and may be solder, for example. The second support portionB is disposed on the second conductive portionB of the conductive substrateand supports the second control terminalsA toE of the control terminals. As shown in, the second support portionB is bonded to the second conductive portionB via a bonding material.

48 48 48 48 481 482 483 The control terminal support(each of the first support portionA and the second support portionB) is provided by a DBC (Direct Bonded copper) substrate, for example. The control terminal supportincludes an insulating layer, a first metal layer, and a second metal layerlaminated on top of each other.

481 481 The insulating layeris made of a ceramic material, for example. The insulating layermay be rectangular in plan view.

11 12 FIGS.and 7 FIG. 482 481 45 482 482 482 482 482 482 482 482 482 482 482 482 482 482 482 As shown inin particular, the first metal layeris formed on the upper surface of the insulating layer. Each control terminalstands on the first metal layer. The first metal layeris Cu or a Cu alloy, for example. As shown inin particular, the first metal layerincludes a first portionA, a second portionB, a third portionC, a fourth portionD, a fifth portionE, and a sixth portionF. The first portionA, the second portionB, the third portionC, the fourth portionD, the fifth portionE, and the sixth portionF are spaced apart and insulated from each other.

482 71 11 10 10 71 482 482 73 482 11 10 10 73 71 46 482 48 47 482 48 7 FIG. The first portionA, to which a plurality of wiresare bonded, is electrically connected to the first obverse surface electrodes(gate electrodes) of the first semiconductor elementsA (the second semiconductor elementsB) via the wires. The first portionA and the sixth portionF are connected via a plurality of wires. Thus, the sixth portionF is electrically connected to the first obverse surface electrodes(gate electrodes) of the first semiconductor elementsA (the second semiconductor elementsB) via the wiresand the wires. As shown in, the first control terminalA is bonded to the sixth portionF of the first support portionA, and the second control terminalA is bonded to the sixth portionF of the second support portionB.

482 72 12 10 10 72 46 482 48 47 482 48 7 FIG. The second portionB, to which a plurality of wiresare bonded, is electrically connected to the second obverse surface electrodes(source electrodes) of the first semiconductor elementsA (the second semiconductor elementsB) via the wires. As shown in, the first control terminalB is bonded to the second portionB of the first support portionA, and the second control terminalB is bonded to the second portionB of the second support portionB.

17 482 482 46 46 482 482 48 47 47 482 482 48 A thermistoris bonded to the third portionC and the fourth portionD. As shown in Fig., the first control terminalsC andD are bonded to the third portionC and the fourth portionD, respectively, of the first support portionA. The second control terminalsC andD are bonded to the third portionC and the fourth portionD, respectively, of the second support portionB.

482 48 482 48 74 2 74 47 482 48 71 74 71 74 7 FIG. The fifth portionE of the first support portionA is not electrically connected to other components. The fifth portionE of the second support portionB, to which a wireis bonded, is electrically connected to the second conductive portionB via the wire. As shown in, the second control terminalE is bonded to the fifth portionE of the second support portionB. Each of the wirestois, for example, a bonding wire. The constituent material of the wirestois not limited and includes one of Au (gold), Al or Cu, for example.

11 12 FIGS.and 11 FIG. 12 FIG. 483 481 483 483 48 2 49 483 48 2 49 As shown inin particular, the second metal layeris formed on the lower surface of the insulating layer. The second metal layeris Cu or a Cu alloy, for example. As shown in, the second metal layerof the first support portionA is bonded to the first conductive portionA via a bonding material. As shown in, the second metal layerof the second support portionB is bonded to the second conductive portionB via a bonding material.

5 6 2 10 10 5 6 201 2 201 5 6 5 6 The first conductive memberand the second conductive member, together with the conductive substrate, form a path for the main circuit current switched by the first semiconductor elementsA and the second semiconductor elementsB. The first conductive memberand the second conductive memberare spaced apart from the obverse surface(the conductive substrate) to the z1 side in the thickness direction z and overlap with the obverse surfacein plan view. In the present embodiment, each of the first conductive memberand the second conductive memberis provided by a plate made of a metal. The metal is Cu or a Cu alloy, for example. Specifically, each of the first conductive memberand the second conductive memberis a metal plate bent as appropriate.

5 12 10 41 42 12 10 41 42 5 10 5 5 51 52 53 54 55 6 7 FIGS.and The first conductive memberis connected to the second obverse surface electrode(the source electrode) of each first semiconductor elementA and the first and the second terminalsandto electrically connect the second obverse surface electrodeof each first semiconductor elementA and the first and the second terminalsandto each other. The first conductive memberforms a path for the main circuit current switched by the first semiconductor elementsA. The first conductive memberhas a maximum dimension in the first direction x of 25 mm to 40 mm, for example, and a maximum dimension in the second direction y of 30 mm to 45 mm, for example. As shown in, the first conductive memberincludes a first wiring portion, a second wiring portion, a third wiring portion, a fourth wiring portion, and a fifth wiring portion.

51 511 512 513 511 41 511 41 59 59 51 51 2 2 The first wiring portionhas a first end, a second end, and a plurality of openings. The first endis connected to the first terminal. The first endand the first terminalare bonded together with a conductive bonding material. The constituent material of the conductive bonding materialis not limited and may be solder, metal paste, or sintered metal, for example. The first wiring portionas a whole has a band shape extending in the first direction x in plan view. The first wiring portionoverlaps with both the second conductive portionB and the first conductive portionA in plan view.

512 511 512 511 6 FIG. The second endis spaced apart from the first endin the first direction x. As shown inin particular, the second endis located on the x1 in the first direction x with respect to the first end.

513 513 51 513 513 513 201 2 2 10 513 201 2 2 10 513 2 2 513 51 513 Each of the openingsis a portion partially cut away in plan view. The openingsare spaced apart from each other in the first direction x. In the illustrated example, the first wiring portionhas three openings. The openingon the x2 side in the first direction x and the openingat the center in the first direction x are located at positions that overlap with the obverse surfaceof the second conductive portionB (the conductive substrate) in plan view and do not overlap with the second semiconductor elementsB in plan view. The openingon the x1 side in the first direction x is located at a position that overlaps with the obverse surfaceof the first conductive portionA (the conductive substrate) in plan view and does not overlap with the first semiconductor elementsA in plan view. The openingsare provided at positions shifted to the y2 side in the second direction y of the second conductive portionB (the first conductive portionA) in plan view. In the present embodiment, the openingsare arcuate notches recessed to the y2 side in the second direction y from the y1-side edge in the first wiring portion. The shape in plan view of the openingsis not limited, and may be a notch as in the present embodiment, or a hole unlike the present embodiment.

52 521 522 523 521 42 521 42 59 52 52 51 52 51 52 2 2 The second wiring portionhas a third end, a fourth end, and a plurality of openings. The third endis connected to the second terminal. The third endand the second terminalare bonded together with a conductive bonding material. The second wiring portionas a whole has a band shape extending in the first direction x in plan view. The second wiring portionis spaced apart from the first wiring portionin the second direction y. The second wiring portionis located on the y1 side in the second direction y with respect to the first wiring portion. The second wiring portionoverlaps with both the second conductive portionB and the first conductive portionA in plan view.

522 521 522 521 6 FIG. The fourth endis spaced apart from the third endin the first direction x. As shown inin particular, the fourth endis located on the x1 in the first direction x with respect to the third end.

523 523 52 523 523 523 201 2 2 20 523 201 2 2 10 523 2 2 523 52 523 Each of the openingsis a portion partially cut away in plan view. The openingsare spaced apart from each other in the first direction x. In the illustrated example, the second wiring portionhas three openings. The openingon the x2 side in the first direction x and the openingat the center in the first direction x are located at positions that overlap with the obverse surfaceof the second conductive portionB (the conductive substrate) in plan view and do not overlap with the second semiconductor elementsB in plan view. The openingon the x1 side in the first direction x is located at a position that overlaps with the obverse surfaceof the first conductive portionA (the conductive substrate) in plan view and does not overlap with the first semiconductor elementsA in plan view. The openingsare provided at positions shifted to the y1 side in the second direction y of the second conductive portionB (the first conductive portionA) in plan view. In the present embodiment, the openingsare arcuate notches recessed to the y1 side in the second direction y from the y2-side edge in the second wiring portion. The shape in plan view of the openingsis not limited, and may be a notch as in the present embodiment, or a hole unlike the present embodiment.

53 51 512 52 522 53 53 10 53 10 6 FIG. 14 FIG. The third wiring portionis connected to both of the first wiring portion(the second end) and the second wiring portion(the fourth end). The third wiring portionhas a band shape extending in the second direction y in plan view. As understood fromin particular, the third wiring portionoverlaps with the first semiconductor elementsA in plan view. As shown in, the third wiring portionis connected to each of the first semiconductor elementsA.

53 531 531 53 531 10 531 53 12 10 59 531 531 531 10 531 531 53 531 5 2 531 14 FIG. a a a a a The third wiring portionhas a plurality of dented regions. As shown inin particular, each of the dented regionsprotrudes to the z2 side in the thickness direction z relative to other portions of the third wiring portion. Each of the dented regionsis connected to one of the first semiconductor elementsA. Each dented regionof the third wiring portionand the second obverse surface electrodeof a relevant first semiconductor elementA are bonded to each other via a conductive bonding material. In the present embodiment, each dented regionis formed with an opening. Preferably, each openingis formed to overlap with the central portion of a first semiconductor elementA in plan view. The openingsare, for example, through-holes formed in the dented regionsof the third wiring portion. The openingsare used, for example, to position the first conductive memberrelative to the conductive substrate. The shape in plan view of openingsmay be a perfect circle, or may be other shapes such as an ellipse or a rectangle.

54 51 52 54 54 51 511 512 52 521 522 54 53 54 53 54 10 6 FIG. The fourth wiring portionis connected to both of the first wiring portionand the second wiring portion. The fourth wiring portionhas a band shape extending in the second direction y in plan view. The fourth wiring portionis connected to the first wiring portionbetween the first endand the second endand connected to the second wiring portionbetween the third endand the fourth end. The fourth wiring portionis spaced apart from the third wiring portionin the first direction x. As shown inin particular, the fourth wiring portionis located on the x2 in the first direction x with respect to the third wiring portion. The fourth wiring portionoverlaps with the second semiconductor elementsB in plan view.

54 541 541 54 541 10 531 53 541 15 FIG. 6 15 FIGS.and 6 FIG. The fourth wiring portionhas a plurality of elevated regions. As shown inin particular, each of the elevated regionsprotrudes to the z1 side in the thickness direction z relative to other portions of the fourth wiring portion. As shown inin particular, the elevated regionsand the second semiconductor elementsB overlap with each other in plan view. As understood fromin particular, in the present embodiment, the positions in the second direction y of the dented regionsof the third wiring portionare the same as those of the elevated regions.

55 53 54 55 5 55 55 51 52 55 55 531 53 55 541 54 The fifth wiring portionis connected to both of the third wiring portionand the fourth wiring portion. The fifth wiring portionhas a band shape extending in the first direction x in plan view. In the present embodiment, the first conductive memberincludes a plurality of (three) fifth wiring portions. The fifth wiring portionsare located between the first wiring portionand the second wiring portionin the second direction y and spaced apart from each other in the second direction y. The fifth wiring portionsare disposed in parallel (or generally in parallel) with each other. The end on the x1 side in the first direction x of each fifth wiring portionis connected between two dented regionsadjacent to each other in the second direction y of the third wiring portion. The end on the x2 side in the first direction x of each fifth wiring portionis connected between two elevated regionsadjacent to each other in the second direction y of the fourth wiring portion.

6 12 10 2 12 10 2 6 10 6 61 62 63 6 7 FIGS.and The second conductive memberis connected to the second obverse surface electrode(the source electrode) of each second semiconductor elementB and the first conductive portionA to electrically connect the second obverse surface electrodeof each second semiconductor elementB and the first conductive portionA to each other. The second conductive memberforms a path for the main circuit current switched by the second semiconductor elementsB. As shown in, the second conductive memberincludes a main part, a plurality of first connecting ends, and a plurality of second connecting ends.

61 10 2 61 55 5 201 2 55 61 55 61 611 611 611 611 55 611 61 6 8 61 6 611 13 FIG. 6 7 10 FIGS.,and The main partis located between the second semiconductor elementsB and the first conductive portionA in the x direction and has a band shape extending in the second direction y in plan view. As shown inin particular, the main partis located on the z2 side in the thickness direction z with respect to the fifth wiring portionof the first conductive memberand located closer to the obverse surface(the conductive substrate) than are the fifth wiring portion. The main partoverlaps with the fifth wiring portionsin plan view. In the present embodiment, as shown inin particular, the main partis formed with a plurality of openings. Each openingis a through-hole penetrating in the thickness direction z, for example. The openingsare aligned in the second direction y in a mutually spaced manner. The openingsdo not overlap with the fifth wiring portionin plan view. The openingsare formed to facilitate the flow of the resin material between the upper side (z1 side in the thickness direction z) and the lower side (z2 side in the thickness direction z) at or near the main part(the second conductive member) during the injection of a flowable resin material to form the sealing resin. The configuration of the main part(the second conductive member) is not limited to this configuration. For example, the openingsmay not be formed.

62 63 61 10 62 12 10 69 63 2 69 69 62 621 621 10 621 621 6 2 621 10 15 FIGS.and The first connecting endsand the second connecting endsare connected to the main partand disposed correspondingly to the second semiconductor elementsB. As shown inin particular, each of the first connecting endsis bonded to the second obverse surface electrodeof a relevant one of the second semiconductor elementsB via a conductive bonding material, and each of the second connecting endsis bonded to the first conductive portionA via a conductive bonding material. The constituent material of the conductive bonding materialis not limited and may be solder, metal paste, or sintered metal, for example. In the present embodiment, each of the first connecting endsis formed with an opening. Preferably, each openingis formed to overlap with the central portion of a second semiconductor elementB in plan view. The openingsare through-hole penetrating in the thickness direction z, for example. The openingsare used, for example, to position the second conductive memberrelative to the conductive substrate. The planar shape of the openingsmay be a perfect circle or other shapes such as an oval, rectangle, or the like.

8 10 10 2 3 302 41 42 43 44 45 48 5 6 71 74 8 8 8 8 81 82 831 834 The sealing resincovers the first semiconductor elementsA, the second semiconductor elementsB, the conductive substrate, the support substrate(excluding the bottom surface), a part of each of the first terminal, the second terminal, the third terminalsand the fourth terminal, a part of each of the control terminals, the control terminal support, the first conductive member, the second conductive member, and the wiresto. The sealing resinis made of black epoxy resin, for example. The sealing resinis formed by molding, for example. The sealing resinhas dimensions of, for example, about 35 mm to 60 mm in the first direction x, about 35 mm to 50 mm in the second direction y, and about 4 mm to 15 mm in the thickness direction z. These dimensions are the size of the largest portion along each direction. In the present embodiment, the sealing resinhas a resin obverse surface, a resin reverse surface, and a plurality of resin side surfacesto.

9 14 FIGS.and 8 FIG. 81 82 81 45 46 46 47 47 81 82 82 302 3 32 302 3 82 82 As shown inin particular, the resin obverse surfaceand the resin reverse surfaceare spaced apart from each other in the thickness direction z. The resin obverse surfacefaces the z1 side in the thickness direction z. The control terminals(the first control terminalsA toD and the second control terminalsA toE) protrude from the resin obverse surface. The resin reverse surfacefaces the z2 side in the thickness direction z. As shown in, the resin reverse surfacehas a frame shape surrounding the bottom surfaceof the support substrate(the first metal layer) as viewed in the thickness direction z. The bottom surfaceof the support substrateis exposed from the resin reverse surfaceand may be flush with the resin reverse surface.

831 834 81 82 831 832 831 832 43 831 41 42 44 832 833 834 833 834 4 FIG. 4 FIG. Each of the resin side surfacestois connected to both of the the resin obverse surfaceand the resin reverse surfaceand sandwiched between these surfaces in the thickness direction z. As shown inin particular, the resin side surfaceand the resin side surfaceare spaced apart from each other in the first direction x. The resin side surfacefaces the x1 side in the first direction x, and the resin side surfacefaces the x2 side in the first direction x. The two third terminalsprotrude from the resin side surface, and the first terminal, the second terminaland the fourth terminalprotrude from the resin side surface. As shown inin particular, the resin side surfaceand the resin side surfaceare spaced apart from each other in the second direction y. The resin side surfacefaces the y1 side in the second direction y, and the resin side surfacefaces the y2 side in the second direction y.

4 FIG. 832 832 832 832 41 44 832 42 44 832 41 44 832 42 44 832 a a a a a As shown in, the resin side surfaceis formed with a plurality of recesses. Each recessis a portion recessed in the first direction x in plan view. One of the recessesis formed between the first terminaland the fourth terminalin plan view, and another one of the recessesis formed between the second terminaland the fourth terminalin plan view. The recessesare provided to increase the creepage distance between the first terminaland the fourth terminalalong the resin side surfaceand the creepage distance between the second terminaland the fourth terminalalong the resin side surface.

9 10 FIGS.and 8 851 86 As shown inin particular, the sealing resinhas a plurality of protrusionsand resin void portions.

85 81 85 8 851 85 85 85 81 85 85 1 1 85 85 851 85 85 85 851 a a b c b b c The protrusionsprotrude from the resin obverse surfacein the thickness direction z. In plan view, the protrusionsare disposed at four corners of the sealing resin. Each protrusionhas a protrusion end surfaceat its extremity (the end on the z1 side in the thickness direction z). The protrusion end surfacesof the protrusionsare parallel (or generally parallel) with the resin obverse surfaceand located on the same plane (x-y plane). Each protrusionmay have the shape of a hollow conical frustum with a bottom, for example. The protrusionsare used as spacers when the semiconductor device Ais mounted on a control circuit board or the like of a device configured to use the power produced by the semiconductor device A. Each protrusionhas a recessand an inner wall surfaceformed around the recess. The shape of each protrusionmay be columnar, and preferably cylindrical. Preferably, the shape of the recessis cylindrical, and the inner wall surfaceis a single perfect circle in plan view.

1 85 85 85 85 85 c b b The semiconductor device Amay be mechanically fixed to a control circuit board or the like by screwing, for example. In such a case, female threads can be formed on the inner wall surfacesof the recessesof the protrusions. Insert nuts may be embedded in the recessesof the protrusions.

9 FIG. 86 81 201 2 86 81 201 86 8 8 As shown in, the resin void portionsextend from the resin obverse surfaceto the obverse surfaceof the conductive substratein the thickness direction z. The resin void portionis tapered, with its sectional area decreasing as proceeding from the resin obverse surfacetoward the obverse surface(toward the z2 side in the thickness direction z). The resin void portionsare formed during the molding of the sealing resinand the area where the sealing resinis not formed during the molding process.

86 8 201 2 513 523 5 2 5 3 2 Though illustration is omitted, the resin void portionsare formed, for example, because the flowable resin material could not flow into these areas as a result of these areas being occupied by pressing members during the molding process of the sealing resin. Such pressing members are used to apply pressing force to the obverse surfaceof the conductive substrateduring the molding process and inserted into the openingsand the openingsof the first conductive member. In this way, the conductive substratecan be held by the pressing members without interference with the first conductive member, which eliminates or reduces the warpage of the support substrate, to which the conductive substrateis bonded.

1 88 88 86 86 88 8 8 9 FIG. In the present embodiment, the semiconductor device Aincludes resin fill portionsas shown inin particular. The resin fill portionsare loaded into the resin void portionsto fill the resin void portions. The resin fill portionsmay be made of epoxy resin as with the sealing resin, but may be made of a material different from the sealing resin.

3 2 10 10 1 1 18 FIG. 18 FIG. 16 FIG. Next, an example of a method for bonding the support substrate, the conductive substrate, the first semiconductor elementsA, and the second semiconductor elementsB in a manufacturing method of the semiconductor device Awill be described with reference to.is a schematic front view corresponding to, showing a step of a method for manufacturing the semiconductor device A.

29 3 29 29 301 33 33 33 3 2 29 2 202 29 29 2 202 29 29 33 2 202 29 29 33 19 2 2 19 19 201 2 2 10 10 19 19 10 102 19 19 2 10 102 19 19 2 18 FIG. b a a a b a a a First, the bonding membersare placed on the support substrateas shown in. Specifically, each bonding memberis placed with the reverse surfacefacing the support surfaceof the first portionA (the second portionB) of the second metal layerof the support substrate. Next, the conductive substrateis placed on the bonding members. The conductive substrateis placed with the reverse surfacefacing the obverse surfacesof the bonding members. More specifically, the first conductive portionA is placed with the reverse surfacefacing the obverse surfaceof the bonding memberplaced on the first portionA. The second conductive portionB is placed with the reverse surfacefacing the obverse surfaceof the bonding memberplaced on the second portionB. Next, bonding membersare placed on the first conductive portionA and the second conductive portionB. Each bonding memberis placed with the reverse surfacefacing the obverse surfaceof the first conductive portionA or the second conductive portionB. Next, a first semiconductor elementA or a second semiconductor elementB is placed on the obverse surfaceof each bonding member. Each first semiconductor elementA is placed with the element reverse surfacefacing the obverse surfaceof one of the bonding membersplaced on the first conductive portionA. Each second semiconductor elementB is placed with the element reverse surfacefacing the obverse surfaceof one of the bonding membersplaced on the second conductive portionB.

3 29 2 19 10 10 Next, the support substrate, the bonding members, the conductive substrate, the bonding members, the first semiconductor elementsA, and the second semiconductor elementsB are set in a pressurizing device as one unit. Then, the pressurizing device applies pressure and heat while applying vibration to cause the mutually facing surfaces of the above components to be brought into direct contact and solid-phase bonded. The pressurizing device is not limited to such a configuration, and may not apply heat or vibration; it can have any configurations capable of solid-phase bonding the mutually facing surfaces of the above components.

1 19 20 FIGS.and Next, examples of use of the semiconductor device Awill be described based on.

19 FIG. 19 FIG. 1 1 1 1 1 90 shows a semiconductor device assembly Bincorporating the semiconductor device A.is a partial sectional view of the semiconductor device assembly B. The semiconductor device assembly Bincludes the semiconductor device Aand a heat sink.

19 FIG. 90 302 1 3 90 302 909 90 1 90 As shown in, the heat sinkis disposed to face the bottom surfaceof the semiconductor device A(the support substrate). The heat sinkis bonded to the bottom surfacevia a bonding layer. The heat sinkis a heat-dissipating member that dissipates the heat generated by the semiconductor device A. The constituent material of the heat sinkis not limited and may be Al (aluminum), Cu (copper) or an alloy of these, for example.

909 90 302 3 909 909 909 The bonding layerbonds the upper surface (the surface facing the z1 side in the thickness direction z) of the heat sinkand the bottom surfaceof the support substrate. The constituent material of the bonding layeris not limited and may be sintered metal, for example. For example, the bonding layermay be a layer of sintered silver (Ag). In such a case, the thickness (the dimension in the thickness direction z) of the bonding layeris relatively small and may be 50 to 500 μm, for example.

20 FIG. 2 1 2 is a schematic view of a vehicle Bin which the semiconductor device Ais mounted. The vehicle Bis, for example, an electric vehicle (EV).

20 FIG. 2 94 95 93 94 94 94 94 95 As shown in, the vehicle Bincludes an on-board charger, a storage battery, and a drive system. The on-board chargerreceives electric power wirelessly from a power supply facility (not shown) installed outdoors. Alternatively, power supply from the power supply facility to the on-board chargermay be performed via a wired connection. The on-board chargerincludes a step-up DC-DC converter. The voltage of the power supplied to the on-board chargeris increased by the converter and then supplied to the storage battery. The increased voltage is, for example, 600 V.

93 2 93 931 932 1 931 95 931 95 931 93 95 931 931 931 1 932 932 931 932 2 2 2 1 931 20 FIG. The drive systemdrives the vehicle B. The drive systemhas an inverterand a driving source. The semiconductor device Aconstitutes a part of the inverter. The power stored in the storage batteryis supplied to the inverter. The power supplied from the storage batteryto the inverteris a direct current. Unlike the drive systemshown in, a step-up DC-DC converter may be additionally provided between the storage batteryand the inverter. The inverterconverts DC power into AC power. The inverterincluding the semiconductor device Ais electrically connected to the driving source. The driving sourcehas an AC motor and a transmission. When the AC power converted by the inverteris supplied to the driving source, the AC motor rotates, and the rotation is transmitted to the transmission. The transmission appropriately reduces the rotation speed transmitted from the AC motor and rotates the drive shaft of the vehicle B. Thus, the vehicle Bis driven. When driving the vehicle B, it is necessary to freely control the rotation speed of the AC motor based on the information such as the amount of movement of the accelerator pedal. The semiconductor device Ain the inverteris necessary to output the AC power with a frequency corresponding to the required rotation speed of the AC motor.

1 Next, the effects of the semiconductor device Awill be described.

19 10 10 2 10 10 2 29 2 3 2 3 According to the present embodiment, the bonding memberis interposed between the first semiconductor elementA (the second semiconductor elementB) and the conductive substrateand solid-phase bonded to each of these. Thus, the first semiconductor elementA (the second semiconductor elementB) and the conductive substrateare firmly bonded together without the application of significant heat. The bonding memberis interposed between the conductive substrateand the support substrateand solid-phase bonded to each of these. Thus, the conductive substrateand the support substrateare firmly bonded together without the application of significant heat.

201 202 2 301 3 201 202 2 301 3 1 According to the present embodiment, the obverse surfaceand the reverse surfaceof the conductive substrateare not provided with a metal layer such as Ag (silver) plating. Also, the support surfaceof the support substrateis not provided with a metal layer such as Ag (silver) plating. Therefore, the present embodiment does not require the process of forming metal layers on the obverse surfaceand the reverse surfaceof the conductive substrateand the process of forming a metal layer on the support surfaceof the support substrate. Thus, the semiconductor device Acan simplify the bonding process and reduce the cost for bonding.

19 29 19 29 The bonding membersandare metal foils in the present embodiment, but the present disclosure is not limited to this. The bonding membersandmay be metal plates.

19 10 10 2 29 2 3 1 10 10 2 1 2 3 In the present embodiment, the bonding memberbonds the first semiconductor elementA (the second semiconductor elementB) and the conductive substrate, and the bonding memberbonds the conductive substrateand the support substrate, but the present disclosure is not limited to this. In the semiconductor device A, the first semiconductor elementA (the second semiconductor elementB) and the conductive substratemay be bonded with solder, metal paste, or sintered metal, for example. In the semiconductor device A, the conductive substrateand the support substratemay be bonded with solder, metal paste, or sintered metal, for example.

48 2 49 10 10 48 2 19 483 48 The control terminal supportis bonded to the conductive substratevia the bonding material(e.g., solder) in the present embodiment, but the present disclosure is not limited to this. As with the first semiconductor elementA and the second semiconductor elementB, the control terminal supportmay be bonded to the conductive substratevia the bonding member. In such a case, a metal layer such as Ag (silver) plating may not be provided on the second metal layerof the control terminal support.

21 22 FIGS.and show another embodiment of the present disclosure. In these figures, the elements that are identical or similar to those of the above embodiment are denoted by the same reference signs as those used for the above embodiment, and the descriptions thereof are omitted. Various parts of each embodiment may be selectively used in any appropriate combination as long as it is technically compatible.

21 22 FIGS.and 21 FIG. 10 FIG. 22 FIG. 16 FIG. 2 2 2 2 1 2 90 90 8 show a semiconductor device Aaccording to a second embodiment of the present disclosure.is a sectional view of the semiconductor device Aand corresponds to.is a schematic front view corresponding to, showing the bonding structure of the semiconductor device A. The semiconductor device Adiffers from the semiconductor device Ain that the semiconductor device Aincludes a heat sinkand a part of the heat sinkis also covered with the sealing resin. The configurations and operations of other parts of the present embodiment are the same as those of the first embodiment. Various parts of the first embodiment and the variations may be optionally used in the present embodiment.

2 90 39 The semiconductor device Afurther includes a heat sinkand a bonding member.

90 3 39 90 90 The heat sinkis bonded to the support substratevia the bonding member. The constituent material of the heat sinkis mainly composed of, for example, Cu (copper), and may be Cur or a Cu alloy. The constituent material of the heat sinkis not limited, may be mainly composed of other metals such as Al (aluminum).

90 901 902 901 902 901 902 901 3 3 39 901 90 The heat sinkhas an obverse surfaceand a reverse surface. The obverse surfaceand the reverse surfaceare spaced apart from each other in the thickness direction z. The obverse surfacefaces the z1 side in the thickness direction z, and the reverse surfacefaces the z2 side in the thickness direction z. The obverse surfacefaces the support substrateand is bonded to the support substratevia the bonding member. The obverse surfaceof the heat sinkis not provided with a metal layer such as Ag (silver) plating.

39 32 3 90 3 90 39 32 39 90 39 19 29 191 192 193 194 195 39 39 39 39 39 39 39 39 192 3 39 193 90 192 39 39 32 302 3 193 39 39 90 901 22 FIG. a b a b a b a b a b The bonding memberis interposed between the first metal layerof the support substrateand the heat sinkto bond the support substrateand the heat sink. The bonding memberand the first metal layerare solid-phase bonded, and the bonding memberand the heat sinkare solid-phase bonded. As shown in, the structure of the bonding memberis similar to that of the bonding membersand, and includes a body layer, an obverse layer, a reverse layer, and intermediate layersand. The bonding memberhas an obverse surfaceand a reverse surface. The obverse surfaceand the reverse surfaceare spaced apart from each other in the thickness direction z. The obverse surfacefaces the z1 side in the thickness direction z, and the reverse surfacefaces the z2 side in the thickness direction z. The obverse surfaceis the surface of the obverse layerthat faces the z1 side in the thickness direction z, and faces the support substrate. The reverse surfaceis the surface of the reverse layerthat faces the z2 side in the thickness direction z, and faces the heat sink. The obverse layer(the obverse surface) of the bonding memberis solid-phase bonded to the first metal layer(the bottom surface) of the support substrate. The reverse layer(the reverse surface) of the bonding memberis solid-phase bonded to the heat sink(the obverse surface).

39 90 90 39 3 29 2 19 10 10 In the present embodiment, solid-phase bonding of various components, including the bonding memberand the heat sink, is performed in a single pressurization process. That is, the heat sink, the bonding member, the support substrate, the bonding member, the conductive substrate, the bonding member, and the first semiconductor elementA (the second semiconductor elementB) are placed in this order in the thickness direction z and transported to a pressurizing device for performing solid-phase bonding, where solid-phase bonding of these components is performed at once.

21 FIG. 8 90 39 In the present embodiment, as shown in, the sealing resincovers a portion of the heat sinkand the bonding memberas well.

19 10 10 2 10 10 2 29 2 3 2 3 39 3 90 3 90 In the present embodiment again, the bonding memberis interposed between the first semiconductor elementA (the second semiconductor elementB) and the conductive substrateand solid-phase bonded to each of these. Thus, the first semiconductor elementA (the second semiconductor elementB) and the conductive substrateare firmly bonded together without the application of significant heat. The bonding memberis interposed between the conductive substrateand the support substrateand solid-phase bonded to each of these. Thus, the conductive substrateand the support substrateare firmly bonded together without the application of significant heat. Further, according to the present embodiment, the bonding memberis interposed between the support substrateand the heat sinkand solid-phase bonded to each of these. Thus, the support substrateand the heat sinkare firmly bonded together without the application of significant heat.

201 202 2 301 302 3 901 90 201 202 2 301 302 3 901 90 2 According to the present embodiment, the obverse surfaceand the reverse surfaceof the conductive substrateare not provided with a metal layer such as Ag (silver) plating. Also, the support surfaceand the bottom surfaceof the support substrateis not provided with a metal layer such as Ag (silver) plating. Further, the obverse surfaceof the heat sinkis not provided with a metal layer such as Ag (silver) plating. Therefore, the present embodiment does not require the process of forming metal layers on the obverse surfaceand the reverse surfaceof the conductive substrate, the process of forming metal layers on the support surfaceand the bottom surfaceof the support substrate, and the process of forming a metal layer on the obverse surfaceof the heat sink. Thus, the semiconductor device Acan simplify the bonding process and reduce the cost for bonding.

The bonding structure and the bonding method according to the present disclosure is also applicable to a semiconductor device having a structure different from those of the first and second embodiments when a first member and a second member constituting the semiconductor device are solid-phase bonded. The bonding structure and the bonding method according to the present disclosure is also applicable to a package incorporating an electronic component other than a semiconductor element when the first member and the second member are solid-phase bonded. The bonding structure and the bonding method according to the present disclosure is also applicable to a device or the like other than a package incorporating a semiconductor element or an electronic component when the first member and the second member are solid-phase bonded.

The bonding structure, the semiconductor device, and the bonding method according to the present disclosure is not limited to the above-described embodiments. Various modifications in design may be made freely in the specific structure of each part of the bonding structure and the semiconductor device as well as the specific process in each step of the bonding method according to the present disclosure.

The present disclosure includes the embodiments described in the following clauses.

a first member including a first layer mainly composed of a first metal; and a second member including a second layer mainly composed of a second metal different from the first metal, wherein the first layer of the first member and the second layer of the second member are solid-phase bonded. A bonding structure comprising:

The bonding structure according to clause 1, wherein the first metal is Cu, and the second metal is Ag.

The bonding structure according to clause 1, wherein the first metal is Cu, and the second metal is Au.

The bonding structure according to clause 1, wherein the first metal is Au, and the second metal is Ag.

1 the bonding structure as set forth in any one of clauses 1 to 4; and 10 10 a semiconductor element (A,B). A semiconductor device (A) comprising:

5 2 a conductive substrate () as the first member; and 19 a first bonding member () as the second member, wherein the semiconductor element is conductively bonded to the conductive substrate via the first bonding member. The semiconductor device according to clause, comprising:

19 The semiconductor device according to clause 5, comprising a first bonding member () as the second member, wherein the semiconductor element is the first member.

192 193 The semiconductor device according to clause 6 or 7, wherein the first bonding member includes an obverse layer () and a reverse layer () on opposite ends in a thickness direction (z), the obverse layer and the reverse layer containing Ag.

191 The semiconductor device according to clause 8, wherein the first bonding member further includes a body layer () interposed between the obverse layer and the reverse layer in the thickness direction, the body layer containing Al.

The semiconductor device according to any one of clauses 6 to 9, wherein the first bonding member is a metal foil.

3 a support substrate () as the first member; and 29 a second bonding member () as the second member, wherein the semiconductor element is mounted on the support substrate via the second bonding member. The semiconductor device according to clause 5, comprising:

2 The semiconductor device according to clause 11, further comprising a conductive substrate () disposed opposite to the support substrate with respect to the second bonding member, the conductive substrate being solid-phase bonded to the second bonding member.

90 a heat sink () as the first member; and 39 a third bonding member () as the second member, wherein heat generated by the semiconductor element is conducted to the heat sink via the third bonding member. The semiconductor device according to clause 5, comprising:

932 a driving source (); and the semiconductor device as set forth in any one of clauses 5 to 13, wherein the semiconductor device is electrically connected to the driving source. A vehicle comprising:

preparing a first member including a first layer mainly composed of a first metal, and a second member including a second layer mainly composed of a second metal different from the first metal; and solid-phase bonding the first layer of the first member and the second layer of the second member. A bonding method comprising:

14 an obverse layer and a reverse layer disposed on opposite ends in a thickness direction and containing Ag; and a body layer interposed between the obverse layer and the reverse layer in the thickness direction and containing Al. The bonding method according to clause, wherein the second member includes:

1 2 10 10 101 102 11 12 13 15 17 19 29 39 191 192 193 194 194 194 195 195 195 19 29 39 19 29 39 2 2 2 201 202 3 301 302 31 32 33 33 33 41 42 43 44 45 451 452 459 46 46 46 46 47 47 47 47 47 48 48 48 481 482 482 482 482 482 482 482 483 49 5 51 511 512 513 52 521 522 523 53 531 531 54 541 55 59 6 61 611 62 621 63 69 71 72 73 74 8 81 82 831 832 832 833 834 85 85 85 85 86 88 90 901 902 909 1 2 93 931 932 94 95 a b a b a a a b b b a a a b c A, A: Semiconductor deviceA: First semiconductor elementB: Second semiconductor element: Element obverse surface: Element reverse surface: First obverse surface electrode: Second obverse surface electrode: Third obverse surface electrode: Reverse surface electrode: Thermistor,,: Bonding member: Body layer: Obverse layer: Reverse layer: Intermediate layer: Ni layer: Cu layer: Intermediate layer: Ni layer: Cu layer,,: Obverse surface,,: Reverse surface: Conductive substrateA: First conductive portionB: Second conductive portion: Obverse surface: Reverse surface: Support substrate: Support surface: Bottom surface: Insulating layer: First metal layer: Second metal layerA: First portionB: Second portion: First terminal: Second terminal: Third terminal: Fourth terminal: Control terminal: Holder: Metal pin: Conductive bonding materialA,B,C,D: First control terminalA,B,C,D,E: Second control terminal: Control terminal supportA: First support portionB: Second support portion: Insulating layer: First metal layerA: First portionB: Second portionC: Third portionD: Fourth portionE: Fifth portionF: Sixth portion: Second metal layer: Bonding material: First conductive member: First wiring portion: First end: Second end: Opening: Second wiring portion: Third end: Fourth end: Opening: Third wiring portion: Dented region: Opening: Fourth wiring portion: Elevated region: Fifth wiring portion: Conductive bonding material: Second conductive member: Main part: Opening: First connecting end: Opening: Second connecting end: Conductive bonding material,,,: Wire: Sealing resin: Resin obverse surface: Resin reverse surface,: Resin side surface: Recess,: Resin side surface: Protrusion: Protrusion end surface: Recess: Inner wall surface: Resin void portion: Resin fill portion: Heat sink: Obverse surface: Reverse surface: Bonding layer B: Semiconductor device assembly B: Vehicle: Drive system: Inverter: Driving source: On-board charger: Storage battery