Scalable Partitioning of Functions Within Application Specific Integrated Circuit or Microelectronics Device

The present disclosure relates to an application specific integrated circuit (ASIC) or microelectronics device, and more specifically to scalable partitioning of functions within an ASIC or microelectronics device.

Some ASIC implementations include multiple identical die connected in a multi-chip-module. Some other ASIC implementations include multiple instantiations of a function(s) are integrated in a single, monolithic die. In some cases, an ASIC in which multiple identical die are connected in a multi-chip-module has increased power consumption (e.g., due to the die-to-die I/O interfaces) compared to an equivalent ASIC in which multiple instantiations of the same function(s) are integrated in a single, monolithic die. However, a single monolithic die will consume more power compared to a multi-chip-module implementation for cases in which the total quantity of instantiated functions is reduced. Functions are digital features, analog features, or a mix of digital features and analog features that define the purpose of the device.

A semiconductor wafer is provided including: a plurality of processing cores; and a plurality of die structures each including at least one processing core of the plurality of processing cores, wherein each processing core includes: a set of first input output (I/O) interfaces configured for communication between the processing core and at least one second processing core of the plurality of processing cores, wherein the processing core and the at least one second processing core are included in a first die structure of the plurality of die structures; and a second input output (I/O) interface configured for communication between the processing core and at least one third processing core of the plurality of processing cores, wherein the at least one third processing core is included in a second die structure of the plurality of die structures, wherein the plurality of processing cores are spaced apart by a target distance associated with separating one or more processing cores of the plurality of processing cores or one or more die structures of the plurality of die structures from the semiconductor wafer.

In any one or combination of the embodiments disclosed herein, each processing core includes: processing circuitry configured to aggregate and process first data received from the at least one second processing core, wherein the processing circuitry generates second data in response to processing the first data; and routing circuitry configured to route the first data, the second data, or both to at least one fourth processing core included in the first die structure or to the at least one third processing core included in the second die structure.

In any one or combination of the embodiments disclosed herein, the routing circuitry is configured to route the first data, the second data, or both based on an address table associated with the plurality of processing cores, the plurality of die structures, or both.

In any one or combination of the embodiments disclosed herein, the routing circuitry is configured to reroute the first data, the second data, or both based on a detected fault associated with the at least one fourth processing core or to the at least one third processing core.

In any one or combination of the embodiments disclosed herein, the first die structure includes: processing circuitry configured to at least one of aggregate and process first data received from at least the second die structure of the plurality of die structures, wherein the processing circuitry generates second data in response to processing the first data; and routing circuitry configured to route the first data, the second data, or both to at least one third die structure of the plurality of die structures.

In any one or combination of the embodiments disclosed herein, the routing circuitry is configured to route the first data, the second data, or both based on an address table associated with the plurality of die structures.

In any one or combination of the embodiments disclosed herein, the routing circuitry is configured to reroute the first data, the second data, or both based on a detected fault associated with the at least one third die structure.

In any one or combination of the embodiments disclosed herein, the second I/O interface is configured for extra short reach (XSR) communications, very short reach (VSR) communications, or ultra short reach (USR) communications, among the plurality of processing cores.

In any one or combination of the embodiments disclosed herein, the first I/O interface, the second I/O interface, or both includes a serial interface or a parallel interface.

In any one or combination of the embodiments disclosed herein, each processing core includes: an active area including one or more circuits; and a crackstop structure surrounding the active area; and a scribe area associated with separating one or more die structures of the plurality of die structures from the semiconductor wafer.

In any one or combination of the embodiments disclosed herein, the semiconductor wafer further includes: a tunneling layer extending under, above, or through the crackstop structure, wherein the tunneling layer is electrically isolated from the crackstop structure.

In any one or combination of the embodiments disclosed herein, each processing core further includes: first electrostatic discharge (ESD) protection circuitry associated with the first set of I/O interfaces; and second ESD processing circuitry associated with the second I/O interface.

In any one or combination of the embodiments disclosed herein, respective structures of the plurality of processing cores are identical.

In any one or combination of the embodiments disclosed herein, a structure of at least one processing core of the plurality of processing cores is different from a structure of at least one other processing core of the plurality of processing cores.

In any one or combination of the embodiments disclosed herein, the second die structure is adjacent the first die structure.

A method of manufacturing a plurality of die structures is provided, the method including: fabricating a plurality of processing cores on a semiconductor wafer based on a reticle set defining scribe lines associated with separating the plurality of processing cores from the semiconductor wafer; and separating the plurality of die structures from the semiconductor wafer based on the reticle set and a target quantity of processing cores for at least one die structure of the plurality of die structures, wherein separating the plurality of die structures from the semiconductor wafer includes cutting the semiconductor wafer based on the scribe lines, wherein the plurality of processing cores are spaced apart by a target distance associated with separating one or more processing cores of the plurality of processing cores or one or more die structures of the plurality of die structures from the semiconductor wafer.

In any one or combination of the embodiments disclosed herein, the method further includes forming, in association with each processing core of the plurality of processing cores: an active area including one or more circuits; a crackstop structure surrounding the active area; and a scribe area associated with separating one or more die structures of the plurality of die structures from the semiconductor wafer.

In any one or combination of the embodiments disclosed herein, the method further includes forming a tunneling layer extending under, above, or through the crackstop structure, wherein the tunneling layer is electrically isolated from the crackstop structure.

In any one or combination of the embodiments disclosed herein, fabricating the plurality of processing cores includes fabricating at least one processing core of the plurality of processing cores with a different orientation relative to at least one other processing core, said different orientation being based on a target configuration of a die structure, and fabricating the plurality of processing cores is based at least in part on the target configuration.

In any one or combination of the embodiments disclosed herein, at least one die structure of the plurality of die structures is fabricated to have a different orientation relative to at least one other die structure of the plurality of die structures, said different orientation being based on a target configuration of the plurality of die structures on the semiconductor wafer, wherein fabricating the plurality of processing cores is based at least in part on the target configuration.

Additional features and advantages are realized through the techniques of the present disclosure. Other embodiments and aspects of the disclosure are described in detail herein and are considered a part of the claimed disclosure. For a better understanding of the disclosure with the advantages and the features, refer to the description and to the drawings.

Processor chips or micro processing chips may include one to multiple processing cores. In some cases, including multiple cores increases performance by sharing or distributing the processing load. Some approaches include designing and manufacturing a chip for each configuration of one to multiple cores. For example, such approaches may involve a separate respective design, manufacturing, and test efforts for a sixteen-core processor and a four-core processor, even though the core utilized in the sixteen-core processor and the four-core processor is the same function. Functions of a device are digital features, analog features, or a mix of digital features and analog features that define the purpose of the device. Accordingly, for example, such approaches may involve multiple non-recurring engineering costs associated with the design and manufacturing of each configuration.

To add some ability to scale a single function from one to many, some approaches use a “chiplet” concept of multiple die within a device package, allowing for a package configuration tailored to target specifications. However, such approaches come at a cost. For example, in some cases, to support die to die communications within the device package, each die may be (in some cases, must be) implement I/O interfaces strong enough to maintain signal integrity from die to bump to substrate or interposer (and from substrate or interposer to bump to die). Approaches using such I/O interfaces, however, results in increased power consumption compared to a monolithic (e.g., non-chiplet) approach.

102 107 103 According to one or more embodiments of the present disclosure, designs on silicon wafer are created by exposing the design into rows and columns across the silicon wafer. The exposed area, referred to as a reticle (e.g., reticleslater described herein), in some cases, may contain the lithography for a design or multiple designs. The design(s) may be singulated from the wafer by slicing the wafer along horizontal and vertical scribe lines (also referred to herein as “kerfs”). The scribe line can be along a reticle (e.g., as illustrated by reticle scribe lineslater described herein) or internal to the reticle (e.g., as illustrated by inter-reticle scribe lineslater described herein). The singulated die(s) are assembled into a chip package.

In one or more embodiments, to allow for the scaling of functions while mitigating the consumption of additional power associated with die-to-die I/O interfaces, example aspects of the present disclosure provide a mechanism to an owning party to leave functions connected at the silicon wafer level or slice the silicon wafer into smaller instantiations (e.g., to as low as one function per singulated die).

In one or more embodiments, using the example of the processor core mentioned above, systems and techniques described herein enable the design of a single processing core that is connected to one or more identical neighboring processing cores via standard routing, but over a gap that allows for the kerf. The systems and techniques described herein support singulating a die from the wafer as a single core or in groups of 1×2 cores, groups of 2×2 cores (e.g., quad core processor), groups of 4×4 cores (e.g., sixteen-core processor), groups of 2×6 cores, and the like. The techniques described herein are not limited to a single function. The techniques described herein may be similarly applied to a collection of functions that can be stand alone or implemented in an array.

1 FIG. 1 FIG. 100 101 100 illustrates a plan view of a semiconductor waferin accordance one or more embodiments of the present disclosure.further illustrates an enlarged view of a portionof the semiconductor wafer.

100 110 110 105 105 105 100 105 105 The semiconductor waferincludes multiple die structures, and each die structuremay include a processing core(also referred to herein as a “core”) formed thereon. Each processing coremay include processing circuitry. In some aspects, each processing coremay be identical. Additionally, or alternatively, in one or more embodiments, the semiconductor wafermay include some processing coresidentical to one another and some processing coresdifferent from one another.

100 107 103 100 105 103 107 103 107 103 107 103 107 103 107 100 110 110 105 110 110 110 105 105 100 110 110 107 110 110 a b e a e a e 1 FIG. 1 FIG. The semiconductor waferincludes reticle scribe linesand inter-reticle scribe linesformed during the design of the semiconductor waferfor separating the processing cores. The inter-reticle scribe linesand scribe linesmay also be referred to as kerfs, and inter-reticle scribe linesmay be designed substantially the same as and have different dimensions than scribe lines. In some examples, an inter-reticle scribe linemay have a width less than the width of a scribe line. In a non-limiting example, an inter-reticle scribe linewidth may be approximately ⅓ the width of a scribe linewidth. In all examples, as described herein, the communication amongst dies across inter-reticle scribe linesand/or scribe linesis possible if desired after fabrication. For example, during a separation process, the semiconductor wafermay be separated into die structures(e.g., die structure-) each including a single processing coreand/or die structures(e.g., die structure-through die structure-) each including multiple processing cores. For simplicity, processing coresincluded in other regions of the semiconductor waferare not illustrated in. In the example of, it is to be understood that lines in bold for indicating the die structure-through die structure-are for illustrative purposes for differentiating between the same, and widths of scribe lines (e.g., scribe lines) associated with die structure-through die structure-are not limited to thicknesses of the lines.

103 107 100 100 110 105 103 107 Although not illustrated herein, it is to be understood that the inter-reticle scribe linesand scribe linesmay span the length and width of the semiconductor wafer, such that during a separation process, the semiconductor wafermay be separated into die structuresof any suitable size (e.g., including any suitable quantity or arrangement of processing cores), by cutting according to one or more portions of the inter-reticle scribe linesand/or scribe lines. The terms “die structure” and “die”may be used interchangeably herein.

100 107 103 The separation process may include sawing or cutting the semiconductor waferalong the scribe linesand/or inter-reticle scribe linesusing a mechanical process (e.g., scribing, sawing) or by a non-contact process (e.g., with a laser). The separation process is not limited thereto, and aspects of the present disclosure may include other suitable techniques supportive of the separation process.

100 110 105 110 105 110 105 110 105 110 105 100 100 110 100 105 110 105 110 a b c d e In an example, the semiconductor wafermay be cut such that die structure-is a single processing core, die structure-is a 1×2 array of processing cores, die structure-is a 2×2 array of processing cores(also referred to as a quad core processor), die structure-is a 3×2 array of processing cores, and die structure-is a 4×3 array of processing cores. Additionally, or alternatively, the semiconductor wafermay be maintained without cutting the semiconductor wafer(e.g., without separating the die structuresfrom the semiconductor wafer). The quantity of processing coresassociated with each die structureis not limited thereto, and aspects of the present disclosure support any suitable quantity or array of processing cores(e.g., a 3×3 array, a 4×4 array, a 1×3 array, and the like) per die structure.

105 105 105 105 110 105 110 110 110 105 110 110 110 103 107 b c For each processing core, a crackstop structure (not illustrated) is formed around the periphery of the processing core. In one or more embodiments, the crackstop structure is formed in dielectric and metal material around an active area of the processing core. The crack stop structure prevents or reduces the likelihood of cracking in the processing core(and accordingly, for example, a die structureincluding the processing core) during the separation process. In an example, for a multi-core die structure(e.g., die structure-, die structure-, and the like), respective crackstop structures associated with processing coresincluded in the multi-core die structureprevent or reduce the likelihood of cracking in the multi-core die structure(e.g., at the edges of the multi-core die structure) during the separation process along inter-reticle scribe linesand/or along scribe lines.

105 113 105 110 105 100 113 105 105 113 100 105 105 100 105 According to one or more embodiments of the present disclosure, the processing coresare spaced apart by a target distanceassociated with separating one or more processing cores(or die structuresincluding the one or more processing cores) from the semiconductor wafer. The target distancemay also be referred to herein as a gap, and represents a minimum distance which allows for selectively separating the processing cores. Some other techniques for fabricating a semiconductor wafer and separating the semiconductor wafer into multi-chip-modules fail to include a spacing between each processing coreaccording to the target distancedescribed herein, and such techniques thus do not support the flexibility described herein for maintaining a semiconductor waferas a whole or separating each of the processing cores(e.g., or any suitable combination or array of processing cores) from a semiconductor wafer. For example, some other techniques may omit such a spacing described herein between each processing core. Example aspects of the crackstop structure are later described herein.

2 2 FIGS.A throughG 2 2 FIGS.A throughG 1 FIG. 105 110 110 105 105 105 110 a d c are block diagrams illustrating example aspects of processing coresand die structuresin accordance with one or more embodiments of the present disclosure. In the examples illustrated at, the die structureis a multi-core die structure including four processing cores(e.g., processing core-through processing core-) and is an example of die structure-illustrated at.

2 FIG.A 105 106 106 106 105 105 110 a d Referring to, each processing coremay include a set of input output (I/O) interfaces(e.g., I/O interface-through I/O interface-) configured for communication (e.g., transmission of data and/or receipt of data) between the processing coreand at least one other processing coreincluded in the same die structure.

105 105 106 105 106 105 105 105 106 105 106 105 105 105 106 105 106 105 a b b a d b b c c b a c c d d c b d For example, processing core-and processing core-may communicate via I/O interface-of processing core-(and I/O interface-of processing core-). Processing core-and processing core-may communicate via I/O interface-of processing core-(and I/O interface-of processing core-). Processing core-and processing core-may communicate via I/O interface-of processing core-(and I/O interface-of processing core-).

105 105 106 105 106 105 d a a d c a Processing core-and processing core-may communicate via I/O interface-of processing core-(and I/O interface-of processing core-).

105 115 105 115 105 Each processing coremay include an analog-to-digital (ADC)/digital-to-analog (DAC) converter. However, embodiments supported by the present disclosure are not limited thereto. For example, each processing coremay include circuitry additional and/or alternative to ADC/DAC converter. In some embodiments, each processing coremay include suitable circuitry capable of performing one or more target functions or operations.

105 120 105 105 110 120 105 105 105 110 110 c c 2 FIG.A Each processing coremay include an I/O interfaceconfigured for communication between the processing coreand one or more processing coresincluded in a different die structure. For example, via I/O interfaceof processing core-, processing core-may communicate with a processing core(not illustrated) that is included in a die structure(not illustrated) different from the die structureof.

1 FIG. 1 FIG. 110 105 110 105 110 120 105 105 110 105 110 120 105 c b c d In an example referring back to, in a multi-chip module (MCM) implementation having a plurality of die structureswithin a package, an upper-left processing coreof die structure-may communicate with a left-side processing coreof die structure-via respective I/O interfacesof the processing cores. In another example described with reference to, a lower-left processing coreof die structure-may communicate with an upper-left processing coreof die structure-via respective I/O interfacesof the processing cores.

120 105 113 105 120 110 100 113 105 120 106 120 105 110 1 FIG. In one or more embodiments, the I/O interfaceis configured for high-bandwidth extra short reach (XSR) communications among the processing cores, and the target distance(see), between processing coresmay correspond to a physical distance supportive of data communications using XSR. Additionally, or alternatively, the I/O interfacemay be configured for one or more other suitable high-bandwidth communication topologies (e.g., short reach (SR), very short reach (VSR), ultra short reach (USR), and the like) or implementations (e.g., for multi-chip modules (MCM) supportive of intercommunication between adjacent die structuresincluded in the semiconductor wafer, and the target distancebetween processing coresmay correspond to a physical distance supportive of data communications using an applied communication topology (and the associated I/O interfaces). According to one or more embodiments of the present disclosure, the I/O interfacesand the I/O interfacesdescribed herein can be any serial or parallel interface suitable for communications among the processing cores(and corresponding die structures).

105 130 105 110 130 105 130 105 In one or more embodiments, each processing coremay include processing circuitry(also referred to herein as a processor) configured to aggregate and process data received from another processing coreor another die structure, or a processing module of a different design and/or type (e.g., application specific integrated circuit (ASIC), field-programmable gate array (FPGA), graphics processing unit (GPU), central processing unit (CPU), and the like). In some aspects, the processing circuitrymay generate additional data in response to processing the received data. Each processing coremay include routing circuitry (not illustrated) configured to route the received data (and/or the additional data generated by the processing circuitryin response to processing the received data) to a further processing core.

105 108 106 109 120 108 109 105 105 105 100 108 109 105 110 108 108 109 105 105 105 108 109 2 FIG.A a d a b d In order to protect the device from electrostatic discharge via the nets (i.e., the metal connections from one logic or analog element to another element) exposed as a process of singulating die, in one or more embodiments, each processing coremay include electrostatic discharge (ESD) protection circuitryrespective to the I/O interfacesand ESD processing circuitryrespective to the I/O interfaces. The ESD processing circuitryand ESD processing circuitrymay protect each processing core(e.g., circuitry included in the processing core) from electrostatic discharge via the nets exposed as a process of singulating the processing coresfrom the semiconductor wafer. In some embodiments, The ESD processing circuitryand ESD processing circuitrymay be of the same or different type or configuration. For simplicity and so as not to obstruct from other features of the processing coresand the die structure, at, ESD processing circuitry-through ESD processing circuitry-and ESD processing circuitryare illustrated at processing core-, but not illustrated with respect to processing core-through processing core-. For simplicity, the ESD protection circuitryand ESD processing circuitryis not illustrated in the further following figures.

130 105 110 130 105 110 2 2 FIGS.B throughD 2 2 FIGS.E throughF Examples of the processing circuitryaggregating and processing data received (e.g., via the routing circuitry) from a processing coreincluded in a different die structureare described with reference to. Examples of the processing circuitryaggregating and processing data received (e.g., via the routing circuitry) from a processing coreincluded in the same die structureare later described with reference to.

110 105 105 110 105 130 105 105 110 130 105 2 FIG.G In one or more embodiments, via the routing circuitry, the die structureis capable of setting or modifying a route via which data is to be propagated among processing cores, based on a detected fault associated with one or more processing coresincluded in the die structure. Example aspects of setting or modifying the route based on a detected fault associated with a processing coreare later described with reference to. In some examples, processing circuitryof each respective processing coremay also include a storage (e.g., memory) (not shown) for storing a routing table for determining the route or path among coreswithin a die. In response to a command from a central control authority (e.g., an on-board processor or other payload-level processor), and/or in response to a detected fault, the routing table(s) may be updated (e.g., by a processing circuitry) to re-route data paths among coresas applicable.

2 2 FIGS.B throughD 105 150 105 110 110 105 150 130 105 150 c a c a c b Referring to, the processing core-may receive data-from a processing coreincluded in a die structure(not illustrated) different from and adjacent to the die structure. The processing core-may aggregate and process the data-(e.g., using processing circuitry). In some examples, the processing core-may generate data-in response to processing the received data.

1 2 FIGS.andB 2 FIG.B 1 FIG. 1 FIG. 1 FIG. 110 110 110 150 110 105 105 110 110 110 c a e c d In an example, with reference to, die structureillustrated inmay be die structure-of, and the die structureproviding the data-may be die structure-of. Additionally, or alternatively, the processing core-may receive data (not illustrated) from a processing coreincluded in another die structure(e.g., die structure-of) adjacent to die structure.

2 2 FIGS.C andD 1 FIG. 110 105 105 105 150 150 105 105 105 106 105 105 105 105 150 150 105 110 110 110 110 120 110 110 a d c a b c b d b c d c a b d With reference to, the example die structureis a quad core processor including processing core-through processing core-, and the processing core-may distribute portions or the entirety of data-(and/or the data-generated by processing core-) to processing core-and processing core-via respective I/O interfacesof processing core-, processing core-, and processing core-. Additionally, or alternatively, the processing core-may distribute portions or the entirety of data-(and/or the data-) to a processing core(not illustrated) included in another die structure(e.g., die structure-of) adjacent to die structurein the same semiconductor package (such as in a MCM implementation) or a die structurein a different semiconductor package, via respective I/O interfacesof die structureand the other die structure.

105 150 130 105 150 105 150 150 105 105 106 105 105 d b c c d b c d a d a. 2 FIG.C Processing core-may aggregate and process the data-(e.g., using processing circuitry). In some examples, the processing core-may generate data-in response to processing the received data. In the example of, the processing core-may distribute portions or the entirety of data-(and/or the data-generated by processing core-) to processing core-via respective I/O interfacesof processing core-and processing core-

105 150 130 105 150 105 150 150 105 105 105 150 150 150 105 150 150 150 105 105 150 a c a d a c d a d d e c d d e c d c c e. Processing core-may aggregate and process the data-(e.g., using processing circuitry). In some examples, the processing core-may generate data-in response to processing the received data. In one or more embodiments, processing core-may provide the data-(and/or the data-generated by processing core-) to processing core-. Processing core-may generate data-in response to processing the data-(and/or data-). Processing core-may provide the data-(and/or data-and/or data-) to processing core-, and processing core-may further process and/or forward the data-

105 105 105 105 106 105 110 110 120 105 105 110 110 110 120 c a b d e c d 1 FIG. 1 FIG. Accordingly, for example, the example aspects described herein support implementations in which processing core-may aggregate data from processing core-, processing core-, and processing core-via respective I/O interfaces, and further, aggregate data from a processing core(not illustrated) included in other die structures(e.g., die structure-ofand/or other types of processing cores types) via respective I/O interfaces. Processing core-may provide the entirety or a portion of the aggregated data to a processing core(not illustrated) included in another die structure(e.g., die structure-of) adjacent to die structure, via respective I/O interfaces.

2 FIG.E 2 2 FIGS.B throughD 105 115 105 150 150 150 115 150 105 150 115 150 105 105 115 115 a b In one or more embodiments, with reference toin an example non-limiting implementation, the processing coresmay each include an ADC/DAC converter, and each processing coremay process received datadescribed herein (not illustrated) (e.g., data-, data-, and the like illustrated at) via a respective ADC/DAC converter, prior to processing the received data. In one or more embodiments, each processing coremay process generated datadescribed herein via a respective ADC/DAC converterprior to forwarding the generated datato another processing core. In some example implementations, one or more processing coresmay be absent a respective ADC/DAC converter, or have the ADC/DAC converterin a power-island mode, low-power mode, or turned off (e.g., no power).

2 FIG.F 2 FIG.F 1 FIG. 105 105 105 105 105 106 105 105 110 110 110 120 d a b a c d d illustrates an example data flow in which processing core-may aggregate data from processing core-, data from processing core-(as provided through processing core-), and data from processing core-via I/O interfaces. In the example of, processing core-may provide the entirety or a portion of the aggregated data to a processing core(not illustrated) included in another die structure(e.g., die structure-of) adjacent to die structure, via respective I/O interfaces.

105 110 105 110 110 3 3 FIGS.A andB Accordingly, for example, the processing coresand die structuresdescribed herein support data aggregation and forwarding among different processing coresand different die structures. Example aspects of data aggregation and forwarding among different die structuresare later described with reference to.

105 110 105 105 105 105 105 105 105 106 105 105 105 105 110 110 110 120 2 FIG.G 2 FIG.G 2 FIG.G 1 FIG. c c d a b a d a d d According to one or more embodiments of the present disclosure, the processing coresand die structuresdescribed herein support rerouting (e.g., via routing circuitry described herein) for cases in which a fault is detected in association with a processing core. For example,illustrates an example data flow in which processing core-is defective (e.g., due to a radiation incident such as a single event effect (SEE) affecting the processing core-, a manufacturing defect, a latent manufacturing defect, or the like). In, processing core-may aggregate data from processing core-and processing core-(e.g., via processing core-) via respective I/O interfacesof processing core-and processing core-. In the example of, processing core-may provide the entirety or a portion of the aggregated data to a processing core(not illustrated) included in another die structure(e.g., die structure-of) proximal (temporally or spatially) to die structure, via respective I/O interfaces.

105 Non-limiting examples of the processing coresdescribed herein include general processing cores (e.g., graphics processing units (GPUs)), central processing units (CPUs), microcontrollers, real-time processors, vector processors, digital signal processors (DSPs), radio frequency (RF) transceivers, controllers (e.g., memory controllers, power system controllers), and the like.

105 105 105 110 5 FIG. According to one or more embodiments of the present disclosure, routing and rerouting (e.g., in the case of a detected fault associated with a processing core) among the processing coresmay be implemented based on addresses included an address table (also referred to herein as a routing table) respective to the processing coresand/or the die structures. Example aspects of the addresses and address table are later described with reference to.

105 110 105 110 110 105 105 105 105 110 110 110 110 110 110 105 110 105 As described herein, in accordance with one or more embodiments of the present disclosure described herein, the processing coresand die structuressupport radiation impact-specific additional personalities (e.g., routing configurations) for routing data between processing coresand/or between die structures, in which a subset of chiplets can be configured to run as redundant chiplets. For example, for a die structureincluding an array (e.g., a 4×4 array, 6×6 array, or the like) of processing cores, a subset of the processing coresmay be implemented as redundant processing coresfor cases in which a processing coreincluded in the die structurehas a defect (e.g., due to radiation impact). In another example, for an array (e.g., a 4×4 array, 6×6 array, or the like) of die structures, a subset of the die structuresmay be implemented as redundant die structuresfor cases in which a die structureincluded in array has a defect (e.g., due to radiation impact). A combination of redundant die structures, redundant processing cores, and a mixture of both redundant die structuresand processing coresmay be implemented within the scope of the present disclosure. In one or more embodiments, the techniques described herein may also include utilizing XSR (or other suitable topologies described herein) to behave redundantly and allow reverse data flow to adapt as applicable to work around a chiplet affected by radiation impact.

3 FIG.A 3 FIG.A 300 310 310 305 310 105 300 310 105 305 310 105 110 310 is a block diagram illustrating an example arrayof die structures, in which each die structureincludes multiple processing cores. In this example, the die structuresare 4×4 matrices of processing cores. However, the present disclosure includes an arrayincluding die structureshaving a diverse type of processing corearrays, such as, for example, 1×2, 2×2, 3×2, 3×3, 4×2, 4×3, 4×3, 4×4, and the like. The processing coresand die structuresinclude example aspects of processing coreand die structuredescribed herein, and repeated illustration and descriptions of like elements are omitted for brevity. In the example of, die structuresare labeled ‘00’ through ‘15’.

3 FIG.A 310 305 305 310 305 305 310 305 305 305 310 305 305 305 a a d b a d a b c a a d. Referring to, die structure-includes processing cores-through-, and die structure-includes respective processing cores-through-. In accordance with one or more embodiments of the present disclosure, with reference to example die structure-, the techniques described herein support rotating one or more processing cores(e.g., processing core-, processing core-) in association with a target configuration for die structure-. For example, rotating one or more processing coressupports routing between processing core-through processing core-

310 305 305 305 310 305 305 305 305 100 305 100 305 305 100 305 305 305 100 b b c b a d In a similar example, with reference to example die structure-, the techniques described herein support rotating one or more processing cores(e.g., processing core-, processing core-) in association with a target configuration for die structure-. For example, rotating one or more processing coressupports routing between processing core-through processing core-. In some example implementations, the processing coresincluded on the wafermay be designed or arranged such that all of the processing coresare of the same orientation throughout the reticle and/or throughout the wafer. In some other example implementations, the processing coresmay be designed or arranged such that one or more of the processing coresincluded on the semiconductor waferis of a different orientation (e.g., is a rotated version) compared to other processing cores. It should be appreciated that such rotating enables aligning a transmit of one processing coreto a receive of another processing corewhile both still may have the same floorplan (on the wafer). Such a configuration is advantageous because there is only one floorplan to design and validate, and then just a rotation / reorientation during fabrication may be applied to assemble a larger array.

305 310 310 305 310 305 310 310 305 305 310 305 305 b b a b c 3 FIG.A In some example implementations, the processing coresof a given die structure(e.g., die structure-) may be designed or arranged such that all of the processing coresof the die structureare of the same orientation. In some other example implementations, the processing coresof a given die structure(e.g., die structure-) may be designed or arranged such that one or more of the processing coresis of a different orientation (e.g., is a rotated version) compared to other processing cores. For example, as indicated by the rotated numbers ‘1’ and ‘3’ illustrated with respect to the die structure-of, processing core-and processing core-have each been rotated 180 degrees.

3 FIG.B 3 FIG.A 3 FIG.A 301 310 310 350 310 305 305 350 305 350 350 305 350 350 305 305 350 350 350 305 350 305 305 350 350 350 350 310 b b a b b a a a a b a a a d d b a c d a c c c a b d c illustrates an example block diagramof the die structure-of, in which the die structure-implements an alternate data flow for processing and routing data-received at the die structure-due to a defect associated with processing core-. For example, processing core-receives the data-. Processing core-may process data-and provide data-(e.g., generated by-in response to processing data-) and/or data-to processing core-. Processing core-may process data-(and/or data-) and provide data-(e.g., generated by-in response to processing data-and/or b) to processing core-. Processing core-may process data-(and/or data-or data-) and provide data-to die structure-of.

3 FIG.C 3 FIG.A 3 FIG.C 302 310 305 305 305 305 310 305 350 305 305 305 350 305 305 305 305 305 305 b a d b c b a e a d b f b c a d b c illustrates an example block diagramof the die structure-ofaccording to another routing configuration. In the example of, data processing may respectively be performed in parallel by a first column (e.g., including processing core-and processing core-) and a second column (e.g., including processing core-and processing core-), without intercommunication between the first column and the second column. It is worth noting that this parallel processing is enabled by a change in the routing table discussed herein, and that the die structure-is physically laid out as discussed previously. For example, processing core-may pass data-(e.g., as generated by or received by processing core-) to processing core-, and processing core-may pass data-(e.g., as generated by or received by processing core-) to processing core-. In some embodiments, the data path between processing core-and processing core-and/or the data path between processing core-and processing core-may be implemented for redundancy as described above, or implemented to enable parallel processing (e.g., polar digital signal processing, GPU-style processing, processing related to artificial intelligence, machine learning, cryptology, video processing, or signal processing, and the like).

4 4 FIGS.A throughD 4 4 FIGS.B throughD 3 FIG.A 4 4 FIGS.B throughD 401 403 310 305 305 310 310 305 a d are examples illustrating aspects of route options and which routing is available as described herein.illustrate examplesthroughof propagating data between die structures(and respective processing cores-through-included in each of the die structures) in accordance with one or more embodiments of the present disclosure. Aspects of propagating data between the die structures(and the included processing cores) are described with reference toand.

4 FIG.A 3 FIG.A 4 FIG.A 3 FIG.A 400 310 305 305 305 310 400 300 400 305 310 400 a d b a With reference to, the propagation of data and the timing associated with accessing or sampling the data may be indicated by an identifierof ‘ABC.D, ’ where ‘A’ refers to a sample time (e.g., temporal instance or temporal period), ‘BC’ refers to die structure(e.g., among die structures labeled ‘00’ through ‘15’ in), and ‘D’ refers to a processing core(e.g., one of processing core-through processing core-) of the die structure. In an example, with reference to the identifierinand the arrayin, the identifierof ‘A00.1’ refers to a sample time ‘A’ associated with accessing data from processing core-(processing core ‘1’) of die structure-(die structure ‘00’). The identifier(and other identifiers) may be included in an address table as described herein.

401 405 305 310 400 305 130 405 305 400 106 106 106 120 120 400 305 120 120 401 120 120 a a a a a b c a b a a b a b 3 FIG.A 2 2 FIGS.A throughG Exampleillustrates various candidate routing pathsusable by processing core-(‘0’) included in the die structure-(‘00’) of. Based on the identifierand corresponding information included in an address table described herein, the processing core-may identify (e.g., by processing circuitrydescribed herein and illustrated in) what data to access, aggregate, and/or process, and further, a routing pathvia which to propagate or pass the data. For example, the processing core-may identify, based on the identifier, whether to propagate the data via an I/O interface-(e.g., a ‘North’ I/O interface), an I/O interface-(e.g., an ‘East’ I/O interface), an I/O interface-(e.g., a ‘South’ I/O interface), an I/O interface-(e.g., an XSR interface), or an I/O interface-(e.g., an XSR interface). Based on the identifier, the processing core-may identify a corresponding entity to which to propagate the data. Although I/O interface-and I/O interface-are illustrated in the example, embodiments of the present disclosure are not limited thereto. For example, in some cases, one of I/O interface-or I/O interface-may be omitted.

400 305 310 402 403 405 401 403 405 In one or more embodiments, the identifiermay be associated with a routing ‘personality’ described herein for activating a redundant path (e.g., for cases in which a processing coreis defective). In some aspects, the routing ‘personality’ may provide a means of identifying a particular die (e.g., die structure) of an array of die within a device. Embodiments of the present disclosure may include programming the routing ‘personalities’ into the fuse block or memory (e.g., non-volatile memory (NVM) on the die. Exampleand examplefurther illustrate examples of routing pathsbeing used in association with propagating or passing data. Referring to examplesthrough, selected or active routing paths among the available routing pathsare indicated as bold arrows.

5 FIG. 1 FIG. 500 105 107 105 113 505 105 is an example viewof processing coresand reticle scribe linesdescribed with reference to, in which the processing coresare spaced apart by a target distance(also referred to herein as a gap or the target kerf) supportive of high-bandwidth connections(e.g., XSR, USR, serial interfaces, parallel interfaces, and the like) described herein between neighboring processing cores.

113 100 107 110 105 107 505 105 105 110 505 105 100 100 105 100 107 113 107 105 105 According to one or more embodiments of the present disclosure, the target distancesupports slicing of the semiconductor wafer, along the scribe lines, into dies (e.g., die structureseach including one or more processing cores). In some cases, slicing along the scribe linesincludes slicing across one or more high-bandwidth connections, which differs from other semiconductor wafers for implementing multi-chip designs, as such other approaches do not provide interconnectivity between adjacent processing coresunless the processing coresare intended to be incorporated in the same die structure. In contrast, the techniques described herein include high-bandwidth connectionsbetween all adjacent processing coresin the semiconductor wafer, which provides increased design flexibility while reducing design overhead. For example and without limitation, a wafercan be provided with uniformly-designed processing coresacross the surface area of the wafer. The scribe linesare designed to have a kerf width of the target distance, which in accordance with one or more embodiments of the present disclosure, allow for dicing along the scribe lineif desired, or maintaining high-speed communications connections between cores, for cases of coreswhich are not separated from each other during the dicing process.

5 FIG. 105 510 515 510 With reference to, each processing coreincludes an active area(including one or more circuits) and a crackstop structuresurrounding the active area.

105 100 107 100 100 105 According to one or more embodiments of the present disclosure, separating the processing coresfrom a semiconductor wafermay be based on scribe linesdefined by a reticle set. In one or more embodiments, the present disclosure supports techniques for updating one or more design rule check (DRC) rules corresponding to reticle boundaries associated with the reticle set and the semiconductor wafer. For example, in some cases, foundry capabilities for fabricating a given semiconductor wafer(and processing coresincluded therein) may be reduced compared to other foundries, and the systems and techniques described herein may include updating one or more DRC rules corresponding to reticle boundaries based on such foundry capabilities.

6 FIG. 6 FIG. 600 110 610 615 620 625 110 603 625 110 is a plan viewillustrating example aspects of adjacent die structures(e.g., Die 1, Die 2) in accordance with one or more embodiments of the present disclosure. Examples of a guard edge, a guard ring(also referred to herein as a guard ring structure), a chip seal, and chip edgeof each die structureis illustrated at. In accordance with one or more embodiments of the present disclosure, scribe lines(kerf) are implemented at the chip edgesof the die structures.

605 110 605 505 5 FIG. Signal route(also referred to herein as die-to-die signal routing) supports communication between the die structures. Signal routeincludes aspects of high-bandwidth connectionsdescribed with reference to.

7 FIG.A 7 FIG.A 700 700 710 710 710 110 615 620 710 a e is a cross-sectional viewillustrating example aspects of a chip seal and guard ring in accordance with one or more embodiments of the present disclosure. Cross-sectional viewillustrates examples of metal layers(e.g., metal layer-through metal layer-) and vias 715 (i.e., metal layer to metal layer vias) supportive of die structuresand scalable partitioning in accordance with one or more embodiments of the present disclosure. Although not illustrated with reference to, embodiments of the present disclosure include implementing the guard ringand chip sealin each of the metal layers.

7 FIG.B 7 FIG.B 6 FIG. 7 FIG.B 705 605 705 630 605 620 is a cross-sectional viewillustrating example aspects of a chip seal, guard ring, and die-to-die signal routein accordance with one or more embodiments of the present disclosure.is a cross-sectional viewtaken along the cross section lineof.illustrates an example of the signal routepassing through the chip seal(chip seal rail).

7 FIG.B 605 710 605 710 710 605 710 615 620 b c In the example of, the signal routemay be implemented at metal layer-, but embodiments of the present disclosure are not limited thereto. For example, the signal routemay be implemented at another metal layer (e.g., metal layer-) of the metal layers. In some aspects, the signal routeis electrically isolated from other metal layers, and more particularly, from the guard ringand chip seal.

705 615 620 605 515 515 515 5 FIG. Cross-sectional viewillustrates example aspects of tunneling for extending through the guard ringand chip seal. For example, the signal routemay be implemented using a tunneling layer which extends through the crackstop structureof. In one or more embodiments, the tunneling layer is electrically isolated from the crackstop structure. In one or more embodiments, the tunneling layer may extend under, above, or through the crackstop structure.

635 605 105 110 105 110 603 6 FIG. In some embodiments, the tunneling layer can be any metal layer within the metal layer stack of the design. In some aspects, the techniques described herein may include selecting the tunneling layerbased on the wafer foundry and foundry design rules. For example, in some cases, based on the wafer foundry and foundry design rules, the techniques described herein may include selecting one of the upper and thicker layer metals to be the layer where the crackstop is not continuous. In some embodiments, as illustrated at, signal routingpasses from one processing core (e.g., a processing coreof a die structure) to the next processing core (e.g., another processing coreof another die structure) across the scribe lines(kerf) and is electrically isolated from the crackstop.

8 FIG. 800 800 100 illustrates an example flowchart of a methodof manufacturing a plurality of die structures in accordance with one or more embodiments of the present disclosure. The methodmay be implemented in association with manufacturing a semiconductor waferdescribed herein in accordance with one or more embodiments of the present disclosure.

805 800 At, the methodincludes fabricating a plurality of processing cores on a semiconductor wafer based on a reticle set defining scribe lines associated with separating the plurality of processing cores from the semiconductor wafer.

810 800 In some aspects, at, the methodmay include forming, in association with each processing core of the plurality of processing cores: an active area including one or more circuits; a crackstop structure surrounding the active area; and a scribe area associated with separating one or more die structures of the plurality of die structures from the semiconductor wafer.

815 800 In some aspects, at, the methodmay include forming a tunneling layer extending under, above, or through the crackstop structure, where the tunneling layer is electrically isolated from the crackstop structure.

820 800 In some aspects, fabricating the plurality of processing cores may include fabricating at least one processing core of the plurality of processing cores with a different orientation relative to at least one other processing core, said different orientation being based on a target configuration of a die structure, and fabricating the plurality of processing cores is based at least in part on the target configuration. In an example, at, the methodmay include rotating at least one processing core of the plurality of processing cores in association with a target configuration of a die structure, where fabricating the plurality of processing cores is based on the target configuration.

800 825 800 In some aspects, at least one die structure of the plurality of die structures may be fabricated to have a different orientation relative to at least one other die structure of the plurality of die structures, said different orientation being based on a target configuration of the plurality of die structures on the semiconductor wafer, wherein fabricating the plurality of processing cores is based at least in part on the target configuration. For example, the methodmay include fabricating at least one die structure of the plurality of die structures to have a different orientation relative to at least one other die structure of the plurality of die structures, based on a target configuration. In an example, at, the methodmay include rotating at least one die structure of the plurality of die structures in association with a target configuration, where fabricating the plurality of processing cores is based on the target configuration.

830 800 At, the methodincludes separating the plurality of die structures from the semiconductor wafer based on the reticle set and a target quantity of processing cores for at least one die structure of the plurality of die structures. In some aspects, separating the plurality of die structures from the semiconductor wafer includes cutting the semiconductor wafer based on the scribe lines. In some aspects, the plurality of processing cores are spaced apart by a target distance associated with separating one or more processing cores of the plurality of processing cores or one or more die structures of the plurality of die structures from the semiconductor wafer.

In the descriptions of the flowcharts herein, the operations may be performed in a different order than the order shown, or the operations may be performed in different orders or at different times. Certain operations may also be left out of the flowcharts, one or more operations may be repeated, or other operations may be added to the flowcharts.

Embodiment 1. A semiconductor wafer comprising: a plurality of processing cores; and a plurality of die structures each comprising at least one processing core of the plurality of processing cores, wherein each processing core comprises: a set of first input output (I/O) interfaces configured for communication between the processing core and at least one second processing core of the plurality of processing cores, wherein the processing core and the at least one second processing core are comprised in a first die structure of the plurality of die structures; and a second input output (I/O) interface configured for communication between the processing core and at least one third processing core of the plurality of processing cores, wherein the at least one third processing core is comprised in a second die structure of the plurality of die structures, wherein the plurality of processing cores are spaced apart by a target distance associated with separating one or more processing cores of the plurality of processing cores or one or more die structures of the plurality of die structures from the semiconductor wafer.

Embodiment 2. The semiconductor wafer as in any prior embodiment, wherein each processing core comprises: processing circuitry configured to aggregate and process first data received from the at least one second processing core, wherein the processing circuitry generates second data in response to processing the first data; and routing circuitry configured to route the first data, the second data, or both to at least one fourth processing core comprised in the first die structure or to the at least one third processing core comprised in the second die structure.

Embodiment 3. The semiconductor wafer as in any prior embodiment, wherein the routing circuitry is configured to route the first data, the second data, or both based on an address table associated with the plurality of processing cores, the plurality of die structures, or both.

Embodiment 4. The semiconductor wafer as in any prior embodiment, wherein the routing circuitry is configured to reroute the first data, the second data, or both based on a detected fault associated with the at least one fourth processing core or to the at least one third processing core.

Embodiment 5. The semiconductor wafer as in any prior embodiment, wherein the first die structure comprises: processing circuitry configured to at least one of aggregate and process first data received from at least the second die structure of the plurality of die structures, wherein the processing circuitry generates second data in response to processing the first data; and routing circuitry configured to route the first data, the second data, or both to at least one third die structure of the plurality of die structures.

Embodiment 6. The semiconductor wafer as in any prior embodiment, wherein the routing circuitry is configured to route the first data, the second data, or both based on an address table associated with the plurality of die structures.

Embodiment 7. The semiconductor wafer as in any prior embodiment, wherein the routing circuitry is configured to reroute the first data, the second data, or both based on a detected fault associated with the at least one third die structure.

Embodiment 8. The semiconductor wafer as in any prior embodiment, wherein the second I/O interface is configured for extra short reach (XSR) communications, very short reach (VSR) communications, or ultra short reach (USR) communications, among the plurality of processing cores.

Embodiment 9. The semiconductor wafer as in any prior embodiment, wherein the first I/O interface, the second I/O interface, or both comprises a serial interface or a parallel interface.

Embodiment 10. The semiconductor wafer as in any prior embodiment, wherein each processing core comprises: an active area comprising one or more circuits; and a crackstop structure surrounding the active area; and a scribe area associated with separating one or more die structures of the plurality of die structures from the semiconductor wafer.

Embodiment 11. The semiconductor wafer as in any prior embodiment, further comprising: a tunneling layer extending under, above, or through the crackstop structure, wherein the tunneling layer is electrically isolated from the crackstop structure.

Embodiment 12. The semiconductor wafer as in any prior embodiment, wherein each processing core further comprises: first electrostatic discharge (ESD) protection circuitry associated with the first set of I/O interfaces; and second ESD processing circuitry associated with the second I/O interface.

Embodiment 13. The semiconductor wafer as in any prior embodiment, wherein respective structures of the plurality of processing cores are identical.

Embodiment 14. The semiconductor wafer as in any prior embodiment, wherein a structure of at least one processing core of the plurality of processing cores is different from a structure of at least one other processing core of the plurality of processing cores.

Embodiment 15. The semiconductor wafer as in any prior embodiment, wherein the second die structure is adjacent the first die structure.

Embodiment 16. A method of manufacturing a plurality of die structures, the method comprising: fabricating a plurality of processing cores on a semiconductor wafer based on a reticle set defining scribe lines associated with separating the plurality of processing cores from the semiconductor wafer; and separating the plurality of die structures from the semiconductor wafer based on the reticle set and a target quantity of processing cores for at least one die structure of the plurality of die structures, wherein separating the plurality of die structures from the semiconductor wafer comprises cutting the semiconductor wafer based on the scribe lines, wherein the plurality of processing cores are spaced apart by a target distance associated with separating one or more processing cores of the plurality of processing cores or one or more die structures of the plurality of die structures from the semiconductor wafer.

Embodiment 17. The method as in any prior embodiment, further comprising forming, in association with each processing core of the plurality of processing cores: an active area comprising one or more circuits; a crackstop structure surrounding the active area; and a scribe area associated with separating one or more die structures of the plurality of die structures from the semiconductor wafer.

Embodiment 18. The method as in any prior embodiment, further comprising: forming a tunneling layer extending under, above, or through the crackstop structure, wherein the tunneling layer is electrically isolated from the crackstop structure.

Embodiment 19. The method as in any prior embodiment, wherein fabricating the plurality of processing cores includes fabricating at least one processing core of the plurality of processing cores with a different orientation relative to at least one other processing core, said different orientation being based on a target configuration of a die structure, and fabricating the plurality of processing cores is based at least in part on the target configuration.

Embodiment 20. The method as in any prior embodiment, wherein at least one die structure of the plurality of die structures is fabricated to have a different orientation relative to at least one other die structure of the plurality of die structures, said different orientation being based on a target configuration of the plurality of die structures on the semiconductor wafer, wherein fabricating the plurality of processing cores is based at least in part on the target configuration.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form detailed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the various embodiments with various modifications as are suited to the particular use contemplated.

While the preferred embodiments have been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the disclosure as first described.