Storage System Including Host Device and Storage Device, Operation Method Thereof and Operation Method of Storage Device

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2024-0126655 filed on Sep. 19, 2024, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties.

Some example embodiments described herein relate to a semiconductor memory, and more particularly, relate to a storage system including a host device and a storage device, an operation method thereof, and/or an operation method of the storage device.

A semiconductor memory may be classified as a volatile memory, which loses data stored therein when a power is turned off and may include memory such as a static random access memory (SRAM) and/or a dynamic random access memory (DRAM). Alternatively a semiconductor memory may be classified as a nonvolatile memory, which retains data stored therein even when a power is turned off, and may include memory such as one or more of a flash memory, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), or a ferroelectric RAM (FRAM).

A flash memory is being widely used as a high-capacity storage medium. A storage device refers to a device, which stores data under control of a host device, such as a computer, a smartphone, or a smart pad. The storage device includes a device which stores data on a magnetic disk, such as a hard disk drive (HDD), or a device which stores data in a semiconductor memory, in particular, a nonvolatile memory, such as a solid state drive (SSD) or a memory card.

With the development of semiconductor fabrication technologies, the capacity of data which are sent to the storage device from a host device such as from a computer, a smartphone, or a smart pad is increasing. In this case, a storage capacity of a buffer memory included in the storage device and provided for data integrity verification or data integrity checking of data received from the host device may be insufficient. Accordingly, there is a desire on a storage device which performs data integrity verification by using a buffer memory with a small storage capacity.

Some example embodiments may provide a storage system including a host device and a storage device and providing improved performance, an operation method thereof, and an operation method of the storage device.

According to some example embodiments, an operation method of a storage device includes receiving first and second write data from an external device, the first and second write data among a plurality of write data included in a first chunk, generating first verification sub-hash data and second verification sub-hash data respectively corresponding to the first write data and the second write data, updating an integrity hash map by storing the first verification sub-hash data and the second verification sub-hash data in the integrity hash map, and performing data integrity verification for the plurality of write data, based on a completion of the integrity hash map updating. The storage device includes a buffer memory configured to store the integrity hash map and having a storage capacity smaller than a data size of the first chunk.

Alternatively or additionally according to some example embodiments, a storage system includes a host device and a storage device. The host device is configured to generate a plurality of host sub-hash data respectively corresponding to a plurality of write data included in a first chunk, generate host hash data based on the plurality of host sub-hash data, generate signature data based on the host hash data, and send the plurality of write data and the signature data to the storage device. The storage device is configured to generate an integrity hash map corresponding to the first chunk and based on the plurality of write data, and perform data integrity verification for the plurality of write data based on the integrity hash map being completed and on the signature data.

Alternatively or additionally according to some example embodiments, an operation method of a storage system which includes a host device and a storage device includes generating, by the host device, a plurality of host sub-hash data respectively corresponding to a plurality of write data included in a first chunk, generating, by the host device, signature data based on the plurality of host sub-hash data, sending, by the host device and to the storage device, first write data and second write data among the plurality of write data, generating, by the storage device, first verification sub-hash data and second verification sub-hash data respectively corresponding to the first write data and the second write data, updating, by the storage device, an integrity hash map by storing the first verification sub-hash data and the second verification sub-hash data in the integrity hash map, and performing, by the storage device, data integrity verification for the plurality of write data, based on the integrity hash map completed. The storage device includes a buffer memory storing the integrity hash map and having a storage capacity smaller than a data size of the first chunk.

Below, some example embodiments will be described in detail and clearly to such an extent that one skilled in the art easily carries out inventive concepts.

In the specification, function blocks of drawings, which respectively correspond to the terms “block”, “unit”, “logic”, etc., may be implemented in the form of software, hardware, or a combination thereof.

1 FIG. 1 FIG. 10 100 200 10 is a block diagram illustrating a storage system according to some example embodiments. Referring to, a storage systemmay include an external device such as a host deviceand a storage device. In an some example, the storage systemmay refer to a computing system, which is configured to process a variety of information, and may include one or more devices such as one or more of a personal computer (PC), a notebook, a laptop, a server, a workstation, a tablet PC, or a smartphone.

100 200 100 200 200 The host devicemay be configured to control the storage device. For example, based on a given interface, the host devicemay store data in the storage deviceand/or may read data stored in the storage device. In some example embodiments, the given interface may include at least one of various interfaces such as an ATA (Advanced Technology Attachment) interface, an SATA (Serial ATA) interface, an e-SATA (external SATA) interface, an SCSI (Small Computer Small Interface) interface, an SAS (Serial Attached SCSI) interface, a PCI (Peripheral Component Interconnection) interface, a PCIe (PCI express) interface, an NVMe (NVM express) interface, an IEEE 1394 interface, an USB (Universal Serial Bus) interface, an SD (Secure Digital) card interface, an MMC (Multi-Media Card) interface, an eMMC (embedded Multi-Media Card) interface, an eUFS (embedded Universal Flash Storage) interface, a CF (Compact Flash) card interface, a CXL (Compute eXpress Link) interface, and a UFS (Universal Flash Storage) interface.

100 110 110 200 100 100 110 100 200 The host devicemay include a host integrity manager. The host integrity managermay generate host hash data based on a plurality of write data to be sent to the storage devicefrom the host device. For example, based on a plurality of write data included in a first chunk, the host devicemay generate host hash data corresponding to the first chunk. The host integrity managermay generate signature data based on the host hash data. Accordingly, the signature data may correspond to the first chunk. The host devicemay send the plurality of write data of the first chunk and the signature data corresponding to the first chunk to the storage device.

200 210 220 100 210 100 220 220 100 210 220 220 220 The storage devicemay include a storage controllerand a non-volatile memory device. In response to a request from the host device, the storage controllermay store data “DATA” (e.g., write data received from the host device) in the non-volatile memory device, and/or may send the data “DATA” stored in the non-volatile memory deviceto the host device. The storage controllermay send a command CMD and an address ADD to the non-volatile memory deviceto store the data “DATA” in the non-volatile memory deviceor to read the data “DATA” stored in the non-volatile memory device.

210 220 210 220 220 Under control of the storage controller, the non-volatile memory devicemay store the data “DATA” and/or may transfer the stored data “DATA” to the storage controller. In some example embodiments, the non-volatile memory devicemay be a NAND flash memory device, but the present disclosure is not limited thereto. In some example embodiments, the non-volatile memory devicemay include a memory cell array configured to store the data “DATA”. For example, the memory cell array may include a plurality of memory cells. In some examples, each of the plurality of memory cells may be or may include FLASH memory cells, such as at least one of single-level cells, multi-level cells, or triple-level cells; example embodiments are not limited thereto.

210 211 212 213 211 100 In some example embodiments, the storage controllermay include a storage integrity manager, a buffer memory, and a data manager. The storage integrity managermay generate an integrity hash map IHM based on the write data received from the host device.

200 100 211 211 211 6 8 9 FIGS.B,, and For example, the storage devicemay receive the plurality of write data included in the first chunk and the signature data corresponding to the first chunk from the host device. In this case, the storage integrity managermay generate the integrity hash map IHM corresponding to the first chunk, based on the plurality of write data. After the generation of the integrity hash map IHM is completed, the storage integrity managermay perform data integrity checking or data integrity verification for the plurality of write data, based on the completed integrity hash map IHM and the signature data. Operations related to the data integrity verification of the storage integrity managerwill be described in more detail with reference to.

212 210 212 220 220 212 212 212 220 The buffer memorymay be configured to store a variety of information necessary for the storage controllerto operate. For example, the buffer memorymay temporarily store data to be stored in the non-volatile memory deviceor data read from the non-volatile memory device. In some example embodiments, the buffer memorymay store the integrity hash map IHM. For example, the buffer memorymay be implemented with one or more of a static random access memory (SRAM), a dynamic random access memory (DRAM), etc. The buffer memorymay operate at a faster read and/or write speed than that of the non-volatile memory device; example embodiments are not limited thereto.

213 100 220 213 100 220 213 100 220 213 212 The data managermay manage the write data received from the host deviceand/or the data read from the non-volatile memory device. In some example embodiments, the data managermay store the plurality of write data included in the first chunk, which are received from the host device, in the non-volatile memory device. In some example embodiments, the data managermay store the plurality of write data received from the host devicein the memory cell array of the non-volatile memory device. Meanwhile, the data managermay store, in the buffer memory, only the write data being currently used for the update of the integrity hash map IHM from among the plurality of write data of the first chunk.

200 100 200 212 212 200 For example, unlike the above description, the storage devicemay perform the data integrity verification for the write data of the first chunk received from the host devicewithout generating the integrity hash map IHM. In this case, for the data integrity verification, the storage deviceshould store all the write data of the first chunk in the buffer memory. Accordingly, the buffer memoryshould have a storage capacity larger than a data size of the first chunk. According to the above description, costs necessary to manufacture the storage devicemay increase.

200 100 200 212 200 212 212 In contrast, as described above, the storage deviceaccording to some example embodiments may perform the data integrity verification or checking for the write data received from the host devicebased on the integrity hash map IHM. To perform the data integrity verification for the write data, the storage devicemay store, in the buffer memory, the integrity hash map IHM whose size is smaller than the data size of the first chunk. Alternatively or additionally, the storage devicemay not store, in the buffer memory, the remaining write data among the plurality of write data of the first chunk other than the write data being currently used to update the integrity hash map IHM. For example, the buffer memorymay have a storage capacity smaller than the data size of the first chunk. Accordingly, a storage device with improved performance, a storage system including the storage device, and/or an operation method thereof may be provided.

2 FIG. 1 FIG. 2 FIG. 210 211 212 213 214 215 216 217 218 219 is a block diagram for describing a storage controller of. Referring to, the storage controllermay include the storage integrity manager, the buffer memory, the data manager, a processor, a flash translation layer (FTL), a read only memory (ROM), an error correction code (ECC) engine, a host interface circuit, and a non-volatile memory interface circuit.

211 212 213 214 215 216 217 218 219 The storage integrity manager, the buffer memory, the data manager, the processor, the FTL, the ROM, the ECC engine, the host interface circuit, and the non-volatile memory interface circuitmay be connected to each other through a bus, such as a wired bus and/or a wireless buss.

211 212 213 1 FIG. The storage integrity manager, the buffer memory, and the data managerare described with reference to, and thus, additional description will be omitted to avoid redundancy.

214 210 214 210 214 220 100 The processormay control some or all the operations of the storage controller. For example, the processormay execute an operating system or firmware for driving the storage controller. The processormay generate the address ADD and the command CMD for controlling the non-volatile memory device, based on a request of the host device.

215 100 220 215 220 The FTLmay perform a role of mapping a logical address received from the host deviceto a physical address used in the non-volatile memory device. In some example embodiments, the FTLmay perform the reliability management operations for the non-volatile memory device.

216 210 216 The ROMmay be used as a read only memory which stores information necessary or used in the operation of the storage controller. For example, the ROMmay be used as a portion of a firmware memory.

217 220 217 217 The ECC enginemay detect and correct an error of data read from the non-volatile memory device. For example, the ECC enginemay have an error correction capability of a given level. The ECC enginemay correct an error of data not exceeding the error correction capability and may treat data whose error level (e.g., of which the number of flipped bits) exceeds the error correction capability as an uncorrectable error.

210 100 218 218 218 The storage controllermay communicate with the host devicethrough the host interface circuit. The host interface circuitmay provide a host interface layer (HIL). In some example embodiments, the host interface circuitmay be implemented based on at least one of various interfaces such as a serial ATA (SATA) interface, a peripheral component interconnect express (PCIe) interface, a serial attached SCSI (SAS), a non-volatile memory express (NVMe) interface, and a universal flash storage (UFS) interface.

210 220 219 219 The storage controllermay communicate with the non-volatile memory devicethrough the non-volatile memory interface circuit. In some embodiments, the non-volatile memory interface circuitmay be implemented based on the NAND interface.

211 213 211 213 210 211 213 220 212 214 In some example embodiments, the storage integrity managerand the data managermay be implemented by hardware, software, or a combination of hardware and software. For example, at least part of the storage integrity managerand the data managermay be included in the storage controllerin the form of a separate circuit, a separate device, or a separate chip. Alternatively, at least part of the storage integrity managerand the data managermay be stored in the non-volatile memory devicein the form of an instruction or may be implemented with a software module to be loaded to the buffer memoryby the processor.

3 FIG. 1 FIG. 3 FIG. 110 1 110 is a diagram for describing an example of an operation of a storage system of. Referring to, in a first operation {circle around (1)}, the host integrity managermay generate host hash data HHA based on a first chunk CHK. Also, the host integrity managermay generate signature data SIG based on the host hash data HHA.

110 1 110 1 1 110 For example, the host integrity managermay apply a hash function such as but not limited to a secure hash function such as SHA-2 to the first chunk CHKto generate the host hash data HHA. For example, the host integrity managermay apply the hash function to all the write data WDto WDn included in the first chunk CHKto generate the host hash data HHA. The host integrity managermay encrypt the host hash data HHA to generate the signature data SIG. For example, the signature data SIG may be a result of encrypting the host hash data HHA with a signature key.

100 200 1 The chunk may refer to a series of data sets. For example, the host devicemay send the software to the storage device. In this case, the software may be composed of a plurality of chunks including the first chunk CHK. Each of the plurality of chunks may include a plurality of write data.

100 1 1 200 100 1 1 200 100 1 1 200 In a second operation {circle around (2)}, the host devicemay send the plurality of write data WDto WDn included in the first chunk CHKand the signature data SIG to the storage device. For example, the host devicemay separate or partition the plurality of write data WDto WDn included in the first chunk CHKby a given unit, so as to be sent to the storage device. For example, the host devicemay separate the write data WDto WDn included in the first chunk CHKin units of two data, so as to be sent to the storage device.

200 100 212 200 1 2 100 1 2 212 In a third operation {circle around (3)}, the storage devicemay store the plurality of write data received from the host devicein the buffer memory. For example, the storage devicemay receive the first write data WDand the second write data WDfrom the host deviceand may store the first write data WDand the second write data WDin the buffer memory.

200 1 1 212 1 1 100 200 1 212 1 100 In a fourth operation {circle around (4)}, the storage devicemay check whether all the write data WDto WDn of the first chunk CHKare stored in the buffer memory(e.g., whether all the write data WDto WDn of the first chunk CHKare received from the host device). In some example embodiments, the storage devicemay check whether the signature data SIG corresponding to the first chunk CHKare stored in the buffer memory(e.g., whether the signature data SIG corresponding to the first chunk CHKare received from the host device).

1 1 1 212 200 1 212 211 1 212 1 110 When both the signature data SIG corresponding to the first chunk CHKand the write data WDto WDn of the first chunk CHKare stored in the buffer memory, in a fifth operation {circle around (5)}, the storage devicemay generate verification hash data VHA based on the plurality of write data WDto WDn stored in the buffer memory. For example, the storage integrity managermay apply the hash function to all the write data WDto WDn stored in the buffer memoryto generate the verification hash data VHA. Accordingly, the verification hash data VHA may correspond to or fingerprint the first chunk CHK. In some example embodiments, the hash function may be the same as the hash function used for the host integrity managerto generate the host hash data HHA.

200 211 In a sixth operation {circle around (6)}, the storage devicemay decrypt the signature data SIG to obtain the host hash data HHA. For example, the storage integrity managermay decrypt the signature data SIG based on the signature key and may obtain the host hash data HHA.

100 200 For example, the host deviceand the storage devicemay share the signature key which is used to generate the signature data SIG (e.g., to encrypt the host hash data HHA) and/or to decrypt the signature data SIG (e.g., to obtain the host hash data HHA). The encryption and/or the decryption may be or include a public-key base encryption/decryption, and/or be or include a private-key based encryption/decryption; example embodiments are not limited thereto.

200 1 1 211 211 1 1 1 In a seventh operation {circle around (7)}, the storage devicemay perform the data integrity verification for the write data WDto WDn of the first chunk CHK. For example, the storage integrity managermay perform the data integrity verification based on whether the verification hash data VHA are the same as the host hash data HHA obtained from the signature data SIG. When the verification hash data VHA are the same as the host hash data HHA, the storage integrity managermay determine that the data integrity verification for the write data WDto WDn of the first chunk CHKsucceeds (e.g., that the data integrity of the write data WDto WDn is secured).

1 200 1 1 220 When the data integrity verification for the plurality of write data WDto WDn succeeds, in an eighth operation {circle around (8)}, the storage devicemay store the write data WDto WDn of the first chunk CHKin the non-volatile memory device.

3 FIG. 100 1 1 200 1 1 100 200 1 1 212 212 1 200 Referring to the example of, as described above, the host devicemay generate the host hash data HHA by applying the hash function to all the write data WDto WDn included in the first chunk CHKonce. Meanwhile, the storage devicemay generate the verification hash data VHA corresponding to the host hash data HHA by applying the hash function to all the write data WDto WDn of the first chunk CHKreceived from the host deviceonce. Accordingly, the storage devicemay generate the verification hash data VHA only when all the write data WDto WDn included in the first chunk CHKare stored in the buffer memory. This indicates that the storage capacity of the buffer memoryshould be larger than the data size of the first chunk CHK. In this case, costs necessary to manufacture the storage devicemay increase.

1 200 1 220 1 Alternatively or additionally, after the data integrity verification for the plurality of write data WDto WDn is completed, the storage devicemay store the plurality of write data WDto WDn in the non-volatile memory device. In this case, the data integrity verification and the write operation related to the plurality of write data WDto WDn may cause the increase in latency.

10 1 1 10 1 212 1 1 212 212 1 According to some example embodiments however, the storage systemmay perform the data integrity verification for the write data WDto WDn of the first chunk CHKbased on an integrity hash map IMH. In this case, the storage systemmay store the integrity hash map IMH whose size is smaller than the data size of the first chunk CHKin the buffer memory, without storing all the write data WDto WDn of the first chunk CHKin the buffer memory. Accordingly, the storage capacity of the buffer memorymay be smaller than the data size of the first chunk CHK.

10 1 1 Alternatively or additionally, the storage systemmay perform the data integrity verification and the write operation for the plurality of write data WDto WDn in parallel. This may indicate that the latency caused due to the data integrity verification and the write operation related to the plurality of write data WDto WDn decreases.

Accordingly, according to some example embodiments, a storage device with improved performance, a storage system including the storage device, and an operation method thereof are provided. A storage system according to some example embodiments will be described in detail with reference to the following drawings.

4 FIG. 1 FIG. 1 2 4 FIGS.,, and 110 100 1 1 is a flowchart for describing an operation method of a host device of. Referring to, in operation S, the host devicemay generate a plurality of host sub-hash data HSH respectively corresponding to a plurality of write data (e.g., WDto WDn) included in the first chunk CHK.

120 100 In operation S, the host devicemay generate the host hash data HHA based on the plurality of host sub-hash data HSH.

130 100 100 In operation S, the host devicemay generate the signature data SIG based on the host hash data HHA. The host devicemay encrypt the host hash data HHA to generate the signature data SIG; the encryption may be or may include a public-key encryption and/or a private-key encryption. Example embodiments are not limited thereto.

110 130 5 FIG.A Operation Sto operation Swill be described in detail with reference to.

140 100 1 1 200 100 1 200 140 5 FIG.B In operation S, the host devicemay separate the signature data SIG and the plurality of write data (e.g., WDto WDn) corresponding to the first chunk CHKinto a plurality of transmission data sets TDS so as to be sent to the storage device. In some example embodiments, the host devicemay send the signature data SIG and the plurality of write data (e.g., WDto WDn) to the storage devicein an out-of-order manner. Operation Swill be described in detail with reference to.

5 FIG.A 4 FIG. 5 FIG.B 4 FIG. 1 5 FIGS.andA 110 130 140 110 111 112 is a diagram for describing operation Sto operation Sof, andis a diagram for describing operation Sof. Referring to, the host integrity managermay include a host hash data generatorand a signature data generator.

111 1 1 111 1 1 The host hash data generatormay receive the first chunk CHKincluding the plurality of write data WDto WDn. The host hash data generatormay generate a plurality of host sub-hash data HSHto HSHn respectively corresponding to the plurality of write data WDto WDn.

111 1 1 111 1 1 2 2 In detail, the host hash data generatormay apply the hash function to each of the plurality of write data WDto WDn to generate the plurality of host sub-hash data HSHto HSHn. For example, the host hash data generatormay apply the hash function to the first write data WDto generate the first host sub-hash data HSH, may apply the hash function to the second write data WDto generate the second host sub-hash data HSH, and may apply the hash function to the n-th write data WDn to generate the n-th host sub-hash data HSHn.

111 1 111 1 The host hash data generatormay generate the host hash data HHA based on the plurality of host sub-hash data HSHto HSHn. In detail, the host hash data generatormay apply the hash function to the plurality of host sub-hash data HSHto HSHn to generate the host hash data HHA.

111 111 5 The hash function refers to a function of mapping data of an arbitrary length to data of a fixed length. The host hash data generatormay apply the hash function to specific write data to generate hash data of a fixed length. For example, the host hash data generatormay use one or more of various hash functions including an MD5 (Message-Digest algorithm) and/or SHA (Secure Hash Algorithm) series. The hash function may be or may include a cryptographic hash function; however, example embodiments are not limited thereto.

112 1 112 The signature data generatormay generate the signature data SIG corresponding to the first chunk CHKbased on the host hash data HHA. The signature data generatormay encrypt the host hash data HHA with the signature key to generate the signature data SIG. The encryption may be or may include a public-key cryptographic encryption and/or a private-key cryptographic encryption; example embodiments are not limited thereto

1 For example, the signature data SIG may refer to information used to check the integrity of the write data WDto WDn and may include a cyclic redundancy check (CRC) code, a checksum code, an error detection code (EDC), an error correction code (ECC), etc.

3 FIG. 110 1 1 1 As described above, according to some example embodiments, unlike the example of, the host integrity managermay apply the hash function to each of the plurality of write data WDto WDn to generate the plurality of host sub-hash data HSHto HSHn, and may apply the hash function to the plurality of host sub-hash data HSHto HSHn to generate the host hash data HHA.

1 5 FIGS.andB 100 1 1 1 1 1 3 2 2 4 100 1 200 1 2 Referring to, the host devicemay separate the plurality of write data WDto WDn included in the first chunk CHKand the signature data SIG into transmission data sets TDSto TDSk. For example, the first transmission data set TDSmay include the first write data WDand the third write data WD, the second transmission data set TDSmay include the second write data WDand the fourth write data WD, and the k-th transmission data set TDSk may include the n-th write data WDn and the signature data SIG. The host devicemay send the transmission data sets TDSto TDSk to the storage devicethrough transmission lines TLand TL.

100 1 200 100 1 1 3 2 For example, the host devicemay send the first transmission data set TDSto the storage device. In this case, the host devicemay send the first write data WDthrough the first transmission line TLand may send the third write data WDthrough the second transmission line TL.

100 1 200 2 200 3 200 2 100 1 1 200 For example, the host devicemay send the first transmission data set TDSto the storage deviceand may then send the second transmission data set TDSto the storage device. In this case, the third write data WDmay be sent to the storage deviceprior to the second write data WD. Accordingly, the host devicemay send the plurality of write data WDto WDn (included in the first chunk CHK) and the signature data SIG to the storage devicein the out-of-order manner.

5 FIG.B 100 1 200 100 1 1 10 For example, unlike the example illustrated in, the host devicemay send the plurality of write data WDto WDn to the storage devicein a sequential manner. In this case, the host deviceshould send the plurality of write data WDto WDn through only one transmission line (e.g., TL). This may indicate that the performance of the storage systemis reduced.

1 2 218 100 200 1 2 2 FIG. 5 FIG.B The first transmission line TLand the second transmission line TLmay be included in a circuit (e.g., the host interface circuitof) for providing an interface between the host deviceand the storage device. An example in which the transmission data set TDS including two write data is sent through two transmission lines (e.g., TLand TL) is illustrated in, but example embodiments are not limited thereto. For example, the number of transmission lines and/or the number of write data included in the transmission data set TDS may be variously changed depending on a way to implement.

6 FIG.A 1 FIG. 6 FIG.B 1 FIG. 1 2 FIGS., 5 6 210 200 1 100 1 1 is a flowchart for describing an operation method of a storage device of, andis a diagram for describing an operation of a storage device of. Referring to, andA toA, in operation S, the storage devicemay receive the transmission data set TDS related to the first chunk CHKfrom the host device. For example, the transmission data set TDS may be one of the transmission data sets TDSto TDSk related to the first chunk CHK.

220 200 100 220 200 1 3 1 100 220 In operation S, the storage devicemay store a plurality of write data WD included in the transmission data set TDS received from the host deviceto the non-volatile memory device. For example, the storage devicemay store the first write data WDand the third write data WDincluded in the first transmission data set TDSreceived from the host devicein the non-volatile memory device.

230 200 100 In operation S, the storage devicemay generate the integrity hash map IHM based on the plurality of write data WD included in the transmission data set TDS received from the host device.

240 200 In operation S, the storage devicemay perform data integrity verification based on the completed integrity hash map IHM.

220 220 230 240 In some example embodiments, the operation of storing the write data in the non-volatile memory device(S) may be performed in parallel with or at least partly in parallel with the operation of generating the integrity hash map IHM (S) and the operation of performing the data integrity verification (S).

1 2 5 6 FIGS.,, andA toB 1 200 1 100 1 1 3 Referring to, at a first time point t, the storage devicemay receive the first transmission data set TDSfrom the host device. The first transmission data set TDSmay include the first write data WDand the third write data WD.

200 1 1 1 200 1 1 3 The storage devicemay identify the plurality of write data (e.g., WDto WDn) based on logical addresses (e.g., logical block addresses (LBAs)) respectively corresponding to the plurality of write data (e.g., WDto WDn) included in the received transmission data set (e.g., TDS). For example, the storage devicemay identify that the plurality of write data included in the received transmission data set (e.g., TDS) are the first write data WDand the third write data WD, based on the logical addresses corresponding to the plurality of write data.

200 1 3 1 3 200 1 3 220 The storage devicemay generate first verification sub-hash data VSHand third verification sub-hash data VSHbased on the first write data WDand the third write data WDand may update the integrity hash map IHM. In some examples, the storage devicemay store the first write data WDand the third write data WDin the non-volatile memory device.

1 1 1 1 In some example embodiments, the integrity hash map IHM may include a data index DATA # corresponding to the write data WDto WDn included in the first chunk CHK, status information Status indicating whether a verification sub-hash corresponding to the write data WDto WDn is generated, and the verification sub-hash data VSH respectively corresponding to the write data WDto WDn.

211 1 1 211 3 3 The storage integrity managermay apply the hash function to the first write data WDto generate the first verification sub-hash data VSH. The storage integrity managermay apply the hash function to the third write data WDto generate the third verification sub-hash data VSH.

211 1 1 211 3 3 The storage integrity managermay update the integrity hash map IHM by changing the status information of data index “1” of the integrity hash map IHM, which corresponds to the first write data WD, to a valid state and storing the first verification sub-hash data VSHin the integrity hash map IHM. In some example embodiments, the storage integrity managermay update the integrity hash map IHM by changing the status information of data index “3” of the integrity hash map IHM, which corresponds to the third write data WD, to a valid state and storing the third verification sub-hash data VSHin the integrity hash map IHM.

In some example embodiments, the valid state may indicate a state where verification sub-hash data corresponding to a data index is generated.

1 1 5 FIG.A In some example embodiments, the hash function used to generate verification sub-hash data (e.g., VSH) may be the same as the hash function used to generate the host sub-hash data (e.g., HSH) of; in some example embodiments, the hash functions may be seeded and/or salted with the same and/or different information.

211 1 3 213 1 3 220 Meanwhile, regardless of whether the integrity hash map IHM is completely updated by the storage integrity managerbased on the first write data WDand the third write data WD, the data managermay store the first write data WDand the third write data WDin the non-volatile memory device.

213 1 3 212 212 1 3 212 212 1 3 In some example embodiments, the data managermay store the first write data WDand the third write data WDin the buffer memory(e.g., a write buffer (not illustrated) included in the buffer memory) and may delete the first write data WDand the third write data WDfrom the buffer memory(e.g., the write buffer (not illustrated) included in the buffer memory) after the update of the integrity hash map IHM corresponding to the first write data WDand the third write data WDis completed.

213 1 3 1 220 211 1 3 In some example embodiments, the operation in which the data managerstores the write data WDand WDof the first transmission data set TDSin the non-volatile memory devicemay be performed in parallel with the operation in which the storage integrity managergenerates the plurality of verification sub-hash data VSHand VSHand updates the integrity hash map IHM.

2 1 200 2 100 2 2 4 200 2 4 2 4 200 2 4 220 At a second time point tfollowing the first time point t, the storage devicemay receive the second transmission data set TDSsent from the host device. The second transmission data set TDSmay include the second write data WDand the fourth write data WD. The storage devicemay generate second verification sub-hash data VSHand fourth verification sub-hash data VSHbased on the second write data WDand the fourth write data WDand may update the integrity hash map IHM. In some example embodiments, the storage devicemay store the second write data WDand the fourth write data WDin the non-volatile memory device.

211 2 2 211 4 4 The storage integrity managermay apply the hash function to the second write data WDto generate the second verification sub-hash data VSH. The storage integrity managermay apply the hash function to the fourth write data WDto generate the fourth verification sub-hash data VSH.

211 2 2 2 211 4 4 4 The storage integrity managermay update the integrity hash map IHM by changing the status information of data index “” of the integrity hash map IHM, which corresponds to the second write data WD, to a valid state and storing the second verification sub-hash data VSHin the integrity hash map IHM. In some example embodiments, the storage integrity managermay update the integrity hash map IHM by changing the status information of data index “” of the integrity hash map IHM, which corresponds to the fourth write data WD, to a valid state and storing the fourth verification sub-hash data VSHin the integrity hash map IHM.

211 2 4 213 2 4 220 Meanwhile, regardless of whether the integrity hash map IHM is completely updated by the storage integrity managerbased on the second write data WDand the fourth write data WD, the data managermay store the second write data WDand the fourth write data WDin the non-volatile memory device.

213 2 4 220 212 212 2 4 212 212 2 4 In some example embodiments, the data managermay store the second write data WDand the fourth write data WDin the non-volatile memory deviceand the buffer memory(e.g., the write buffer (not illustrated) included in the buffer memory) and may delete the second write data WDand the fourth write data WDfrom the buffer memory(e.g., the write buffer (not illustrated) included in the buffer memory) after the update of the integrity hash map IHM corresponding to the second write data WDand the fourth write data WDis completed.

213 2 4 2 220 211 2 4 In some example embodiments, the operation in which the data managerstores the write data WDand WDof the second transmission data set TDSin the non-volatile memory devicemay be performed in parallel with or at least partly in parallel with the operation in which the storage integrity managergenerates the plurality of verification sub-hash data VSHand VSHand updates the integrity hash map IHM.

3 2 200 100 200 At a third time point tfollowing the second time point t, the storage devicemay receive the k-th transmission data set TDSk sent from the host device. The k-th transmission data set TDSk may include the n-th write data WDn and the signature data SIG. The storage devicemay generate the n-th verification sub-hash data VSHn based on the n-th write data WDn and may update the integrity hash map IHM.

211 211 1 The storage integrity managermay apply the hash function to the n-th write data WDn to generate the n-th verification sub-hash data VSHn. The storage integrity managermay update the integrity hash map IHM by changing the status information of data index “n” of the integrity hash map IHM, which corresponds to the n-th write data WDn, to a valid state and storing the n-th verification sub-hash data VSHn in the integrity hash map IHM. According to the above description, in the integrity hash map IHM, the pieces of status information corresponding to all the data indexesto n may be set to the valid state.

211 213 220 1 1 220 213 212 Meanwhile, regardless of whether the update of the integrity hash map IHM is completed by the storage integrity manager, the data managermay store the n-th write data WDn in the non-volatile memory device. According to the above description, all the write data WDto WDn included in the first chunk CHKmay be stored in the non-volatile memory device. Also, the data managermay store the signature data SIG in the buffer memory.

213 220 212 212 212 212 Meanwhile, the data managermay store the n-th write data WDn in the non-volatile memory deviceand the buffer memory(e.g., the write buffer (not illustrated) included in the buffer memory) and may delete the n-th write data WDn from the buffer memory(e.g., the write buffer (not illustrated) included in the buffer memory) after the update of the integrity hash map IHM corresponding to the n-th write data WDn is completed.

213 220 211 In some example embodiments, the operation in which the data managerstores the write data (e.g., WDn) in the non-volatile memory devicemay be performed in parallel with or at least partly in parallel with the operation in which the storage integrity managergenerates verification sub-hash data (e.g., VSHn) and updates the integrity hash map IHM.

4 3 200 1 200 200 1 1 At a fourth time point tfollowing the third time point t, the storage devicemay check whether the integrity hash map IHM corresponding to the first chunk CHKis completed. When the integrity hash map IHM is completed, the storage devicemay generate the verification hash data VHA based on the integrity hash map IHM and may obtain the host hash data HHA based on the signature data SIG. The storage devicemay perform data integrity verification for the write data WDto WDn of the first chunk CHKbased on the verification hash data VHA and the host hash data HHA.

1 1 1 1 1 1 1 211 In some example embodiments, the number of data indexesto n of the integrity hash map IHM, denoted as “n”, may be equal to the number of write data WDto WDn included in the first chunk CHK, denoted as “n”, For example, all the verification sub-hash data VSHto VSHn corresponding to the write data WDto WDn may be stored in the integrity hash map IHM. In this case, the pieces of status information corresponding to all the data indexesto n of the integrity hash map IHM may be set to the valid state. Accordingly, as the pieces of status information corresponding to all the data indexesto n of the integrity hash map IHM are checked as the valid state, the storage integrity managermay determine that the integrity hash map IHM is completed.

1 1 1 211 For example, in some example embodiments, when all the verification sub-hash data VSHto VSHn corresponding to the write data WDto WDn of the first chunk CHKare stored in the integrity hash map IHM, the storage integrity managermay determine that the integrity hash map IHM is completed.

211 1 5 FIG.A The storage integrity managermay apply the hash function to the plurality of verification sub-hash data VSHto VSHn stored in the integrity hash map IHM to generate the verification hash data VHA. In some example embodiments, the hash function used to generate the verification hash data VHA may be the same as the hash function used to generate the host hash data HHA in.

211 211 The storage integrity managermay decrypt the signature data SIG to obtain the host hash data HHA. For example, the storage integrity managermay decrypt the signature data SIG based on the signature key and may obtain the host hash data HHA.

100 200 In some example embodiments, the host deviceand the storage devicemay share the signature key, which is used to generate the signature data SIG (i.e., to encrypt the host hash data HHA) or to decrypt the signature data SIG (i.e., to obtain the host hash data HHA).

211 1 1 211 The storage integrity managermay perform data integrity checking or verification for the write data WDto WDn of the first chunk CHK. For example, the storage integrity managermay perform the data integrity verification based on whether the verification hash data VHA are the same as the host hash data HHA obtained from the signature data SIG.

211 1 1 1 211 1 1 1 When the verification hash data VHA are the same as the host hash data HHA, the storage integrity managermay determine that the data integrity verification for the write data WDto WDn of the first chunk CHKsucceeds (i.e., that the data integrity of the plurality of write data WDto WDn is secured). When the verification hash data VHA are different from the host hash data HHA, the storage integrity managermay determine that the data integrity verification for the write data WDto WDn of the first chunk CHKis failed (e.g., that the data integrity of the write data WDto WDn is not secured).

4 200 1 212 200 1 211 1 211 1 1 1 In some example embodiments, after the fourth time point t, the storage devicemay delete the signature data SIG corresponding to the first chunk CHKfrom the buffer memory. In some example embodiments, the storage devicemay reset the integrity hash map IHM corresponding to the first chunk CHK. For example, the storage integrity managermay change pieces of status information corresponding to the data indexesto n to an invalid state in the integrity hash map IHM. In some example embodiments, the storage integrity managermay delete the plurality of verification sub-hash data VSHto VSHn which correspond to the write data WDto WDn of the first chunk CHKand are stored in the integrity hash map IHM.

211 211 5 Meanwhile, the hash function refers to a function of mapping data of an arbitrary length to data of a fixed length. The storage integrity managermay apply the hash function to specific write data to generate hash data of a fixed length. For example, the storage integrity managermay use various hash functions including an MD5 (Message-Digest algorithm) and/or SHA (Secure Hash Algorithm) series.

200 1 200 1 3 1 212 As described above, according to some example embodiments, the storage devicemay perform data integrity checking or data integrity verification on the plurality of write data WDto WDn based on the integrity hash map IHM. Accordingly, for the data integrity verification, the storage devicemay store the integrity hash map IHM, the signature data SIG, and write data included in a currently received transmission data set (e.g., only the write data WDand WDwhen a current time point is the first time point t) in the buffer memory.

212 1 1 212 1 1 200 212 200 3 FIG. 3 FIG. For example, the storage capacity of the buffer memorynecessary for or used for the data integrity verification according to some example embodiments may be smaller than the sum of data sizes of the plurality of write data WDto WDn (e.g., the data size of the first chunk CHK). According to the above descriptions, the storage capacity of the buffer memorymay be smaller than the sum of the data sizes of the plurality of write data WDto WDn (e.g., the data size of the first chunk CHK). For example, according to some example embodiments, the storage deviceincluding the buffer memorywhose capacity is smaller than that in the example ofmay be implemented. Accordingly, according to some example embodiments, compared to the example of, manufacturing costs of the storage devicemay decrease.

200 1 220 200 1 220 1 1 1 3 FIG. Also, according to some example embodiments, the storage devicemay perform the operation of updating the integrity hash map IHM and the operation of storing the write data WDto WDn in the non-volatile memory devicein parallel. For example, the storage devicemay store the write data WDto WDn in the non-volatile memory devicewithout waiting for the completion of the data integrity verification for the write data WDto WDn of the first chunk CHK. This may mean that the latency caused due to the data integrity verification and the write indicate related to the write data WDto WDn decreases compared to the example of.

7 FIG. 6 FIG.A 1 FIGS. 220 6 7 221 200 220 213 1 3 1 100 is a flowchart for describing operation Sofin detail. Referring toandA to, in operation S, the storage devicemay store the plurality of write data WD included in the transmission data set TDS in the memory cell array of the non-volatile memory device. For example, the data managermay store the write data WDand WDincluded in the first transmission data set TDSreceived from the host devicein the memory cell array.

222 200 100 213 100 1 3 1 220 In operation S, the storage devicemay send a storage completion signal corresponding to the received transmission data set TDS to the host device. For example, the data managermay send, to the host device, the storage completion signal indicating that the write data (e.g., WDand WD) included in the first transmission data set TDSare stored in the non-volatile memory device.

223 200 1 100 213 1 1 100 1 1 100 200 210 210 200 2 100 6 FIG.A 7 FIG. 6 FIG.A In operation S, the storage devicemay determine whether all the write data WD included in the first chunk CHKare received from the host device. For example, the data managermay check whether all the write data WDto WDn included in the first chunk CHKare received from the host device. For example, all the write data WDto WDn included in the first chunk CHKmay not be received from the host device. In this case, the storage devicemay proceed to operation Sof(refer to “A” in). For example, in operation Sof, the storage devicemay receive the second transmission data set TDSfrom the host device.

8 FIG. 6 FIG.A 1 4 8 FIGS.andto 230 231 200 100 200 1 1 3 100 211 1 1 211 3 3 is a flowchart for describing operation Sofin detail. Referring to, in operation S, the storage devicemay generate a plurality of verification sub-hash data VSH respectively corresponding to the plurality of write data WD included in the transmission data set TDS from the host device. For example, the storage devicemay receive the first transmission data set TDSincluding the first write data WDand the third write data WDfrom the host device. In this case, the storage integrity managermay apply the hash function to the first write data WDto generate the first verification sub-hash data VSH. Also, the storage integrity managermay apply the hash function to the third write data WDto generate the third verification sub-hash data VSH.

232 200 211 1 3 1 3 In operation S, the storage devicemay update the integrity hash map IHM. For example, the storage integrity managermay update the integrity hash map IHM by storing the first verification sub-hash data VSHand the third verification sub-hash data VSHin the integrity hash map IHM and changing status information corresponding to the first write data WDand the third write data WDto a valid state.

233 200 200 236 200 234 13 FIG. 8 FIG. In operation S, the storage devicemay determine whether a power-off situation occurs. When the power-off situation occurs, the storage devicemay proceed to operation Sof(refer to “B” in). When the power-off situation does not occur, the storage devicemay perform operation S.

234 200 1 200 235 200 210 210 200 2 100 6 FIG.A 8 FIG. In operation S, the storage devicemay determine whether the integrity hash map IHM corresponding to the first chunk CHKis completed. When the integrity hash map IHM is completed, the storage devicemay perform operation S. When the integrity hash map IHM is not completed, the storage devicemay proceed to operation Sof(refer to “A” in). For example, in operation S, the storage devicemay receive the second transmission data set TDSfrom the host device.

1 1 1 1 211 For example, all the verification sub-hash data VSHto VSHn corresponding to the write data WDto WDn of the first chunk CHKmay be stored in the integrity hash map IHM. In this case, pieces of status information respectively corresponding to all the data indexesto n of the integrity hash map IHM may be set to the valid state. In this case, the storage integrity managermay determine that the integrity hash map IHM is completed.

235 200 1 212 211 212 212 200 240 212 200 210 8 210 200 2 100 6 FIG.A In operation S, the storage devicemay determine whether the signature data SIG corresponding to the first chunk CHKare stored in the buffer memory. For example, the storage integrity managermay check the buffer memoryto determine whether the signature data SIG are stored. When the signature data SIG are stored in the buffer memory, the storage devicemay perform operation S. When there is a state where the signature data SIG are not stored in the buffer memory, the storage devicemay proceed to operation Sof(refer to “A” stored in.). For example, in operation S, the storage devicemay receive the second transmission data set TDSfrom the host device.

9 FIG. 6 FIG.A 1 4 9 FIGS.andto 240 241 200 1 211 1 is a flowchart for describing operation Sofin detail. Referring to, in operation S, the storage devicemay generate the verification hash data VHA based on the plurality of verification sub-hash data VSHto VSHn included in the completed integrity hash map IHM. For example, the storage integrity managermay apply the hash function to the plurality of verification sub-hash data VSHto VSHn to generate the verification hash data VHA.

242 200 211 212 In operation S, the storage devicemay obtain the host hash data HHA based on the signature data SIG. For example, the storage integrity managermay decrypt the signature data SIG stored in the buffer memoryto obtain the host hash data HHA.

243 200 1 1 211 1 1 1 In operation S, the storage devicemay determine data integrity for the write data WDto WDn included in the first chunk CHKbased on whether the verification hash data VHA are the same as the host hash data HHA. For example, when the verification hash data VHA are the same as the host hash data HHA, the storage integrity managermay determine that the data integrity verification for the write data WDto WDn of the first chunk CHKsucceeds (i.e., that the data integrity of the write data WDto WDn is secured).

10 FIG. 1 FIG. 1 4 10 FIGS.andto 310 100 200 1 1 200 is a flowchart for describing an operation method of a storage device ofwhen a power-off situation occurs. Referring to, in operation S, the host devicemay stop the power supply to the storage devicebefore the write data WDto WDn of the first chunk CHKare completely sent to the storage device.

10 100 200 100 For example, when a power-off request is received from the user of the storage system, the host devicemay recognize the occurrence of the power-off situation. For example, when aa sudden power off (SPO) situation occurs where the power supply to the storage deviceis suddenly blocked, the host devicemay recognize the occurrence of the power-off situation. The SPO may be or correspond to a blackout and/or a brownout event; however, example embodiments are not limited thereto

320 100 1 200 In operation S, the host devicemay stop sending the write data WDto WDn to the storage device.

330 100 200 10 100 200 100 100 340 In operation S, the host devicemay determine whether a power-on situation occurs in the storage device. For example, when a power-on request is received from the user of the storage system, the host devicemay recognize the occurrence of the power-on situation. For example, when the sudden power-off situation of the storage deviceis terminated, the host devicemay recognize the occurrence of the power-on situation. When the power-on situation occurs, the host devicemay perform operation S.

340 100 200 In operation S, the host devicemay resume the power supply to the storage device.

350 100 1 200 100 1 200 100 2 2 4 1 200 In operation S, the host devicemay send write data whose storage completion signal is not received from among the plurality of write data WDto WDn to the storage device. For example, when the host devicereceives the storage completion signal corresponding to the first transmission data set TDS, the storage devicemay be powered off and may then be powered on. In this case, the host devicemay send the second transmission data set TDSincluding the second write data WDand the fourth write data WDwithout resending the first transmission data set TDSto the storage device.

200 1 1 100 For example, even though the power-off situation occurs in the storage devicewhile the write data WDto WDn included in the first chunk CHKare being sent, the host devicemay not resend a plurality of write data transmitted already.

11 FIG. 1 FIG. 1 4 11 FIGS.andto 1 200 1 1 2 1 3 1 3 220 1 200 1 100 is a diagram for describing an operation of a storage device ofwhen a power-off situation occurs. Referring to, at the first time point t, the storage devicemay be in a state where the first transmission data set TDSincluding the first write data WDand the second write data WDare received. According to the above description, there may be a state where the first verification sub-hash data VSHand the third verification sub-hash data VSHare stored in the integrity hash map IHM. Also, there may be a state where the first write data WDand the third write data WDare stored in the non-volatile memory device. Meanwhile, a first time point tmay be a time point after the storage devicesends the storage completion signal corresponding to the first transmission data set TDSto the host device.

1 2 200 100 200 Between the first time point tand the second time point t, the power-off situation may occur in the storage device. In other words, the power supply from the host deviceto the storage devicemay be stopped.

2 211 220 200 14 FIG. At a second time point t, the storage integrity managermay back up the integrity hash map IHM to the non-volatile memory devicebased on an auxiliary power (e.g., AP of) supplied from the inside of the storage device.

3 212 212 14 FIG. At a third time point t, the power supply to the buffer memorymay be stopped (e.g., the supply of the auxiliary power (e.g., AP of) may be stopped). In this case, the integrity hash map IHM of the buffer memorybeing a volatile memory device may be deleted (or lost).

3 4 200 100 200 Between the third time point tand a fourth time point t, the power-on situation may occur in the storage device. In other words, the power supply from the host deviceto the storage devicemay be resumed.

4 211 220 212 At the fourth time point t, the storage integrity managermay load the integrity hash map IHM backed up to the non-volatile memory deviceto the buffer memory.

5 200 2 100 211 2 4 2 4 2 213 2 4 2 220 At a fifth time point t, the storage devicemay receive the second transmission data set TDSfrom the host device. The storage integrity managermay generate the verification sub-hash data VSHand VSHbased on the write data WDand WDincluded in the second transmission data set TDSand may update the integrity hash map IHM. Also, the data managermay store the write data WDand WDincluded in the second transmission data set TDSin the non-volatile memory device.

200 1 212 200 1 3 FIG. As described above, the power-off situation may occur before the data integrity verification is completed. In this case, for example, when the storage deviceoperates like the example of, the write data (e.g., WDto WDn) stored in the buffer memorymay be deleted. Accordingly, after the power-on situation occurs, the storage deviceshould again receive the write data WDto WDn.

200 220 200 1 3 1 According to some example embodiments, as described above, when the power-off situation occurs, the storage devicemay back up the integrity hash map IHM to the non-volatile memory device. This may indicate that the storage devicedoes not again receive the write data (e.g., WDand WD) after the power-on situation occurs. Accordingly, when the power-off situation occurs, the latency due to the data integrity verification for the plurality of write data WDto WDn may decrease.

12 FIG. 1 FIG. 1 4 12 FIGS.andto 1 FIG. 200 210 220 230 210 220 210 220 is a block diagram for describing a storage device ofin detail. Referring to, the storage devicemay include the storage controller, the non-volatile memory device, and an auxiliary power (AP) supply. The storage controllerand the non-volatile memory devicerespectively correspond to the storage controllerand the non-volatile memory deviceof, and thus, additional description will be omitted to avoid redundancy.

100 200 200 230 210 220 In some example embodiments, the power supply from the host deviceto the storage devicemay be stopped (e.g., the power-off situation may occur in the storage device). When the power-off situation occurs, the auxiliary power supplymay generate an auxiliary power AP and may supply the auxiliary power AP to the storage controllerand the non-volatile memory device.

230 230 In some example embodiments, the auxiliary power supplymay include one or more capacitors for generating the auxiliary power AP. In some example embodiments, the auxiliary power supplymay have a structure where at least two capacitors are connected in parallel.

210 220 211 220 When the power-off situation occurs, the storage controllerand the non-volatile memory devicemay operate based on the auxiliary power AP. In some example embodiments, when the power-off situation occurs, the storage integrity managermay back up the integrity hash map IHM to the non-volatile memory devicebased on the auxiliary power AP.

13 FIG. 1 FIG. 1 4 13 FIGS.andto 13 FIG. 236 200 220 211 230 is a flowchart for describing an operation method of a storage device ofwhen a power-off situation occurs. Referring to, in operation S, the storage devicemay back up the integrity hash map IHM to the non-volatile memory devicebased on the auxiliary power AP. For example, the storage integrity managermay back up the integrity hash map IHM based on the auxiliary power AP generated from the auxiliary power supply(refer to).

237 200 100 200 200 238 In operation S, the storage devicemay determine whether a power-on situation occurs. For example, when the power supply from the host deviceis resumed, the storage devicemay determine that the power-on situation occurs. When the power-on situation occurs, the storage devicemay perform operation S.

238 200 212 211 220 212 In operation S, the storage devicemay load the backed-up integrity hash map IHM to the buffer memory. For example, the storage integrity managermay load the integrity hash map IHM backed up to the non-volatile memory deviceto the buffer memory.

14 FIG. 1 FIG. 1 4 14 FIGS.andto 211 211 211 211 a b c. is a block diagram for describing a storage integrity manager of. Referring to, the storage integrity managermay include a verification hash data generator, a signature data analyzer, and a data integrity determiner

211 1 1 211 211 211 1 a a a a The verification hash data generatormay generate the verification sub-hash data VSH, based on the write data WD. For example, the write data WD may be one of the plurality of write data WDto WDn of the first chunk CHK. The verification hash data generatormay apply the hash function to the write data WD to generate the verification sub-hash data VSH corresponding to the write data WD. The verification hash data generatormay update the integrity hash map IHM by storing the verification sub-hash data VSH in the integrity hash map IHM and changing status information corresponding to the write data WD to a valid state. Also, the verification hash data generatormay apply the hash function to a plurality of verification sub-hash data (e.g., VSHto VSHn) stored in the completed integrity hash map IHM to generate the verification hash data VHA.

211 1 211 100 b b The signature data analyzermay decrypt the signature data SIG corresponding to the first chunk CHKto obtain the host hash data HHA. The signature data analyzermay decrypt the signature data SIG based on the signature key and may obtain the host hash data HHA. In this case, the signature key may be the same as the key used for the host deviceto generate the signature data SIG.

211 1 1 211 1 1 c c The data integrity determinermay perform data integrity verification for the write data WDto WDn of the first chunk CHKbased on the verification hash data VHA and the host hash data HHA. In some example embodiments, the data integrity determinermay generate a verification result signal VRS indicating a result of the data integrity verification for the write data WDto WDn of the first chunk CHK.

211 211 c c For example, when the verification hash data VHA are the same as the host hash data HHA, the data integrity determinermay generate the verification result signal VRS indicating the data integrity verification success. For example, when the verification hash data VHA are different from the host hash data HHA, the data integrity determinermay generate the verification result signal VRS indicating the data integrity verification failure.

15 FIG.A 1 FIG. 15 FIG.B 1 FIG. 15 15 FIGS.A andB 1 2 4 14 FIGS.,, andto is a diagram for describing an example of an operation of a storage device ofwhen data integrity verification is failed.is a flowchart for describing an example of an operation method of a storage device ofwhen data integrity verification is failed.will be described with reference to.

15 FIG.A 200 1 1 213 211 1 213 1 c Referring to, in a first operation {circle around (1)}, the storage devicemay determine whether data integrity verification for the plurality of write data WDto WDn included in the first chunk CHKis failed. In detail, the data managermay receive the verification result signal VRS from the data integrity determiner. For example, the verification result signal VRS may include information indicating that the data integrity verification for the plurality of write data WDto WDn is failed. Accordingly, the data managermay check that the data integrity verification for the plurality of write data WDto WDn is failed.

213 100 1 1 100 1 1 200 In a second operation {circle around (2)}, the data managermay send a verification failure signal VFS to the host device. For example, the verification failure signal VFS may refer to a signal requesting to resend the write data WDto WDn of the first chunk CHK. In some example embodiments, the host devicemay resend the write data WDto WDn of the first chunk CHKto the storage devicein response to the verification failure signal VFS.

213 1 1 220 212 213 1 213 1 200 1 In a third operation {circle around (3)}, the data managermay treat the write data WDto WDn of the first chunk CHK, which are stored in the non-volatile memory device(e.g., the memory cell array) and experience the data integrity verification failure, as invalid data. For example, in a mapping table MT of the buffer memory, the data managermay mark that data stored at physical addresses corresponding to the first to n-th write data WDto WDn are invalid data. That is, the data managermay invalidate the first to n-th write data WDto WDn. According to the above operation, the storage devicemay prevent the plurality of write data WDto WDn experiencing the data integrity verification failure from being treated as valid data.

For example, the invalid data may include data which are stored in the memory cell array but are not accessed by the deletion or update on a file system any more. For example, the invalid data may refer to data targeted for the erase operation from among a plurality of data stored in the memory cell array.

15 FIG.B 410 200 1 1 200 Referring to, in operation S, the storage devicemay check that the data integrity verification for the write data WDto WDn included in the first chunk CHKis failed. In detail, the storage devicemay check that the data integrity verification is failed, based on the verification result signal VRS.

420 200 1 100 In operation S, the storage devicemay send the verification failure signal VFS corresponding to the plurality of write data WDto WDn to the host device.

430 200 1 220 1 220 1 220 200 440 1 220 200 450 In operation S, the storage devicemay determine whether all the received write data WDto WDn are stored in the non-volatile memory device(e.g., whether all the received write data WDto WDn are stored in the memory cell array of the non-volatile memory device). When all the write data WDto WDn are stored in the non-volatile memory device, the storage devicemay perform operation S. When at least some of the plurality of write data WDto WDn are not stored in the non-volatile memory device, the storage devicemay perform operation S.

210 1 220 210 1 220 1 210 220 1 220 200 1 220 For example, after the storage controllersends write commands corresponding to the plurality of write data WDto WDn to the non-volatile memory device, the storage controllermay check the failure of the data integrity verification for the plurality of write data WDto WDn. In this case, there may be a state where the non-volatile memory devicefails to process all the write commands corresponding to the plurality of write data WDto WDn. That is, for example, there may be a state where some of the write commands received from the storage controllerare stored (or present) in a command queue of the non-volatile memory device. In other words, there may be a state where all the write data WDto WDn are not stored in the memory cell array of the non-volatile memory device. In this case, the storage devicemay determine that all the received write data WDto WDn are not stored in the non-volatile memory device.

440 200 1 220 212 213 1 213 1 In operation S, the storage devicemay treat the plurality of write data WDto WDn stored in the non-volatile memory deviceas invalid data. For example, in the mapping table MT of the buffer memory, the data managermay mark that the plurality of data stored at the physical addresses corresponding to the plurality of write data WDto WDn are invalid data. That is, the data managermay invalidate the plurality of write data WDto WDn.

450 200 1 220 1 4 1 5 220 212 213 213 1 4 213 5 In operation S, the storage devicemay treat the plurality of write data WDto WDn already stored in the non-volatile memory deviceas invalid data. For example, there may be a state where the first to fourth write data WDto WDamong the plurality of write data WDto WDn are stored in the memory cell array, and there may be a state where write commands corresponding to the fifth to n-th write data WDto WDn are stored (or present) in the command queue of the non-volatile memory device. In this case, in the mapping table MT of the buffer memory, the data manager, the data managermay mark that the first to fourth write data WDto WDare invalid data. Also, in some example embodiments, in the mapping table MT, the data managermay release the mapping between logical addresses and physical addresses corresponding to the fifth to n-th write data WDto WDn.

460 200 220 210 220 5 220 220 5 In operation S, the storage devicemay stop the write operation for write data not stored in the non-volatile memory device. For example, the storage controllermay send, to the non-volatile memory device, a write stop command for the write command corresponding to the fifth to n-th write data WDto WDn stored (or present) in the command queue of the non-volatile memory device. The non-volatile memory devicemay not perform the write operation for the fifth to n-th write data WDto WDn in response to the write stop command.

16 FIG.A 1 FIG. 16 FIG.B 1 FIG. 16 16 FIGS.A andB 1 2 4 15 FIGS.,, andtoB is a diagram for describing another example of an operation of a storage device ofwhen data integrity verification is failed.is a flowchart for describing another example of an operation method of a storage device ofwhen data integrity verification is failed.will be described with reference to.

16 FIG.A 15 FIG.A A first operation {circle around (1)} and a second operation {circle around (2)} ofare similar to the first operation {circle around (1)} and the second operation {circle around (2)} of, and thus, additional description will be omitted to avoid redundancy.

200 1 100 1 220 200 1 1 1 2 2 2 1 For example, the storage devicemay encrypt the plurality of write data WDto WDn received from the host devicebased on storage keys Kto Kn, so as to be stored in the memory cell array of the non-volatile memory device. For example, the storage devicemay encrypt the first write data WDbased on the first storage key Khaving a first encryption value Vso as to be stored in the memory cell array, may encrypt the second write data WDbased on the second storage key Khaving a second encryption value Vso as to be stored in the memory cell array, and may encrypt the n-th write data WDn based on the n-th storage key Kn having an n-th encryption value Vn so as to be stored in the memory cell array. For example, the storage keys Kto Kn may be stored in the memory cell array.

15 15 FIGS.A andB 1 200 1 1 1 1 1 1 1 10 As described with reference to, when the data integrity verification for the plurality of write data WDto WDn is failed, the storage devicemay treat the plurality of write data WDto WDn as invalid data. However, even in this case, before the erase operation for the plurality of write data WDto WDn is performed, the plurality of encrypted write data WDto WDn and the storage keys Kto Kn stored in the memory cell array may be read from the outside. This may mean that the plurality of encrypted write data WDto WDn are capable of being decrypted through the storage keys Kto Kn. As a result, the write data WDto WDn of the user of the storage systemmay be leaked out to the outside.

16 FIG.A 213 1 1 Returning to, in a third operation {circle around (3)}, the data managermay change key values of the storage keys Kto Kn corresponding to the plurality of write data WDto WDn experiencing the data integrity verification failure.

213 1 1 1 2 2 2 For example, the data managermay change the key value corresponding to the first storage key Kfrom the first encryption value Vto a first invalid value X, may change the key value corresponding to the second storage key Kfrom the second encryption value Vto a second invalid value X, and may change the key value corresponding to the n-th storage key Kn from the n-th encryption value Vn to an n-th invalid value Xn.

1 1 1 1 1 1 10 According to the above description, when the plurality of encrypted write data WDto WDn and the storage keys Kto Kn are read from the outside, it may be impossible to decrypt the plurality of encrypted write data WDto WDn based on the changed key values Xto Xn of the storage keys Kto Kn. Accordingly, the write data WDto WDn of the user of the storage systemmay be prevented from being leaked out.

16 FIG.B 510 200 1 1 200 Referring to, in operation S, the storage devicemay check that the data integrity verification for the plurality of write data WDto WDn included in the first chunk CHKis failed. In detail, the storage devicemay check that the data integrity verification is failed, based on the verification result signal VRS.

520 200 1 100 100 1 1 200 In operation S, the storage devicemay send the verification failure signal VFS corresponding to the plurality of write data WDto WDn to the host device. In some example embodiments, the host devicemay resend the write data WDto WDn of the first chunk CHKto the storage devicein response to the verification failure signal VFS.

530 200 1 1 1 220 213 1 1 1 In operation S, the storage devicemay change the key values Vto Vn of the storage keys Kto Kn corresponding to the plurality of write data WDto WDn stored in the non-volatile memory device. For example, the data managermay change the key values Vto Vn of the storage keys Kto Kn to the invalid values Xto Xn.

1 200 15 15 FIGS.A andB 16 16 FIGS.A andB In some example embodiments, when the data integrity verification for the write data WDto WDn is failed, the storage devicemay perform both the invalidation operation described with reference toand the key change operation described with reference to.

17 FIG. 1 FIG. 17 FIG. 1 4 16 FIGS.andtoB 17 FIG. 5 FIG.A 1100 100 1 1 100 1 1 1 is a flowchart for describing an operation of a storage system of.will be described with reference to. Referring to, in operation S, the host devicemay generate the signature data SIG based on the plurality of write data WD (e.g., WDto WDn) included in the first chunk CHK. For example, as described with reference to, the host devicemay generate the plurality of host sub-hash data HSHto HSHn respectively corresponding to the plurality of write data WDto WDn, may generate the host hash data HHA based on the plurality of host sub-hash data HSHto HSHn, and may generate the signature data SIG based on the host hash data HHA.

1200 100 1 1 3 200 100 1 1 1 1 3 200 5 FIG.B In operation S, the host devicemay send the first transmission data set TDSincluding the first write data WDand the third write data WDto the storage device. For example, as described with reference to, the host devicemay separate the plurality of write data WDto WDn into the plurality of transmission data sets TDSto TDSk and may then send the first transmission data set TDSincluding the first write data WDand the third write data WDto the storage device.

1300 200 1 In operation S, the storage devicemay process the first transmission data set TDS.

1310 200 1 3 100 220 200 1 3 1 100 7 FIG. In detail, in operation S, the storage devicemay store the first write data WDand the third write data WDreceived from the host devicein the non-volatile memory device. For example, as described with reference to, the storage devicemay store the first write data WDand the third write data WDin the memory cell array and may send the storage completion signal corresponding to the first transmission data set TDSto the host device.

1320 200 1 1 200 1 3 1 3 200 1 3 200 1 8 13 FIGS.to In operation S, the storage devicemay manage data integrity for the write data (e.g., WDto WDn) included in the first chunk CHKbased on the integrity hash map IHM. For example, as described with reference to, the storage devicemay generate the first verification sub-hash data VSHand the third verification sub-hash data VSHbased on the first write data WDand the third write data WD. The storage devicemay generate the integrity hash map IHM storing the first verification sub-hash data VSHand the third verification sub-hash data VSH. When the integrity hash map IHM is completed, the storage devicemay perform data integrity verification for the write data WDto WDn, based on the integrity hash map IHM.

1400 200 1 1 1 200 1 100 1 1 1500 In operation S, the storage devicemay determine whether data integrity verification related to the first chunk CHKis performed. For example, when data integrity verification for the plurality of write data WDto WDn included in the first chunk CHKis performed, the storage devicemay not receive a transmission data set corresponding to the first chunk CHKfrom the host deviceanymore. For example, when the data integrity verification for the plurality of write data WDto WDn included in the first chunk CHKis not performed, operation Smay be performed.

1500 200 2 2 4 200 In operation S, the storage devicemay send the second transmission data set TDSincluding the second write data WDand the fourth write data WDto the storage device.

1500 1300 1400 200 2 4 220 After operation S, as in the above description given in operation Sand operation S, the storage devicemay store the received write data WDand WDin the non-volatile memory deviceand may manage the integrity hash map IHM.

18 FIG. 1 FIG. 18 FIG. 1 4 17 FIGS.andto 18 FIG. 6 FIG.B 100 1 2 is a diagram for describing an example of an operation of a storage system of.will be described with reference to. Referring to, unlike the description given with reference to, the host devicemay send transmission data sets corresponding to the first chunk CHKand transmission data sets corresponding to a second chunk CHKin the out-of-order manner.

200 1 2 200 1 1 1 200 1 2 2 a b In some example embodiments, the storage devicemay generate a plurality of integrity hash maps IHMand IHMand may perform data integrity verification. For example, the storage devicemay perform data integrity verification for write data (e.g., WDto WDna) of the first chunk CHKbased on the first integrity hash map IHM. Also, the storage devicemay perform data integrity verification for write data (e.g., WDto WDnb) of the second chunk CHKbased on the second integrity hash map IHM.

1 200 1 1 100 1 1 3 1 200 1 3 1 1 3 200 1 1 3 1 a a a a a a a a a a In detail, for example, at the first time point t, the storage devicemay receive a first transmission data set TDScorresponding to the first chunk CHKfrom the host device. The first transmission data set TDSmay include the first write data WDand the third write data WDof the first chunk CHK. The storage devicemay generate first verification sub-hash data VSHand third verification sub-hash data VSHcorresponding to the first chunk CHKbased on the first write data WDand the third write data WD. The storage devicemay update the first integrity hash map IMHby storing the first verification sub-hash data VSHand the third verification sub-hash data VSHin the first integrity hash map IMH.

2 1 200 2 2 100 200 1 1 2 2 100 b a a At the second time point tfollowing the first time point t, the storage devicemay receive a second transmission data set TDScorresponding to the second chunk CHKfrom the host device. That is, the storage devicemay receive the first transmission data set TDScorresponding to the first chunk CHKprior to a second transmission data set (e.g., TDS) corresponding to the second chunk CHKfrom the host device.

2 2 4 2 200 2 4 2 2 4 200 2 2 4 2 b b b b b b b b b The second transmission data set TDSmay include second write data WDand fourth write data WDof the second chunk CHK. The storage devicemay generate second verification sub-hash data VSHand fourth verification sub-hash data VSHcorresponding to the second chunk CHKbased on the second write data WDand the fourth write data WD. The storage devicemay update the second integrity hash map IMHby storing the second verification sub-hash data VSHand the fourth verification sub-hash data VSHin the second integrity hash map IMH.

19 FIG. 1000 is a diagram of a data centerto which a memory device is applied, according to an embodiment.

19 FIG. 1000 1000 1000 1100 1100 1200 1200 1100 1100 1200 1200 1100 1100 1200 1200 n m n m n m Referring to, the data centermay be a facility that collects various types of pieces of data and provides services and be referred to as a data storage center. The data centermay be a system for operating a search engine and a database, and may be a computing system used by companies, such as banks, or government agencies. The data centermay include application serverstoand storage serversto. The number of application serverstoand the number of storage serverstomay be variously selected according to embodiments. The number of application serverstomay be different from the number of storage serversto.

1100 1200 1110 1210 1120 1220 1200 1210 1200 1220 1220 1220 1210 1220 1200 1210 1220 1210 1220 1210 1200 1100 1100 1150 1200 1250 1250 1200 The application serveror the storage servermay include at least one of processorsandand memoriesand. The storage serverwill now be described as an example. The processormay control all operations of the storage server, access the memory, and execute instructions and/or data loaded in the memory. The memorymay be or may include one or more of a double-data-rate synchronous DRAM (DDR SDRAM), a high-bandwidth memory (HBM), a hybrid memory cube (HMC), a dual in-line memory module (DIMM), Optane DIMM, and/or a non-volatile DIMM (NVMDIMM). In some embodiments, the numbers of processorsand memoriesincluded in the storage servermay be variously selected. In some example embodiments, the processorand the memorymay provide a processor-memory pair. In some example embodiments, the number of processorsmay be different from the number of memories. The processormay include a single-core processor or a multi-core processor. The above description of the storage servermay be similarly applied to the application server. In some embodiments, the application servermay not include a storage device. The storage servermay include at least one storage device. The number of storage devicesincluded in the storage servermay be variously selected according to embodiments.

1100 1100 1200 1200 1300 1300 1200 1200 1300 n m m The application serverstomay communicate with the storage serverstothrough a network. The networkmay be implemented by using a fiber channel (FC) or Ethernet. In this case, the FC may be a medium used for relatively high-speed data transmission and use an optical switch with high performance and high availability. The storage serverstomay be provided as file storages, block storages, or object storages according to an access method of the network.

1300 1300 1300 In some example embodiments, the networkmay be or may include a storage-dedicated network, such as a storage area network (SAN). For example, the SAN may be or may include an FC-SAN, which uses an FC network and is implemented according to an FC protocol (FCP). Alternatively or additionally, the SAN may be or may include an Internet protocol (IP)-SAN, which uses a transmission control protocol (TCP)/IP network and is implemented according to a SCSI over TCP/IP or Internet SCSI (iSCSI) protocol. Alternatively or additionally, the networkmay be a general network, such as a TCP/IP network. For example, the networkmay be implemented according to a protocol, such as one or more of FC over Ethernet (FCoE), network attached storage (NAS), and NVMe over Fabrics (NVMe-oF).

1100 1200 1100 1100 1200 1200 n m. Hereinafter, the application serverand the storage serverwill mainly be described. A description of the application servermay be applied to another application server, and a description of the storage servermay be applied to another storage server

1100 1200 1200 1300 1100 1200 1200 1300 1100 m m The application servermay store data, which is requested by a user or a client to be stored, in one of the storage serverstothrough the network. Also, the application servermay obtain data, which is requested by the user or the client to be read, from one of the storage serverstothrough the network. For example, the application servermay be implemented as a web server or a database management system (DBMS).

1100 1120 1150 1100 1300 1100 1220 1220 1250 1250 1200 1200 1300 1100 1100 1100 1200 1200 1100 1100 1100 1200 1200 1250 1250 1200 1200 1120 1120 1100 1100 1220 1220 1200 1200 1300 n n n m m m n m n m m m n n m m The application servermay access a memoryor a storage device, which is included in another application server, through the network. Alternatively, the application servermay access memoriestoor storage devicesto, which are included in the storage serversto, through the network. Thus, the application servermay perform various operations on data stored in application serverstoand/or the storage serversto. For example, the application servermay execute an instruction for moving or copying data between the application serverstoand/or the storage serversto. In this case, the data may be moved from the storage devicestoof the storage serverstoto the memoriestoof the application serverstodirectly or through the memoriestoof the storage serversto. The data moved through the networkmay be data encrypted for security or privacy.

1200 1254 1210 1251 1240 1251 1254 1250 1254 The storage serverwill now be described as an example. An interfacemay provide physical connection between a processorand a controllerand a physical connection between a network interface card (NIC)and the controller. For example, the interfacemay be implemented using a direct attached storage (DAS) scheme in which the storage deviceis directly connected with a dedicated cable. For example, the interfacemay be implemented by using various interface schemes, such as one or more of ATA, SATA, e-SATA, an SCSI, SAS, PCI, PCIe, NVMe, IEEE 1394, a USB interface, an SD card interface, an MMC interface, an eMMC interface, a UFS interface, an eUFS interface, and/or a CF card interface.

1200 1230 1240 1230 1210 1250 1240 1250 1210 The storage servermay further include a switchand the NIC (Network InterConnect). The switchmay selectively connect the processorto the storage deviceor selectively connect the NICto the storage devicevia the control of the processor.

1240 1240 1300 1240 1210 1230 1254 1240 1210 1230 1250 In some example embodiments, the NICmay include a network interface card and a network adaptor. The NICmay be connected to the networkby a wired interface, a wireless interface, a Bluetooth interface, or an optical interface. The NICmay include an internal memory, a digital signal processor (DSP), and a host bus interface and be connected to the processorand/or the switchthrough the host bus interface. The host bus interface may be implemented as one of the above-described examples of the interface. In some example embodiments, the NICmay be integrated with at least one of the processor, the switch, and the storage device.

1200 1200 1100 1100 1150 1150 1250 1250 1120 1120 1220 1220 m n n m n m In the storage serverstoor the application serversto, a processor may transmit a command to storage devicestoandtoor the memoriestoandtoand program or read data. In this case, the data may be data of which an error is corrected by an ECC engine. The data may be data on which a data bus inversion (DBI) operation or a data masking (DM) operation is performed, and may include cyclic redundancy code (CRC) information. The data may be data encrypted for security or privacy.

1150 1150 1250 1250 1252 1252 1252 1252 n m m m Storage devicestoandtomay transmit a control signal and a command/address signal to NAND flash memory devicestoin response to a read command received from the processor. Thus, when data is read from the NAND flash memory devicesto, a read enable (RE) signal may be input as a data output control signal, and thus, the data may be output to a DQ bus. A data strobe signal DQS may be generated using the RE signal. The command and the address signal may be latched in a page buffer depending on a rising edge or falling edge of a write enable (WE) signal.

1251 1250 1251 1251 1252 1252 1210 1200 1210 1200 1110 1110 1100 1100 1253 1252 1252 1253 1251 1252 1250 m m n n The controllermay control all operations of the storage device. In some example embodiments, the controllermay include SRAM. The controllermay write data to the NAND flash memory devicein response to a write command or read data from the NAND flash memory devicein response to a read command. For example, the write command and/or the read command may be provided from the processorof the storage server, the processorof another storage server, or the processorsandof the application serversand. DRAMmay temporarily store (or buffer) data to be written to the NAND flash memory deviceor data read from the NAND flash memory device. Also, the DRAMmay store metadata. Here, the metadata may be user data or data generated by the controllerto manage the NAND flash memory device. The storage devicemay include a secure element (SE) for security or privacy.

According to some example embodiments a storage device may generate a hash map based on a plurality of write data received from a host device. The storage device may perform data integrity verification for the plurality of write data based on the hash map. In this case, the storage space of the buffer memory may decrease. Accordingly, a storage system including a host device and a storage device and providing improved performance, an operation method thereof, and an operation method of the storage device are provided.

Any of the elements and/or functional blocks disclosed above may include or be implemented in processing circuitry such as hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc. The processing circuitry may include electrical components such as at least one of transistors, resistors, capacitors, etc. The processing circuitry may include electrical components such as logic gates including at least one of AND gates, OR gates, NAND gates, NOT gates, etc.

Any or all of the elements described with reference to the above figures may communicate with any or all other elements described with reference to the same or other above figures. For example, any element may engage in one-way and/or two-way and/or broadcast communication with any or all other elements in any of the figures, to transfer and/or exchange and/or receive information such as but not limited to data and/or commands, such as in a serial and/or parallel manner, via a bus such as a wireless and/or a wired bus (not illustrated). The information may be in encoded various formats, such as in an analog format and/or in a digital format, without being limited thereto.

While inventive concepts have been described with reference to embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the following claims. Additionally, example embodiments are not necessarily mutually exclusive with one another. For example, some example embodiments may include one or more features described with reference to one or more figures, and may also include one or more other features described with reference to one or more other figures.