Display Device

Pursuant to 35 U.S.C. § 119(a), this application claims the benefit of an earlier filing date and right of priority to Korean Patent Application No. 10-2024-0125868, filed Sep. 13, 2024, the disclosure of which is incorporated herein by reference in its entirety.

The present disclosure relates to display devices.

Electroluminescent display devices are divided into inorganic light emitting display devices and organic light emitting display devices according to a material of a light emitting layer. An active-matrix type organic light emitting display device includes organic light emitting diodes (OLEDs) which emit light by themselves, and have advantages in that a response speed is fast and luminous efficiency, luminance, and a viewing angle are large.

In organic light-emitting display devices, organic light-emitting diodes (OLEDs) are formed in each of pixels. These organic light-emitting display devices not only respond quickly and have excellent light-emitting efficiency, luminance, and viewing angle, but also have excellent contrast ratio and color reproduction rate because they can express black tones as complete black.

A display device according to implementations of the present disclosure may include a display panel including a first area and a second area in which a plurality of pixels are arranged; a plurality of gate drivers disposed in the first area and the second area; a first clock line connected to the gate driver disposed in the first area; a second clock line connected to the gate driver disposed in the second area; and a level shifter configured to generate a first clock signal and a second clock signal to be applied to each of the first clock line and the second clock line, respectively, wherein the first clock signal and the second clock signal have different voltage levels or gate-on times.

A display device according to implementations of the present disclosure may include a display panel including a first area and a second area in which a plurality of pixels are arranged; a plurality of gate drivers disposed in the first area and the second area; and a timing controller configured to generate a first clock signal and a second clock signal to be respectively applied to gate drivers disposed in the first area and the second area, wherein the first clock signal and the second clock signal have different gate-on times.

A display device according to implementations of the present disclosure may include a display panel including a first area and a second area in which a plurality of pixels are arranged; a plurality of gate drivers disposed in the first area and the second area; and a level shifter configured to generate a first clock signal and a second clock signal to be respectively applied to gate drivers disposed in the first area and the second area, wherein the first clock signal and the second clock signal have different voltage levels.

Display devices, for example, a liquid crystal display device or an organic light emitting display device, can include a display panel including a plurality of sub-pixels, a driver outputting a driving signal for driving the display panel, a power supply generating power to be supplied to the display panel or the driver, and the like.

To achieve a narrow bezel of a display panel, a gate driver that outputs gate signals is positioned between the pixels in the display area. However, depending on the display panel's shape, a delay may occur in the clock signal applied to the gate driver, which causes a delay in the gate signals output to the gate driver, resulting in luminance deviations depending on the area.

The present disclosure describes implementations that can address the above-described necessity and problems.

The present disclosure provides a display device that can improve luminance deviations between different areas of the display panel.

It should be noted that objects of the present disclosure are not limited to the above-described objects, and other objects of the present disclosure will be clear to those skilled in the art from the following descriptions.

According to the present disclosure, by dividing a display area of a display panel based on its shape, separating clock lines that apply clock signals to gate drivers disposed in the divided areas, and applying clock signals having different voltage levels or gate-on times through the separated clock lines, luminance deviations between the different areas may be alleviated.

According to the present disclosure, power consumption may be reduced depending on the areas, thereby enabling low-power operation of the display devices.

The effects of the present specification are not limited to the above-mentioned effects, and other effects that are not mentioned will be clearly understood by those skilled in the art from the following description and the appended claims.

Advantages and features of the present specification and methods of achieving them will become clear with reference to preferable implementations, which are described in detail, in conjunction with the accompanying drawings. However, the present specification is not limited to the implementations to be described below and may be implemented in different forms, the implementations are only provided to completely disclose the present disclosure and completely convey the scope of the present disclosure to those skilled in the art, and the present specification is defined by the disclosed claims.

Since the shapes, sizes, proportions, angles, numbers, and the like disclosed in the drawings for describing the implementations of the present disclosure are only exemplary, the present disclosure is not limited to the illustrated items. The same reference numerals indicate the same components throughout the specification. Further, in describing the present disclosure, when it is determined that a detailed description of related known technology may unnecessarily obscure the gist of the present disclosure, the detailed description thereof will be omitted.

When ‘including,’ ‘having,’ ‘consisting,’ and the like mentioned in the present specification are used, other parts may be added unless ‘only’ is used. A case in which a component is expressed in a singular form includes a plural form unless explicitly stated otherwise.

In interpreting the components, it should be understood that an error range is included even when there is no separate explicit description.

In the case of a description of a positional relationship, for example, when the positional relationship of two parts is described as ‘on,’ ‘at an upper portion,’ ‘at a lower portion,’ ‘next to, and the like, one or more other parts may be located between the two parts unless ‘immediately’ or ‘directly’ is used.

Although first, second, and the like are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, a first component, which is mentioned, below may also be a second component within the technical spirit of the present disclosure.

The same reference numerals may refer to substantially the same elements throughout the present disclosure.

The following implementations can be partially or entirely bonded to or combined with each other and can be linked and operated in technically various ways. The implementations can be carried out independently of or in association with each other.

Hereinafter, various implementations of the present disclosure will be described in detail with reference to the accompanying drawings.

1 1 FIGS.A toB are block diagrams illustrating a display device according to an implementation of the present disclosure.

100 100 150 The display device according to an implementation of the present disclosure includes a display panel, and a display panel driving circuit for writing pixel data to pixels of the display panel. Additionally, the display device includes a power supply.

100 100 The display panelmay be, but is not limited to, a panel having a rectangular structure with a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. For example, the display panelmay be a heterogeneous panel of which at least a portion is curved or elliptical.

100 102 103 102 100 101 101 The display area AA of the display panelincludes a pixel array to display an input image. The pixel array includes a plurality of data lines, a plurality of gate linescrossing the data lines, and pixels arranged in a matrix form. The display panelmay further include power lines commonly connected to the pixels. The power lines may be commonly connected to pixel circuits to supply a voltage required for driving pixelsto the pixels.

101 Each of the pixelsmay be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color implementation. Each pixel may further include a white sub-pixel. Each sub-pixel includes a pixel circuit for driving a light emitting element. The light emitting element may include an OLED or an inorganic light emitting diode (LED). Each pixel circuit is connected to the data lines, the gate lines, and the power lines. In the following description, a pixel may be interpreted as a sub-pixel.

1 1 100 103 102 1 The display area AA includes a plurality of pixel lines Lto Ln. Each of the pixel lines Lto Ln includes one line of pixels arranged along the line direction (X-axis direction) in the pixel array of the display panel. Those pixels arranged in one pixel line share the same gate lines. The sub-pixels arranged in the column direction Y along the data line direction share the same data lines. One horizontal period is a time period obtained by dividing one frame period by the total number of pixel lines Lto Ln.

100 100 The display panelmay be implemented with a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device in which an image is displayed on the screen and a real object in the background is visible. The display panelmay be made of a flexible display panel.

150 300 101 100 150 150 140 120 101 101 The power supplyreceives an input voltage applied from a host systemand outputs a voltage needed to drive the pixelsof the display paneland the display panel driving circuit. To this end, the power supplymay include a direct current to direct current converter (DC-DC converter). The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, and the like. The power supplymay output a constant voltage (or direct current voltage), such as gate-on voltage, gate-off voltage, pixel driving voltage, cathode voltage, reference voltage, IC driving voltage of the display panel driving circuit, through the DC-DC converter. The gate-on voltage and the gate-off voltage may be supplied to the level shifterand the gate driver. Voltages such as pixel driving voltage, cathode voltage, and reference voltage may be supplied to the pixelsthrough the power lines commonly connected to the pixels.

150 110 110 130 300 The power supplymay further include a gamma voltage generator. The gamma voltage generator receives a high-potential reference voltage and a low-potential reference voltage and outputs a plurality of gamma reference voltages divided at specific intervals on a preset gamma curve, for example, a 2.2 gamma curve. The gamma reference voltages are supplied to the data driver. In the data driver, the gamma reference voltages are subdivided by a voltage dividing circuit into grayscale voltages. The gamma voltage generator may be implemented with a programmable gamma circuit that may adjust the voltage of each of the gamma reference voltages according to digital data. The timing controller, the host system, or a separate external device may update digital data stored in a register of the programmable gamma circuit through a communication interface.

101 100 130 110 120 The display panel driving circuit writes pixel data of the input image to the pixelsof the display panelunder the control of the timing controller. The display panel driving circuit includes a data driverand a gate driver.

1 1 FIGS.A toB 110 The display panel driving circuit may further include a touch sensor driver for driving touch sensors. The touch sensor driver is not shown in. The data driverand the touch sensor driver may be integrated into one source drive IC.

110 130 110 110 The data driverreceives pixel data of the input image as a digital signal from the timing controllerand outputs a data voltage. The data drivermay receive gamma reference voltages and generate gamma compensation voltages for each grayscale through a voltage dividing circuit. The per-grayscale gamma compensation voltages are supplied to a digital to analog converter (hereinafter referred to as “DAC”) disposed in each channel of the data driver.

110 130 The data driversamples and latches digital data received from the timing controllerand then inputs the digital data to the DAC. Here, the digital data includes pixel data of the input image. Additionally, the digital data may include mode selection data for selecting first mode and second mode. The DAC converts the pixel data into a gamma compensation voltage and outputs a data voltage of the pixel data.

120 100 120 100 The gate drivermay be formed on the display paneltogether with the circuit elements and wiring lines of the display area AA. The gate drivermay be disposed in at least one of left and right non-display areas outside the display area AA in the display panelor at least a part thereof may be disposed within the display area AA.

120 103 130 120 103 120 The gate driversequentially outputs pulses of the gate signals to the gate linesunder the control of the timing controller. The gate drivermay sequentially supply the gate signals to the gate linesby shifting the pulses of the gate signals using shift registers. When a plurality of gate signals are applied to each pixel, the gate drivermay include a plurality of shift registers. The gate signal may include a scan signal being input to the pixel circuit through a plurality of gate lines, and an emission signal (or EM signal).

120 120 101 1 FIG.B The gate drivermay be disposed in Gate In Panel (GIP) fashion in the non-display area, or in Gate in Active area (GIA) fashion between subpixels SP in the display area AA. For example, as shown in, the circuit of the gate drivermay be located between the pixelswithin the display area AA.

130 300 1 The timing controllerreceives digital video data of an input image and a timing signal synchronized with this data from the host system. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical period and horizontal period may be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The horizontal synchronization signal Hsync and the data enable signal DE have a periodicity of 1 horizontal period (H).

130 110 120 300 130 110 120 The timing controllermay control the display panel driving circuit by generating a data timing control signal for controlling the operation timing of the data driverand a gate timing control signal for controlling the operation timing of the gate driverbased on the timing signals Vsync, Hsync, DE received from the host system. The timing controllermay synchronize the data driverand the gate driverby controlling the operation timing of the display panel driving circuit.

130 120 140 140 130 120 The gate timing control signal output from the timing controllermay be input to the shift register of the gate driverthrough the level shifter. The level shiftermay convert a voltage of the gate timing control signal received from the timing controllerto a swing width between the gate-on voltage and the gate-off voltage and supply it to the gate driver.

130 120 140 The timing controllermay analyze the input image for each frame and generate a control signal for selectively outputting gate signals according to the analysis result. The generated control signal may be provided to the shift register of the gate driverthrough the level shifter.

300 300 100 130 The host systemmay include a main board of one of a television system, a set-top box, a navigation system, a personal computer (PC), a vehicle system, a mobile terminal, and a wearable terminal. The host systemmay scale an image signal from a video source according to the resolution of the display panel, and may transmit it to the timing controllertogether with the timing signals.

2 FIG. 3 FIG. 2 FIG. is a diagram illustrating a shape of the display panel according to an implementation of the present disclosure, andis a diagram illustrating a configuration of the gate driver shown in.

2 FIG. 1 2 Referring to, the display panel according to an implementation of the present disclosure may have an irregular shape, such as a shape with varying length depending on position, rather than a rectangular shape. The display panel may include a first area Aand a second area Ain which the image is displayed, depending on its shape. The first area may be longer in the Y-axis direction than the second area.

120 120 The gate drivermay be formed along the column direction between the pixels, but are not necessarily limited thereto. For example, the gate drivermay be formed along the row direction between the pixels.

120 The gate drivermay include a scan driver that output a scan signal. The scan driver may output the scan signal based on a clock signal and a low potential voltage.

3 FIG. 1 2 3 4 5 6 7 8 1 2 Referring to, the gate driver according to an implementation of the present disclosure may include a first transistor T, a second transistor T, a third transistor T, a fourth transistor T, a fifth transistor T, a sixth transistor T, a seventh transistor or pull-up transistor T, an eighth transistor or pull-down transistor T, a first capacitor C, and a second capacitor C.

1 81 82 1 81 82 The first transistor Tis turned on by a previous clock signal CLK(n−1) and connects a first nodeand a second node. The first transistor Tincludes a gate electrode to which the previous clock signal CLK(n−1) is applied, a first electrode connected to the first node, and a second electrode connected to the second node.

2 1 82 2 82 1 The second transistor Tis turned on by the voltage from a second control node Qb(n) and connects a first power line PL, to which a high potential voltage VGH is applied to the second node. The second transistor Tincludes a gate electrode connected to the second control node Qb(n), a first electrode connected to the second node, and a second electrode connected to the first power line PL.

3 2 3 2 The third transistor Tis turned on by a next clock signal CLK(n+2) and connects a second power line PL, to which a low potential voltage VGL is applied, to the second control node Qb(n). The third transistor Tincludes a gate electrode to which the next clock signal CLK(n+2) is applied, a first electrode connected to the second power line PL, and a second electrode connected to the second control node Qb(n)

4 81 1 4 81 1 The fourth transistor Tis turned on by the voltage from the first nodeand connects the second control node Qb(n) to the first power line PL. The fourth transistor Tincludes a gate electrode connected to the first node, a first electrode connected to the second control node Qb(n), and a second electrode connected to the first power line PL.

5 82 5 2 82 The fifth transistor Tis turned on by a low potential voltage VGL and connects the second nodeto a first control node Q(n). The fifth transistor Tincludes a gate electrode connected to the second power line PL, a first electrode connected to the second node, and a second electrode connected to the first control node Q(n).

6 82 1 6 82 1 The sixth transistor Tis turned on by the voltage from the second nodeand connects the second control node Qb(n) to the first power line PL. The sixth transistor Tincludes a gate electrode connected to the second node, a first electrode connected to the second control node Qb(n), and a second electrode connected to the first power line PL.

7 7 The seventh transistor Tis turned on by the voltage from the first control node Q(n) and outputs the low potential voltage VGL to an output node OUT. The seventh transistor Tincludes a gate electrode connected to the first control node Q(n), a first electrode connected to the clock line CL to which the clock signal CLK(n) is applied, and a second electrode connected to the output node OUT.

8 8 1 The eighth transistor Tis turned on by the voltage from the second control node Qb(n) and outputs the high potential voltage VGH to the output node OUT. The eighth transistor Tincludes a gate electrode connected to the second control node Qb(n), a first electrode connected to the output node OUT, and a second electrode connected to the first power line PL.

1 7 2 8 The first capacitor Cis connected between the gate electrode and the second electrode of the seventh transistor T. The second capacitor Cis connected between the gate electrode and the second electrode of the eighth transistor T.

Because the gate driver outputs the gate signal based on the clock signal and the low potential voltage, any delay in the clock signal may cause a delay in the gate signal.

4 4 FIGS.A toC are diagrams for explaining the principle of applying a clock signal according to a comparative example.

4 4 FIGS.A toC 130 140 130 0 140 Referring to, in a comparative example, a clock signal GCLK may be generated using the timing controllerand the level shifter. In other words, the timing controllermay generate a clock signal GCLKhaving a first voltage level VCC and apply the clock signal to the level shifter.

140 1 1 0 1 2 The level shiftermay generate the clock signal GCLK having a second voltage level, namely a gate-on voltage VGHand a gate-off voltage VGL, from the clock signal GCLKhaving the first voltage level, and then apply the clock signal GCLK to all gate drivers of the first area Aand the second area Ain the display panel.

1 2 1 2 1 2 The clock signal GCLK is applied equally to all gate drivers in the first area Aand the second area A. Because the lengths of the wires through which the clock signal is applied vary depending on the areas, the RC delay varies. For example, the RC delay in the first area Ais greater than that in the second area A. Consequently, a delay in the clock signal GCLK occurs depending on the areas, which leads to a delay in the gate signal GOUT, resulting in variations in gate-on time and causing luminance deviation. Specifically, since the gate-on time of the gate signal GOUT in the first area Ais shorter than that in the second region A, the luminance in the first area is relatively lower.

Therefore, implementations propose measures to improve the delay deviation in the clock signal.

In a first implementation, it is intended to separate the clock lines to which the clock signal is applied depending on the areas, and apply clock signals having different voltage levels through the separated clock lines, respectively.

5 5 FIGS.A toC are diagrams for explaining the principle of applying a clock signal according to a first implementation.

5 5 FIGS.A toC 1 2 130 140 130 0 140 140 a b. Referring to, the first implementation may generate clock signals GCLKand GCLKhaving different voltage levels depending on the areas using the timing controllerand the level shifter. Specifically, the timing controllermay generate the clock signal GCLKhaving the first voltage level VCC and apply the clock signal to a first level shifterand a second level shifter

140 1 2 2 0 1 1 1 a The first level shiftermay generate a first clock signal GCLKhaving a second voltage level, i.e., a second gate-on voltage VGHand a second gate-off voltage VGL, from the clock signal GCLKhaving a first voltage level, and apply the generated first clock signal GCLKto all gate drivers in the first area Aof the display panel through a first clock line CL.

140 2 1 1 0 2 2 2 b The second level shiftermay generate the second clock signal GCLKhaving a second voltage level, i.e., a first gate-on voltage VGHand a first gate-off voltage VGL, from the clock signal GCLKhaving a first voltage level, and apply the generated second clock signal GCLKto all gate drivers in the second area Aof the display panel through a second clock line CL.

2 1 2 1 Here, the gate-on voltages are set such that the second gate-on voltage VGH>the first gate-on voltage VGH, and the gate-off voltages are set such that the second gate-off voltage VGL<the first gate-off voltage VGL.

1 2 2 1 2 1 1 2 1 2 By applying the first clock signal GCLKhaving VGHand VGLto the first area Aand the second clock signal GCLKhaving VGHand VGLto the second area A, the gate-on time deviation in the gate signal output from the gate driver in each area A, Amay be alleviated.

In the first implementation, the gate-on voltage of the clock signal applied to an area with relatively high RC delay is increased, and the gate-off voltage is decreased, but the implementation is not necessarily limited thereto. For example, the gate-on voltage of the clock signal applied to an area with relatively low RC delay may be decreased, and the gate-off voltage may be increased.

Data showing the results of improving the luminance deviation between the areas is shown in Table 1 below.

TABLE 1 Category Comparative Example Implementation Areas A1 A2 A1 A2 VGL −15.0 V −15.0 V −15.5 V −15.0 V 63Gray 27.1 nit 25.6 nit 25.6 mit 25.6 nit 31Gray 5.7 nit 5.2 nit 5.2 nit 5.2 nit

As shown in Table 1 above, it may be seen that in the comparative example where the same clock signal is applied to all of the areas, there is luminance variation between the areas, whereas in the implementation, the luminance variation between the areas is alleviated.

In a second implementation, it is intended to separate the clock lines to which a clock signal is applied depending on the areas, and to apply clock signals having different gate-on times through the separated clock lines, respectively.

6 6 FIGS.A toD are diagrams for explaining the principle of applying a clock signal according to a second implementation.

6 6 FIGS.A toC 1 2 130 140 130 1 2 140 Referring to, the second implementation may generate clock signals GCLKand GCLKhaving different gate-on times depending on the areas using the timing controllerand the level shifter. Specifically, the timing controllermay generate clock signals GCLK′ and GCLK′ having different gate-on times of the first voltage level VCC and apply them to the level shifter.

2 1 Here, the clock signal GCLK′ may be generated with a shorter gate-on time than that of the clock signal GCLK′.

140 1 2 1 1 1 2 1 1 1 2 2 2 The level shiftergenerates a first clock signal GCLKand a second clock signal GCLKhaving the second voltage level, i.e., a gate-on voltage VGHand a gate-off voltage VGL, from the clock signals GCLK′ and GCLK′ having different gate-on times of the first voltage level VCC, respectively, may apply the generated first clock signal GCLKto all gate drivers in the first area Aof the display panel through a first clock line CL, and may apply the generated second clock signal GCLKto all gate drivers in the second area Aof the display panel through a second clock line CL.

Here, the timing controller generates the clock signals having different gate-on times, but is not limited thereto. For example, the clock signals having different gate-on times may be generated by the level shifter.

6 FIG.D 130 0 140 Referring to, the timing controllermay generate the clock signal GCLKhaving the first voltage level VCC and apply the clock signal to the level shifter.

140 1 2 1 1 0 1 1 1 2 2 2 The level shiftermay generate the first clock signal GCLKand the second clock signal GCLKhaving different gate-on times of the second voltage level, i.e., a gate-on voltage VGHand a gate-off voltage VGL, from the clock signal GCLKhaving the first voltage level VCC, may apply the generated first clock signal GCLKto all gate drivers in the first area Aof the display panel through a first clock line CL, and may apply the generated second clock signal GCLKto all gate drivers in the second area Aof the display panel through a second clock line CL.

1 1 2 2 1 2 By applying the first clock signal GCLKhaving a first gate-on time to the first area Aand the second clock signal GCLKhaving a second gate-on time to the second area A, the gate-on time deviation in the gate signal output from the gate driver of each area A, Amay be alleviated.

In the second implementation, the gate-on time of the clock signal applied to an area with relatively high RC delay is increased, but the implementation is not necessarily limited thereto. For example, the gate-on time of the clock signal applied to an area with relatively low RC delay may be decreased.

1 2 Furthermore, in the implementation of the present disclosure, it is intended to slightly adjust the voltage level or the gate-on time of the clock signal in a boundary region where the first area Aand the second area Aare adjacent to each other.

7 7 FIGS.A toB are diagrams for explaining, as an example, the principle of applying a clock signal to a boundary region.

7 FIG.A 7 FIG.B 1 2 Referring toto, in the implementation of the present disclosure, a boundary region where the first area Aand the second area Aare adjacent to each other may be divided into a plurality of boundary areas, and clock signals having different voltage levels may be applied to the gate drivers disposed in each of the plurality of boundary areas.

1 2 3 4 5 6 1 2 3 4 5 6 For example, the boundary region may be divided into first to sixth boundary areas,,,,, and, and clock signals having six pairs of voltage levels may be applied to the separated first to sixth boundary areas,,,,, andthrough six pairs of clock lines, respectively.

2 2 1 1 1 6 The second clock signal GCLKhaving the voltage level applied to the second area Ais applied to the first boundary area, and the first clock signal GCLKhaving the voltage level applied to the first area Ais applied to the sixth boundary area.

2 1 2 3 4 5 2 1 Clock signals having voltage levels between the voltage level of the second clock signal GCLKand the voltage level of the first clock signal GCLKare applied to the second to fifth boundary areas,,, and. For example, clock signals having voltage levels between the gate-on voltage VGH or the gate-off voltage VGL of the second clock signal GCLKand the first clock signal GCLKmay be applied.

1 2 3 4 5 6 A clock signal with a gate-off voltage VGL of −15.0 V is applied to the first boundary area. A clock signal with a gate-off voltage VGL of −15.1 V is applied to the second boundary area. A clock signal with a gate-off voltage VGL of −15.2 V is applied to the third boundary area. A clock signal with a gate-off voltage VGL of −15.3 V is applied to the fourth boundary area. A clock signal with a gate-off voltage VGL of −15.4 V is applied to the fifth boundary area. A clock signal with a gate-off voltage VGL of −15.5 V is applied to the sixth boundary area.

1 2 3 4 5 6 In this implementation, the voltage levels of the clock signals to be applied to the first to sixth boundary areas,,,,, andmay be generated to increase or decrease by a constant magnitude.

130 140 That is, the timing controllergenerates a clock signal having the first voltage level and applies it to the level shifter.

140 The level shiftermay include six level shifters LS, and each of the six level shifters LS may generate clock signals having voltage levels based on pairs of different gate-on voltage VGH and gate-off voltage VGL from the clock signal having the first voltage level.

150 140 The power supplymay supply pairs of different gate-on voltage VGH and gate-off voltage VGL to the six level shifters LS included in the level shifter, respectively.

8 8 FIGS.A toB are diagrams for explaining, as another example, the principle of applying a clock signal to a boundary region.

8 8 FIGS.A andB 1 2 1 2 Referring to, in an implementation of the present disclosure, a boundary region where the first area Aand the second area Aare adjacent to each other may be divided into a plurality of boundary areas, and clock signals having different gate-on times may be applied to the gate drivers disposed in each of the plurality of boundary areas. Here, some of the gate drivers disposed in each boundary area may be configured to apply gate signals to the pixels in the first area Aand some other gate drivers may be configured to apply gate signals to the pixels in the second area A, but the configuration is not necessarily limited thereto.

1 2 3 4 5 6 1 2 3 4 5 6 For example, the boundary region may be divided into first to sixth boundary areas,,,,, and, and clock signals having six pairs of gate-on times may be applied to the separated first to sixth boundary areas,,,,, andthrough six pairs of clock lines, respectively.

2 2 1 1 1 6 The second clock signal GCLKhaving the gate-on time applied to the second area Ais applied to the first boundary area, and the first clock signal GCLKhaving the gate-on time applied to the first area Ais applied to the sixth boundary area.

2 1 2 3 4 5 Clock signals having gate-on times between the gate-on time of the second clock signal GCLKand the gate-on time of the first clock signal GCLKare applied to the second to fifth boundary areas,,, and.

1 2 3 4 5 6 A clock signal with a gate-on time of 5.0 μs is applied to the first boundary area. A clock signal with a gate-on time of 5.1 μs is applied to the second boundary area. A clock signal with a gate-on time of 5.2 μs is applied to the third boundary area. A clock signal with a gate-on time of 5.3 μs is applied to the fourth boundary area. A clock signal with a gate-on time of 5.4 μs is applied to the fifth boundary area. A clock signal with a gate-on time of 5.5 μs is applied to the sixth boundary area.

1 2 3 4 5 6 In this implementation, the gate-on times of the clock signals to be applied to the first to sixth boundary areas,,,,, andmay be generated to increase or decrease by a constant magnitude.

130 140 140 130 In one example, the timing controllergenerates clock signals having different gate-on times of the first voltage level and applies them to the level shifter. The level shiftermay generate clock signals having second voltage levels, namely a gate-on voltage VGH and a gate-off voltage VGL, from the clock signals having different gate-on times provided from the timing controller.

130 140 140 130 In another example, the timing controllergenerates clock signals having first voltage levels and applies them to the level shifter. The level shiftermay generate clock signals having second voltage levels, i.e., different gate-on times of the gate-on voltage VGH and the gate-off voltage VGL, from the clock signal having the first voltage level applied from the timing controller.

150 140 130 In this case, the power supplymay supply predetermined gate-on voltage VGH and gate-off voltage VGL to the level shifterunder the control of the timing controller.

Although the implementations of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the implementations disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-described implementations are illustrative in all aspects and do not limit the present disclosure.