Control Device of Power Switch

This application claims the priority benefit of Taiwan application serial no. 113135133, filed on Sep. 16, 2024. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

The disclosure relates to a control device of a power switch, and in particular, relates to a control device of a power switch capable of preventing generation of voltage spikes by an input voltage when the power switch is turned off.

In electronic devices, power switches are installed most of the time to control the voltage supply operation. Due to the presence of stray inductance in the circuit loop, rapidly turning off a power switch under conditions of large output and input currents may generate a large and instantaneous current change in the circuit loop. This instantaneous current change may cause the phenomenon of input voltage spikes to appear in the input voltage. Further, this voltage spike phenomenon may lead to damage of peripheral passive components or power components and may also generate unnecessary electromagnetic interference, and the normal operation of the electronic device is thus affected.

The disclosure provides a control device of a power switch configured to decrease generation of voltage spikes by an input voltage during a procedure of turning off the power switch.

The disclosure provides a control device of a power switch, and the control device includes a discharge current generator. The discharge current generator is coupled between a control end of the power switch and a reference voltage. In a time period when the power switch is turned off, the discharge current generator combines a first current and a second current in a first sub-time period to generate a third current and sets the control end of the power switch to be discharged according to the third current. The discharge current generator merely provides the second current in a second sub-time period and sets the control end of the power switch to be discharged according to the second current. The third current is greater than the second current. The first current decreases with time in the first sub-time period. The second current is a constant current.

To sum up, in the disclosure, the control device of the power switch provides the hybrid third current (a combination of the first current and the second current) in the first sub-time period during the procedure of turning off the power switch to discharge the control end of the power switch, so that the power switch may quickly enter the off state. Further, in the second sub-time period following the first sub-time period, only the constant second current is provided to discharge the control end of the power switch, so that the control voltage of the power switch decreases slowly in the second time period. In this way, under the soft start control mechanism, the control device of the power switch can take into account the turn-off rate of the power switch, and the working efficiency of the power switch is effectively improved.

To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.

1 FIG. 1 FIG. 100 With reference to,is a schematic diagram illustrating a control device of a power switch according to an embodiment of the disclosure. A control deviceis coupled to a control end of a power switch PSW to control a control voltage VG on the control end of the power switch PSW and adjusts the control voltage VG to turn on or turn off the power switch PSW. In this embodiment, the power switch PSW is constructed by a transistor MP. The transistor MP may be an N-type transistor, and first end (e.g., a source) thereof may receive an input voltage VIN. A second end (e.g., a drain) of the transistor MP may generate an output voltage VOUT. A control end (e.g., a gate) of the transistor MP may receive the control voltage VG.

100 110 110 100 100 The control deviceincludes a discharge current generator. The discharge current generatoris coupled between the control end of the power switch PSW and a reference voltage VSS. In a time period when the control deviceexecutes a turn-off procedure of the power switch PSW, the control devicemay simultaneously provide a first current and a second current in a first sub-time period, generate a third current by combining the first current and the second current, and discharge the control end of the power switch PSW using the third current. The third current is greater than the second current. A current flow direction of the third current is from the control end of the power switch PSW towards the reference voltage VSS, and in this embodiment, the reference voltage VSS may be a reference ground voltage.

110 By discharging the control end of the power switch PSW using the third current, the discharge current generatormay, in the first sub-time period, cause the control voltage VG to decrease rapidly, thereby enabling the transistor MP to enter a cut-off state within the first sub-time period.

100 100 It is worth noting that the first current provided by the control devicemay be a ramp current that decreases with time, while the second current provided by the control devicemay be a constant current. Taking the linear decrease of the first current in the first sub-time period as an example, the control voltage VG may also correspondingly decrease linearly in the first sub-time period.

100 Next, in the second time period following the first time period, the control devicemay change to provide only the second current and discharge the control end of the power switch PSW using the second current. In this way, in the second time period, the control voltage VG may decrease slowly, so that generation of a voltage spike on the input voltage VIN is effectively decreased.

100 110 110 110 According to the above, in the disclosure, the control deviceprovides the discharge current generatorand sets the discharge current generatorto discharge the control end of the power switch PSW using the third current, which is a ramp current, in the first sub-time period, so that the control voltage VG is accordingly reduced and the transistor MP is set to quickly enter a cut-off region. The discharge current generatoralso provides the constant second current to discharge the control end of the power switch PSW in the second sub-time period and causes the control voltage VG to decrease slowly, so that the stability of the input voltage VIN is controlled.

2 FIG.A 2 FIG.A 200 201 201 201 210 220 230 210 220 210 1 230 2 220 230 1 1 1 5 1 With reference to,is a circuit schematic diagram illustrating a control device of the power switch according to another embodiment of the disclosure. A control deviceincludes a discharge current generator. The discharge current generatoris coupled to a control end CE of the power switch and is used to adjust the control voltage VG. The discharge current generatorincludes a ramp voltage generatorand current sourcesand. The ramp voltage generatoris used to generate a ramp voltage VRP in a first sub-time period based on an enable signal EN. The current sourceis coupled to the ramp voltage generatorand the control end CE of the power switch and provides a first current IDin the first sub-time period according to the ramp voltage VRP. The current sourceis coupled to the control end CE of the power switch and generates a second current IDin the first sub-time period and the second sub-time period according to the enable signal EN. In this embodiment, the current sourcesandare coupled to a switch SWtogether and are coupled to the control end CE of the power switch through the switch SW. The switch SWmay be constructed by a transistor M, which is controlled by an inverted enable signal ENB and is turned on when the enable signal EN is at logic value 0 (inverted enable signal ENB is at logic value 1). Conversely, when the enable signal EN is at logic value 1 (inverted enable signal ENB is at logic value 0), the switch SWis turned off.

220 1 230 2 1 2 1 220 230 3 1 2 230 2 In this embodiment, the current sourceis constructed by a transistor M, while the current sourceis constructed by a transistor M. The transistors Mand Mare connected in parallel between the switch SWand the reference voltage VSS. In the first sub-time period, the current sourcesandprovide a third current ID(equal to a sum of the first current IDand the second current ID) together to the control end CE. In the second sub-time period, only the current sourceprovides the second current IDto the control end CE.

210 211 1 3 212 211 1 211 1 1 1 3 212 1 211 3 212 3 The ramp voltage generatorincludes a current source, a capacitor C, a transistor M, and a current source. The current sourceand the capacitor Care connected in series. The current sourcemay provide a reference current IRto the capacitor Cbased on a power voltage VDD and is used to charge the capacitor C. The transistor Mis coupled between the current sourceand a mutually coupled end point of the capacitor Cand the current source. The transistor Macts as a switch and may be turned on or off according to the inverted enable signal ENB. The current sourceis coupled between the transistor Mand the reference voltage VSS.

2 FIG.A 2 FIG.B 2 FIG.B 2 FIG.A 200 200 211 1 0 1 1 3 1 212 3 212 1 2 211 1 With reference toandtogether,is an operation waveform diagram illustrating the control deviceaccording to the embodiment ofof the disclosure. In an initial state when the control deviceexecutes a turn-off procedure of the power switch, the ramp voltage VRP provided at the mutually coupled end point of the current sourceand the capacitor Cis at a relatively high voltage value. When the turn-off procedure of the power switch is initiated, the enable signal EN transitions to a logic value ofand may enter a first sub-time period TS. In the first sub-time period TS, the transistor Mis turned on according to the inverted enable signal ENB, which has a logic value of. Herein, the capacitor Cl is coupled to the current sourcethrough the transistor M. The current sourcethen discharges the capacitor Cthrough a reference current IRit provides. As a result, the ramp voltage VRP may decrease linearly. It is worth noting that when the enable signal EN transitions to a logic value of 1, the current sourcemay be turned off to stop providing the reference current IR.

1 220 1 1 1 220 1 230 2 1 230 2 1 In the first sub-time period TS, the current sourcegenerates the first current IDaccording to the ramp voltage VRP. As the ramp voltage VRP decreases with time in the first sub-time period TS, the first current IDgenerated by the current sourceis a ramp current that decreases with time during the first sub-time period TS. On the other hand, the current sourcemay generate the second current IDin the first sub-time period TSaccording to the inverted enable signal ENB, which has a logic value of 1. Since the inverted enable signal ENB has a constant voltage value, the current sourcemay generate the second current IDas a constant current in the first sub-time period TS.

1 1 201 1 2 1 2 In the first sub-time period TS, the switch SWmay be turned on according to the inverted enable signal ENB. Therefore, the discharge current generatormay combine the first current IDand the second current ID, draw a third current (equal to the sum of the first current IDand the second current ID) from the control end CE of the power switch, and set the control end CE of the power switch to be discharged according to the third current, so that a voltage value of the control voltage VG is decreased.

1 1 In this embodiment, when the control voltage VG is pulled down to equal a sum of the output voltage VOUT and a threshold voltage of a power transistor of the power switch, the power switch may be correspondingly turned off. Based on the control voltage VG, in the first sub-time period TS, turn-off time tOFF of the power switch may be effectively reduced due to the rapid decrease of the first current ID, which is a ramp current.

2 220 1 201 2 230 2 Next, in the second sub-time period TS, as the ramp voltage VRP has approached the reference voltage VSS, the current sourcemay stop generating the first current ID. At this time, the discharge current generatormerely provides the second current IDthrough the current sourceand sets the control end CE of the power switch to be discharged only according to the second current ID. Under these conditions, the control voltage VG decreases slowly. A current IIN at an input end of the power switch may gradually decrease as the control voltage VG decreases, without generating the phenomenon of current surge. Under the premise of not generating the phenomenon of current surge, the input voltage of the power switch also may not generate a voltage spike.

2 After the second sub-time period TS, the control voltage VG may be directly pulled down to equal the reference voltage VSS.

2 FIG.A 4 3 1 4 3 220 It is worth mentioning that in, transistors Mand Mmay construct an inverter. An inverter IVis used to receive the enable signal EN and generate the inverted enable signal ENB. The inverter constructed by the transistors Mand Mmay receive the inverted enable signal ENB, generate an output signal that has a time delay but has a same phase as the enable signal EN, and output this output signal to the control end of the current source.

1 2 212 In this embodiment, a capacitance value of the capacitor Cand a current value of the reference current IRprovided by the current sourcemay determine a slope of the ramp voltage VRP when it decreases.

3 FIG. 3 FIG. 300 300 310 320 310 320 With reference to,is a schematic diagram illustrating a control device of the power switch according to an embodiment of the disclosure. A control deviceis coupled to the control end of the power switch PSW to control the control voltage VG on the control end of the power switch PSW and adjusts the control voltage VG to turn on or turn off the power switch PSW. The control deviceincludes a discharge current generatorand a comparator. The discharge current generatorand the comparatorare coupled to each other.

310 210 320 320 310 310 310 310 1 FIG. In this embodiment, the discharge current generatoris similar to the discharge current generatorin the embodiment of. The comparatoris configured to compare the control voltage VG on the control end of the power switch with the output voltage VOUT of the power switch to generate a detection signal DET. When the voltage value of the control voltage VG is less than a sum of voltage values of the output voltage VOUT and a bias voltage, the comparatoruses the generated detection signal DET to control the discharge current generatorto start gradually decreasing the voltage value of the generated ramp voltage at a specific time point. Further, in this embodiment, the ramp voltage provided by the discharge current generatordoes not gradually decrease with time at the beginning of the first sub-time period. According to the detection signal DET, the discharge current generatoronly starts to decrease the voltage value of the ramp voltage when the voltage value of the control voltage VG decreases to less than the sum of the output voltage VOUT and the bias voltage. In other words, at the beginning of the first sub-time period, the discharge current generatormay maintain the provided first current at a relatively high current value for a period of time, which may accelerate the turn-off operation of the power switch.

4 FIG.A 4 FIG.B 4 FIG.A 4 FIG.B 4 FIG.A 2 FIG.A 400 400 410 420 410 210 210 3 410 420 With reference toandtogether,is a circuit schematic diagram illustrating a control device of the power switch according to another embodiment of the disclosure.is an operation waveform diagram illustrating a control deviceaccording to the embodiment ofof the disclosure. In this embodiment, the control deviceincludes a discharge current generatorand a comparator. The discharge current generatorhas a similar circuit structure to the discharge current generatorin, and description of the similarities therebetween is not repeated. Different from the discharge current generator, in this embodiment, a control end of the transistor Min the discharge current generatorreceives the detection signal DET, and the detection signal DET is provided by the comparator.

420 1 2 8 9 10 1 2 1 2 1 2 8 9 1 2 6 7 1 2 8 9 1 2 10 10 9 1 The comparatorincludes a plurality of diodes Dand D, transistors M, M, and M, bias current sources Iband Ib, and inverters INVand INV. The diodes Dand Dand the transistors Mand Mare connected in series sequentially, with diodes Dand Dbeing constructed by transistors Mand Mrespectively. An anode of diode Dis coupled to the control end CE of the power switch, while a cathode of diode Dis coupled to the transistor M. The transistor Mis coupled to the bias current source Ib. In addition, the bias current source Iband the transistor Mare connected in series between the power voltage VDD and the reference voltage VSS, with a control end of transistor Mcoupled to a mutually coupled end of the transistor Mand the bias current source Ib.

1 2 1 2 2 The inverters INVand INVare connected in series, where an input end of inverter INVis coupled to an output terminal of bias current source Ib, while an output terminal of inverter INVgenerates the detection signal DET.

1 2 420 3 3 The series-connected diodes Dand Dare used to provide a bias voltage. When the control voltage VG is less than a sum of the output voltage VOUT and the bias voltage, the comparatormay provide the detection signal DET with a logic value of 1. By providing the detection signal DET having a logic value of 1 to the control end of the transistor M, the transistor Mis turned on and the ramp voltage VRP starts to decrease with time.

4 FIG.B 1 1 1 1 1 1 With reference to, in a time period TA, since the control voltage VG is not less than the sum of the output voltage VOUT and the bias voltage, the detection signal DET is at logic value 0, the ramp voltage VRP maintains a fixed relatively high voltage value, and the first current IDcorrespondingly maintains a fixed relatively high current value during the time period TA. After the control voltage VG becomes less than the sum of the output voltage VOUT and the bias voltage, in the first sub-time period TSand outside the time period TA, the ramp voltage VRP and the first current IDbegin to gradually decrease with time. Through this mechanism, the turn-off time tOFF of the power switch may be further reduced.

2 220 1 410 2 230 2 Similarly, in the second sub-time period TS, since the ramp voltage VRP has approached the reference voltage VSS, the current sourcemay stop generating the first current ID. At this time, the discharge current generatormerely provides the second current IDthrough the current sourceand sets the control end CE of the power switch to be discharged only according to the second current ID. Under these conditions, the control voltage VG decreases slowly. The current IIN at the input end of the power switch may gradually decrease as the control voltage VG decreases, without generating the phenomenon of current surge.

1 It is worth mentioning that in this embodiment, the transistor Mmay first operate in a triode region and then operate in a saturation region in the first sub-time period.

5 FIG. 5 FIG. 500 510 520 5 510 51 520 500 5 510 520 51 With reference to,is a schematic diagram illustrating a control device of the power switch according to another embodiment of the disclosure. A control deviceincludes a discharge current generator, a boost circuit, and a switch SW. The discharge current generatorand the switch SWare connected in series between the control end of the power switch PSW and the reference voltage VSS. The boost circuitis coupled to the control end of the power switch PSW. When the control deviceis to enable the power switch PSW to be turned on, the switch SWmay be opened according to the inverted enable signal ENB, thereby disconnecting the discharge current generatorfrom the control end of the power switch PSW. The boost circuitmay enable the power switch PSW to be turned on by raising the control voltage VG. The inverted enable signal ENB is generated by the inverter IVbased on the enable signal EN.

500 5 510 510 510 210 410 420 2 FIG.A 4 FIG.A When the control deviceis to turn off the power switch PSW, the switch SWmay be turned on according to the inverted enable signal ENB, thereby connecting the discharge current generatorto the control end of the power switch PSW. The discharge current generatormay discharge the control end of the power switch PSW by generating current, thereby reducing the control voltage VG to turn off the power switch PSW. The discharge current generatormay be implemented using the discharge current generatorof the embodiment inof the disclosure or it may also be implemented using the discharge current generatorof the embodiment inof the disclosure together with the comparator. The relevant details have been explained thoroughly in the aforementioned embodiments and are not to be repeated herein.

In view of the foregoing, in the control device provided by the disclosure, during the procedure of turning off the power switch, different currents in multiple stages are provided to discharge the control end of the power switch, so that the control voltage is decreased in a segmented manner. In this way, the power switch may be quickly turned off in the first sub-time period. The control voltage may decrease slowly in the second sub-time period. Under the premise of not delaying the turn-off time of the power switch, the generation of voltage spikes by the input voltage is effectively reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.