Data Compression Device, Data Compression/Decompression System, and Memory System

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2024-161015, filed Sep. 18, 2024, the entire contents of which are incorporated herein by reference.

Embodiments described herein relate generally to a data compression device, a data compression/decompression system, and a memory system.

For example, in a data compressor with an LZ77-type dictionary compression circuit, data which has been previously input is buffered in a dictionary buffer, and data which matches the input data is retrieved in the previous data in the dictionary buffer. If the matching data is stored in the dictionary buffer, the matching data is replaced with a match distance indicating an address of the dictionary buffer and a match length indicating a length of the matching data, which are output as dictionary compression results, and compression is thereby executed. One of methods of improving the compression efficiency of the dictionary compression circuit is to increase the dictionary size (i.e., a parameter indicating how many bytes can be retrieved for previous matching or not). However, if the dictionary size increases, the circuit size of the dictionary buffer and the dictionary search logic for searching for matches from the dictionary buffer increases.

In general, according to one embodiment, a data compression device includes N (N is an integer of two or more) data compression circuits, a dictionary buffer concatenation control circuit, and a longest match selection circuit. The N data compression circuits each includes a first dictionary compression circuit. The dictionary buffer concatenation control circuit controls switching between a first mode and a second mode. The first mode is a mode in which each of the N data compression circuits operate independently. The second mode is a mode in which the N data compression circuits cooperate. In the second mode, the longest match selection circuit selects a dictionary compression result with a longest match length from among the dictionary compression results of the N first dictionary compression circuits in the N data compression circuits. The first dictionary compression circuit includes a dictionary buffer for buffering the uncompressed data to be input and compressed, as dictionary data. In the first mode, the dictionary buffer concatenation control circuit inputs the N uncompressed data different from each other to the N data compression circuits. In the second mode, the dictionary buffer concatenation control circuit concatenates the N dictionary buffers by storing, when registering the dictionary data to an i-th (i is an integer of 1 or more and N−1 or less) dictionary buffer out of the N dictionary buffers of the N data compression circuits, oldest dictionary data stored in the i-th dictionary buffer in the (i+1)-th dictionary buffer, and inputs same uncompressed data to the N data compression circuits.

Embodiments will be described hereinafter with reference to the accompanying drawings.

First, a first embodiment will be described.

1 FIG. 1 FIG. 1 1 2 1 2 is a view showing an example of a configuration of a memory systemof the first embodiment.shows an example of a configuration of an information processing system including both a memory systemand a hostconnected to the memory systemas a storage. The hostis an information processing apparatus such as a server or a personal computer.

1 11 12 1 1 1 12 The memory systemincludes a memory controllerand a flash memory. In this example, the memory systemis implemented as a solid state drive (SSD). The memory systemcan be implemented as not only SSD, but also various types of data storage devices. In other words, the memory systemcan be equipped with not only the flash memory, but also various types of storage media.

11 1 11 111 112 113 114 115 116 The memory controlleris a device that controls the overall operations of the memory system. The memory controllerincludes a processor, a host interface circuit, a memory interface circuit, a data compression device, a data decompression device, and an error check and correct (ECC) circuit.

111 11 11 12 2 12 2 11 111 11 The processorimplements various processes that the memory controlleris to execute, by running programs referred to as firmware or the like. The various processes that the memory controlleris to execute include a write process of writing data to the flash memoryin response to write commands from the host, a read process of reading data stored in the flash memoryin response to read commands from the host, and the like. An example in which the various processes to be executed by the memory controllerare implemented by the processorexecuting firmware. However, the processes may also be improved by dedicated hardware built in the memory controller, such as an electrical circuit.

112 2 113 12 12 The host interface circuitcontrols communication conforming to predetermined communication standards with the host. The memory interface circuitcontrols writing data to the flash memoryand reading data from the flash memory.

114 12 115 12 1 The data compression devicecompresses the write data that is requested to be written to the flash memoryby the write commands to generate compressed data. The data decompression devicedecompresses the compressed data corresponding to the read data that is requested to be read from the flash memoryby the read commands to obtain the read data. In other words, the memory systemof the first embodiment has a data compression and decompression system which compresses and decompresses data.

116 114 116 12 111 12 113 111 114 12 113 2 111 12 113 116 116 12 115 111 115 111 2 2 111 12 2 2 The ECC circuitexecutes an error correction process for the compressed data generated by the data compression device. More specifically, when a write command is received, the ECC circuitgenerates an error correction code to detect and correct errors in preparation for a case where errors may occur in future in the compressed data to be written to the flash memory. Then, the processoris configured to write the error correction code to the flash memoryvia the memory interface circuit. In other words, the processoris configured to write data based on the compressed data generated by the data compression device, to the flash memoryvia the memory interface circuit. In addition, when receiving a read command from the host, the processorreads data based on the received read command, from the flash memory, via the memory interface circuit. The ECC circuitexecutes the error correction process on the read data. In other words, the ECC circuitchecks whether or not an error occurs in the compressed data read from the flash memory, by using the error correction code, and, if an error is detected, corrects the error. The read data which is subjected to the error correction process is input to the decompression deviceas compressed data by the processor, and the decompression devicedecompresses the input compressed data. The processorsends the decompressed data to the hostin response to the read command from the host. In other words, the processoris configured to decompress data based on data read from the flash memoryand to send the decompressed data to the host, in response to the read command from the host.

2 FIG. is a view showing a comparative example to illustrate increasing a circuit scale of a dictionary compressor as a dictionary size is increased to improve a compression efficiency of the dictionary compressor.

2 FIG.(A) 80 81 shows an example of a configuration of a compressed intellectual property (IP)that includes a dictionary compressorwith a dictionary size of 2 KiB.

81 811 812 811 811 812 811 The dictionary compressorincludes a dictionary bufferbuffering previously input data and a dictionary search logicsearching for data which matches the currently input data from the dictionary buffer. The dictionary bufferhas a capacity which enables past 2 KiB of previously input data to be buffered. In addition, the dictionary search logichas the ability to search for data which matches the current input data from 2 KiB of previously input data buffered in the dictionary buffer.

80 82 81 The compressed IPfurther includes an entropy coding unitwhich executes entropy coding on the dictionary compression results output from the dictionary compressor.

2 FIG.(B) 90 91 911 90 912 811 In contrast,shows an example of a configuration of a compressed IPthat includes a dictionary compressorwith a dictionary size of 4 KiB. The dictionary bufferof the compressed IPhas a capacity which enables 4 KiB of previously input data to be buffered. In addition, a dictionary search logichas the ability to search for data which matches the current input data from 4 KiB of previously input data buffered in the dictionary buffer.

90 92 91 The compressed IPfurther includes an entropy coding unitwhich executes entropy coding on the dictionary compression results output from a dictionary compressor.

811 812 81 80 911 912 91 90 2 FIG.(A) 2 FIG.(B) As is clarified from comparison between the dictionary bufferand the dictionary search logicof the dictionary compressorin the compressed IPinand the dictionary bufferand the dictionary search logicof the dictionary compressorin the compressed IPin, increasing the dictionary size of the dictionary compressor, for example from 2 KiB to 4 KiB, in order to improve the compression efficiency of the dictionary compressor results in an increase in the circuit scale of the dictionary compressor.

114 1 In contrast, the data compression devicein the memory systemof the first embodiment achieves an increase in the dictionary size by diverting existing resources without causing an increase in the circuit scale of the dictionary compressor. This point will be described below in detail.

3 FIG. 114 1 is a view showing an example of a configuration of the data compression devicein the memory systemof the first embodiment.

114 0 1 21 1 2 21 The data compression deviceof the first embodiment includes two compressed IP (Coreand Core). Subscripts (-and -) are used if the compressed IPneed to be distinguished in the following descriptions, and the subscripts are omitted if they do not need to be distinguished. Subscripts may also be used for other components that exist in multiple parts.

21 32 The compressed IPentropy-encodes the dictionary compression results output by the dictionary compressor of LZ77 method, by an entropy coding unit. The entropy encoding method is, for example, Huffman encoding.

31 41 42 43 44 41 31 811 911 31 41 42 41 2 FIG.(A) 2 FIG.(B) A dictionary compressoris, for example, dictionary compression hardware (HW) with a dictionary size of 2 KiB and an input throughput of 4 Bytes/cycle, and includes a 2 KiB shift register, a byte-by-byte comparison unit, a match length calculation unit, and a longest match determination unit. The shift registeris a dictionary buffer that buffers (stores) the data previously input to the dictionary compressor, such as the dictionary bufferinand the dictionary bufferin. Then, if data is input to the dictionary compressorafter that, the shift registeris used when the byte-by-byte comparison unitsearches for data which matches the input data, in the dictionary data stored in the shift register.

31 31 41 41 42 41 43 41 42 44 41 When 4 bytes of uncompressed data are input to the dictionary compressorin each cycle, the dictionary compressorwrites the input uncompressed data to the shift register. The uncompressed data written to the shift registeris treated as dictionary data. The byte-by-byte comparison unitcompares the uncompressed data stored in the shift registerwith a size of a maximum of 2 KiB with the 4-byte input uncompressed data. Next, in the match length calculation unit, calculation of the match length for all match distances, which are the match distances, i.e., the distances from certain uncompressed data in the input uncompressed data to certain uncompressed data in the uncompressed data held in the shift registeris executed based on the comparison results of the byte comparison unit. Finally, the longest match length among the match lengths of all the match distances is selected in the longest match determination unit. The shift registeris shifted 4 bytes per cycle in a direction of pushing out the previously input data, and the input uncompressed data is written in empty 4 bytes.

22 41 31 0 21 1 41 31 1 21 2 1 21 2 114 2 11 The dictionary buffer concatenation controllercontrols the connection between the shift registerof the dictionary compressorof the compressed IP (Core)-and the shift registerof the dictionary compressorof the compressed IP (Core)-, and controls the input of uncompressed data to the compressed IP (Core)-, based on the compression level input to the data compression device. The compression level is a value indicating the level among predetermined number of levels, of the compression efficiency requested by the hostto the memory controller.

22 0 21 1 1 21 2 41 31 0 21 1 31 1 21 2 0 21 1 1 21 2 If the compression level is less than a predetermined threshold value, the dictionary buffer concatenation controllercontrols the compressed IP (Core)-and the compressed IP (Core)-to operate independently. In other words, the shift registerof the dictionary compressorof the compressed IP (Core)-is not connected to the shift register of the dictionary compressorof the compressed IP (Core)-, and separate uncompressed data is input to each of the compressed IP (Core)-and the compressed IP (Core)-.

0 21 1 1 21 2 114 114 As a result, the compressed IP (Core)-and the compressed IP (Core)-can operate in parallel, and the data compression deviceprovides two compressed IP with a 4-byte/cycle, 2-KiB dictionary size as the first mode, and the overall input throughput of the data compression devicebecomes 8 bytes/cycle.

22 41 0 21 1 41 1 21 2 22 41 31 1 21 2 41 0 21 1 41 1 21 2 22 41 0 21 1 41 1 21 2 41 31 1 21 2 41 31 0 21 1 22 51 In contrast, when the compression level is above a predetermined threshold, the dictionary buffer concatenation controllercontrols the shift registerof the compressed IP (Core)-and the shift registerof the compressed IP (Core)-to operate as a single dictionary buffer. The dictionary buffer concatenation controllerhas used the input to the shift registerof the dictionary compressorof the compressed IP (Core)-as input uncompressed data until the shift registerof the compressed IP (Core)-and the shift registerof the compressed IP (Core)-are concatenated to each other. If the compression level is more than or equal to a predetermined threshold value, the dictionary buffer concatenation controllerconcatenates the shift registerof the compressed IP (core)-and the shift registerof the compressed IP (core)-, and switches the input to the shift registerof the dictionary compressorof the compressed IP (Core)-to the oldest dictionary data that has been pushed out of the shift registerof the dictionary compressorof the compressed IP (Core)-. More specifically, the dictionary buffer concatenation controllercontrols the switch.

22 42 31 1 21 2 1 21 2 0 21 1 22 52 In addition, the dictionary buffer concatenation controllerswitches the input to the byte-by-byte comparison unitof the dictionary compressorof the compressed IP (Core)-from the uncompressed data that is the input to the compressed IP (Core)-to the uncompressed data that is the input to the compressed IP (Core)-. More specifically, the dictionary buffer concatenation controllercontrols the switch.

44 31 0 21 1 44 31 1 21 2 23 23 32 0 21 1 53 22 44 1 21 2 33 54 22 32 1 21 2 22 44 1 21 2 33 54 32 1 21 2 22 32 1 21 2 44 1 21 2 32 1 21 2 The match length of the match output from the longest match determination unitof the dictionary compressorof the compressed IP (Core)-is compared with the match length of the match output from the longest match determination unitof the dictionary compressorof the compressed IP (Core)-by the longest match selector. The longest match is selected by the longest match selector, and is input to the entropy coding unitof the compressed IP (Core)-under the control of the switchby the dictionary buffer concatenation controller. In addition, in this case, the output of the longest match determination unitof the compressed IP (Core)-is switched to be supplied to the discard controller, under the control of the switchby the dictionary buffer concatenation controller, and the entropy coding unitof the compressed IP (Core)-does not operate. In other words, the dictionary buffer concatenation controllerswitches the output of the longest match determination unitof the compressed IP (Core)-to be supplied to the discard controller, by controlling the switch, and controls the entropy coding unitof the compressed IP (Core)-not to operate. In other words, the dictionary buffer concatenation controllersets the entropy coding unitof the compressed IP (Core)-, which is in operation by being supplied with the output of the longest match determination unitof the compressed IP (Core)-, in a non-operated state by cutting off the input to the entropy coding unitof the compressed IP (Core)-.

41 0 21 1 1 21 2 42 43 44 As a result, the shift registersof the compressed IP (Core)-and the compressed IP (Core)-are concatenated to form a 4 KiB dictionary and, accordingly, the byte-by-byte comparison unit, the match length calculation unit, and the longest match determination unitare also concatenated to obtain the match search results for the 4 KiB dictionary.

114 114 As a result, the data compression deviceprovides one compressed IP with a 4-byte/cycle and 4-KiB dictionary size as the second mode, and the overall input throughput of the data compression devicebecomes 4 bytes/cycle. The input throughput at concatenation of the dictionary buffers is halved compared to that in a case where the dictionary buffers are not concatenated but, instead, increase in the compression ratio can be expected by doubling the dictionary size. In addition, since this method can be achieved by diverting existing components, the increase in circuit size caused by the increase in dictionary size can also be suppressed.

4 FIG. 21 114 1 is a view showing both a manner of viewing a compressed IPwith and without the dictionary buffer concatenation in the data compression deviceand a configuration of a dictionary buffer in a case where the dictionary buffer concatenation is formed, in the memory systemof the first embodiment.

4 FIG.(A) 21 shows a manner of viewing the compressed IPwith and without dictionary buffer concatenation, which is determined by the compression level.

21 114 When the compression level is less than a predetermined threshold value, the dictionary buffer concatenation is not formed (OFF). In this case, each of the two compressed IPoperates independently at 4 bytes/cycle and a dictionary size of 2 KiB. In this case, the overall input throughput of the data compression deviceis 8 bytes/cycle.

21 114 In contrast, if the compression level is more than or equal to a predetermined threshold value, the dictionary buffer concatenation is formed (ON). In this case, the two compressed IPcooperate at a 4-byte/cycle and 4-KiB dictionary size. In this case, the overall input throughput of the data compression deviceis 4 bytes/cycle.

4 FIG.(B) 41 31 0 21 1 41 31 1 21 2 41 31 0 21 1 shows an example of the dictionary buffer configuration in a case where the dictionary buffer concatenation is formed (ON). When the dictionary buffer concatenation is formed (ON), the uncompressed data is first input to the shift registerof the dictionary compressorof the compressed IP (Core)-. The uncompressed data is shifted 4 bytes per cycle, and is input to the shift registerof the dictionary compressorof the compressed IP (Core)-when pushed out of the shift registerof the dictionary compressorof the compressed IP (Core)-.

114 1 41 31 1 21 2 As described above, the data compression devicein the memory systemof the first embodiment can increase the dictionary size by diverting the existing resource of the shift registerof the dictionary compressorof the compressed IP (Core)-.

Next, a second embodiment will be described.

The second embodiment is also an example of a memory system implemented as an SSD, similarly to the first embodiment. The same components as those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

5 FIG. 114 1 is a view showing an example of a configuration of a data compression devicein a memory systemof the second embodiment.

114 41 31 0 21 1 41 31 1 21 2 34 1 21 2 32 In the data compression deviceof the second embodiment, a shift registerof a dictionary compressorof compressed IP (Core)-is concatenated to a shift registerof a dictionary compressorof compressed IP (Core)-. Furthermore, a delay bufferof the compressed IP (Core)-in which an entropy coding unitdoes not operate at concatenation of the dictionary buffers is diverted (used) as a dictionary buffer. As a result, the second embodiment can increase the dictionary size more than the first embodiment.

32 34 0 21 1 0 21 2 The entropy coding unituses dynamic Huffman coding (i.e., Huffman coding method generating a code table based on the appearance frequency of input symbols) as the entropy coding method, and includes a delay bufferconfigured with, for example, 10 KiB-SRAM in each of the compressed IP (Core)-and the compressed IP (Core)-for the purpose of buffering input symbols during the cycle period of the code table generation.

34 32 31 0 21 1 31 The symbols of the dictionary compression results are buffered in the delay buffer. The entropy coding unitcounts the appearance frequency of each symbol included in a block of a predetermined size, and then constructs a Huffman tree based on the obtained appearance frequency to generate an encoding table. The dictionary compressorof the compressed IP (Core)-has the same configuration as the dictionary compressorof the first embodiment.

31 0 21 2 45 31 22 The dictionary compressorof the compressed IP (Core)-includes a hash-based dictionary search unitin addition to the configuration of the dictionary compressorof the first embodiment. The operations of the dictionary buffer concatenation controllerin the second embodiment are as follows.

22 0 21 1 1 21 2 41 31 0 21 1 31 1 21 2 0 21 1 1 21 2 45 If the compression level is less than a predetermined threshold value, the dictionary buffer concatenation controllercontrols the compressed IP (Core)-and the compressed IP (Core)-to operate independently. In other words, the shift registerof the dictionary compressorof the compressed IP (Core)-is not connected to the shift register of the dictionary compressorof the compressed IP (Core)-, and separate uncompressed data is input to each of the compressed IP (Core)-and the compressed IP (Core)-. In addition, the hash-based dictionary search unitdoes not operate.

34 0 21 1 34 0 21 2 44 0 21 1 1 21 2 The inputs to the delay bufferof the compressed IP (Core)-and the delay bufferof the compressed IP (Core)-are the outputs of the longest match determination unitsin the compressed IP (Core)-and the compressed IP (Core)-, respectively.

0 21 1 0 21 2 114 114 As a result, similarly to the first embodiment, the compressed IP (Core)-and the compressed IP (Core)-can operate in parallel, and the data compression deviceprovides two compressed IP with a 4-byte/cycle, 2-KiB dictionary size as the first mode, and the overall input throughput of the data compression devicebecomes 8 bytes/cycle.

22 41 0 21 1 41 1 21 2 34 1 21 2 22 41 31 1 21 1 41 31 0 21 1 22 51 In contrast, if the compression level is more than or equal to a predetermined threshold value, the dictionary buffer concatenation controllerconcatenates and controls the shift registerof the compressed IP (Core)-, the shift registerof the compressed IP (Core)-, and the delay bufferof the compressed IP (Core)-to operate as a single dictionary buffer. The dictionary buffer concatenation controllerswitches the input to the shift registerof the dictionary compressorof the compressed IP (Core)-from the uncompressed data input to the oldest dictionary data pushed out of the shift registerof the dictionary compressorof the compressed IP (Core)-. More specifically, the dictionary buffer concatenation controllercontrols the switch.

22 42 1 21 2 1 21 2 0 21 1 22 52 In addition, the dictionary buffer concatenation controllerswitches the input to the byte-wise comparison unitof the dictionary compressor of the compressed IP (Core)-from the uncompressed data that is the input to the compressed IP (Core)-to the uncompressed data that is the input to the compressed IP (Core)-. More specifically, the dictionary buffer concatenation controllercontrols the switch.

22 34 1 21 2 44 1 21 2 41 31 1 21 2 22 54 55 Furthermore, the dictionary buffer concatenation controllerswitches the input to the delay bufferof the compressed IP (Core)-from the output result of the longest match determination unitof the compressed IP (Core)-to the oldest dictionary data pushed out of the shift registerof the dictionary compressorof the compressed IP (Core)-. More specifically, the dictionary buffer concatenation controllercontrols the switchesand.

34 1 21 2 45 34 The write policy for the delay bufferof the compressed IP (Core)-is a ring buffer. The hash-based dictionary search unitexecutes a hash-based dictionary search process on the dictionary data written to the delay buffer.

23 44 0 21 1 44 1 21 2 455 45 34 32 0 21 1 0 21 1 45 1 21 2 The longest match selectorcompares the output of the longest match determination unitof the compressed IP (Core)-, the output of the longest match determination unitof the compressed IP (Core)-, and an output of a match length calculation unitof the hash-based dictionary search unit, and outputs the match with the longest match length to both the delay bufferand the entropy coding unitof the compressed IP (Core)-. In addition, the uncompressed data which is the input to the compressed IP (Core)-is input to the hash-based dictionary search unitof the compressed IP (Core)-.

45 451 1 451 2 452 453 454 455 454 34 1 21 2 451 1 34 34 452 34 45 451 2 452 453 454 34 453 45 455 The hash-based dictionary search unitincludes a hash calculation unit-, a hash calculation unit-, a hash registration unit, a hash search unit, a hash table unit, and a match length calculation unit. The hash table unithas an array with the number of elements=H, and a 14-bit (≈ceil(1024×10)) delay buffer address and D 1-bit flags indicating validity/invalidity of the delay buffer address are stored in each entry in the array. For example, H=512 and D=4. When data is written to the delay bufferof the compressed IP (Core)-, at the dictionary buffer concatenation operation, the hash calculation unit-calculates a hash value based on at least a part of the data written to the delay buffer. The hash value is calculated based on, for example, the first 3 bytes of the data written to the delay buffer. The hash registration unitdetermines index (0 to H−1) of the array in the hash table unit based on the hash value, and writes the delay buffer address of the data written to the delay bufferto the entry corresponding to the determined index. The D delay buffer addresses included in the array entry are updated according to the FIFO policy. When the uncompressed data is input to the hash-based dictionary search unit, the hash calculation unit-calculates a hash value based on at least a part of the uncompressed data input. The method of calculating the hash value is the same as the method of calculating the hash value used for the hash registration unit. The hash search unitdetermines the index (0 to H−1) of the array in the hash table unitbased on the hash value, and reads the entry corresponding to the determined index from the array. At least some of D′ (D′≤D) delay buffer addresses indicated to be valid by the flag among the D delay buffer addresses included in the entry read from the array, are selected, and dictionary data is read from the delay buffer. The selection criterion is, for example, the order of shorter match distance (i.e., the order of delayed timing of being pushed in the FIFO), but is not limited to this. The selection may be executed by additionally storing a part of the hash value in addition to the delay buffer address and the valid/invalid flags, as an array entry, and comparing this value with the hash value input to the hash search unit. The read dictionary data is compared with the uncompressed data input to the hash-based dictionary search unitin the match length calculation unit, and the match length is calculated.

44 0 21 1 44 1 21 2 455 45 23 32 0 21 1 32 1 21 2 The output of the longest match determination unitof the compressed IP (Core)-, the output of the longest match determination unitof the compressed IP (Core)-, and the output of the match length calculation unitof the hash-based dictionary search unitare compared in the longest match selector, and the match with the longest match length is selected and input to the entropy coding unitof the compressed IP (Core)-. The entropy coding unitof the compressed IP (Core)-does not operate.

41 0 21 1 41 1 21 2 34 1 21 2 114 21 114 As a result, the shift registerof the compressed IP (Core)-, the shift registerof the compressed IP (Core)-, and the delay bufferof the compressed IP (Core)-are concatenated to constitute a 14 KiB dictionary, and the result of the match search for the 14 KiB dictionary is obtained. As a result, the data compression deviceprovides one compressed IPwith a 4-byte/cycle and 14-KiB dictionary size, in the second mode, and the overall input throughput of the data compression devicebecomes 4 bytes/cycle. In comparison with the first embodiment, the input throughput is the same, the dictionary size is increased by 10 KiB, and the improvement in compression ratio can be expected.

6 FIG. is a view showing a configuration of a dictionary buffer in a case where dictionary buffer concatenation of the data compression device is formed, in the memory system of the second embodiment.

41 31 0 21 1 41 31 1 21 2 41 31 0 21 1 41 31 1 21 2 34 1 21 2 If the dictionary buffer concatenation is formed, uncompressed data is first input to the shift registerof the dictionary compressorof the compressed IP (Core)-. The uncompressed data is shifted 4 bytes per cycle, and is input to the shift registerof the dictionary compressorof the compressed IP (Core)-when pushed out of the shift registerof the dictionary compressorof the compressed IP (Core)-. Furthermore, when the uncompressed data is pushed out of the shift registerof the dictionary compressorof the compressed IP (Core)-, the uncompressed data is input to the delay bufferof the compressed IP (Core)-.

114 1 41 31 1 21 2 34 1 21 2 As described above, the data compression devicein the memory systemof the second embodiment can increase the dictionary size by diverting the existing resources, i.e., the shift registerof the dictionary compressorof the compressed IP (Core)-and the delay bufferof the compressed IP (Core)-.

Next, a third embodiment will be described.

The third embodiment is also an example of a memory system implemented as an SSD, similarly to the first and second embodiments. The same components as those in the first and second embodiments are denoted by the same reference numerals and their descriptions are omitted.

7 FIG. 114 115 1 is a view showing an example of a configuration of a data compression deviceand a data decompression devicein a memory systemof the third embodiment.

114 115 115 61 115 0 61 1 1 61 2 In the data compression deviceof the third embodiment, the data decompression deviceis applied as an existing resource which is diverted to increase the dictionary size. The data decompression deviceincludes two decompressed IPwith a decompression throughput of 4 Bytes/cycle. More specifically, the data decompression deviceincludes decompressed IP (Core)-and decompressed IP (Core)-.

61 71 72 73 1 61 2 74 45 The decompressed IPincludes an entropy decoding unit, a dictionary decompressor, and a dictionary bufferof 32 KiB-SRAM. In addition, the decompressed IP (Core)-includes a hash-based dictionary search unitsimilar to the hash-based dictionary search unitof the second embodiment.

73 1 61 2 21 In the third embodiment, the dictionary bufferfor dictionary decompression, which is included in the decompressed IP (Core)-is diverted as the dictionary buffer of the compressed IP, thereby increasing the dictionary size at the compression.

22 0 21 1 1 21 2 114 0 61 1 1 61 2 115 41 31 0 21 1 114 41 31 1 21 2 114 0 21 1 1 21 2 0 61 1 1 61 2 115 74 1 61 2 115 If the compression level is less than a predetermined threshold value, the dictionary buffer concatenation controllercontrols such that the compressed IP (Core)-and the compressed IP (Core)-of the data compression device, and the decompressed IP (Core)-and the decompressed IP (Core)-of the data decompression deviceoperate independently of each other. In other words, the shift registerof the dictionary compressorof the compressed IP (Core)-of the data compression deviceis not connected to the shift registerof the dictionary compressorof the compressed IP (Core)-of the data compression device, and separate uncompressed data is input to the compressed IP (Core)-and the compressed IP (Core)-, and separate compressed data is input to decompressed IP (Core)-and decompressed IP (Core)-of data decompression device. In addition, the hash-based dictionary search unitof the decompressed IP (Core)-of the data decompression devicedoes not operate.

0 21 1 1 21 2 114 0 61 1 1 61 2 115 114 21 114 115 61 115 As a result, the compressed IP (Core)-and the compressed IP (Core)-of the data compression devicecan operate in parallel, and the decompressed IP (Core)-and the decompressed IP (Core)-of the data decompression devicecan operate in parallel. The data compression deviceprovides two compressed IPwith a 4-byte/cycle and 2-KiB dictionary size, in the first mode, and the overall input throughput of the data compression devicebecomes 8 bytes/cycle. The data decompression deviceprovides two decompressed IPwith 4 Byte/cycle and a dictionary size of 32 KiB, and an output throughput of the overall data decompression deviceis 8 bytes/cycle.

22 41 0 21 1 114 41 1 21 2 73 1 21 2 115 22 41 31 0 21 1 114 41 31 0 21 1 114 22 51 In contrast, if the compression level is more than or equal to a predetermined threshold value, the dictionary buffer concatenation controllercontrols to concatenate the shift registerof the compressed IP (Core)-of the data compression device, the shift registerof the compressed IP (Core)-, and the dictionary bufferof the decompressed IP (Core)-of the data decompression deviceand to operate as a single dictionary buffer. The dictionary buffer concatenation controllerswitches the input to the shift registerof the dictionary compressorof the compressed IP (Core)-of the data compression devicefrom the uncompressed data input to the oldest dictionary data pushed out of the shift registerof the dictionary compressorof the compressed IP (Core)-of the data compression device. More specifically, the dictionary buffer concatenation controllercontrols the switch.

22 42 31 1 21 2 114 1 21 2 114 0 21 1 114 22 52 In addition, the dictionary buffer concatenation controllerswitches the input to the byte-wise comparison unitof the dictionary compressorof the compressed IP (Core)-of the data compression devicefrom the uncompressed data input that is the input to the compressed IP (Core)-of the data compression deviceto the uncompressed data that is the input to the compressed IP (Core)-of the data compression device. More specifically, the dictionary buffer concatenation controllercontrols the switch.

22 73 1 61 2 72 1 61 2 115 41 31 1 21 2 114 22 56 Furthermore, the dictionary buffer concatenation controllerswitches the input to the delay bufferof the compressed IP (Core)-from the output result of the dictionary decompressorof the decompressed IP (Core)-of the data decompression deviceto the oldest dictionary data pushed out of the shift registerof the dictionary compressorof the compressed IP (Core)-of the data compression device. More specifically, the dictionary buffer concatenation controllercontrols the switch.

71 72 1 61 2 115 At this time, the entropy decoding unitand the dictionary decompressorof the decompressed IP (Core)-of the data decompression devicedo not operate.

73 1 61 2 115 74 73 1 61 2 115 The writing policy for the dictionary bufferof the decompressed IP (Core)-of the data decompression deviceis a ring buffer. The hash-based dictionary search unitexecutes a hash-based dictionary search process for the dictionary data written to the dictionary bufferof the decompressed IP (Core)-of the data decompression device.

23 44 31 0 21 1 114 44 31 1 21 2 114 745 74 1 61 2 115 74 0 21 1 114 0 21 1 74 115 The longest match selectorcompares the output of the longest match determination unitof the dictionary compressorof the compressed IP (Core)-of the data compression device, the output of the longest match determination unitof the dictionary compressorof the compressed IP (Core)-of the data compression device, and the output of the match length calculation unitof the hash-based dictionary search unitof the decompressed IP (Core)-of the data decompression device, and outputs the match with the longest match length to both the hash-based dictionary search unitand the entropy coding unit of the compressed IP (Core)-of the data compression device. In addition, the uncompressed data which is the input to the compressed IP (Core)-is input to the hash-based dictionary search unitof the decompression device.

41 0 21 1 114 41 1 21 2 114 73 1 61 2 115 Accordingly, the shift registerof the compressed IP (Core)-of the data compression device, the shift registerof the compressed IP (Core)-of the data compression device, and the dictionary bufferof the decompressed IP (Core)-of the data decompression deviceare concatenated to constitute a 36 KiB dictionary, and the result of the match search for the 36 KiB dictionary is obtained.

114 21 114 115 114 114 115 As a result, the data compression deviceprovides one compressed IPwith a 4-byte/cycle and 36-KiB dictionary size, in the second mode, and the overall input throughput of the data compression devicebecomes 4 bytes/cycle. In addition, the output throughput of the overall data decompression deviceis 8 bytes/cycle when the dictionary buffer is not concatenated in the data compression device, and 4 bytes/cycle when the dictionary buffer is concatenated. In comparison with the first embodiment, the input throughput of the data compression deviceis the same, the output throughput of the data decompression deviceis halved, the dictionary size is increased by 24 KiB, and the improvement in compression ratio can be expected.

8 FIG. 114 1 is a view showing a configuration of a dictionary buffer in a case where dictionary buffer concatenation of the data compression deviceis formed, in the memory systemof the third embodiment.

41 31 0 21 1 114 41 31 1 21 2 114 41 31 0 21 1 114 73 0 61 2 115 41 31 0 21 2 114 If the dictionary buffer concatenation is formed, the uncompressed data is first input to the shift registerof the dictionary compressorof the compressed IP (Core)-of the data compression device. The uncompressed data is shifted 4 bytes per cycle, and is input to the shift registerof the dictionary compressorof the compressed IP (Core)-of the data compression devicewhen pushed out of the shift registerof the dictionary compressorof the compressed IP (Core)-of the data compression device. Furthermore, the uncompressed data is input to the dictionary bufferof the decompressed IP (Core)-of the data decompression devicewhen pushed out of the shift registerof the dictionary compressorof the compressed IP (Core)-of the data compression device.

114 1 41 31 1 21 2 114 73 1 61 2 115 As described above, the data compression devicein the memory systemof the third embodiment can increase the dictionary size by diverting the existing resources, i.e., the shift registerof the dictionary compressorof the compressed IP (Core)-of the data compression deviceand the dictionary bufferof the decompressed IP (Core)-of the data decompression device.

Next, a fourth embodiment will be described.

The fourth embodiment is also an example of a memory system implemented as an SSD, similarly to the first to third embodiments. The same components as those in the first to third embodiments are denoted by the same reference numerals and their descriptions are omitted.

9 FIG. 114 115 1 is a view showing an example of a configuration of a data compression deviceand a data decompression devicein a memory systemof the fourth embodiment.

9 FIG. 114 0 21 115 0 61 0 61 74 As shown in, in the fourth embodiment, the data compression deviceincludes one compressed IP (Core). In addition, the data decompression devicealso includes one decompressed IP (Core). The decompressed IP (Core)increases a hash-based dictionary search unit.

22 0 21 114 41 0 21 114 73 0 61 115 In the fourth embodiment, the dictionary buffer concatenation controllerof the compressed IP (Core)of the data compression device, in the second mode, concatenates the shift registerof the compressed IP (Core)of the data compression deviceand the dictionary bufferof the decompressed IP (Core)of the data decompression deviceto constitute a 34 KiB dictionary buffer.

10 FIG. 114 1 is a view showing a configuration of a dictionary buffer in a case where dictionary buffer concatenation of the data compression deviceis formed, in the memory systemof the fourth embodiment.

41 31 0 21 114 73 0 61 115 41 31 0 21 114 If the dictionary buffer concatenation is formed, the uncompressed data is first input to the shift registerof the dictionary compressorof the compressed IP (Core)of the data compression device. The uncompressed data is shifted 4 bytes per cycle, and is input to the dictionary bufferof the decompressed IP (Core)of the data decompression devicewhen pushed out of the shift registerof the dictionary compressorof the compressed IP (Core)of the data compression device.

114 0 21 115 0 61 114 1 73 0 61 115 As described above, even in the configuration that the data compression deviceincludes only one compressed IP (Core)and the data decompression deviceincludes only one decompressed IP (Core), the data compression devicein the memory systemof the fourth embodiment can increase the dictionary size by diverting the existing resource of the dictionary bufferof the decompressed IP (Core)of data decompression device.

Next, a fifth embodiment will be described.

The fifth embodiment is also an example of a memory system implemented as an SSD, similarly to the first to fourth embodiments. The same components as those in the first to fourth embodiments are denoted by the same reference numerals and their descriptions are omitted.

11 FIG. 114 1 is a view showing an example of a configuration of the data compression devicein the memory systemof the fifth embodiment.

11 FIG. 114 0 1 2 21 1 3 32 21 34 22 114 41 0 21 1 41 1 21 2 41 2 21 3 34 1 21 2 34 2 21 3 As shown in, in the fifth embodiment, the data compression deviceincludes three compressed IP (Core, Core, and Core)(-to). The entropy coding unitof each compressed IPis a dynamic Huffman code, similarly to the second embodiment, and uses a delay bufferconfigured with 10 KiB-SRAM. In the fifth embodiment, the dictionary buffer concatenation controllerof the data compression device, in the second mode, concatenates the shift registerof the compressed IP (Core)-, the shift registerof the compressed IP (Core)-, the shift registerof the compressed IP (Core)-, the delay bufferof the compressed IP (Core)-, and the delay bufferof the compressed IP (Core)-to constitute a 26 KiB dictionary buffer.

22 41 31 1 21 2 41 31 0 21 1 22 51 1 21 2 When the compression level is more than or equal to a predetermined threshold value, Furthermore, the dictionary buffer concatenation controllerswitches the input to the shift registerof the dictionary compressorof the compressed IP (Core)-from the uncompressed data input to the oldest dictionary data pushed out of the shift registerof the dictionary compressorof the compressed IP (Core)-. More specifically, the dictionary buffer concatenation controllercontrols the switchof the compressed IP (Core)-.

22 42 31 1 21 2 1 21 2 0 21 1 22 52 1 21 2 In addition, the dictionary buffer concatenation controllerswitches the input to the byte-wise comparison unitof the dictionary compressorof the compressed IP (Core)-from the uncompressed data that is the input to the compressed IP (Core)-to the uncompressed data input that is the input to the compressed IP (Core)-. More specifically, the dictionary buffer concatenation controllercontrols the switchof the compressed IP (Core)-.

22 41 31 2 21 3 41 31 1 21 2 22 51 2 21 3 Furthermore, the dictionary buffer concatenation controllerswitches the input to the shift registerof the dictionary compressorof the compressed IP (Core)-from the uncompressed data input to the oldest dictionary data pushed out of the shift registerof the dictionary compressorof the compressed IP (Core)-. More specifically, the dictionary buffer concatenation controllercontrols the switchof the compressed IP (Core)-.

22 42 31 2 21 3 2 21 3 0 21 1 22 52 2 21 3 In addition, the dictionary buffer concatenation controllerswitches the input to the byte-wise comparison unitof the dictionary compressorof the compressed IP (Core)-from the uncompressed data input that is the input to the compressed IP (Core)-to the uncompressed data input that is the input to the compressed IP (Core)-. More specifically, the dictionary buffer concatenation controllercontrols the switchof the compressed IP (Core)-.

22 34 1 21 2 44 1 21 2 41 31 2 21 3 22 54 55 1 21 2 Furthermore, the dictionary buffer concatenation controllerswitches the input to the delay bufferof the compressed IP (Core)-from the output of the longest match determination unitof the compressed IP (Core)-to the oldest dictionary data pushed out of the shift registerof the dictionary compressorof the compressed IP (Core)-. More specifically, the dictionary buffer concatenation controllercontrols the switchesandof the compressed IP (Core)-.

22 34 2 21 3 44 2 21 3 34 1 21 2 Furthermore, the dictionary buffer concatenation controllerswitches the input to the delay bufferof the compressed IP (Core)-from the output of the longest match determination unitof the compressed IP (Core)-to the oldest dictionary data that is overwritten in the delay bufferof the compressed IP (Core)-.

23 44 0 21 1 44 1 21 2 44 2 21 3 455 45 1 21 2 455 45 2 21 3 34 0 21 1 32 0 21 1 0 21 1 45 1 21 2 45 2 21 3 The longest match selectorcompares the output of the longest match determination unitof the compressed IP (Core)-, the output of the longest match determination unitof the compressed IP (Core)-, the output of the longest match determination unitof the compressed IP (Core)-, and the output of the match length calculation unitof the hash-based dictionary search unitof the compressed IP (Core)-, and the output of the match length calculation unitof the hash-based dictionary search unitof the compressed IP (Core)-, and outputs the match with the longest match length to both the delay bufferof the compressed IP (Core)-and the entropy coding unitof the compressed IP (Core)-. In addition, the uncompressed data which is the input to the compressed IP (Core)-is input to the hash-based dictionary search unitof the compressed IP (Core)-and the hash-based dictionary search unitof the compressed IP (Core)-.

41 0 21 1 41 1 21 2 41 2 21 3 34 1 21 2 34 1 21 2 Accordingly, the shift registersof the compressed IP (Core)-, the shift registersof the compressed IP (Core)-, the shift registersof the compressed IP (Core)-, the delay buffersof the compressed IP (Core)-, and the delay bufferof the compressed IP (Core)-are concatenated to constitute a 26 KiB dictionary, and the result of the match search for the 26 KiB dictionary is obtained.

21 114 114 As a result, the data compression device provides one compressed IPwith 4-byte/cycle and a dictionary size of 26 KiB, in the second mode, and the overall input throughput of the data compression deviceis 4 bytes/cycle. In comparison with the first embodiment, the input throughput of the entire data compression deviceis the same, the dictionary size is increased by 24 KiB, and the improvement in compression ratio can be expected.

12 FIG. 114 1 is a view showing a configuration of a dictionary buffer in a case where dictionary buffer concatenation of the data compression deviceis formed, in the memory systemof the fifth embodiment.

41 31 0 21 1 41 31 1 21 2 41 31 0 21 1 41 31 1 21 2 41 31 2 21 3 If the dictionary buffer concatenation is formed, uncompressed data is first input to the shift registerof the dictionary compressorof the compressed IP (Core)-. The uncompressed data is shifted 4 bytes per cycle, and is input to the shift registerof the dictionary compressorof the compressed IP (Core)-when pushed out of the shift registerof the dictionary compressorof the compressed IP (Core)-. Similarly, when the uncompressed data is pushed out of the shift registerof the dictionary compressorof the compressed IP (Core)-, the uncompressed data is input to the shift registerof the dictionary compressorof the compressed IP (Core)-.

41 31 2 21 3 34 1 21 2 34 1 21 1 34 2 21 3 In addition, when the uncompressed data is pushed out of the shift registerof the dictionary compressorof the compressed IP (Core)-, the uncompressed data is input to the delay bufferof the compressed IP (Core)-. Furthermore, when the uncompressed data is pushed out of the delay bufferof the compressed IP (Core)-, the uncompressed data is input to the delay bufferof the compressed IP (Core)-.

114 1 41 31 1 21 2 41 31 2 21 3 34 1 21 2 34 2 21 3 As described above, the data compression devicein the memory systemof the fifth embodiment can further increase the dictionary size by diverting the existing resources, i.e., the shift registerof the dictionary compressorof the compressed IP (Core)-, the shift registerof the dictionary compressorof the compressed IP (Core)-, the delay bufferof the compressed IP (Core)-, and the delay bufferof the compressed IP (Core)-.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel devices and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modification as would fall within the scope and spirit of the inventions.