Semiconductor Device and Method for Manufacturing the Same

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2024-161093, filed on Sep., 18, 2024, the entire contents of which are incorporated herein by reference.

Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the semiconductor device.

As one of MOSFETs, a MOSFET including a field plate electrode (also abbreviated as FPMOSFET or FPMOS) is known. Among the FPMOSs, there is known an FP trench MOS in which a gate electrode and a field plate electrode are disposed in an insulating region embedded in a trench of a semiconductor layer.

In the FP trench MOS, the gate electrode and the field plate electrode are separated from each other by an insulating region. Since the insulating region has a large dielectric constant, a capacitance between the gate electrode and the field plate electrode is large. Due to this, performance of a device may be affected, such as an increase in switching loss.

A semiconductor device according to an embodiment includes a first electrode, a second electrode facing the first electrode in a first direction, and a semiconductor layer disposed between the first electrode and the second electrode. The semiconductor layer includes a first conductivity type first semiconductor region electrically connected to the second electrode, and a second conductivity type second semiconductor region disposed on the first semiconductor region. The semiconductor device further includes: an insulating region disposed in the semiconductor layer and having a cavity extending from an upper end in the first direction; a first control electrode disposed in the insulating region so as to face the second semiconductor region in a second direction orthogonal to the first direction; a second control electrode disposed in the insulating region so as to face the first control electrode in the second direction with the cavity interposed between the first control electrode and the second control electrode; and a conductive portion electrically connected to the first electrode, disposed in the insulating region, and having an upper surface at least partially exposed to a bottom of the cavity.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The embodiment does not limit the present invention. The drawings are schematic or conceptual, and a ratio between portions and the like are not necessarily the same as actual ones. In the specification and the drawings, elements similar to those previously described are denoted by the same reference numerals, and detailed description thereof is appropriately omitted.

+ − + − + − + − + − + − In the following description, notations of n, n, n, p, p, and pmay be used to represent a relative level of an impurity concentration in a semiconductor region. nindicates that an n-type impurity concentration is relatively higher than n, and nindicates that the n-type impurity concentration is relatively lower than n. pindicates that a p-type impurity concentration is relatively higher than p, and pindicates that the p-type impurity concentration is relatively lower than p. When both a p-type impurity and an n-type impurity are contained in each region, each of these notations represents a relative level of a net impurity concentration after these impurities are compensated for each other. The n-type, n-type, and n-type are examples of the first conductivity type in the claims. The p-type, p-type, and p-type are examples of the second conductivity type in the claims. Note that, in the following description, the n-type and the p-type may be inverted. That is, the first conductivity type may be p-type, and the second conductivity type may be n-type.

Note that an impurity concentration can be measured by, for example, secondary ion mass spectrometry (SIMS). A relative level of the impurity concentration can also be determined from a level of a carrier concentration obtained by, for example, scanning capacitance microscopy (SCM).

31 − − In the description of the embodiment, an XYZ orthogonal coordinate system is used. A direction directed from a drain electrode toward an n-type semiconductor region is defined as a Z direction. Two directions perpendicular to the Z direction and orthogonal to each other are defined as an X direction and a Y direction. For description, a direction directed from the drain electrode toward the n-type semiconductor region is referred to as “upper”, and a direction opposite to “upper” is referred to as “lower”. These directions are based on a relative positional relationship between the drain electrode and the n-type semiconductor region, and are independent of the direction of gravity.

1 1 1 1 2 FIGS.and 1 FIG. 2 FIG. 1 FIG. A semiconductor deviceaccording to a first embodiment will be described with reference to.is a cross-sectional view of the semiconductor device, andis an enlarged view of a region A in. The semiconductor deviceis an FP trench MOS in which a gate electrode and a field plate electrode are disposed in an insulating region formed in a trench of a semiconductor layer.

1 2 3 4 5 6 6 7 8 The semiconductor deviceincludes a source electrode, a drain electrode, a semiconductor layer, an insulating region, a pair of gate electrodesA andB, a field plate electrode, and an interlayer insulating film.

2 3 6 6 7 The source electrodeis an example of the first electrode in the claims, the drain electrodeis an example of the second electrode in the claims. The gate electrodeA is an example of the first control electrode in the claims, and the gate electrodeB is an example of the second control electrode in the claims. The field plate electrodeis an example of the conductive portion in the claims.

1 Hereinafter, each component of the semiconductor devicewill be described.

2 2 43 44 4 2 7 2 The source electrodefunctions as a source electrode of the MOSFET. As described later, the source electrodeis electrically connected to a source regionand a high concentration regionof the semiconductor layerdescribed later. In addition, the source electrodeis electrically connected to the field plate electrode. The source electrodeis made of, for example, copper (Cu), titanium (Ti), tungsten (W), or aluminum (Al).

3 3 2 3 41 4 3 a The drain electrodefunctions as a drain electrode of the MOSFET. The drain electrodefaces the source electrodein the Z-axis direction. The drain electrodeis electrically connected to a drain regionof the semiconductor layer. The drain electrodeis made of, for example, copper (Cu), titanium (Ti), titanium nitride (TiN), tungsten (W), or aluminum (Al).

4 41 41 42 43 44 4 2 3 4 4 a The semiconductor layerincludes a drift region, the drain region, a base region, the source region, and the high concentration region. The semiconductor layeris disposed between the source electrodeand the drain electrode. In the present embodiment, the semiconductor layeris made of silicon. Note that the semiconductor layermay be constituted by a semiconductor other than silicon.

41 41 42 43 41 41 41 41 a a a The drift regionand the drain regionare examples of the first semiconductor region in the claims. The base regionis an example of the second semiconductor region in the claims, and the source regionis an example of the third semiconductor region in the claims. Note that the first semiconductor region in the claims may include both the drift regionand the drain region, or may include only one of the drift regionand the drain region.

41 41 41 41 41 a − 15 −3 16 −3 The drift regionfunctions as a drift region of the MOSFET. The drift regionis disposed on the drain region. In the present embodiment, the drift regionis an n-type semiconductor region. The drift regionhas an n-type impurity concentration of, for example, 1×10cmor more and 2×10cmor less.

41 41 41 3 3 3 41 41 a a a a + 18 −3 21 −3 The drain regionfunctions as a drain region of the MOSFET. The drain regionis disposed between the drift regionand the drain electrode, and is electrically connected to the drain electrodeby being in ohmic contact or the like with the drain electrode. In the present embodiment, the drain regionis an n-type semiconductor region. The drain regionhas an n-type impurity concentration of, for example, 1×10cmor more and 1×10cmor less.

41 41 2 3 3 3 a As described above, the n-type semiconductor region including the drift regionand the drain regionis disposed between the source electrodeand the drain electrode, and is electrically connected to the drain electrodeby being in ohmic contact or the like with the drain electrode.

42 42 41 4 5 42 42 16 −3 20 −3 The base regionfunctions as a base region of the MOSFET. The base regionis disposed on the drift regionand is disposed in the semiconductor layerso as to be sandwiched between the insulating regions. In the present embodiment, the base regionis a p-type semiconductor region. The base regionhas a p-type impurity concentration of, for example, 1×10cmor more and 1×10cmor less.

43 43 42 2 42 43 2 2 43 43 + 18 −3 22 −3 The source regionfunctions as a source region of the MOSFET. The source regionis located between the base regionand the source electrodeas viewed in the Z-axis direction, and is disposed on the base region. The source regionis electrically connected to the source electrodeby being in ohmic contact or the like with the source electrode. In the present embodiment, the source regionis an n-type semiconductor region. The source regionhas an n-type impurity concentration of, for example, 1×10cmor more and 1×10cmor less.

44 42 2 44 2 44 42 44 44 42 44 2 + 18 −3 22 −3 The high concentration regionis disposed on the base regionand is electrically connected to the source electrode. In order to reduce recovery loss, the high concentration regionis disposed in a portion adjacent to a bottom portion of a contact plug of the source electrode. In the present embodiment, the high concentration regionis a p-type semiconductor region having an impurity concentration higher than that of the base region. The high concentration regionhas a p-type impurity concentration of, for example, 1×10cmor more and 1×10cmor less. With the high concentration region, minority carriers accumulated in the base regionare injected into the high concentration region, pass through the contact plug, and are discharged to the source electrode.

5 4 5 6 6 2 7 5 5 The insulating regionis disposed in the semiconductor layer. The insulating regionis an insulating film that electrically insulates the gate electrodesA andB from the source electrodeand the field plate electrode. In the present embodiment, the insulating regionis a silicon oxide film. Note that the insulating regionmay be made of another material such as a silicon nitride film.

1 2 FIGS.and 5 3 2 3 4 6 6 7 6 6 7 As illustrated in, the insulating regionhas a cavity C extending from an upper end toward the drain electrodein the Z-axis direction. The cavity C has a tapered portion Ctp whose length (that is, width) in the X-axis direction increases as it goes from the source electrodetoward the drain electrode(that is, from an upper surface to a lower surface of the semiconductor layer). The tapered portion Ctp causes an air gap to exist between the gate electrodesA andB and the field plate electrode. As a result, a capacitance Cgs between the gate electrodesA andB and the field plate electrodecan be reduced.

1 2 FIGS.and 8 Note that, as illustrated in, an opening in an upper portion of the cavity C is closed with an insulating material constituting the interlayer insulating film.

6 5 42 6 The gate electrodeA is disposed in the insulating regionso as to face the base regionin the X-axis direction. The gate electrodeA extends in the Y-axis direction.

6 5 6 6 6 6 The gate electrodeB is disposed in the insulating regionso as to face the gate electrodeA in the X-axis direction with the cavity C interposed between the gate electrodeA and the gate electrodeB. The gate electrodeB extends in the Y-axis direction.

6 6 6 6 The gate electrodeA and the gate electrodeB are electrically connected to each other. In the present embodiment, the gate electrodeA and the gate electrodeB are made of conductive polysilicon or the like containing a p-type or n-type impurity.

7 5 6 6 7 6 7 6 7 2 7 The field plate electrodeis disposed in the insulating regionso as to be located below the gate electrodeA and the gate electrodeB. Note that the field plate electrodeis not disposed immediately below the gate electrodeA and the field plate electrodeis not disposed immediately below the gate electrodeB. The field plate electrodeis electrically connected to the source electrode. The field plate electrodeextends in the Y-axis direction.

7 18 −3 22 −3 The field plate electrodeis made of conductive polysilicon doped with a p-type or n-type impurity. In the present embodiment, the impurity is phosphorus (P). An impurity concentration is, for example, 1×10cmor more and 1×10cmor less. Note that the impurity may be an element larger than silicon, such as arsenic (As) or antimony (Sb).

2 FIG. 7 6 6 7 As illustrated in, an upper surface of the field plate electrodeis exposed to a bottom of the cavity C. This causes an air gap to exist between the gate electrodesA andB and the field plate electrode.

8 5 43 8 8 8 6 6 2 8 The interlayer insulating filmcovers the insulating regionand a part of the source region. In the present embodiment, the interlayer insulating filmis made of borophosphosilicate glass (BPSG). Note that the interlayer insulating filmmay be constituted by another insulating film such as a silicon oxide film, a silicon nitride film, a high dielectric constant film (High-k film), or a low dielectric constant film (Low-k film). The interlayer insulating filmcan sufficiently ensure insulation between the gate electrodesA andB and the source electrode. Note that the interlayer insulating filmmay be omitted.

1 5 6 6 5 7 5 6 6 7 1 6 7 6 7 As described above, in the semiconductor deviceaccording to the first embodiment, the cavity C extending from an upper end thereof in the Z-axis direction is formed in the insulating region, the gate electrodesA andB are disposed in the insulating regionso as to sandwich the cavity C therebetween, and the field plate electrodeis disposed in the insulating regionsuch that at least a part of an upper surface thereof is exposed to a bottom of the cavity C. This causes an air gap of the cavity C to exist between the gate electrodesA andB and the field plate electrode, and therefore the capacitance Cgs can be reduced. In the semiconductor device, since a cavity of the tapered portion Ctp is formed between the gate electrodeA and the field plate electrodeand between the gate electrodeB and the field plate electrode, the capacitance Cgs can be effectively reduced.

2 FIG. 7 7 7 2 7 6 6 7 7 3 7 Note that, as illustrated in, an upper end of the field plate electrodemay be located near a lower end of the tapered portion Ctp. As a result, the capacitance Cgs can be sufficiently reduced while an effect of improving withstand voltage by the field plate electrodeis maintained. That is, when the upper end of the field plate electrodeis located above the tapered portion Ctp (on the source electrodeside) (when the field plate electrodefills the tapered portion Ctp), there is no air gap between the gate electrodesA andB and the field plate electrode, and therefore there is a risk that the capacitance Cgs cannot be sufficiently reduced. On the other hand, when the upper end of the field plate electrodeis located below the tapered portion Ctp (on the drain electrodeside), an original function of the field plate electrode(improvement in withstand voltage) may be weakened.

8 7 An insulating material of the interlayer insulating filmmay reach the inside of the tapered portion Ctp from an upper opening of the cavity C. Furthermore, the insulating material may reach the field plate electrode. Even in these cases, since an air gap remains in the tapered portion Ctp, the capacitance Cgs can be reduced.

1 3 3 FIGS.A toI An example of a method for manufacturing the semiconductor devicewill be described with reference to process cross-sectional views of.

41 5 5 First, a semiconductor layer (silicon wafer or the like) having the n-type semiconductor regionA is prepared, and a trench is formed on an upper surface of the semiconductor layer. Thereafter, an insulating film (a silicon oxide film in this case) is formed on the upper surface of the semiconductor layer and an inner wall of the trench by performing thermal oxidation to form an insulating regionA filling the trench. Thereafter, a groove is formed in the insulating regionA by performing chemical dry etching (CDE).

3 FIG.A 7 Next, as illustrated in, polysilicon is deposited in the above groove by chemical vapor deposition (CVD) or the like. Polysilicon contains an impurity such as phosphorus or arsenic. Thereafter, excessive polysilicon is etched back by performing CDE to form a conductive portionA.

3 FIG.B 5 7 Next, as illustrated in, a part of the insulating regionA is selectively removed by performing wet etching to expose an upper portion of the conductive portionA.

3 FIG.C 45 7 Next, as illustrated in, an insulating filmis formed on the upper surface of the semiconductor layer, the inner wall of the trench, and the exposed conductive portionA by performing thermal oxidation. Specifically, a first insulating film is formed on one inner wall (left inner wall) of the trench, a second insulating film is formed on the other inner wall (right inner wall) of the trench, and a third insulating film is formed on the exposed conductive portion.

7 7 41 7 7 5 7 5 5 7 7 3 FIG.C Since the conductive portionA contains an impurity such as phosphorus, the conductive portionA is more easily oxidized (amplified oxidation) than the semiconductor regionA. Therefore, the third insulating film formed on the conductive portionA is thicker than the first and second insulating films formed on the inner walls of the trench. In addition, even in an unexposed portion of the conductive portionA, a portion relatively shallow from an upper surface of the insulating regionA is thermally oxidized. In the conductive portionA in the insulating regionA, a portion close to the upper surface of the insulating regionA is thermally oxidized to form a thick oxide film. As a result, as illustrated in, a tapered regionAtp is automatically formed in the conductive portionA.

3 FIG.D 45 45 7 6 6 7 Next, as illustrated in, polysilicon is deposited by performing CVD in the groove between the insulating filmformed on the inner wall of the trench and the insulating filmformed on the conductive portionA. Note that a material deposited in the groove is not limited to polysilicon as long as the material has conductivity. Thereafter, a gate conductive portionAA and a gate conductive portionBA sandwiching the conductive portionA therebetween are formed by etching back excessive polysilicon. As described above, in this step, the conductive material is deposited in the groove between the first insulating film and the third insulating film to form a first gate conductive portion, and the conductive material is deposited in the groove between the second insulating film and the third insulating film to form a second gate conductive portion.

3 FIG.E 6 6 45 6 6 6 6 6 6 7 45 Next, as illustrated in, upper portions of the gate conductive portionsAA andBA are oxidized by performing thermal oxidation (buffer oxidation) to be integrated with the insulating film. Portions of the gate conductive portionsAA andBA that have not been oxidized serve as the gate electrodesA andB. The gate electrodesA andB are formed so as to sandwich the conductive portionA therebetween. Thereafter, etching is performed to thin the insulating filmon an upper surface of the semiconductor layer.

3 FIG.F 41 42 42 43 42 41 42 43 41 Next, as illustrated in, ions of a p-type impurity are implanted to the semiconductor regionA to form the base region. Thereafter, ions of an n-type impurity are implanted to the base regionto form the source regionin an upper portion of the base region. A portion of the semiconductor regionA where the base regionor the source regionhas not been formed serves as the drift region.

3 FIG.G 7 45 45 7 7 Next, as illustrated in, a resist film R having an opening at a position corresponding to the conductive portionA is formed on the insulating film. The opening of the resist film R is formed by photolithography. Thereafter, the insulating filmimmediately above the conductive portionA is removed by performing reactive ion etching (RIE) using the resist film R as a mask to form a hole H in which the conductive portionA is exposed to a bottom surface thereof.

3 FIG.H 7 7 6 6 7 7 7 7 7 Next, as illustrated in, the conductive portionA exposed to the hole H is selectively removed by performing etching such as CDE. Specifically, the conductive portionA is removed until an upper surface thereof is located below the gate electrodesA andB. As a result, the field plate electrodeis formed, and the cavity C is formed. The tapered regionAtp is removed to form the tapered portion Ctp. A portion of the conductive portionA remaining without being removed in this step serves as the field plate electrode. Note that, by grasping an etching rate in advance, the upper surface of the field plate electrodemay be caused to be located near a lower end of the tapered portion Ctp.

3 FIG.I 8 45 8 Next, as illustrated in, the resist film R is removed, and then the interlayer insulating filmis formed on the insulating filmby performing CVD. Note that, in this step, there is a possibility that the interlayer insulating film(a silicon oxide film in this case) enters the cavity C. However, since the tapered portion Ctp is not filled with an insulating material, an air gap remains at least in the tapered portion Ctp.

8 43 42 44 8 2 3 Thereafter, although not illustrated, a contact hole penetrating the interlayer insulating filmand the source regionand reaching the base regionis formed, and ions of a p-type impurity are implanted to the contact hole to form the high concentration region. Thereafter, a metal material is deposited so as to fill the contact hole and embed the interlayer insulating filmby performing CVD to form the source electrode. Thereafter, a metal material is deposited on a lower surface of the semiconductor layer to form the drain electrode.

1 1 7 7 4 FIG. s A semiconductor deviceA according to a second embodiment will be described with reference to. In the semiconductor deviceA, an insulating filmwhich is an etching stopper film is disposed on an upper surface of a field plate electrode. Hereinafter, the second embodiment will be described focusing on a difference from the first embodiment.

1 2 3 4 5 6 6 7 8 The semiconductor deviceA of the present embodiment includes a source electrode, a drain electrode, a semiconductor layer, an insulating region, a pair of gate electrodesA andB, a field plate electrode, and an interlayer insulating film.

7 7 7 7 s s s An upper surface of the field plate electrodeis covered with the insulating film. In the present embodiment, the insulating filmis a silicon oxide film. Note that a material of the insulating filmis not limited to silicon oxide, and may be any material as long as it functions as an etching stopper.

5 1 3 6 6 7 6 6 7 As in the first embodiment, the insulating regionof the semiconductor deviceA has a cavity C extending from an upper end toward the drain electrodein the Z-axis direction and having a tapered portion Ctp. As a result, according to the present embodiment, the same effects as those of the first embodiment can be obtained. That is, since an air gap exists between the gate electrodesA andB and the field plate electrode, a capacitance Cgs between the gate electrodesA andB and the field plate electrodecan be reduced.

1 5 5 FIGS.A toF An example of a method for manufacturing the semiconductor deviceA will be described with reference to process cross-sectional views of.

41 5 5 First, a semiconductor layer (silicon wafer or the like) having an n-type semiconductor regionA is prepared, and a trench is formed on an upper surface of the semiconductor layer. Thereafter, an insulating regionA (a silicon oxide film in this case) is formed on the upper surface of the semiconductor layer and an inner wall of the trench by performing thermal oxidation. Thereafter, a groove is formed in the insulating regionA filling the trench by performing CDE.

5 FIG.A 7 6 6 7 7 1 Next, as illustrated in, polysilicon is deposited in the above groove by performing CVD. Polysilicon contains an impurity such as phosphorus or arsenic. Thereafter, excessive polysilicon is etched back by performing CDE to form a conductive portionA. At this time, polysilicon in the groove is removed more (deeper) than in the case described in the first embodiment. Specifically, polysilicon is removed up to a region below a region where the gate electrodesA andB are to be formed. The conductive portionA serves as the field plate electrodeof the semiconductor deviceA.

5 FIG.B 7 7 7 s s Next, as illustrated in, the insulating film(etching stopper film) is formed on an upper surface of the conductive portionA by performing thermal oxidation. Here, the insulating filmis made of silicon oxide.

7 7 7 s 5 FIG.C Next, polysilicon is deposited on the insulating filmby performing CVD. Polysilicon contains an impurity such as phosphorus or arsenic. Thereafter, as illustrated in, excessive polysilicon is etched back by performing CDE to form a conductive portionB. The conductive portionB is an example of the second conductive portion in the claims.

5 FIG.D 3 3 FIGS.C toG 5 7 5 7 s Next, as illustrated in, a part of the insulating regionA is selectively removed by performing wet etching to expose the conductive portionB. Note that, at this time, an upper surface of the insulating regionA is caused to be located above the insulating film. Thereafter, the steps described with reference toin the first embodiment are performed.

5 FIG.E 7 7 7 s Next, as illustrated in, the conductive portionB exposed to the hole H is selectively removed by performing etching such as CDE. At this time, since the insulating filmfunctions as an etching stopper, the conductive portionA is not removed. Through this step, the cavity C having the tapered portion Ctp is formed.

5 FIG.F 8 45 44 2 3 Next, as illustrated in, the resist film R is removed, and then the interlayer insulating filmis formed on the insulating filmby performing CVD. Thereafter, as in the case of the first embodiment, a contact hole is formed to form the high concentration region. Thereafter, the source electrodeand the drain electrodeare formed.

1 7 7 7 7 7 1 7 s 4 FIG. Through the above steps, the semiconductor deviceA according to the second embodiment is manufactured. According to the present embodiment, by covering the upper surface of the conductive portionA with the insulating film, it is possible to prevent the conductive portionA from being removed in the etching step of forming the cavity C. As a result, the height of the upper surface of the field plate electrodecan be easily controlled. As a result, for example, as illustrated in, the upper end of the field plate electrodeis easily caused to be located near a lower end of the tapered portion Ctp. As a result, it is possible to provide the semiconductor deviceA capable of sufficiently reducing the capacitance Cgs while maintaining an effect of improving withstand voltage by the field plate electrode.

According to at least one embodiment described above, the capacitance between the gate electrode and the field plate electrode can be reduced.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.