Gunn Diode with Layered Structure

A Gunn diode, also referred to as a transferred electron device (TED), is a two-terminal device that is characterized by a current-voltage (I-V) curve with a region of negative differential resistance, or more generally, negative impedance. The Gunn diode is based on the Gunn effect, which produces oscillations along the negative differential resistance region. As the electric field applied to the diode increases, the current though the diode initially increases and then decreases in a cyclical manner, leading to periodic fluctuations in current. The current fluctuations produce high-frequency oscillations, typically in the microwave frequencies, e.g., between 300 megahertz (MHz) and 300 gigahertz (GHz).

The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.

A diode is a two-terminal device that conducts current in one direction, referred to as the forward direction, while generally blocking current in the opposite direction, referred to as the reverse direction. In the forward direction, current enters through one terminal, which is called the anode, and leaves through the other terminal, which is called the cathode. When at least a minimum voltage, referred to as a forward voltage, is applied to the anode, this turns on the diode and current flows across the diode in the forward direction, from the anode to the cathode. Different types of materials may be used to form a diode. Many semiconductor diodes include a p-n junction, which is an interface between two types of semiconductor materials, p-type and n-type. Semiconductor diodes may include silicon, germanium, or other types of semiconductor materials.

Gunn diodes do not include a p-n junction. Instead, Gunn diodes include a stack of n-doped material, with two highly doped regions (referred to as doped regions or n+ regions) near the terminals, and a lightly doped region (referred to as an n region, active region, or buffer region) between the highly doped region. In conductor and semiconductor materials, a charge carrier is a particle or quasiparticle that can move within the material, carrying a conductive charge and resulting in a net motion of particles through the material. In some semiconductors, the main charge carriers are electrons, while in others, the main charge carriers are electron holes (i.e., electron vacancies), generally referred to as holes. A semiconductor material or semiconductor region with holes as the primary charge carrier is referred to as p-type, and a semiconductor material or semiconductor region with electrons as the primary charge carrier is referred to as n-type. The oscillation effect of a Gunn diode is exhibited in stacks of n-type materials with electron charge carriers.

When a voltage is applied across the lightly n-doped active region, an electric field develops across the active region. Initially, current across the device increases, but after reaching the threshold voltage, the Gunn diode operates in a negative differential resistance region in which the current decreases. After a current pulse exits the device, another pulse is generated by again increasing the voltage. The series of current pulses produces a sustained oscillation at an oscillation frequency, where the frequency may be based on device characteristics, such as thickness of the active region and operating temperature.

In a Gunn diode, one of the n+ regions is generally larger than the other, with the current traveling through the larger n+ region, through the n region, and then though the smaller n+ region. The larger n+ region provides good ohmic contact and low contact resistance with the anode, which ensures efficient carrier injection and provides proper electric field distribution through the device.

Gunn diodes have been used as oscillators for various applications, such as radio frequency (RF) communications, microwave transmitters, military radar, and various sensors. For RF devices, the active region and n+ regions each have a thickness of around a micron. As disclosed herein, semiconductor processing techniques can be used to produce Gunn diodes at much smaller scales and that operate at lower voltages. The Gunn diodes disclosed herein be used in integrated circuit (IC) products, for example, to provide an on-die processor clock, or to provide one or more on-die synchronization clocks to enable frequency matching for multi-die systems.

In some embodiments disclosed herein, Gunn diodes are formed using a set of layered semiconductor materials, which may be deposited over a substrate. One or more upper layers may be n-doped, and contacts may be formed over the uppermost semiconductor layer. The layered semiconductor materials may include alternating layers of indium, gallium, and arsenic (e.g., indium gallium arsenide, or InGaAs) and indium, aluminum, and arsenic (e.g., indium aluminum arsenide, or InAlAs). In particular, an uppermost layer of the stack may include two regions of highly-doped InGaAs, where each region forms one of the n+ regions of a Gunn diode. A layer of InAlAs is directly below the two regions of highly-doped InGaAs; this layer forms the active region of the Gunn diode. The InAlAs layer is n-doped at a lower dopant concentration than the two InGaAs regions. The two InGaAs regions may have different sizes and/or dopant concentrations, e.g., with a larger region having a lower dopant concentration at the anode side, and a smaller region having a higher dopant concentration at the cathode side.

Further alternating layers of InGaAs and InAlAs may be below the active layer; these layers may form templating layers for depositing the active layers and highly-doped regions with low rates of defects in the lattice structures. InGaAs and AlGaAs are both III-V semiconductor materials with similar lattice structures. In general, III-V semiconductors materials have high carrier mobilities and high bandgaps. The layers of III-V materials may be deposited over a substrate, which may also be a III-V material, such as InGaAs, InAlAs, gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP).

In some embodiments, a gate is included between the two contacts and over the active layer. The gate electrode and/or a layer of gate dielectric may be between the two highly-doped InGaAs regions. The gate may apply a bias voltage to the active region of the Gunn diode. For example, the gate may bias the Gunn diode in the negative differential resistance region of its I-V curve.

The Gunn diodes described herein may advantageously be used in low-temperature environments, such as cooled IC devices. In general, when semiconductor devices operate at lower temperatures, they have improved performance. For example, lower temperatures can lead to increased drive currents across transistors, and transistors operating at lower temperatures generally experience lower leakage. In Gunn diodes, a lower temperature leads to a steeper and longer negative differential range, which can improve performance and stability of the Gunn diodes described herein.

The Gunn diodes described herein may be implemented in combination with one or more components associated with an IC. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on an IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.

For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details and/or that the present disclosure may be practiced with only some of the described aspects. In other instances, well known features are omitted or simplified in order not to obscure the illustrative implementations.

In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. The meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”

The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−20% of a target value, unless specified otherwise. Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

In the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, as used herein, a “logic state” of a ferroelectric memory cell refers to one of a finite number of states that the cell can have, e.g., logic states “1” and “0,” each state represented by a different polarization of the ferroelectric material of the cell. In another example, as used herein, a “READ” and “WRITE” memory access or operations refer to, respectively, determining/sensing a logic state of a memory cell and programming/setting a logic state of a memory cell. In other examples, the term “connected” means a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” means either a direct electrical or magnetic connection between the things that are connected or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. In yet another example, a “high-k dielectric” refers to a material having a higher dielectric constant (k) than silicon oxide. The terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc.

2 2 FIGS.A-B 2 FIG. For convenience, if a collection of drawings designated with different letters are present, e.g.,, such a collection may be referred to herein without the letters, e.g., as “.”

1 FIG. 3 6 FIGS.- 1 FIG. 100 100 100 illustrates a cross-section of a Gunn diode, also referred to as a diode, according to some embodiments of the present disclosure. The Gunn diodeillustrates different regions and materials that may be included in Gunn diode devices., described further below, illustrate specific layered Gunn diode structures that may include the regions described with respect to.

1 3 6 FIGS.and- 1 FIG. 1 FIG. 102 104 106 108 A number of elements referred to in the description ofwith reference numerals are illustrated in these figures with different patterns, with a legend showing the correspondence between the reference numerals and patterns being provided at the bottom of the drawing pages. For example, the legend inillustrates thatuses different patterns to show a conductor, a first n+ material, a second n+ material, and an active material.

100 110 110 102 120 104 122 106 124 108 110 110 120 124 112 114 110 110 112 114 112 114 a b a b a b The diodeincludes two layersandof the conductor, a first n+ regionof the first n+ material, a second n+ regionof the second n+ material, and an active regionof the active material. The layersandare generally referred to as metal layers, and the layers-are generally referred to as semiconductor layers. Two terminalsandare represented on the metal layersand; in this case, the terminalis the anode, and the terminalis the cathode. The forward direction, from the anodeto the cathode, is indicated by the arrow labelled I.

102 102 The conductormay include one or more metals or metal alloys, with materials such as copper, ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, and aluminum, tantalum nitride, tungsten, doped silicon, doped germanium, or alloys and mixtures of any of these. In some embodiments, the conductormay include one or more electrically conductive alloys, oxides, or carbides of one or more metals.

104 106 108 x 1-x 0.7 0.3 One or more of the materials,, andmay include a III-V semiconductor, such as combinations of indium, gallium, aluminum, and/or arsenic. In some embodiments, one or more of the semiconductor materials may include a compound semiconductor with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of at least one element of group V of the periodic table (e.g., P, As, Sb). For some embodiments, one or more of the semiconductor materials may include a III-V material having a high electron mobility, such as, but not limited to InGaAs, InP, InSb, and InAs. For some such embodiments, one or more of the semiconductor materials may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some InGaAs embodiments, the In content (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., InGaAs). For other embodiments, one or more of the semiconductor materials may be a group IV material having a high hole mobility, such as, but not limited to Ge or a Ge-rich SiGe alloy. For some example embodiments, one or more of the semiconductor materials may have a Ge content between 0.6 and 0.9, and may be at least 0.7.

104 106 108 120 122 124 124 120 122 120 122 124 104 106 108 The materials,, andof the first n+ region, second n+ region, and active region, respectively, are selected such that the active regionhas a lower dopant concentration than the first n+ regionand second n+ region. The first n+ region, second n+ region, and active regionall have the same charge carrier, i.e., n-type charge carriers. In conductor and semiconductor materials, a charge carrier is a particle or quasiparticle that can move within the material, carrying a conductive charge and resulting in a net motion of particles through the material. In some semiconductors, the main charge carriers are electrons, while in others, the main charge carriers are electron holes (i.e., electron vacancies), generally referred to as holes. A semiconductor material or semiconductor region with electrons as the primary charge carrier is referred to as n-type. Doping may be used to create an n-type material; for example, silicon can be doped with another element such that the resulting doped material is n-type. Suitable n-type dopants for one or more of the materials,, andmay include phosphorus, arsenic, antimony, phosphorous, tellurium, sulfur, tin, silicon, germanium, etc.

108 104 106 104 108 106 108 104 106 104 106 108 104 106 108 108 104 106 16 18 −3 18 24 −3 In general, the active materialmay have a relatively low level of a dopant, e.g., a lower dopant concentration than the first n+ materialand the second n+ material. For example, the first n+ materialis a highly-doped n-type material, the active materialis a lower-doped n-type material, and the second n+ materialis a highly-doped n-type material. The active materialmay have a dopant concentration on the order of 10to 10cm. The first n+ materialand second n+ materialmay each have a dopant concentration on the order of 10to 10cm. In some embodiments, the dopant concentration of the n+ materialsandis at least ten times greater, at least 100 times greater, or at least 1000 times greater than the dopant concentration of the active material. In some embodiments, different dopants (e.g., different ones of the phosphorus, arsenic, antimony, etc.) may be included in different ones of the materials,, and. In some embodiments, the active materialmay have the same dopant as the first n+ materialand/or the second n+ material, but at a lower concentration.

120 122 120 122 120 122 112 114 120 122 1 FIG. In some embodiments, the n+ regionsandhave different dopant concentrations. The heights selected for the n+ regionsandmay be inversely related to the dopant concentrations of the n+ regionsand. At the anode, a relatively large collector has a relatively low dopant concentration, and at the cathode, a relatively small emitter has a relatively high dopant concentration. For example, the first n+ region, which is larger (as shown in), may have a lower dopant concentration than the second n+ region, which is smaller.

2 FIG. 2 FIG. 2 FIG. 210 220 210 210 212 214 210 212 th th illustrates example I-V curves for the Gunn diodes disclosed herein.illustrates voltage V along the x-axis and current I along the y-axis.includes two example I-V curvesandof a Gunn diode at different operating temperatures. The Gunn diode has a negative differential resistance region, also referred to as an NDR region. In general, in a negative differential resistance device, voltage is a single valued function of the current, but the current is a multivalued function of the voltage. Turning first to the curve, the NDR region for this curveis between the pointsand; in this portion of the curve, the current decreases as the voltage increases. The voltage at the pointis a threshold voltage Vfor the Gunn diode. When the voltage difference across the Gunn diode increases beyond V, the current density starts to decrease. The current further decreases with an increase in the applied voltage. In this region, the device exhibits negative resistance.

124 114 214 When the current pulse enters the active layer (e.g., the active region), the voltage difference across the active layer decreases. This prevents another current pulse from passing through the device until the previous current pulse passes through the other end (e.g., through the cathode). The voltage difference across the device then rises again, and another pulse begins traversing the active layer. The current continues pulsing in this manner, producing an oscillation at a particular oscillating frequency. If the voltage were further increased, beyond the point, which is referred to as the valley voltage or valley point, the current starts increasing again and the device again exhibits positive resistance.

210 220 210 220 220 222 224 222 224 th The curverepresents device operation at a first temperature. The second curverepresents device operation of the same device at a second temperature that is lower than the first temperature. For example, the curvemay characterize a device at 300 Kelvin, and the curvemay characterize the same device at 100 Kelvin. The NDR region for the curveis between the pointsand, where the voltage of the pointis the threshold voltage V, and the voltage at the pointis the valley voltage.

210 220 210 220 220 210 220 210 224 214 210 220 220 220 210 In this example, the threshold voltages of the curvesandare the same or substantially the same; in some embodiments, the threshold voltages of the two curvesandmay be different. The peak current at the threshold voltage of the curveis higher than the peak current at the threshold voltage of the curve. In addition, the valley voltage of the curveis higher than the valley voltage of the curve, and the current at the valley pointis lower than the current at the valley point. Furthermore, the curvedecreases more sharply or steeply than the curve. A Gunn diode may have improved performance at lower temperatures (e.g., at the lower temperature of the second curve) as represented by the exaggerated shape of the curvecompared to the curve.

3 FIG. 300 100 is a cross-section illustrating a layered Gunn diode structure, according to some embodiments of the present disclosure. The Gunn diodeis an example implementation of the Gunn diodedescribed above. In this example, rather than the diode being arranged vertically with current traveling in a vertical direction, current travels horizontally, as indicated by the arrow labelled I.

300 310 310 110 110 100 300 320 120 100 322 122 100 320 322 310 310 310 320 310 322 a b a b a b a b The Gunn diodeincludes two contactsand, corresponding to the metal layersandof the Gunn diode. The diodeincludes a first n+ region, which corresponds to the first n+ regionof the diode, and a second n+ region, which corresponds to the second n+ regionof the diode. The n+ regionsandare electrically coupled and in physical and electrical contact with contactsand, respectively. In particular, contactis over the n+ region, and contactis over the n+ region.

324 324 124 320 322 320 322 324 320 322 324 324 320 322 320 322 310 310 324 330 332 334 336 340 1 FIG. a b An active layeror active region, which corresponds to the active regionof, is in a layer below the n+ regionsand. The n+ regionsandare directly over and in contact with the active layer. The n+ regionsandare in a layer over the active layer, where the n+ regionsare arranged at different positions within this layer. Here, the first n+ regionis at a different position along the x-direction from the second n+ region, and the two n+ regionsandare physically separated from each other. In this example, contactis the anode, and contactis the cathode. The active layeris formed over a set of templating layers,,, and, which are formed over a substrate.

320 322 302 302 302 302 320 322 302 320 322 320 322 320 322 320 300 322 300 1 FIG. 1 FIG. 18 24 −3 The two n+ regionsandinclude an n+ material. The first n+ materialmay include indium, gallium, and arsenic, e.g., InGaAs or GaInAs. The first n+ materialfurther includes one or more dopants, e.g., any of the n-type dopants described with respect to. The n+ materialmay have a dopant concentration on the order of 10to 10cm, as described with respect to. While the n+ regionsandare both depicted as including the n+ material, in some embodiments, the n+ regionsandmay include different materials. For example, different dopants (e.g., different ones of the phosphorus, arsenic, antimony, etc.) may be included in different ones of the n+ regionsand. As another example, the two n+ regionsandmay have the same dopant or same set of dopants, but at different dopant concentrations. For example, the n+ region, which is the n+ region at the anode end of the Gunn diode, may have a lower dopant concentration than the n+ region, which is the n+ region at the cathode end of the Gunn diode.

320 322 320 322 320 300 322 300 320 322 4 FIG. The n+ regionsandmay have a height or thickness measured in the z-direction in the orientation shown that is less than 20 nm, less than 10 nm, between 1 and 20 nm, between 1 and 10 nm, between 5 and 10 nm, or within some other range. In some embodiments, the n+ regionsandhave the same or approximately the same thickness (e.g., the thicknesses are within 25%, 10%, or 5% of each other, or within some other tolerance). In some embodiments, one n+ region may be thicker than the other, e.g., the n+ region, which is the n+ region at the anode end of the Gunn diode, be at least 25% thicker, at least 50% thicker, or at least twice as thick as the n+ region, which is the n+ region at the cathode end of the Gunn diode. In addition, or alternatively, the n+ regionsandmay have different widths, as illustrated in.

324 304 304 304 304 302 304 302 304 324 1 FIG. 1 FIG. 16 18 −3 The active layerincludes an active material. The active materialmay include indium, aluminum, and arsenic, e.g., InAlAs. The active materialmay further include one or more dopants, e.g., any of the n-type dopants described with respect to. The active materialmay have a relatively low level of a dopant, e.g., a lower dopant concentration than the n+ material. The active materialmay have a dopant concentration on the order of 10to 10cm. As described with respect to, the dopant concentration of the n+ materialmay be at least ten times greater than (within one order of magnitude of), at least 100 times greater than (within two orders of magnitude of), or at least 1000 times greater than (within three orders of magnitude of) the dopant concentration of the active material. The active layermay have a thickness measured in the z-direction in the orientation shown that is less than 50 nm, less than 30 nm, less than 20 nm, between 10 and 30 nm, between 10 and 20 nm, between 15 and 30 nm, or within some other range.

320 322 324 300 The n+ regionsandand the active layermay be formed using epitaxial growth. In general, epitaxial growth involves crystal growth or material deposition in which crystalline layers are grown over an existing crystal structure, where the grown layers are formed with one or more well-defined orientations with respect to the underlying crystal structure. To form Gunn diodes, the epitaxial growth process is well-controlled and produces crystal layers having a minimal amount of defects. High consistency in crystal structure in the epitaxial growth process may be obtained using the set of templating layers having similar crystal structure to the materials of the Gunn diode.

3 FIG. 310 320 322 324 300 324 330 332 334 336 340 330 336 330 336 330 324 In particular, the upper layers of the structure shown in, e.g., the contacts, the layer with the n+ regionsand, and the active layer, may be considered to make up the Gunn diode. As noted above, the active layeris formed over a set of templating layers,,, and, which are formed over a substrate. The templating layers-may include each include indium, arsenic, and one of gallium or aluminum, alternating between whether gallium or aluminum are included in the layer. The templating layers-may include low levels of dopants or may not be doped. For example, the uppermost templating layerand, in some cases, one or more lower layers, may include some dopants that migrated from the active layer.

330 336 304 324 302 320 322 304 302 324 330 324 320 322 330 336 304 302 300 The templating layers-may each have a similar crystal structure to the active materialin the active layerand the n+ materialin the n+ regionsand. The active materialand the n+ materialare single crystal materials that are epitaxially deposited. In general, when a first layer of a first crystalline material (e.g., the active layer) is epitaxially deposited over a second layer of a second crystalline material (e.g., the templating layer), it is beneficial for the first crystalline material to have a similar structure to the second crystalline material. The similarity of structure helps the first crystalline material form the proper crystal structure when deposited over the second crystalline material. The growing of a first crystalline material over a different, second crystalline material is referred to as heteroepitaxial growth. In this example, forming the active layer, and then, the n+ regionsandover the stack of templating layers-may result in the active materialand n+ materialin the Gunn diodehaving highly regular crystal structures with minimal defects.

330 334 306 332 336 308 306 308 306 302 302 306 308 304 304 308 In the embodiment shown, the layersandinclude a first templating materialand the layersandinclude a second templating material. The first templating materialmay include indium, gallium, and arsenic (e.g., InGaAs), and the second templating materialmay include indium, aluminum, and arsenic (e.g., InAlAs). While the first templating materialand n+ materialmay both include indium, gallium, and arsenic, the n+ materialincludes a higher concentration of a dopant than the first templating material, which may have a relatively low dopant concentration, or may not be doped. Likewise, while the second templating materialand the active materialmay both include indium, aluminum, and arsenic, the active materialincludes a higher concentration of a dopant than the second templating material, which may have a relatively low dopant concentration, or may not be doped.

330 332 334 334 336 334 332 330 The layermay have a thickness or height in the z-direction that is less than 20 nm, less than 10 nm, between 1 and 20 nm, between 1 and 10 nm, between 5 and 10 nm, or within some other range. The layermay have a thickness in the z-direction that is less than 50 nm, less than 30 nm, less than 20 nm, between 10 and 30 nm, between 10 and 20 nm, between 15 and 30 nm, or within some other range. The layermay have a thickness in the z-direction that is less than 50 nm, less than 30 nm, less than 20 nm, between 10 and 50 nm, between 10 and 30 nm, between 20 and 50 nm, or within some other range. The layermay have a thickness in the z-direction that is less than 100 nm, less than 50 nm, less than 20 nm, between 10 and 50 nm, between 25 and 75 nm, between 50 and 100 nm, or within some other range. The layersandmay each be thicker than the layersand.

336 340 340 308 306 308 308 The layermay be formed over a substrate. The substratemay include a III-V materialthat serves as a suitable template for depositing the first templating materialwith a single-crystal structure. For example, the III-V materialmay include one or more elements from group III of the periodic table (also referred to as the boron group), such as aluminum, gallium, and indium, and one or more elements from group V of the periodic table (also referred to as the nitrogen group), such as nitrogen, phosphorus, arsenic, and antimony. For example, the III-V materialmay be InGaAs, InAlAs, gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP), among other examples.

4 FIG. 3 FIG. 3 FIG. 400 100 400 410 420 422 424 400 430 436 330 336 430 436 440 340 is a cross-section illustrating a layered Gunn diode structure with asymmetrical contacts, according to some embodiments of the present disclosure. The Gunn diodeis another example implementation of the Gunn diodedescribed above. The Gunn diodeincludes contacts, n+ regionsand, and an active layer. The Gunn diodeis formed over a set of templating layers-, which are similar to the layers-of. The layers-are over a substrate, which is similar to the substrateof.

400 410 410 110 110 100 410 410 310 310 310 310 410 410 410 410 410 410 410 410 410 410 a b a b a b a b a b a b a b a b a b a b. 3 FIG. 4 FIG. The Gunn diodeincludes two contactsand, corresponding to the metal layersandof the Gunn diode. Contactsandare similar to contactsand, except that whereas contactsandwere symmetric in the cross-section shown in, with equal widths in the x-direction, contactsandare asymmetric in the cross-section illustrated in, with different widths in the x-direction. In this example, contactis wider than contact. For example, contactmay be at least 25% wider, at least 50% wider, or at least twice as side as contact. Contactsandmay additionally or alternatively have different widths in the y-direction, e.g., contactmay have a greater width in the y-direction (e.g., into the page in the orientation shown) than contact

400 420 120 100 422 122 100 420 422 302 420 422 320 322 320 322 420 422 420 422 420 422 420 422 420 422 420 422 420 422 420 422 3 FIG. 4 FIG. 1 FIG. The diodefurther includes a first n+ region, which corresponds to the first n+ regionof the diode, and a second n+ region, which corresponds to the second n+ regionof the diode. The n+ regionsandinclude the n+ material, which may be doped InGaAs, as described above. The n+ regionsandare similar to the n+ regionsand, except that whereas n+ regionsandwere symmetric in the cross-section shown in, with equal widths in the x-direction, n+ regionsandare asymmetric in the cross-section illustrated in, with different widths in the x-direction. In this example, n+ regionis wider than n+ region. For example, n+ regionmay be at least 25% wider, at least 50% wider, or at least twice as side as n+ region. N+ regionsandmay additionally or alternatively have different widths in the y-direction, e.g., n+ regionmay have a greater width in the y-direction (e.g., into the page in the orientation shown) than n+ region. In some embodiments, n+ regionmay additionally or alternatively be taller than n+ region, e.g., as shown in. As noted above, the dopant concentrations of the n+ regionsandmay be different, e.g., the larger n+ regionmay have a lower dopant concentration than the smaller n+ region.

420 422 420 410 422 410 420 424 422 424 422 424 420 424 420 422 410 410 410 410 a b a b a b In general, the n+ region, which corresponds to the anode, may be larger than the n+ region. An area of contact between the n+ regionand the contactmay have a larger area than an area of contact between the n+ regionand the contact. Likewise, an area of contact between the n+ regionand the active layermay have a larger area than an area of contact between the n+ regionand the active layer. In some embodiments, the contact area between the n+ regionand the active layeris larger than the contact area between the n+ regionand the active layer, while the contact area between the respective n+ regionsandand the contactsandare the same, e.g., if the contactsandhave equal sizes.

300 400 2 FIG. The example diodesandare two-terminal devices. In some embodiments, a Gunn diode may include a gate electrically coupled to the active layer. The gate may apply a bias voltage to the Gunn diode, e.g., to bias the Gunn diode into the NDR region described with respect to.

5 FIG. 3 FIG. 3 FIG. 3 FIG. 3 FIG. 3 FIG. 500 510 510 520 522 524 510 310 520 522 320 322 524 324 500 530 536 330 336 530 536 540 340 a b is a cross-section illustrating a first gated Gunn diode structure, according to some embodiments of the present disclosure. The Gunn diodeincludes contactsand, n+ regionsand, and an active layer. The contactsare similar to the contactsof. The n+ regionsandare similar to the n+ regionsandof. The active layeris similar to the active layerof. The Gunn diodeis formed over a set of templating layers-, which are similar to the layers-of. The layers-are over a substrate, which is similar to the substrateof.

500 550 524 320 322 520 522 524 520 522 550 510 510 520 522 550 552 502 554 504 502 552 a b The Gunn diodefurther includes a gatecoupled to the active layer. Like the n+ regionsand, the n+ regionsandare in a same layer over the active layer, and the n+ regionsandare at different positions along the x-direction. The gateis between the two contactsandand between the two n+ regionsand. The gateincludes a gate electrode, which includes an electrode material, and a gate dielectric, which includes a dielectric material. The electrode materialmay include at least one metal, and in particular, one or more n-type work function metals, such as hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrodemay include a stack of two or more metal layers, e.g., where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer.

504 504 504 504 In various embodiments, the dielectric materialmay include one or more high-k dielectric materials and may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the dielectric materialmay include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, the dielectric materialincludes nitrogen, e.g., silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, zinc nitride, hafnium nitride, etc. In some embodiments, the gate dielectricmay have a thickness between about 0.5 nanometers and 10 nanometers, including all values and ranges therein, e.g., between about 1 and 5 nanometers, or between about 1 and 3 nanometers.

554 520 522 552 510 510 552 520 522 554 520 522 554 510 510 554 520 522 a b a b In this example, the gate dielectricis within the same layer as the n+ regionsand, and the gate electrodeis within the same layer as the contactsand. In other examples, at least a portion of the gate electrodemay be in the same layer as the n+ regionsand(e.g., if the gate dielectricis thinner than the n+ regionsand), or at least a portion of the gate dielectricmay be in the same layer as the contactsand(e.g., if the gate dielectricis thicker than the n+ regionsand).

6 FIG. 3 FIG. 3 FIG. 3 FIG. 3 FIG. 3 FIG. 600 610 610 620 622 624 610 310 620 622 320 322 624 324 600 630 636 330 336 630 636 640 340 a b is a cross-section illustrating a second gated Gunn diode structure, according to some embodiments of the present disclosure. The Gunn diodeincludes contactsand, n+ regionsand, and an active layer. The contactsare similar to the contactsof. The n+ regionsandare similar to the n+ regionsandof. The active layeris similar to the active layerof. The Gunn diodeis formed over a set of templating layers-, which are similar to the layers-of. The layers-are over a substrate, which is similar to the substrateof.

600 650 624 650 652 502 654 504 650 610 610 620 622 654 610 610 620 622 652 654 652 620 622 652 610 610 5 FIG. 5 FIG. 6 FIG. a b a b a b. The Gunn diodefurther includes a gatecoupled to the active layer. The gateincludes a gate electrode, which includes the electrode materialdescribed with respect to, and a gate dielectric, which includes the dielectric materialdescribed with respect to. The gateis between the two contactsandand between the two n+ regionsand. In particular, in this example, the gate dielectricextends between the two contactsandand between the two n+ regionsand. The gate electrodeis over the gate dielectric, and a bottom surface of the gate electrodeis above the top surfaces of the n+ regionsand. The bottom surface of the gate electrodemay be even with (as shown in) or, alternatively, above or below the top surfaces of the contactsand

7 FIG. 7 FIG. 7 FIG. 3 6 FIGS.- 5 FIG. 6 FIG. 2 FIG. 710 720 710 720 710 720 710 illustrates an example oscillation response of the Gunn diodes disclosed herein, according to some embodiments of the present disclosure.illustrates voltage V along the y-axis and time along the x-axis, showing a voltage response over a period of time.includes an input voltage pulseand an output oscillation voltage, where the input voltage pulseis applied to a Gunn diode (e.g., any of the Gunn diodes shown in), and the output oscillation voltageillustrates the response of the Gunn diode to the input voltage pulse. To produce the output oscillation voltage, the input voltage pulse, optionally in combination with a voltage applied at a gate (e.g., the gate illustrated inor), causes the Gunn diode to enter its NDR region, as described with respect to.

720 The oscillation frequency of the output oscillation voltagemay vary based on the input voltage and/or the operating temperature of the Gunn diode. For example, for a particular device, an operating temperature of 300 Kelvin (K) and an input voltage pulse of 1.8 V may produce an output with an oscillation frequency of around 2 gigahertz (GHz), while a lower operating temperature of 4 K and the same input voltage pulse of 1.8 V may produce an output with a lower oscillation frequency, e.g., between 1 and 1.5 GHz, e.g., around 1.25 GHz. As another example, for a Gunn diode with an operating temperature of 300 K and a lower input voltage pulse of 1.6 V, the output may have an oscillation frequency of less than 1 GHz, e.g., around 0.75 GHz. In this example, keeping the input voltage of 1.6 V and lowering the operating temperature to 4 K may increase the oscillation frequency, e.g., to around 0.9 or 1 GHz.

8 12 FIGS.- The Gunn diodes, and circuits including Gunn diodes, as disclosed herein may be included in any suitable electronic device.illustrate various examples of apparatuses that may include the one or more Gunn diodes disclosed herein, which may have been fabricated using the processes disclosed herein.

8 8 FIGS.A andB 1 2 4 7 FIGS.,, and- 9 FIG. 11 FIG. 1500 1502 1500 1502 1500 1502 1500 1502 1502 1640 1500 1502 1502 1502 1802 are top views of a wafer and dies that include one or more IC structures including one or more Gunn diodes in accordance with any of the embodiments disclosed herein. The wafermay be composed of semiconductor material and may include one or more dieshaving IC structures formed on a surface of the wafer. Each of the diesmay be a repeating unit of a semiconductor product that includes any suitable IC structure (e.g., the IC structures as shown in any of, or any further embodiments of the IC structures described herein). After the fabrication of the semiconductor product is complete (e.g., after manufacture of one or more IC structures with one or more of the transistors as described herein, included in a particular electronic component, e.g., in a transistor or in a memory device), the wafermay undergo a singulation process in which each of the diesis separated from one another to provide discrete “chips” of the semiconductor product. In particular, devices that include one or more of the transistors as disclosed herein may take the form of the wafer(e.g., not singulated) or the form of the die(e.g., singulated). The diemay include one or more transistors (e.g., one or more of the transistorsof, discussed below) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components (e.g., one or more of the non-planar transistors described herein). In some embodiments, the waferor the diemay include a memory device (e.g., an SRAM device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die. For example, a memory array formed by multiple memory devices may be formed on a same dieas a processing device (e.g., the processing deviceof) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

9 FIG. 8 FIG.A 8 FIG.B 8 FIG.B 8 FIG.A 1600 1600 1602 1500 1502 1602 1602 1502 1500 is a cross-sectional side view of an IC devicethat may include one or more Gunn diodes in accordance with any of the embodiments disclosed herein. The IC devicemay be formed on a substrate(e.g., the waferof) and may be included in a die (e.g., the dieof). The substratemay be any substrate as described herein. The substratemay be part of a singulated die (e.g., the diesof) or a wafer (e.g., the waferof).

1600 1604 1602 1604 1640 1602 1604 1620 1622 1640 1620 1624 1620 1640 1640 9 FIG. The IC devicemay include one or more device layersdisposed on the substrate. The device layermay include features of one or more transistors(e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the substrate. The device layermay include, for example, one or more source and/or drain (S/D) regions, a gateto control current flow in the transistorsbetween the S/D regions, and one or more S/D contactsto route electrical signals to/from the S/D regions. The transistorsmay include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistorsare not limited to the type and configuration depicted inand may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.

1640 1622 Each transistormay include a gateformed of at least two layers, a gate electrode layer and a gate dielectric layer.

The gate electrode layer may be formed on the gate interconnect support layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor, respectively. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer.

Further metal layers may be included for other purposes, such as a barrier layer or/and an adhesion layer.

For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 electron Volts (eV) and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, tungsten, tungsten carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

1640 In some embodiments, when viewed as a cross-section of the transistoralong the source-channel-drain direction, the gate electrode may be formed as a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may be implemented as a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may be implemented as one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. In some embodiments, the gate electrode may consist of a V-shaped structure (e.g., when a fin of a FinFET transistor does not have a “flat”upper surface, but instead has a rounded peak).

1640 1640 Generally, the gate dielectric layer of a transistormay include one layer or a stack of layers, and the one or more layers may include silicon oxide, silicon dioxide, and/or a high-k dielectric material. The high-k dielectric material included in the gate dielectric layer of the transistormay include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

1600 1600 The IC devicemay include one or more Gunn diodes at any suitable location in the IC device.

1620 1602 1622 1640 1620 1602 1620 1602 1620 1620 1620 1620 1602 1620 The S/D regionsmay be formed within the substrateadjacent to the gateof each transistor, using any suitable processes known in the art. For example, the S/D regionsmay be formed using either an implantation/diffusion process or a deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrateto form the S/D regions. An annealing process that activates the dopants and causes them to diffuse farther into the substratemay follow the ion implantation process. In the latter process, an epitaxial deposition process may provide material that is used to fabricate the S/D regions. In some implementations, the S/D regionsmay be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regionsmay be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions. In some embodiments, an etch process may be performed before the epitaxial deposition to create recesses in the substratein which the material for the S/D regionsis deposited.

1640 1604 1604 1606 1610 1604 1622 1624 1628 1606 1610 1606 1610 1619 1600 9 FIG. Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the transistorsof the device layerthrough one or more interconnect layers disposed on the device layer(illustrated inas interconnect layers-). For example, electrically conductive features of the device layer(e.g., the gateand the S/D contacts) may be electrically coupled with the interconnect structuresof the interconnect layers-. The one or more interconnect layers-may form an ILD stackof the IC device.

1628 1606 1610 1628 1606 1610 9 FIG. 9 FIG. The interconnect structuresmay be arranged within the interconnect layers-to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structuresdepicted in). Although a particular number of interconnect layers-is depicted in, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

1628 1628 1628 1628 1602 1604 1628 1628 1602 1604 1628 1628 1606 1610 a b a a b b a 9 FIG. In some embodiments, the interconnect structuresmay include trench contact structures(sometimes referred to as “lines”) and/or via structures(sometimes referred to as “holes”) filled with an electrically conductive material such as a metal. The trench contact structuresmay be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrateupon which the device layeris formed. For example, the trench contact structuresmay route electrical signals in a direction in and out of the page from the perspective of. The via structuresmay be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrateupon which the device layeris formed. In some embodiments, the via structuresmay electrically couple trench contact structuresof different interconnect layers-together.

1606 1610 1626 1628 1626 9 FIG. The interconnect layers-may include a dielectric materialdisposed between the interconnect structures, as shown in. The dielectric materialmay take the form of any of the embodiments of the dielectric material provided between the interconnects of the IC structures disclosed herein.

1626 1628 1606 1610 1626 1606 1610 In some embodiments, the dielectric materialdisposed between the interconnect structuresin different ones of the interconnect layers-may have different compositions. In other embodiments, the composition of the dielectric materialbetween different interconnect layers-may be the same.

1606 1604 1606 1628 1628 1628 1606 1624 1604 a b a A first interconnect layer(referred to as Metal 1 or “M1”) may be formed directly on the device layer. In some embodiments, the first interconnect layermay include trench contact structuresand/or via structures, as shown. The trench contact structuresof the first interconnect layermay be coupled with contacts (e.g., the S/D contacts) of the device layer.

1608 1606 1608 1628 1628 1608 1628 1606 1628 1628 1608 1628 1628 b a a a b a b A second interconnect layer(referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer. In some embodiments, the second interconnect layermay include via structuresto couple the trench contact structuresof the second interconnect layerwith the trench contact structuresof the first interconnect layer. Although the trench contact structuresand the via structuresare structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer) for the sake of clarity, the trench contact structuresand the via structuresmay be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

1610 1608 1608 1606 A third interconnect layer(referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layeraccording to similar techniques and configurations described in connection with the second interconnect layeror the first interconnect layer.

1600 1634 1636 1606 1610 1636 1628 1640 1636 1600 1600 1606 1610 1636 The IC devicemay include a solder resist material(e.g., polyimide or similar material) and one or more bond padsformed on the interconnect layers-. The bond padsmay be electrically coupled with the interconnect structuresand configured to route the electrical signals of the transistor(s)to other external devices. For example, solder bonds may be formed on the one or more bond padsto mechanically and/or electrically couple a chip including the IC devicewith another component (e.g., a circuit board). The IC devicemay have other alternative configurations to route the electrical signals from the interconnect layers-than depicted in other embodiments. For example, the bond padsmay be replaced by or may further include other analogous features (e.g., posts) that route the electrical signals to external components.

10 FIG. 1700 1700 1702 1700 1740 1702 1742 1702 1740 1742 1700 is a cross-sectional side view of an IC device assemblythat may include components having or being associated with (e.g., being electrically connected by means of) one or more Gunn diodes in accordance with any of the embodiments disclosed herein. The IC device assemblyincludes a number of components disposed on a circuit board(which may be, e.g., a motherboard). The IC device assemblyincludes components disposed on a first faceof the circuit boardand an opposing second faceof the circuit board; generally, components may be disposed on one or both facesand. In particular, any suitable ones of the components of the IC device assemblymay include one or more of the non-planar transistors disclosed herein.

1702 1702 1702 In some embodiments, the circuit boardmay be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board. In other embodiments, the circuit boardmay be a non-PCB substrate.

1700 1736 1740 1702 1716 1716 1736 1702 10 FIG. 10 FIG. The IC device assemblyillustrated inincludes a package-on-interposer structurecoupled to the first faceof the circuit boardby coupling components. The coupling componentsmay electrically and mechanically couple the package-on-interposer structureto the circuit boardand may include solder balls (as shown in) male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

1736 1720 1704 1718 1718 1716 1720 1704 1704 1704 1702 1720 1720 1502 1600 1720 1704 1704 1720 1716 1702 1720 1702 1704 1720 1702 1704 1704 10 FIG. 8 FIG.B 9 FIG. 10 FIG. The package-on-interposer structuremay include an IC packagecoupled to an interposerby coupling components. The coupling componentsmay take any suitable form for the application, such as the forms discussed above with reference to the coupling components. Although a single IC packageis shown in, multiple IC packages may be coupled to the interposer; indeed, additional interposers may be coupled to the interposer. The interposermay provide an intervening substrate used to bridge the circuit boardand the IC package. The IC packagemay be or include, for example, a die (the dieof), an IC device (e.g., the IC deviceof), or any other suitable component. In some embodiments, the IC packagemay include one or more Gunn diodes, as described herein. Generally, the interposermay spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposermay couple the IC package(e.g., a die) to a ball grid array (BGA) of the coupling componentsfor coupling to the circuit board. In the embodiment illustrated in, the IC packageand the circuit boardare attached to opposing sides of the interposer; in other embodiments, the IC packageand the circuit boardmay be attached to a same side of the interposer. In some embodiments, three or more components may be interconnected by way of the interposer.

1704 1704 1704 1708 1710 1706 1704 1714 1704 1736 The interposermay be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposermay be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposermay include metal interconnectsand vias, including but not limited to TSVs. The interposermay further include embedded devices, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer. The package-on-interposer structuremay take the form of any of the package-on-interposer structures known in the art.

1700 1724 1740 1702 1722 1722 1716 1724 1720 The IC device assemblymay include an IC packagecoupled to the first faceof the circuit boardby coupling components. The coupling componentsmay take the form of any of the embodiments discussed above with reference to the coupling components, and the IC packagemay take the form of any of the embodiments discussed above with reference to the IC package.

1700 1734 1742 1702 1728 1734 1726 1732 1730 1726 1702 1732 1728 1730 1716 1726 1732 1720 1734 10 FIG. The IC device assemblyillustrated inincludes a package-on-package structurecoupled to the second faceof the circuit boardby coupling components. The package-on-package structuremay include an IC packageand an IC packagecoupled together by coupling componentssuch that the IC packageis disposed between the circuit boardand the IC package. The coupling componentsandmay take the form of any of the embodiments of the coupling componentsdiscussed above, and the IC packagesandmay take the form of any of the embodiments of the IC packagediscussed above. The package-on-package structuremay be configured in accordance with any of the package-on-package structures known in the art.

11 FIG. 8 FIG. 9 FIG. 10 FIG. 2400 2400 1502 2400 1600 1700 is a block diagram of an example computing devicethat may include one or more components including one or more Gunn diodes in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the computing devicemay include a die (e.g., the dieof) having one or more Gunn diodes as described herein. Any one or more of the components of the computing devicemay include, or be included in, an IC deviceofor an IC device assemblyof.

11 FIG. 2400 2400 A number of components are illustrated inas included in the computing device, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing devicemay be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

2400 2400 2400 2412 2412 2400 2416 2414 2416 2414 11 FIG. Additionally, in various embodiments, the computing devicemay not include one or more of the components illustrated in, but the computing devicemay include interface circuitry for coupling to the one or more components. For example, the computing devicemay not include a display device, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display devicemay be coupled. In another set of examples, the computing devicemay not include an audio input deviceor an audio output device, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input deviceor audio output devicemay be coupled.

2400 2402 2402 2400 2404 2404 2402 The computing devicemay include a processing device(e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing devicemay include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing devicemay include a memory, which may itself include one or more memory devices such as volatile memory (e.g., DRAM), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memorymay include memory that shares a die with the processing device. This memory may be used as cache memory and may include embedded DRAM (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).

2400 2406 2406 2400 In some embodiments, the computing devicemay include a communication chip(e.g., one or more communication chips). For example, the communication chipmay be configured for managing wireless communications for the transfer of data to and from the computing device. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

2406 2406 2406 2406 2406 2400 2408 The communication chipmay implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 1402.11 family), IEEE 1402.16 standards (e.g., IEEE 1402.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 1402.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 1402.16 standards. The communication chipmay operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chipmay operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chipmay operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chipmay operate in accordance with other wireless protocols in other embodiments. The computing devicemay include an antennato facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

2406 2406 2406 2406 2406 2406 In some embodiments, the communication chipmay manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chipmay include multiple communication chips. For instance, a first communication chipmay be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chipmay be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chipmay be dedicated to wireless communications, and a second communication chipmay be dedicated to wired communications.

2400 2410 2410 2400 2400 The computing devicemay include a battery/power circuitry. The battery/power circuitrymay include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing deviceto an energy source separate from the computing device(e.g., AC line power).

2400 2412 2412 The computing devicemay include a display device(or corresponding interface circuitry, as discussed above). The display devicemay include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

2400 2414 2414 The computing devicemay include an audio output device(or corresponding interface circuitry, as discussed above). The audio output devicemay include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

2400 2416 2416 The computing devicemay include an audio input device(or corresponding interface circuitry, as discussed above). The audio input devicemay include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

2400 2418 2418 The computing devicemay include an other output device(or corresponding interface circuitry, as discussed above). Examples of the other output devicemay include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

2400 2420 2420 The computing devicemay include an other input device(or corresponding interface circuitry, as discussed above). Examples of the other input devicemay include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

2400 2422 2422 2400 The computing devicemay include a GPS device(or corresponding interface circuitry, as discussed above). The GPS devicemay be in communication with a satellite-based system and may receive a location of the computing device, as known in the art.

2400 2424 2424 2400 2402 2404 2424 The computing devicemay include a security interface device. The security interface devicemay include any device that provides security features for the computing deviceor for any individual components therein (e.g., for the processing deviceor for the memory). Examples of security features may include authorization, access to digital certificates, access to items in keychains, etc. Examples of the security interface devicemay include a software firewall, a hardware firewall, an antivirus, a content filtering device, or an intrusion detection device.

2400 2426 2428 In some embodiments, the computing devicemay include a temperature detection deviceand a temperature regulation device.

2426 2400 2402 2404 2426 2400 2400 2400 2426 2426 2400 2428 2402 2404 2426 2402 2426 2400 The temperature detection devicemay include any device capable of determining temperatures of the computing deviceor of any individual components therein (e.g., temperatures of the processing deviceor of the memory). In various embodiments, the temperature detection devicemay be configured to determine temperatures of an object (e.g., the computing device, components of the computing device, devices coupled to the computing device, etc.), temperatures of an environment (e.g., a data center that includes, is controlled by, or otherwise associated with the computing device), and so on. The temperature detection devicemay include one or more temperature sensors. Different temperature sensors of the temperature detection devicemay have different locations within and around the computing device. A temperature sensor may generate data (e.g., digital data) representing detected temperatures and provide the data to another device, e.g., to the temperature regulation device, the processing device, the memory, etc. In some embodiments, a temperature sensor of the temperature detection devicemay be turned on or off, e.g., by the processing deviceor an external system. The temperature sensor detects temperatures when it is on and does not detect temperatures when it is off. In other embodiments, a temperature sensor of the temperature detection devicemay detect temperatures continuously and automatically or detect temperatures at predefined times or at times triggered by an event associated with the computing deviceor any components therein.

2428 2426 2400 2400 2428 The temperature regulation devicemay include any device configured to change (e.g., decrease) temperatures, e.g., based on one or more target temperatures and/or based on temperature measurements performed by the temperature detection device. A target temperature may be a preferred temperature. A target temperature may depend on a setting in which the computing deviceoperates. In some embodiments, the target temperature may be 200 Kelvin degrees or lower. In some embodiments, the target temperature may be 20 Kelvin degrees or lower, or 5 Kelvin degrees or lower. Target temperatures for different objects and different environments of, or associated with, the computing devicecan be different. In some embodiments, cooling provided by the temperature regulation devicemay be a multi-stage process with temperatures ranging from room temperature to 4K or lower.

2428 2400 2428 2426 2400 2400 2428 2428 2428 3 2428 2400 In some embodiments, the temperature regulation devicemay include one or more cooling devices. Different cooling device may have different locations within and around the computing device. A cooling device of the temperature regulation devicemay be associated with one or more temperature sensors of the temperature detection deviceand may be configured to operate based on temperatures detected the temperature sensors. For instance, a cooling device may be configured to determine whether a detected ambient temperature is above the target temperature or whether the detected ambient temperature is higher than the target temperature by a predetermined value or determine whether any other temperature-related condition associated with the temperature of the computing deviceis satisfied. In response to determining that one or more temperature-related condition associated with the temperature of the computing deviceare satisfied (e.g., in response to determining that the detected ambient temperature is above the target temperature), a cooling device may trigger its cooling mechanism and start to decrease the ambient temperature. Otherwise, the cooling device does not trigger any cooling. A cooling device of the temperature regulation devicemay operate with various cooling mechanisms, such as evaporation cooling, radiation cooling, conduction cooling, convection cooling, other cooling mechanisms, or any combination thereof. A cooling device of the temperature regulation devicemay include a cooling agent, such as a water, oil, liquid nitrogen, liquid helium, etc. In some embodiments, the temperature regulation devicemay be, for example, a dilution refrigerator, a helium-refrigerator, or a liquid helium refrigerator. In some embodiments, the temperature regulation deviceor any portions thereof (e.g., one or more of the individual cooling devices) may be connected to the computing devicein close proximity (e.g., less than about 1 meter) or may be provided in a separate enclosure where a dedicated heat exchanger (e.g., a compressor, a heating, ventilation, and air conditioning (HVAC) system, liquid helium, liquid nitrogen, etc.) may reside.

2400 2400 2400 By maintaining the target temperatures, the energy consumption of the computing device(or components thereof) can be reduced, while the computing efficiency may be improved. For example, when the computing device(or components thereof) operates at lower temperatures, energy dissipation (e.g., heat dissipation) may be reduced. Further, energy consumed by semiconductor components (e.g., energy needed for switching transistors of any of the components of the computing device) can also be reduced. Various semiconductor materials may have lower resistivity and/or higher mobility at lower temperatures. That way, the electrical current per unit supply voltage may be increased by lowering temperatures. Conversely, for the same current that would be needed, the supply voltage may be lowered by lowering temperatures. As energy corelates to the supply voltage, the energy consumption of the semiconductor components may lower too. In some implementations, the energy savings due to reducing heat dissipation and reducing energy consumed by semiconductor components of the computing device or components thereof may outweigh (sometimes significantly outweigh) the costs associated with energy needed for cooling.

2400 2400 The computing devicemay have any desired form factor, such as a handheld or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing devicemay be any other electronic device that processes data.

12 FIG. 8 FIG. 9 FIG. 9 FIG. 10 FIG. 11 FIG. 2500 2500 1502 2500 1700 2500 1600 1700 2500 2400 2500 2402 2400 is a block diagram of an example processing devicethat may include one or more IC devices with one or more Gunn diodes in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the processing devicemay include a die (e.g., the dieof) having one or more Gunn diodes as described herein. Any one or more of the components of the processing devicemay include, or be included in, an IC device assembly(). Any one or more of the components of the processing devicemay include, or be included in, an IC deviceofor an IC device assemblyof. Any one or more of the components of the processing devicemay include, or be included in, a computing deviceof; for example, the processing devicemay be the processing deviceof the computing device.

12 FIG. 2500 2500 A number of components are illustrated inas included in the processing device, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the processing devicemay be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single SoC die or coupled to a single support structure, e.g., to a single carrier substrate.

2500 2500 2500 2504 2504 12 FIG. Additionally, in various embodiments, the processing devicemay not include one or more of the components illustrated in, but the processing devicemay include interface circuitry for coupling to the one or more components. For example, the processing devicemay not include a memory, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a memorymay be coupled.

2500 2502 The processing devicemay include logic circuitry(e.g., one or more circuits configured to implement logic/compute functionality). Examples of such circuits include ICs implementing one or more of input/output (I/O) functions, arithmetic operations, pipelining of data, etc.

2502 2504 2502 2504 In some embodiments, the logic circuitrymay include one or more circuits responsible for read/write operations with respect to the data stored in the memory. To that end, the logic circuitrymay include one or more I/O ICs configured to control access to data stored in the memory.

2502 2504 2504 2502 2502 2504 2504 2500 2502 2504 In some embodiments, the logic circuitrymay include one or more high-performance compute dies, configured to perform various operations with respect to data stored in the memory(e.g., arithmetic and logic operations, pipelining of data from one or more memory dies of the memory, and possibly also data from external devices/chips). In some embodiments, the logic circuitrymay be configured to only control I/O access to data but not perform any operations on the data. In some embodiments, the logic circuitrymay implement ICs configured to implement I/O control of data stored in the memory, assemble data from the memoryfor transport (e.g., transport over a central bus) to devices/chips that are either internal or external to the processing device, etc. In some embodiments, the logic circuitrymay not be configured to perform any operations on the data besides I/O and assembling for transport to the memory.

2500 2504 2504 2404 2504 2500 2404 2400 2504 2502 11 FIG. The processing devicemay include a memory, which may include one or more ICs configure to implement memory circuitry (e.g., ICs implementing one or more of memory devices, memory arrays, control logic configured to control the memory devices and arrays, etc.). In some embodiments, the memorymay be implemented substantially as described above with reference to the memory(). In some embodiments, the memorymay be a designated device configured to provide storage functionality for the components of the processing device(i.e., local), while the memorymay be configured to provide system-level storage functionality for the entire computing device(i.e., global). In some embodiments, the memorymay include memory that shares a die with the logic circuitry.

2504 2504 In some embodiments, the memorymay include a flat memory (also sometimes referred to as a “flat hierarchy memory” or a “linear memory”) and, therefore, may also be referred to as a “basin memory.” As known in the art, a flat memory or a linear memory refers to a memory addressing paradigm in which memory may appear to the program as a single contiguous address space, where a processor can directly and linearly address all of the available memory locations without having to resort to memory segmentation or paging schemes. Thus, the memory implemented in the memorymay be a memory that is not divided into hierarchical layer or levels in terms of access of its data.

2504 2504 2504 1 2 n i i+1 In some embodiments, the memorymay include a hierarchical memory. In this context, hierarchical memory refers to the concept of computer architecture where computer storage is separated into a hierarchy based on features of memory such as response time, complexity, capacity, performance, and controlling technology. Designing for high performance may require considering the restrictions of the memory hierarchy, i.e., the size and capabilities of each component. With hierarchical memory, each of the various memory components can be viewed as part of a hierarchy of memories (m, m, . . . m) in which each member mis typically smaller and faster than the next highest member mof the hierarchy. To limit waiting by higher levels, a lower level of a hierarchical memory structure may respond by filling a buffer and then signaling for activating the transfer. For example, in some embodiments, the hierarchical memory implemented in the memorymay be separated into four major storage levels: 1) internal storage (e.g., processor registers and cache), 2) main memory (e.g., the system RAM and controller cards), and 3) on-line mass storage (e.g., secondary storage), and 4) off-line bulk storage (e.g., tertiary, and off-line storage). However, as the number of levels in the memory hierarchy and the performance at each level has increased over time and is likely to continue to increase in the future, this example hierarchical division provides only one non-limiting example of how the memorymay be arranged.

2500 2506 2406 2506 2500 2406 2400 11 FIG. The processing devicemay include a communication device, which may be implemented substantially as described above with reference to the communication chip(). In some embodiments, the communication devicemay be a designated device configured to provide communication functionality for the components of the processing device(i.e., local), while the communication chipmay be configured to provide system-level communication functionality for the entire computing device(i.e., global).

2500 2508 2500 2508 The processing devicemay include interconnects, which may include any element or device that includes an electrically conductive material for providing electrical connectivity to one or more components of, or associated with, a processing deviceor/and between various such components. Examples of the interconnectsinclude conductive lines/wires (also sometimes referred to as “lines” or “metal lines” or “trenches”) and conductive vias (also sometimes referred to as “vias” or “metal vias”), metallization stacks, redistribution layers, metal-insulator-metal (MIM) structures, etc.

2500 2510 2426 2500 2510 2500 2426 2400 11 FIG. The processing devicemay include a temperature detection devicewhich may be implemented substantially as described above with reference to the temperature detection deviceofbut configured to determine temperatures on a more local scale, i.e., of the processing deviceof components thereof. In some embodiments, the temperature detection devicemay be a designated device configured to provide temperature detection functionality for the components of the processing device(i.e., local), while the temperature detection devicemay be configured to provide system-level temperature detection functionality for the entire computing device(i.e., global).

2500 2512 2428 2500 2512 2500 2428 2400 11 FIG. The processing devicemay include a temperature regulation devicewhich may be implemented substantially as described above with reference to the temperature regulation deviceofbut configured to regulate temperatures on a more local scale, i.e., of the processing deviceof components thereof. In some embodiments, the temperature regulation devicemay be a designated device configured to provide temperature regulation functionality for the components of the processing device(i.e., local), while the temperature regulation devicemay be configured to provide system-level temperature regulation functionality for the entire computing device(i.e., global).

2500 2514 2410 2514 2500 2410 2400 11 FIG. The processing devicemay include a battery/power circuitrywhich may be implemented substantially as described above with reference to the battery/power circuitryof. In some embodiments, the battery/power circuitrymay be a designated device configured to provide battery/power functionality for the components of the processing device(i.e., local), while the battery/power circuitrymay be configured to provide system-level battery/power functionality for the entire computing device(i.e., global).

2500 2516 2424 2516 2516 11 FIG. The processing devicemay include a hardware security devicewhich may be implemented substantially as described above with reference to the security interface deviceof. In some embodiments, the hardware security devicemay be a physical computing device configured to safeguard and manage digital keys, perform encryption and decryption functions for digital signatures, authentication, and other cryptographic functions. In some embodiments, the hardware security devicemay include one or more secure cryptoprocessors chips.

The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Unless specified otherwise, in various embodiments, features described with respect to one of the drawings may be combined with those described with respect to other drawings.

The following paragraphs provide various examples of the embodiments disclosed herein.

Example 1 provides a device including a first region extending in a first direction, the first region including indium, aluminum, and arsenic; a second region over a first portion of the first region; and a third region over a second portion of the first region, the second region and the third region arranged at different positions along the first direction, the second region and the third region including indium, gallium, and arsenic.

Example 2 provides the device of example 1, where the first region has a first n-type doping concentration, the second region has a second n-type doping concentration, and the second n-type doping concentration is greater than the first n-type doping concentration.

Example 3 provides the device of example 2, where the third region has a third n-type doping concentration, and the third n-type doping concentration is greater than the first n-type doping concentration.

Example 4 provides the device of example 3, where the third n-type doping concentration is within an order of magnitude of the second n-type doping concentration.

Example 5 provides the device of any preceding example, where the second region has a first width along the first direction, the third region has a second width along the first direction, and the first width is greater than the second width.

Example 6 provides the device of example 5, where the third region has a higher n-type doping concentration than the second region.

Example 7 provides the device of any preceding example, further including a fourth region under the first region, the fourth region including indium, gallium, and arsenic.

Example 8 provides the device of example 7, further including a fifth region under the fourth region, the fifth region including indium, aluminum, and arsenic.

Example 9 provides the device of example 8, further including a sixth region under the fifth region, the sixth region including indium, gallium, and arsenic.

Example 10 provides the device of example 9, further including a seventh region under the sixth region, the seventh region including indium, aluminum, and arsenic.

Example 11 provides the device of any preceding example, where the device is formed over a substrate, the substrate including a III-V material.

Example 12 provides the device of any preceding example, further including a gate over a third portion of the first region, the third portion between the first portion and the second portion.

Example 13 provides the device of example 12, where the gate is over a dielectric region, the dielectric region between the gate and the first region, and the dielectric region between the second region and the third region.

Example 14 provides a device including a first layer including indium, aluminum, and arsenic; a second layer including indium, gallium, and arsenic; a third layer including a first doped semiconductor region and a second doped semiconductor region, where the first and second doped semiconductor regions include indium, gallium, and arsenic, and where the first layer is between the second layer and the third layer; a first conductive structure coupled (e.g., conductively coupled, e.g., directly electrically connected and/or directly physically connected) to the first doped semiconductor region; and a second conductive structure coupled (e.g., conductively coupled, e.g., directly electrically connected and/or directly physically connected) to the second doped semiconductor region.

Example 15 provides the device of example 14, the third layer further including a dielectric region, the dielectric region between the first doped semiconductor region and the second doped semiconductor region.

Example 16 provides the device of example 15, further including a third conductive structure, where the dielectric region is between the third conductive structure and the first layer.

Example 17 provides the device of any of examples 14-16, where the first layer has a first n-type doping concentration, the first region of the third layer has a second n-type doping concentration, and the second n-type doping concentration is greater than the first n-type doping concentration.

Example 18 provides the device of any of examples 14-17, further including a fourth layer including indium, aluminum, and arsenic, the second layer between the first layer and the fourth layer; and a fifth layer including indium, gallium, and arsenic, the fourth layer between the second layer and the fifth layer.

Example 19 provides the device of any of examples 14-18, where a distance between the second layer and the third layer is between 10 and 30 nanometers.

Example 20 provides the device of any of examples 14-19, where a distance between the first layer and the first conductive structure is between 5 and 10 nanometers.

Example 21 provides a diode including a first layer including indium, aluminum, and arsenic, the first layer having a first thickness between 10 nanometers (nm) and 30 nm; and a second layer including a first region over a first portion of the first layer; and a second region over a second portion of the first layer, the first region and the second region including indium, gallium, and arsenic, and the second layer having a second thickness between 5 and 10 nm.

Example 22 provides the diode of example 21, where the second thickness is less than the first thickness.

Example 23 provides the diode of example 21 or 22, where the first layer further includes an n-dopant.

Example 24 provides the diode of example 23, where the second layer further includes an n-dopant, and a dopant concentration of the second layer is greater than a dopant concentration of the first layer.

Example 25 provides the diode of any of examples 21-24, where the diode is in an IC device, and the IC device is coupled (e.g., conductively coupled, e.g., directly electrically connected) to a circuit board.

The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description.