Integrated Circuit Performing Loopback Operation and Method of Operating the Same

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2024-0128858, filed on Sep. 24, 2024, which is incorporated herein by reference in its entirety.

Various embodiments of the present disclosure relate to an integrated circuit, and more particularly, to a technique for verifying a receiving operation of the integrated circuit.

A memory stores write data transmitted from a memory controller and provides the stored data as read data. When an error occurs in the write data during the receiving process of the write data, an error occurs in all operations of the memory. Therefore, verification of data receiving circuits of the memory is greatly important.

One of the methods for verifying a data receiving operation of the memory is the use of a loopback operation. The loopback operation refers to the operation of transmitting the data received by the memory back to the memory controller and verifying the transmitted data.

In accordance with an embodiment of the present disclosure, an integrated circuit may include a loopback clock terminal; a loopback data terminal; a first data terminal; a second data terminal disposed farther from the loopback data terminal than the first data terminal; a first data receiver configured to receive first data through the first data terminal; a second data receiver configured to receive second data through the second data terminal; a first sampler configured to sample, based on multi-phase clocks, the first data received by the first data receiver to generate multi-phase first data; a second sampler configured to sample, based on the multi-phase clocks, the second data received by the second data receiver to generate multi-phase second data; a first delay circuit configured to delay one of the multi-phase first data; a second delay circuit configured to delay one of the multi-phase second data, the second delay circuit having a larger delay value than the first delay circuit; a clock delay circuit configured to delay one of the multi-phase clocks; a loopback data sampler configured to sample, based on a clock delayed by the clock delay circuit, one of data delayed by the first delay circuit and data delayed by the second delay circuit; a loopback data transmitter configured to transmit data sampled by the loopback data sampler to the loopback data terminal; and a loopback clock transmitter configured to transmit the clock delayed by the clock delay circuit to the loopback clock terminal.

th th th th th th th th th In accordance with an embodiment of the present disclosure, an integrated circuit may include first to Ndata receiving circuits configured to receive, based on multi-phase clocks, first to Ndata through first to Ndata terminals to generate first to Nmulti-phase data, respectively, where “N” is an integer equal to or greater than 2; first to Ndelay circuits configured to delay first to Ndata having a selected phase, among the first to Nmulti-phase data, respectively; a clock delay circuit configured to delay a clock having the selected phase, among the multi-phase clocks; and a loopback circuit configured to transmit a clock delayed by the clock delay circuit to a loopback clock terminal, and transmit, based on the clock delayed by the clock delay circuit, one of first to Ndata having the selected phase, delayed by the first to Ndelay circuits, to a loopback data terminal.

th th th th th th In accordance with an embodiment of the present disclosure, a method of operating an integrated circuit may include receiving, based on multi-phase clocks, first to Ndata through first to Ndata terminals to generate first to Nmulti-phase data, respectively, where N is an integer equal to or greater than 2; delaying first to Ndata having a selected phase, among the first to Nmulti-phase data, respectively; delaying a clock having the selected phase, among the multi-phase clocks; and transmitting the delayed clock to a loopback clock terminal, and transmitting, based on the delayed clock, one of the delayed first to Ndata having the selected phase, to a loopback data terminal.

Various embodiments of the present disclosure are directed to technology of stably operating a loopback operation of an integrated circuit.

According to embodiments of the present disclosure, it is possible to perform a loopback operation while compensating for a skew difference according to positions of data terminals of an integrated circuit.

Hereinafter, various embodiments according to the technical spirit of the present disclosure are described below with reference to the accompanying drawings.

1 FIG. 1 FIG. 100 100 is a block diagram illustrating a memoryin accordance with an embodiment of the present disclosure.illustrates portions related to a loopback operation in the memory.

1 FIG. 100 0 110 0 110 120 0 120 130 140 150 111 0 111 131 151 Referring to, the memorymay include data terminals DQ<> to DQ<M>, a data clock terminal WCK, a loopback clock terminal LBDQS, a loopback data terminal LBDQ, data receiving circuits_to_M, delay circuits_to_M, a multi-phase clock generation circuit, a clock delay circuit, a loopback circuit, data phase selectors_to_M, a clock phase selector, and a data terminal selector.

0 100 0 150 0 150 150 The data terminals DQ<> to DQ<M> are terminals through which data are inputted to and outputted from the memory, where “M” is an integer equal to or greater than 1. The data terminals DQ<> to DQ<M> may be physically positioned to be close to and far from the loopback circuitand the loopback clock terminal LBDQS. Herein, the data terminal DQ<> is the farthest data terminal from the loopback circuit, and the data terminal DQ<M> is the closest data terminal to the loopback circuit.

0 0 The data clock terminal WCK is a terminal to which a data clock for strobing the data inputted to the data terminals DQ<> to DQ<M>is inputted. The data is inputted to each of the data terminals DQ<> to DQ<M> at a rising edge and a falling edge of the data clock. Herein, one data clock terminal WCK is illustrated, but the data clock may be a differential signal, and the data clock terminal WCK may be configured with two terminals for receiving the differential signal.

100 0 0 0 7 8 8 15 7 The loopback data terminal LBDQ is a terminal to which data looped back by the memoryis outputted. Data having a selected phase of a selected data terminal among the data terminals DQ<> to DQ<M> is outputted to the loopback data terminal LBDQ. A data rate of the data outputted to the loopback data terminal LBDQ may be ¼ of a data rate of the data inputted to the data terminals DQ<> to DQ<M>. Because the data rate of the data looped back through the loopback data terminal LBDQ is low, there is a low possibility that an error occurs during a loopback process. Namely, it may be possible to exclude an error occurring during the loopback process of data and detect an error occurring during a data receiving process. The loopback data terminal LBDQ may include a dedicated terminal for outputting loopback data, and a data terminal that is not used for the loopback operation may be used as the loopback data terminal. For example, during the loopback operation for verification of the data terminals DQ<> to DQ<>, the data terminal DQ<> may be used as the loopback data terminal LBDQ, and during the loopback operation for verification of the data terminals DQ<> to DQ<>, the data terminal DQ<> may be used as the loopback data terminal LBDQ. The loopback data terminal LBDQ may refer to a dedicated terminal only for the loopback operation or a data terminal used for the loopback operation.

The loopback clock terminal LBDQS is a terminal to which a loopback clock for strobing data outputted to the loopback data terminal LBDQ is outputted. Because the loopback clock is a clock for strobing data, it is also referred to as a loopback data strobe signal. The loopback clock terminal LBDQS may include a dedicated terminal for outputting the loopback clock, and a read data strobe signal terminal RDQS for outputting a read data strobe signal may be used as the loopback clock terminal LBDQS. The loopback clock terminal LBDQS may refer to a dedicated terminal only for the loopback operation or the read data strobe signal terminal RDQS used for outputting the loopback clock.

130 0 90 180 270 0 90 180 270 0 90 180 270 The multi-phase clock generation circuitmay generate multi-phase clocks WCK_, WCK_, WCK_, and WCK_using the data clock inputted to the data clock terminal WCK. A frequency of the multi-phase clocks WCK_, WCK_, WCK_, and WCK_is ½ of a frequency of the data clock, and phases of the multi-phase clocks WCK_, WCK_, WCK_, and WCK_may differ by 90°.

110 0 110 0 0 90 180 270 110 0 0 0 90 180 270 0 0 0 90 0 180 0 270 110 1 1 0 90 180 270 1 0 1 90 1 180 1 270 110 0 90 180 270 0 90 180 270 th The data receiving circuits_to_M may receive data through the data terminals DQ<> to DQ<M> using the multi-phase clocks WCK_, WCK_, WCK_, and WCK_. The data receiving circuit_may receive data of the data terminal DQ<> using the multi-phase clocks WCK_, WCK_, WCK_, and WCK_, and generate first multi-phase data DATA<>_, DATA<>_, DATA<>_, and DATA<>_. The data receiving circuit_may receive data of the data terminal DQ<> using the multi-phase clocks WCK_, WCK_, WCK_, and WCK_, and generate second multi-phase data DATA<>_, DATA<>_, DATA<>_, and DATA<>_. Similarly, the data receiving circuit_M may receive data of the data terminal DQ<M> using the multi-phase clocks WCK_, WCK_, WCK_, and WCK_, and generate (M+1)multi-phase data DATA<M>_, DATA<M>_, DATA<M>_, and DATA<M>_.

111 0 111 0 0 0 270 1 0 1 270 0 270 110 0 110 111 1 1 0 1 90 1 180 1 270 110 1 The data phase selectors_to_M may select data having a phase selected by phase selection information PHASE_SEL among the multi-phase data DATA<>_to DATA<>_, DATA<>_to DATA<>_, and DATA<M>_to DATA<M>_received by the data receiving circuits_to_M. For example, the data phase selector_may select and output one of the multi-phase data DATA<>_, DATA<>_, DATA<>_, and DATA<>_generated by the data receiving circuit_, according to the phase selection information PHASE_SEL.

120 0 120 0 1 120 0 120 0 120 120 1 120 1 120 0 120 0 120 0 The delay circuits_to_M may delay data DATA<>_SP, DATA<>_SP, and DATA<M>_SP having the selected phase. The delay circuits_to_M may have different delay values, and a delay circuit corresponding to a terminal that is closer to the loopback clock terminal LBDQS among the data terminals DQ<> to DQ<M> may have a larger delay value. That is, the delay circuit_M may have the largest delay value, and the delay circuit_M-may have the second largest delay value. In addition, the delay circuit_may have the second smallest delay value, and the delay circuit_may have the smallest delay value. Depending on design, the delay value of the delay circuit_may be designed to be substantially “0”. That is, the delay circuit_may be omitted.

131 0 90 180 270 130 131 111 0 111 111 0 111 131 111 0 0 180 131 180 The clock phase selectormay select and output one of the multi-phase clocks WCK_, WCK_, WCK_, and WCK_generated by the multi-phase clock generation circuit, according to the phase selection information PHASE_SEL. Because the clock phase selectorand the data phase selectors_to_M operate in response to the same phase selection information PHASE_SEL, a phase selected by the data phase selectors_to_M may be the same as a phase selected by the clock phase selector. For example, when the data phase selector_selects the data DATA<>_, the clock phase selectormay select the clock WCK_.

140 131 140 0 0 150 The clock delay circuitmay delay a clock WCK_SP having a phase selected by the clock phase selector. A delay value of the clock delay circuitmay be set to a value corresponding to a delay value of a path through which data is transmitted from the data terminal DQ<> disposed farthest from the loopback clock terminal LBDQS among the data terminals DQ<> to DQ<M> to the loopback circuit.

151 0 1 120 0 120 270 0 0 270 270 0 The data terminal selectormay select one of data DATA<>_SPD, DATA<>_SPD, and DATA<M>_SPD obtained by the delay of the delay circuits_to_M, according to data terminal selection information DQ_SEL. The data terminal selection information DQ_SEL is information for selecting a data terminal to be a target for the loopback operation. Data selected by the data terminal selection information DQ_SEL and the phase selection information PHASE_SEL is the target for the loopback operation. For example, when a phaseis selected by the phase selection information PHASE_SEL and the data terminal DQ<> is selected by the data terminal selection information DQ_SEL, the data DATA<>_corresponding to the phaseinputted to the data terminal DQ<> becomes the target for the loopback operation.

150 140 151 140 The loopback circuitmay transmit a clock WCK_SPD obtained by the delay of the clock delay circuitto the loopback clock terminal LBDQS, and transmit data DATA_SEL_SPD selected by the data terminal selectorto the loopback data terminal LBDQ using the clock WCK_SPD obtained by the delay of the clock delay circuit.

2 FIG. 1 FIG. 130 is a block diagram illustrating an embodiment of the multi-phase clock generation circuitillustrated in.

2 FIG. 130 210 220 Referring to, the multi-phase clock generation circuitmay include a data clock receiverand a divider.

210 210 The data clock receivermay receive the data clock of the data clock terminal WCK. As described above, the data clock may be a differential signal, and a quantity of the data clock terminal WCK may be two. Accordingly, the data clock receivermay be a differential receiver.

220 210 0 90 180 270 0 90 180 270 0 90 180 270 The dividermay divide the data clock received by the data clock receiverand generate the multi-phase clocks WCK_, WCK_, WCK_, and WCK_. The frequency of the multi-phase clocks WCK_, WCK_, WCK_, and WCK_may be ½ of the frequency of the data clock, and the phases of the multi-phase clocks WCK_, WCK_, WCK_, and WCK_may differ by 90°.

3 FIG. 1 FIG. 110 0 is a block diagram illustrating an embodiment of the data receiving circuit_illustrated in.

3 FIG. 110 0 310 320 Referring to, the data receiving circuit_may include a data receiverand a sampler.

310 0 The data receivermay receive data through the data terminal DQ<>.

320 310 0 90 180 270 320 321 324 321 324 0 90 180 270 321 0 0 0 324 270 0 270 The samplermay sample the data received by the data receiverusing the multi-phase clocks WCK_, WCK_, WCK_, and WCK_. The samplermay include D flip-flopsto. Each of the D flip-flopstomay sample the data at a rising edge of a corresponding multi-phase clock among the multi-phase clocks WCK_, WCK_, WCK_, and WCK_. For example, the D flip-flopmay sample the data at the rising edge of the multi-phase clock WCK_to generate the first multi-phase data DATA<>_, and the D flip-flopmay sample the data at the rising edge of the multi-phase clock WCL_to generate the first multi-phase data DATA<>_.

4 FIG. 4 FIG. 110 0 0 90 180 270 0 0 0 0 90 0 180 0 270 320 is a timing diagram illustrating an operation of the data receiving circuit_, in accordance with an embodiment of the present disclosure. Referring to, a relationship between the data clock WCK and the multi-phase clocks WCK_, WCK_, WCK_, and WCK_and a relationship between the data of the data pad DQ<> and the first multi-phase data DATA<>_, DATA<>_, DATA<>_, and DATA<>_generated by the samplermay be seen.

3 FIG. 3 FIG. 110 0 110 1 110 Althoughillustrates only the data receiving circuit_, the other data receiving circuits_to_M may also be configured in the same manner as illustrated in.

5 FIG. 1 FIG. 150 is a block diagram illustrating an embodiment of the loopback circuitillustrated in.

5 FIG. 150 510 520 530 Referring to, the loopback circuitmay include a loopback data sampler, a loopback data transmitter, and a loopback clock transmitter.

510 151 140 510 140 The loopback data samplermay sample the data DATA_SEL_SPD selected by the data terminal selectorusing the clock WCK_SPD obtained by the delay of the clock delay circuit. The loopback data samplermay include a D flip-flop that samples the data DATA_SEL_SPD at a rising edge of the clock WCK_SPD obtained by the delay of the clock delay circuit.

520 510 The loopback data transmittermay transmit data obtained by the sampling of the loopback data samplerto the loopback data terminal LBDQ.

530 510 140 The loopback clock transmittermay transmit the clock WCK_SPD used during the sampling operation of the loopback data sampler, that is, the clock WCK_SPD obtained by the delay of the clock delay circuit, to the loopback clock terminal LBDQS.

1 5 FIGS.to 100 Referring back to, the loopback operation of the memoryis described.

130 0 90 180 279 0 90 180 279 110 0 110 110 0 110 0 0 90 180 270 The multi-phase clock generation circuitmay generate the multi-phase clocks WCK_, WCK_, WCK_, and WCK_using the data clock received by the data clock terminal WCK. The multi-phase clocks WCK_, WCK_, WCK_, and WCK_are transmitted to the data receiving circuits_to_M, and the data receiving circuits_to_M may receive the data of the data terminals DQ<> to DQ<M> using the multi-phase clocks WCK_, WCK_, WCK_, and WCK_.

0 0 0 270 1 0 1 270 0 270 110 0 110 0 150 120 0 120 110 0 110 150 120 0 120 110 0 150 110 1 110 150 Among the multi-phase data DATA<>_to DATA<>_, DATA<>_to DATA<>_, and DATA<M>_to DATA<M>_generated by the data receiving circuits_to_M, respectively, the data DATA<>_SP to DATA<M>_SP having the phase selected by the phase selection information PHASE_SEL are transmitted to the loopback circuitthrough the delay circuits_to_M. Although distances between the data receiving circuits_to_M and the loopback circuitare different, a difference in the distances may be compensated for because the delay values of the delay circuits_to_M are different. That is, the time for data to be transmitted from the farthest data receiving circuit_to the loopback circuitmay be the same as the time for data to be transmitted from other data receiving circuits_to_M to the loopback circuit.

0 90 180 270 140 Among the multi-phase clocks WCK_, WCK_, WCK_, and WCK_, the clock WCK_SP having the phase selected by the phase selection information PHASE_SEL is delayed by the clock delay circuit. Accordingly, the same delay time as time taken in the process of data being transmitted from the data receiving circuits to the loopback circuit may be reflected in the clock WCK_SP.

151 0 120 0 120 510 150 151 140 510 520 530 The data terminal selectormay select one of the data DATA<>_SPD to DATA<M>_SPD obtained by the delay of the delay circuits_to_M, according to the data terminal selection information DQ_SEL, and the loopback data samplerof the loopback circuitmay sample the data DATA_SEL_SPD selected by the data terminal selectorusing the clock WCK_SPD obtained by the delay of the clock delay circuit. The data obtained by the sampling of the loopback data sampleris outputted to the loopback data terminal LBDQ by the loopback data transmitter, and the clock WCK_SPD is outputted to the loopback clock terminal LBDQS by the loopback clock transmitter.

100 100 Consequently, data selected by the data terminal selection information DQ_SEL and the phase selection information PHASE_SEL is looped back to a memory controller through the loopback data terminal LBDQ, and a clock for strobing the loopback data is looped back to the memory controller through the loopback clock terminal LBDQS. The memory controller may check whether the memoryhas correctly received the data by checking the data and clock to be looped back. Because a data rate of the loopback data is ¼ of a data rate of the data received by the memory, there is a low possibility that an error occurs. Therefore, the memory controller may check the loopback data in which only the error occurring during the data receiving process is reflected, excluding the error occurring during the loopback process.

Although it is described according to embodiments described above that a loopback operation is performed in a memory, it is to be understood that the embodiments are not only applicable to the memory, but may also be used to verify a data receiving operation of a general integrated circuit.

Although the technical spirit of the present disclosure has been described above according to embodiments, this is only for describing the embodiments according to the concept of the present disclosure, and the present disclosure is not limited to the above embodiments. Various embodiments may be applied by those skilled in the art, to which the present disclosure pertains, within the scope of the technical spirit of the present disclosure. Furthermore, the embodiments may be combined to form additional embodiments.