Deposition Mask

This application claims priority to Korean Patent Application No. 10-2024-0131335, filed on Sep. 27, 2024, and all the benefits accruing therefrom under 35 U.S.C. § 119, the content of which in its entirety is herein incorporated by reference.

The present disclosure relates to a deposition mask.

A head mounted display (HMD) is an image display device that is worn on a user's head in the form of glasses or a helmet and focuses on a distance close to the user's eyes. The head mounted display may realize virtual reality (VR) or augmented reality (AR).

The head mounted display enlarges and displays an image displayed on a small display device using a plurality of lenses. Therefore, a display device applied to the head mounted display may be desired to provide a high-resolution image, for example, an image having a resolution of 3000 pixels per inch (PPI) or higher. To this end, organic light emitting diode on silicon (OLEDoS), which is a high-resolution small-sized organic light emitting display device, may be used as the display device applied to the head mounted display. The OLEDoS is a device that displays an image by disposing an organic light emitting diode (OLED) on a semiconductor wafer substrate including a complementary metal oxide semiconductor (CMOS).

In order to manufacture high-resolution display panels with a resolution of 3000 pixels per inch (PPI) or higher, a high-resolution deposition mask is desired. For example, the deposition mask may be manufactured by forming a membrane having a plurality of pixel openings on a substrate, such as a silicon wafer, and forming cell openings by partially etching the substrate to expose the pixel openings.

The deposition mask may be used in a deposition process for forming organic light emitting layers on a backplane substrate. During the deposition process, the backplane substrate may be disposed on the deposition mask, and a deposition source for providing a vapor deposition material may be disposed on a lower portion of the deposition mask. The vapor deposition material may be deposited on the backplane substrate through the pixel openings of the deposition mask.

Embodiments of the present disclosure provide a deposition mask with reduced global warpage.

However, embodiments of the present disclosure are not restricted to those set forth herein. The above and other embodiments of the present disclosure will become more apparent to one of ordinary skill in the art to which the present disclosure pertains by referencing the detailed description of the present disclosure given below.

According to an embodiment of the present disclosure, a deposition mask includes a mask frame in which a cell opening is defined, and a membrane disposed on the mask frame and partitioned into a mask cell area disposed on the cell opening and a grid area disposed on the mask frame not to overlap the cell opening, where a plurality of mask cell areas is defined in the membrane, and the mask cell areas are disposed in a matrix form having a plurality of rows in a first direction and a plurality of columns in a second direction intersecting the first direction.

In an embodiment, a number of the mask cell areas disposed in one of the plurality of rows may be equal to or greater than a number of the mask cell areas disposed in one of the plurality of columns.

In an embodiment, the number of the mask cell areas disposed in one of the plurality of columns may be 70% or greater and 100% or less of the number of the mask cell areas disposed in one of the plurality of rows.

In an embodiment, the number of the mask cell areas disposed in one of the plurality of rows and the number of the mask cell areas disposed in one of the plurality of columns are defined by the following inequality:

where CX denotes the number of the mask cell areas disposed in the one of the plurality of rows, and CY denotes the number of the mask cell areas disposed in the one of the plurality of columns.

In an embodiment, the plurality of mask cell areas may have a same size as each other.

In an embodiment, a length of the mask cell area in the first direction may be equal to or length than a length of the mask cell area in the second direction.

In an embodiment, the length of the mask cell area in the second direction may be 70% or greater and 100% or less of the length of the mask cell area in the first direction.

In an embodiment, the length of the mask cell area in the first direction and the length of the mask cell area in the second direction may satisfy the following inequality:

where CW denotes the length of the mask cell area in the first direction, and CL denotes the length of the mask cell area in the second direction.

In an embodiment, a length of a gap between the mask cell areas in the first direction may be equal to or longer than a length of a gap between the mask cell areas in the second direction.

In an embodiment, the length of a gap between the mask cell areas in the second direction may be 70% or greater and 100% or less of the length of a gap between the mask cell areas in the first direction.

In an embodiment, the length of a gap between the mask cell areas in the first direction and the length of a gap between the mask cell areas in second direction may satisfy the following inequality:

where CIW denotes the length of the gap between the mask cell areas in the first direction, and CIL denotes the length of the gap between the mask cell areas in the second direction.

In an embodiment, a number of the mask cell areas disposed in each row may gradually decrease from a row disposed on a center side of the membrane to a row disposed in an outer side of the membrane in the second direction, and a number of the mask cell areas disposed in each column may gradually decrease from a column disposed on a center side of the membrane to a column disposed in an outer side of the membrane in the first direction.

In an embodiment, a total length of the mask cell areas on an imaginary line passing through the center side of the membrane and extending in the first direction may satisfy equal to or longer than a total length of the mask cell areas on an imaginary line passing through the center side of the membrane and extending in a fourth direction intersecting the first direction and the second direction.

In an embodiment, the first direction and the second direction may satisfy orthogonal to each other, and the fourth direction may intersect the first direction or the second direction at an angle of about 45°.

In an embodiment, the total length of the mask cell areas on an imaginary line passing through the center side of the membrane and extending in a fourth direction intersecting the first direction and the second direction may satisfy 70% or greater and 100% or less of the total length of the mask cell areas on an imaginary line passing through the center side of the membrane and extending in the first direction.

In an embodiment, the total length of the mask cell areas on an imaginary line passing through the center side of the membrane and extending in the first direction and the total length of the mask cell areas on an imaginary line passing through the center side of the membrane and extending in a fourth direction intersecting the first direction and the second direction may satisfy the following inequality:

where CTWL denotes the total length of the mask cell areas on the imaginary line extending in the first direction, and CTDL denotes the total length of the mask cell areas on the imaginary line extending in the fourth direction.

In an embodiment, a plurality of pixel openings may be defined through the membrane in the mask cell area.

In an embodiment, the membrane may include an inorganic film layer disposed on the mask frame, and a nitride layer disposed on the inorganic film layer.

In an embodiment, the deposition mask may further include a first rear inorganic film layer disposed below the mask frame with a first rear opening defined therein, a second rear inorganic film layer disposed below the first rear inorganic film layer with a second rear opening defined therein.

In an embodiment, the first rear inorganic film layer may include a same material as the inorganic film layer, and the second rear inorganic film layer may include a same material as the nitride layer.

According to an embodiment of the present disclosure, an electronic device includes a display device manufactured by a deposition mask, where the deposition mask includes a mask frame in which a cell opening is defined, and a membrane disposed on the mask frame and partitioned into a mask cell area disposed on the cell opening and a grid area disposed on the mask frame not to overlap the cell opening, where a plurality of mask cell areas is provided in the membrane, and the mask cell areas are disposed in a matrix form having a plurality of rows in a first direction and a plurality of columns in a second direction intersecting the first direction.

In embodiments of the deposition mask according to the present disclosure, deposition defects are effectively prevented by reducing global warpage by adjusting the size or arrangement shape of a plurality of mask cell areas.

The effects according to the embodiments of the present disclosure are not limited to those mentioned above and more various effects are included in the following description of the present disclosure.

The invention now will be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. This invention may, however, be embodied in many different forms, and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout.

It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

It will be understood that, although the terms “first,” “second,” “third” etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, “a first element,” “component,” “region,” “layer” or “section” discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a”, “an,” “the,” and “at least one” do not denote a limitation of quantity, and are intended to include both the singular and plural, unless the context clearly indicates otherwise. Thus, reference to “an” element in a claim followed by reference to “the” element is inclusive of one element and a plurality of the elements. For example, “an element” has the same meaning as “at least one element,” unless the context clearly indicates otherwise. “At least one” is not to be construed as limiting “a” or “an.” “Or” means “and/or.” As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

Furthermore, relative terms, such as “lower” or “bottom” and “upper” or “top,” may be used herein to describe one element's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in one of the figures is turned over, elements described as being on the “lower” side of other elements would then be oriented on “upper” sides of the other elements. The term “lower,” can therefore, encompasses both an orientation of “lower” and “upper,” depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as “below” or “beneath” other elements would then be oriented “above” the other elements. The terms “below” or “beneath” can, therefore, encompass both an orientation of above and below.

“About” or “approximately” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, 20%, 10% or 5% of the stated value.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Embodiments are described herein with reference to cross section illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as flat may, typically, have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims.

Features of various embodiments of the present disclosure may be combined partially or totally. As will be clearly appreciated by those skilled in the art, technically various interactions and operations are possible. Various embodiments can be practiced individually or in combination.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

1 FIG. 2 FIG. 1 FIG. is a schematic exploded perspective view illustrating a display device according to an embodiment.is a schematic plan view for describing the display device illustrated in.

1 2 FIGS.and 10 10 10 10 Referring to, a display deviceaccording to an embodiment is a device that displays a moving image or a still image. The display deviceaccording to an embodiment may be applied to portable electronic devices such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), navigation, and an ultra mobile PC (UMPC). For example, the display deviceaccording to an embodiment may be applied to a display unit of a television (TV), a laptop computer, a monitor, a billboard, or the Internet of Things (IoT). Alternatively, the display deviceaccording to an embodiment may be applied to a smart watch, a watch phone, and a head mounted display (HMD) for implementing virtual reality and augmented reality.

10 100 200 300 400 500 The display deviceaccording to an embodiment includes a display panel, a heat dissipation layer, a circuit board, a timing control circuit, and a power supply circuit.

100 100 1 2 1 3 100 100 1 2 100 10 100 The display panelmay be formed in a planar shape similar to a quadrangle when viewed in a plan view. In an embodiment, for example, the display panelmay have a planar shape similar to a quadrangle having short sides in a first direction DRand long sides in a second direction DRintersecting the first direction DRwhen viewed in a third direction DR, which is a thickness direction of the display panel. In the display panel, a corner where the short side in the first direction DRand the long side in the second direction DRmeet may be rounded to have a predetermined curvature or may be formed at a right angle. The planar shape of the display panelis not limited to the quadrangle, and may be formed similarly to other polygons, circles, or ovals. A planar shape of the display devicemay follow the planar shape of the display panel, but the embodiment of the present specification is not limited thereto.

2 FIG. 2 FIG. 100 610 620 700 100 In an embodiment, as shown in, the display panelincludes a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, a plurality of data lines DL, a scan driver, a light emitting driver, and a data driver. The display panelmay be divided into a display area DAA for displaying an image and a non-display area NDA that does not display an image, as illustrated in.

1 2 1 2 2 1 The plurality of pixels PX may be disposed in the display area DAA. The plurality of pixels PX may be arranged in a matrix form in the first direction DRand the second direction DR. The plurality of scan lines SL and the plurality of emission control lines EL may extend in the first direction DRand may be disposed (or arranged) in the second direction DR. The plurality of data lines DL may extend in the second direction DRand may be disposed (or arranged) in the first direction DR.

1 2 The plurality of scan lines SL includes a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines GBL. The plurality of emission control lines EL include a plurality of first emission control lines ECLand a plurality of second emission control lines ECL.

1 2 3 1 2 3 700 3 FIG. 7 FIG. The plurality of pixels PX include a plurality of sub-pixels SP, SP, and SP. The plurality of sub-pixels SP, SP, and SPmay include a plurality of pixel transistors as illustrated in, and the plurality of pixel transistors may be formed through a semiconductor process and may be disposed on a semiconductor substrate (SSUB in). In an embodiment, for example, the plurality of pixel transistors of the data drivermay include or be formed of a complementary metal oxide semiconductor (CMOS), but the embodiment of the present specification is not limited thereto.

1 2 3 1 2 1 2 3 Each of the plurality of sub-pixels SP, SP, and SPmay be connected to a corresponding write scan line GWL, a corresponding control scan line GCL, a corresponding bias scan line GBL, a corresponding first emission control line ECL, a corresponding second emission control line ECL, and a corresponding data line DL. Each of the plurality of sub-pixels SP, SP, and SPmay receive a data voltage of the data line DL based on a write scan signal of the write scan line GWL, and may emit light from a light emitting element based on the data voltage.

610 620 700 The scan driver, the light emitting driver, and the data drivermay be disposed in the non-display area NDA.

610 620 7 FIG. The scan driverincludes a plurality of scan transistors, and the light emitting driverincludes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors may be formed through a semiconductor process and may be formed on a semiconductor substrate (SSUB in). In an embodiment, for example, the plurality of scan transistors and the plurality of light emitting transistors may include or be formed of CMOS, but the embodiment of the present specification is not limited thereto.

610 611 612 613 611 612 613 400 611 400 612 613 The scan drivermay include a write scan signal output unit, a control scan signal output unit, and a bias scan signal output unit. Each of the write scan signal output unit, the control scan signal output unit, and the bias scan signal output unitmay receive a scan timing control signal SCS from the timing control circuit. The write scan signal output unitmay generate write scan signals based on the scan timing control signal SCS of the timing control circuitand sequentially output the write scan signals to the write scan lines GWL. The control scan signal output unitmay generate control scan signals based on the scan timing control signal SCS and sequentially output the control scan signals to the control scan lines GCL. The bias scan signal output unitmay generate bias scan signals based on the scan timing control signal SCS and sequentially output the bias scan signals to the bias scan lines GBL.

620 621 622 621 622 400 621 1 622 2 The light emitting driverincludes a first emission control driverand a second emission control driver. Each of the first emission control driverand the second emission control drivermay receive an emission timing control signal ECS from the timing control circuit. The first emission control drivermay generate first emission control signals based on the emission timing control signal ECS and sequentially output the first emission control signals to the first emission control lines ECL. The second emission control drivermay generate second emission control signals based on the emission timing control signal ECS and sequentially output the second emission control signals to the second emission control lines ECL.

700 7 FIG. The data drivermay include a plurality of data transistors, and the plurality of data transistors may be formed through a semiconductor process and may be formed on a semiconductor substrate (SSUB in). In an embodiment, for example, the plurality of data transistors may be formed of CMOS, but the embodiment of the present specification is not limited thereto.

700 400 700 1 2 3 610 1 2 3 The data drivermay receive digital video data DATA and a data timing control signal DCS from the timing control circuit. The data driverconverts the digital video data DATA into analog data voltages based on the data timing control signal DCS and outputs the converted analog data voltages to the data lines DL. In this case, the sub-pixels SP, SP, and SPmay be selected by the write scan signals of the scan driver, and the data voltages may be supplied to the selected sub-pixels SP, SP, and SP.

200 100 3 100 200 100 200 100 200 The heat dissipation layermay overlap the display panelin the third direction DR, which is a thickness direction of the display panel. The heat dissipation layermay be disposed on one surface of the display panel, for example, a rear surface thereof. The heat dissipation layerserves to dissipate heat generated from the display panel. The heat dissipation layermay include a metal layer such as graphite, silver (Ag), copper (Cu), or aluminum (Al) having high thermal conductivity.

300 1 1 100 300 300 300 300 300 100 200 300 1 1 100 300 300 4 FIG. 4 FIG. 1 FIG. 4 FIG. 4 FIG. The circuit boardmay be electrically connected to a plurality of first pads (PDin) of a first pad portion (PDAin) of the display panelby using a conductive adhesive member such as an anisotropic conductive film. The circuit boardmay be a flexible printed circuit board or flexible film including or made of a flexible material.illustrates an embodiment where the circuit boardis in an unfolded state, but the circuit boardmay be bent. In a state where the circuit boardis bent, one end of the circuit boardmay be disposed on the rear surface of the display paneland/or a rear surface of the heat dissipation layer. The other end of the circuit boardmay be connected to a plurality of first pads (PDin) of a first pad portion (PDAin) of the display panelby using a conductive adhesive material. One end of the circuit boardmay be an end opposite to the other end of the circuit board.

400 400 100 400 610 620 400 700 The timing control circuitmay receive digital video data and timing signals from the outside (or an external device or circuit). The timing control circuitmay generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panelbased on the timing signals. The timing control circuitmay output the scan timing control signal SCS to the scan driverand output the emission timing control signal ECS to the light emitting driver. The timing control circuitmay output the digital video data and the data timing control signal DCS to the data driver.

500 500 100 3 FIG. The power supply circuitmay generate a plurality of panel driving voltages based on a power voltage from the outside. In an embodiment, for example, the power supply circuitmay generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT and supply the generated driving voltages to the display panel. The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT will be described later in greater detail with reference to.

400 500 300 400 100 300 500 100 300 In an embodiment, each of the timing control circuitand the power supply circuitmay be formed as an integrated circuit (IC) and attached to one surface of the circuit board. In such an embodiment, the scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuitmay be supplied to the display panelthrough the circuit board. In an embodiment, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuitmay be supplied to the display panelthrough the circuit board.

400 500 100 610 620 700 400 500 400 500 700 1 7 FIG. 4 FIG. Alternatively, each of the timing control circuitand the power supply circuitmay be disposed in the non-display area NDA of the display panel, similarly to the scan driver, the light emitting driver, and the data driver. In such an embodiment, the timing control circuitmay include a plurality of timing transistors, and each of the power supply circuitsmay include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors may be formed through a semiconductor process and may be formed on a semiconductor substrate (SSUB in). In an embodiment, for example, the plurality of timing transistors and the plurality of power transistors may include or be formed of CMOS, but the embodiment of the present specification is not limited thereto. Each of the timing control circuitand the power supply circuitmay be disposed between the data driverand the first pad portion (PDAin).

3 FIG. 2 FIG. is an equivalent circuit diagram illustrating an example of a first sub-pixel illustrated in.

3 FIG. 1 1 2 1 Referring to, in an embodiment, the first sub-pixel SPmay be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emission control line ECL, the second emission control line ECL, and the data line DL. In addition, the first sub-pixel SPmay be connected to a first driving voltage line VSL to which the first driving voltage VSS corresponding to a low potential voltage is applied, a second driving voltage line VDL to which the second driving voltage VDD corresponding to a high potential voltage is applied, and a third driving voltage line VIL to which the third driving voltage VINT corresponding to an initialization voltage is applied.

1 1 6 1 2 The first sub-pixel SPincludes a plurality of transistors Tto T, a light emitting element LE, a first capacitor CP, and a second capacitor CP.

1 The light emitting element LE emits light corresponding to a driving current (Ids) flowing through a channel of a first transistor T. An amount of light emitted from the light emitting element LE may be proportional to the driving current (Ids). A first electrode of the light emitting element LE may be an anode electrode, and a second electrode of the light emitting element LE may be a cathode electrode. In an embodiment, the light emitting element LE may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer disposed between the first electrode and the second electrode, but the embodiment of the present specification is not limited thereto. In another embodiment, for example, the light emitting element LE may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode. In such an embodiment, the light emitting element LE may be a micro light emitting diode.

1 The first transistor Tmay be a driving transistor that controls a source-drain current (Ids, hereinafter, referred to as “driving current”) flowing between a source electrode and a drain electrode based on a voltage applied to a gate electrode.

2 1 2 1 1 A second transistor Tmay be connected between one electrode of the first capacitor CPand the data line DL. The second transistor Tis turned on by the write scan signal of the write scan line GWL and connects one electrode of the first capacitor CPto the data line DL. Accordingly, the data voltage of the data line DL may be applied to one electrode of the first capacitor CP.

3 1 2 3 1 2 1 1 A third transistor Tmay be connected between a first node Nand a second node N. The third transistor Tis turned on by the write control signal of the write control line GCL and connects the first node Nto the second node N. Accordingly, when the gate electrode and the source electrode of the first transistor Tare connected, the first transistor Tmay operate like a diode.

4 2 3 4 1 2 3 1 5 3 5 3 A fourth transistor Tmay be connected between the second node Nand a third node N. The fourth transistor Tis turned on by the first emission control signal of the first emission control line ECLand connects the second node Nto the third node N. Accordingly, the driving current of the first transistor Tmay be supplied to the light emitting element LE. A fifth transistor Tmay be connected between the third node Nand the third driving voltage line VIL. The fifth transistor Tis turned on by the bias scan signal of the bias scan line GBL and connects the third node Nto the third driving voltage line VIL. Accordingly, the third driving voltage VINT of the third driving voltage line VIL may be applied to the first electrode of the light emitting element LE.

6 1 6 2 1 1 A sixth transistor Tmay be connected between the source electrode of the first transistor Tand the second driving voltage line VDL. The sixth transistor Tis turned on by the second emission control signal of the second emission control line ECLand connects the source electrode of the first transistor Tto the second driving voltage line VDL. Accordingly, the second driving voltage VDD of the second driving voltage line VDL may be applied to the source electrode of the first transistor T.

1 1 2 2 1 The first capacitor CPis defined or formed between the first node Nand the drain electrode of the second transistor T. The second capacitor CPis defined or formed between the gate electrode of the first transistor Tand the second driving voltage line VDL.

1 6 1 6 1 6 1 6 Each of the first to sixth transistors Tto Tmay be a metal-oxide-semiconductor field effect transistor (MOSFET). In an embodiment, for example, each of the first to sixth transistors Tto Tmay be a p-type MOSFET, but the embodiment of the present specification is not limited thereto. Each of the first to sixth transistors Tto Tmay be an n-type MOSFET. Alternatively, each of some of the first to sixth transistors Tto Tmay be a p-type MOSFET, and each of the remaining transistors may be an n-type MOSFET.

3 FIG. 3 FIG. 1 1 6 1 2 1 3 1 illustrates an embodiment where the first sub-pixel SPincludes six transistors Tto Tand two capacitors CPand CP, but it should be noted that the equivalent circuit diagram of the first sub-pixel SPis not limited to that illustrated in FIG.. In an embodiment, for example, the number of transistors and capacitors of the first sub-pixel SPis not limited to that illustrated in.

2 3 1 2 3 3 FIG. In addition, an equivalent circuit diagram of a second sub-pixel SPand an equivalent circuit diagram of a third sub-pixel SPmay be substantially the same as the equivalent circuit diagram of the first sub-pixel SPdescribed with reference to. Therefore, any repetitive detailed descriptions of the equivalent circuit diagram of the second sub-pixel SPand the equivalent circuit diagram of the third sub-pixel SPwill be omitted in the present disclosure.

4 FIG. 1 FIG. is a schematic plan view illustrating an example of a display panel illustrated in.

4 FIG. 100 100 610 620 700 710 720 1 2 Referring to, the display area DAA of the display panelaccording to an embodiment includes a plurality of pixels PX arranged in a matrix form. The non-display area NDA of the display panelaccording to an embodiment includes a scan driver, a light emitting driver, a data driver, a first distribution circuit, a second distribution circuit, a first pad portion PDA, and a second pad portion PDA.

610 620 610 1 620 1 610 620 The scan drivermay be disposed on a first side of the display area DAA, and the light emitting drivermay be disposed on a second side of the display area DAA. In an embodiment, for example, the scan drivermay be disposed on one side of the display area DAA in the first direction DR, and the light emitting drivermay be disposed on the other side of the display area DAA in the first direction DR. However, the embodiment of the present specification is not limited thereto, and the scan driverand the light emitting drivermay be disposed on both the first side and the second side of the display area DAA.

1 1 300 1 1 2 1 700 2 The first pad portion PDAmay include a plurality of first pads PDconnected to pads or bumps of the circuit boardthrough a conductive adhesive member. The first pad portion PDAmay be disposed on a third side of the display area DAA. In an embodiment, for example, the first pad portion PDAmay be disposed on one side of the display area DAA in the second direction DR. The first pad portion PDAmay be disposed on the outside of the data driverin the second direction DR.

2 2 100 2 The second pad portion PDAmay include a plurality of second pads PDcorresponding to test pads for testing whether the display panelis normally operating. The plurality of second pads PDmay be connected to a jig or probe pin or to a test circuit board during the test process. The test circuit board may be a printed circuit board including or made of a rigid material or a flexible printed circuit board including or made of a flexible material.

2 2 2 2 720 2 The second pad portion PDAmay be disposed on a fourth side of the display area DAA. In an embodiment, for example, the second pad portion PDAmay be disposed on the other side of the display area DAA in the second direction DR. The second pad portion PDAmay be disposed on the outside of the second distribution circuitin the second direction DR.

710 1 710 1 1 1 710 100 710 2 The first distribution circuitdistributes data voltages applied through the first pad portion PDAto the plurality of data lines DL. In an embodiment, for example, the first distribution circuitmay distribute data voltages applied through one first pad PDof the first pad portion PDAto P data lines DL (P is a positive integer greater than or equal to 2), thereby reducing the number of first pads PD. The first distribution circuitmay be disposed on a third side of the display area DAA of the display panel. In an embodiment, for example, the first distribution circuitmay be disposed on one side of the display area DAA in the second direction DR.

720 2 610 620 2 720 720 100 720 2 The second distribution circuitdistributes signals applied through the second pad portion PDAto the scan driver, the light emitting driver, and the data lines DL. The second pad portion PDAand the second distribution circuitmay be components for testing the operation of each pixel PX of the display area DAA. The second distribution circuitmay be disposed on a fourth side of the display area DAA of the display panel. In an embodiment, for example, the second distribution circuitmay be disposed on the other side of the display area DAA in the second direction DR.

7 FIG. 7 FIG. 4 FIG. A cathode connection portion CCA may be an area where a second electrode (CAT in) of a display element layer (EML in) is connected to the first driving voltage line VSL of the non-display area NDA. The cathode connection portion CCA may be disposed outside at least one side of the display area DAA. In an embodiment, for example, the cathode connection portion CCA may be disposed outside at least one of the left, right, upper, and lower sides of the display area DAA. Alternatively, the cathode connection portion CCA may be disposed to surround the display area DAA as illustrated into minimize a deviation in the first driving voltage VSS due to a voltage drop (IR drop) or voltage rising (IR rising) of the second electrode CAT in the display area DAA.

5 FIG. 4 FIG. 6 FIG. 4 FIG. is a schematic enlarged plan view illustrating an example of a display area of.is a schematic enlarged plan view illustrating another example of the display area of.

5 6 FIGS.and 1 1 2 2 3 3 Referring to, each of the plurality of pixels PX includes a first light emitting area EA, which is a light emitting area of the first sub-pixel SP, a second light emitting area EA, which is a light emitting area of the second sub-pixel SP, and a third light emitting area EA, which is a light emitting area of the third sub-pixel SP.

1 2 3 1 2 3 5 6 FIGS.and The first light emitting area EA, the second light emitting area EA, and the third light emitting area EAmay have a quadrangular or hexagonal planar shape as illustrated in, but the embodiment of the present specification is not limited thereto. The first light emitting area EA, the second light emitting area EA, and the third light emitting area EAhave a planar shape other than the quadrangle or hexagon, such as a polygon, circle, ellipse, or irregular shape.

5 FIG. 1 2 1 1 3 1 2 3 2 1 2 3 In an embodiment, as illustrated in, in each of the plurality of pixels PX, the first light emitting area EAand the second light emitting area EAmay be adjacent to each other in the first direction DR. In addition, the first light emitting area EAand the third light emitting area EAmay be adjacent to each other in the first direction DR. In addition, the second light emitting area EAand the third light emitting area EAmay be adjacent to each other in the second direction DR. An area of the first light emitting area EA, an area of the second light emitting area EA, and an area of the third light emitting area EAmay be different from each other.

6 FIG. 1 2 3 4 1 3 1 2 4 2 1 2 1 2 3 2 1 4 2 3 4 1 1 1 2 1 2 2 1 Alternatively, as illustrated in, the light emitting areas EA, EA, EA, and EAmay have a hexagonal planar shape. In such an embodiment, the first light emitting area EAand the third light emitting area EAmay be adjacent to each other in the first direction DR, and the second light emitting area EAand a fourth light emitting area EAmay be adjacent to each other in the second direction DR. In addition, the first light emitting area EAand the second light emitting area EAmay be adjacent to each other in a first diagonal direction DD, and the second light emitting area EAand the third light emitting area EAmay be adjacent to each other in a second diagonal direction DD. In addition, the first light emitting area EAand the fourth light emitting area EAmay be adjacent to each other in the second diagonal direction DD, and the third light emitting area EAand the fourth light emitting area EAmay be adjacent to each other in the first diagonal direction DD. The first diagonal direction DD, which is a direction between the first direction DRand the second direction DR, may indicate a direction inclined by about 45 degrees compared to the first direction DRand the second direction DR, and the second diagonal direction DDmay be a direction perpendicular to the first diagonal direction DD.

1 2 3 The first sub-pixel SPmay emit first light, the second sub-pixel SPmay emit second light, and the third sub-pixel SPmay emit third light. Here, the first light may be light of a blue wavelength band, the second light may be light of a green wavelength band, and the third light may be light of a red wavelength band. In an embodiment, for example, the blue wavelength band may indicate that a main peak wavelength of light is included in a wavelength band of about 370 nanometers (nm) to about 460 nm, the green wavelength band may indicate that a main peak wavelength of light is included in a wavelength band of about 480 nm to about 560 nm, and the red wavelength band may indicate that a main peak wavelength of light is included in a wavelength band of about 600 nm to about 750 nm.

1 2 3 1 2 3 4 4 2 5 FIG. 6 FIG. Each of the plurality of pixels PX may include three light emitting areas EA, EA, and EAas illustrated inor may include four light emitting areas EA, EA, EA, and EAas illustrated in. In such an embodiment, the fourth light emitting area EAmay emit a same second light as the second light emitting area EA, but the embodiment of the present specification is not limited thereto.

1 1 2 3 4 6 FIG. The light emitting areas of the plurality of pixels PX may be disposed in a stripe structure in which the light-emitting areas are arranged in the first direction DR, a PenTile® structure in which the light emitting areas EA, EA, EA, and EAare arranged in a rhombus shape as illustrated in, or a hexagonal structure in which the light emitting regions are arranged in a hexagonal shape.

7 FIG. 5 FIG. 1 1 is a schematic cross-sectional view illustrating an example of the display panel taken along line I-I′ of.

7 FIG. 100 Referring to, an embodiment of the display panelincludes a semiconductor backplane SBP, a light emitting element backplane EBP, a display element layer EML, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL, and a polarizing plate POL.

1 6 4 FIG. The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR, respectively. The plurality of pixel transistors PTR may correspond to the first to sixth transistors Tto Tdescribed with reference to.

The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB may be a substrate doped with first-type impurities. A plurality of well areas WA may be disposed on an upper surface of the semiconductor substrate SSUB. The plurality of well areas WA may be areas doped with second-type impurities. The second-type impurity may be different from the first-type impurity described above. In an embodiment, for example, where the first-type impurity is a p-type impurity, the second-type impurity may be an n-type impurity. In another embodiment, where the first-type impurity is an n-type impurity, the second-type impurity may be a p-type impurity.

Each of the plurality of well areas WA includes a source area SA corresponding to a source electrode of the pixel transistor PTR, a drain area DA corresponding to a drain electrode thereof, and a channel area CH disposed between the source area SA and the drain area DA.

A lower insulating film BINS may be disposed between the gate electrode GE and the well area WA. A side insulating film SINS may be disposed on a side surface of the gate electrode GE. The side insulating film SINS may be disposed on the lower insulating film BINS.

3 3 Each of the source area SA and the drain area DA may be an area doped with first-type impurities. A gate electrode GE of the pixel transistor PTR may overlap the well area WA in the third direction DR, which is a thickness direction of the semiconductor substrate SSUB. The channel area CH may overlap the gate electrode GE in the third direction DR. The source area SA may be disposed on one side of the gate electrode GE, and the drain area DA may be disposed on the other side of the gate electrode GE.

1 2 1 2 1 2 Each of the plurality of well areas WA further includes a first low-concentration impurity area LDDdisposed between the channel area CH and the source area SA and a second low-concentration impurity area LDDdisposed between the channel area CH and the drain area DA. The first low-concentration impurity area LDDmay be an area having an impurity concentration lower than that of the source area SA due to the lower insulating film BINS. The second low-concentration impurity area LDDmay be an area having an impurity concentration lower than that of the drain area DA due to the lower insulating film BINS. A distance between the source area SA and the drain area DA may be increased by the first low-concentration impurity area LDDand the second low-concentration impurity area LDD, which may increase a length of the channel area CH of each pixel transistor PTR.

1 2 1 A first semiconductor insulating film SINSmay be disposed on the semiconductor substrate SSUB. A semiconductor insulating film SINSmay be disposed on the first semiconductor insulating film SINS.

2 1 2 A plurality of contact terminals CTE may be disposed on the second semiconductor insulating film SINS. Each of the plurality of contact terminals CTE may be connected to a corresponding one of the gate electrode GE, the source area SA, and the drain area DA of each of the plurality of pixel transistors PTR through a hole defined through the first semiconductor insulating film SINSand the second semiconductor insulating film SINS. The plurality of contact terminals CTE may include or be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one thereof.

3 3 A third semiconductor insulating film SINSmay be disposed on a side surface of each of the plurality of contact terminals CTE. An upper surface of each of the plurality of contact terminals CTE may be exposed without being covered by the third semiconductor insulating film SINS.

1 2 3 Each of the first semiconductor insulating film SINS, the second semiconductor insulating film SINS, and the third semiconductor insulating film SINSmay be formed of (or defined by) an inorganic film including at least one selected from silicon nitride carbon (SiCN) or silicon oxide (SiOx), but the embodiment of the present specification is not limited thereto.

In an embodiment, the semiconductor substrate SSUB may be replaced with a glass substrate or a polymer resin substrate such as polyimide. In such an embodiment, thin film transistors may be disposed on the glass substrate or the polymer resin substrate. The glass substrate may be a rigid substrate that is not bent, and the polymer resin substrate may be a flexible substrate that may be bent or curved.

1 8 1 9 1 11 1 9 1 8 The light emitting element backplane EBP includes a plurality of conductive layers MLto ML, a plurality of vias VAto VA, and a plurality of insulating films INSto INS. In addition, the light emitting element backplane EBP includes a plurality of insulating films INSto INSdisposed between the first to eighth conductive layers MLto ML.

1 8 1 8 1 8 1 4 FIG. The first to eighth insulating films INSto INSserve to insulate the first to eighth conductive layers MLto ML. The first to eighth conductive layers MLto MLserve to implement the circuit of the first sub-pixel SPillustrated inby connecting the plurality of contact terminals CTE exposed from the semiconductor backplane SBP.

1 6 1 6 1 2 1 8 4 5 1 8 In an embodiment, for example, only the first to sixth transistors Tto Tare formed on the semiconductor backplane SBP, and the first to sixth transistors Tto Tand the first and second capacitors Cand Care connected through the first to eighth conductive layers MLto ML. In addition, the drain area corresponding to the drain electrode of the fourth transistor T, the source area corresponding to the source electrode of the fifth transistor T, and the first electrode AND of the light emitting element LE are also connected through the first to eighth conductive layers MLto ML.

1 8 1 8 1 8 1 8 1 8 1 8 x The first to eighth conductive layers MLto MLand the first to eighth vias VAto VAmay be formed of substantially a same material as each other. The first to eighth conductive layers MLto MLand the first to eighth vias VAto VAmay include or be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one thereof. The first to eighth vias VAto VAmay be formed of substantially a same material as each other. The first to eighth insulating films INSto INSmay be formed of an inorganic film including silicon oxide (SiO), but the embodiment of the present specification is not limited thereto.

9 8 8 9 x A ninth insulating film INSmay be disposed on the eighth insulating film INSand the eighth conductive layer ML. The ninth insulating film INSmay be formed of an inorganic film including silicon oxide (SiO), but the embodiment of the present specification is not limited thereto.

9 8 9 9 Each of the ninth vias VAmay be connected to the eighth conductive layer MLexposed by penetrating or extending through the ninth insulating film INS. The ninth vias VAmay include or be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one thereof.

10 11 The display element layer EML may be disposed on the light emitting element backplane EBP. The display element layer EML may include tenth and eleventh insulating films INSand INS, a reflective electrode RL, first electrodes AND, a light emitting stack IL, a second electrode CAT, a pixel defining film PDL, and a plurality of trenches TRC.

9 1 2 3 1 2 3 7 FIG. The reflective electrode RL may be disposed on the ninth insulating film INS. The reflective electrode RL may include at least one or more reflective electrodes RL, RL, RL, and RLA. In an embodiment, for example, the reflective electrode RL may include first to fourth reflective electrodes RL, RL, RL, and RLA as illustrated in.

1 9 9 2 1 3 2 4 3 The first reflective electrodes RLmay be disposed on the ninth insulating film INSand may be connected to the ninth via VA. Each of second reflective electrodes RLmay be disposed on the first reflective electrode RLcorresponding thereto. Each of third reflective electrodes RLmay be disposed on the second reflective electrode RLcorresponding thereto. Each of fourth reflective electrodes RLmay be disposed on the third reflective electrode RLcorresponding thereto.

2 2 1 3 4 Since the second reflective electrode RLmay be an electrode that substantially reflects light from the light emitting elements, a thickness of the second reflective electrode RLmay be greater than a thickness of the first reflective electrode RL, a thickness of the third reflective electrode RL, and a thickness of the fourth reflective electrode RL.

1 1 2 3 4 The first reflective electrodes RLmay include or be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one thereof. In an embodiment, for example, the first reflective electrodes RLmay include titanium nitride (TiN), the second reflective electrodes RLmay include aluminum (Al), the third reflective electrodes RLmay include titanium nitride (TiN), and the fourth reflective electrodes RLmay include titanium (Ti).

10 9 10 10 11 10 A tenth interlayer insulating film INSmay be disposed on the ninth interlayer insulating film INS. The tenth interlayer insulating film INSmay be disposed between the reflective electrodes RL adjacent to each other. The tenth interlayer insulating film INSmay be a film for planarizing a level difference caused by the reflective electrodes RL. The eleventh interlayer insulating film INSmay be disposed on the tenth interlayer insulating film INSand the reflective electrode RL.

10 11 The tenth interlayer insulating film INSand the eleventh interlayer insulating film INSmay be formed of or defined by an inorganic film including silicon oxide (SiOx), but the embodiment of the present specification is not limited thereto.

11 1 2 3 11 1 2 3 1 2 3 11 1 2 3 The eleventh interlayer insulating film INSmay be an optical auxiliary layer for adjusting a resonance distance of light emitted from the light emitting stack IL in at least one sub-pixel of the first sub-pixel SP, the second sub-pixel SP, and the third sub-pixel SP. A thickness of the eleventh interlayer insulating film INSin the first sub-pixel SP, the second sub-pixel SP, and the third sub-pixel SPmay be different from each other. That is, in order to adjust a distance from the reflective electrode RL to the second electrode CAT according to a main wavelength of light emitted from each of the first sub-pixel SP, the second sub-pixel SP, and the third sub-pixel SP, the thickness of the eleventh interlayer insulating film INSmay be set in each of the first sub-pixel SP, the second sub-pixel SP, and the third sub-pixel SP.

7 FIG. 11 1 11 2 11 2 11 3 1 2 2 3 In an embodiment, for example, as illustrated in, the thickness of the eleventh interlayer insulating film INSin the first sub-pixel SPmay be greater than the thickness of the eleventh interlayer insulating film INSin the second sub-pixel SP, and the thickness of the eleventh interlayer insulating film INSin the second sub-pixel SPmay be greater than the thickness of the eleventh interlayer insulating film INSin the third sub-pixel SP. In such an embodiment, a distance between the first electrode AND and the reflective electrode RL in the first sub-pixel SPmay be greater than a distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SP. In addition, the distance between the first electrode AND and the reflective electrode RL in the second sub-pixel SPmay be greater than a distance between the first electrode AND and the reflective electrode RL in the third sub-pixel SP.

10 4 11 10 10 1 10 2 10 2 10 3 Each of the tenth vias VAmay be connected to the fourth reflective electrodes RLexposed by penetrating or extending through the eleventh interlayer insulating film INS. The tenth vias VAmay include or be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one thereof. A thickness of the tenth via VAin the first sub-pixel SPmay be greater than a thickness of the tenth via VAin the second sub-pixel SP, and the thickness of the tenth via VAin the second sub-pixel SPmay be greater than a thickness of the tenth via VAin the third sub-pixel SP.

11 10 10 1 9 1 8 The first electrode AND of each of the light emitting elements LE may be disposed on the eleventh interlayer insulating film INSand may be connected to the tenth via VA. The first electrode AND of each of the light emitting elements LE may be connected to the drain area DA or the source area SA of the pixel transistor PTR through the tenth via VA, the reflective electrode RL, the first to ninth vias VAto VA, the first to eighth conductive layers MLto ML, and the contact terminal CTE. The first electrode AND of each of the light emitting elements LE may include or be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one thereof. In an embodiment, for example, the first electrode AND of each of the light emitting elements LE may be formed of titanium nitride (TiN).

1 2 3 1 2 3 The pixel defining film PDL may be disposed on a partial area of the first electrode AND of each of the light emitting elements LE. The pixel defining film PDL may cover an edge of the first electrode AND of each of the light emitting elements LE. The pixel defining film PDL may partition the first light emitting areas EA, the second light emitting areas EA, and the third light emitting areas EA. Each of the first light emitting area EA, the second light emitting area EA, and the third light emitting area EAmay be an area in which the light emitting element LE including the first electrode AND, the light emitting stack IL, and the second electrode CAT is disposed.

1 1 2 2 3 3 The first light emitting area EAmay be defined as an area in which the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SPto emit light. The second light emitting area EAmay be defined as an area in which the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SPto emit light. The third light emitting area EAmay be defined as an area in which the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SPto emit light.

1 2 3 1 2 1 3 2 1 2 3 1 3 2 1 2 3 x x x The pixel defining film PDL may include first to third pixel defining films PDL, PDL, and PDL. The first pixel defining film PDLmay be disposed on the edge of the first electrode AND of each of the light emitting elements LE, the second pixel defining film PDLmay be disposed on the first pixel defining film PDL, and the third pixel defining film PDLmay be disposed on the second pixel defining film PDL. The first pixel defining film PDL, the second pixel defining film PDL, and the third pixel defining film PDLmay be formed of an inorganic film including silicon oxide (SiO). Alternatively, the first pixel defining film PDLand the third pixel defining film PDLare formed of an inorganic film including silicon nitride (SiN), while the second pixel defining film PDLmay be formed of an inorganic film including silicon oxide (SiO). Each of a thickness of the first pixel defining film PDL, a thickness of the second pixel defining film PDL, and a thickness of the third pixel defining film PDLmay be about 500 angstrom (Å).

1 1 2 3 In order to effectively prevent the first encapsulation inorganic film TFEfrom being disconnected due to the step coverage, the first pixel defining film PDL, the second pixel defining film PDL, and the third pixel defining film PDLmay have a cross-sectional structure with a step-shaped level difference. The step coverage refers to a ratio of the extent to which a thin film is applied to an inclined portion relative to the extent to which a thin film is applied to a flat portion. As the step coverage is low, the possibility of the thin film disconnected at the inclined portion may increase.

1 2 3 11 Each of the plurality of trenches TRC may be defined through the first pixel defining film PDL, the second pixel defining film PDL, and the third pixel defining film PDL. In each of the plurality of trenches TRC, at least a portion of the eleventh interlayer insulating film INSmay have a recessed shape.

1 2 3 1 2 3 7 FIG. At least one trench TRC may be disposed between the sub-pixels SP, SP, and SPadjacent to each other.illustrates an embodiment where two trenches TRC are disposed between the sub-pixels SP, SP, and SPadjacent to each other, but the embodiment of the present specification is not limited thereto.

1 2 3 1 2 3 7 FIG. 8 FIG. The light emitting stack IL may include a plurality of stack layers IL, IL, and IL.illustrates an embodiment where the light emitting stack IL has a three-tandem structure including a first stack layer IL, a second stack layer IL, and a third stack layer IL, but the embodiment of present specification is not limited thereto. In another embodiment, for example, the light emitting stack IL may have a two-tandem structure including two stack layers as illustrated in.

1 2 3 1 2 3 1 2 3 In the three-tandem structure, the light emitting stack IL may have a tandem structure including a plurality of stack layers IL, IL, and ILthat emit different lights, respectively. In an embodiment, for example, the light emitting stack IL may include a first stack layer ILthat emits light of a first color, a second stack layer ILthat emits light of a second color, and a third stack layer ILthat emits light of a third color. The first stack layer IL, the second stack layer IL, and the third stack layer ILmay be sequentially stacked.

1 2 3 The first stack layer ILmay have a structure in which a first hole transporting layer, a first light emitting layer emitting first light, and a first electron transporting layer are sequentially stacked. The second stack layer ILmay have a structure in which a second hole transporting layer, a second light emitting layer emitting second light, and a second electron transporting layer are sequentially stacked. The third stack layer ILmay have a structure in which a third hole transporting layer, a third organic light emitting layer emitting third light, and a third electron transporting layer are sequentially stacked.

2 1 1 2 1 2 A first charge generation layer for supplying charges to the second stack layer ILand supplying electrons to the first stack layer ILmay be disposed between the first stack layer ILand the second stack layer IL. The first charge generation layer may include an n-type charge generation layer that supplies electrons to the first stack layer ILand a p-type charge generation layer that supplies holes to the second stack layer IL. The n-type charge generation layer may include a dopant of a metallic material.

3 2 2 3 2 3 A second charge generation layer for supplying charges to the third stack layer ILand supplying electrons to the second stack layer ILmay be disposed between the second stack layer ILand the third stack layer IL. The second charge generation layer may include an n-type charge generation layer that supplies electrons to the second stack layer ILand a p-type charge generation layer that supplies holes to the third stack layer IL.

1 1 1 1 2 3 2 1 2 1 2 3 2 3 2 3 2 The first stack layer ILmay be disposed on the first electrodes AND and the pixel defining film PDL, and in each of the trenches TRC, a residual film RIL disposed on a bottom surface of the trench TRC may include a same material as the first stack layer IL. Due to the trench TRC, the first stack layer ILmay be disconnected between the sub-pixels SP, SP, and SPadjacent to each other. The second stack layer ILmay be disposed on the first stack layer IL. Due to the trench TRC, the second stack layer ILmay be disconnected between the sub-pixels SP, SP, and SPadjacent to each other. A cavity ESS or empty space may be disposed between the residual film RIL and the second stack layer ILin the trench TRC. The third stack layer ILmay be disposed on the second stack layer IL. The third stack layer ILmay not be disconnected by the trench TRC and may be disposed to cover the second stack layer ILin each of the trenches TRC.

1 2 3 1 2 3 In the three-tandem structure, each of the plurality of trenches TRC may be a structure for disconnecting the first to third hole transporting layers, the first charge generation layer, and the second charge generation layer of the first to third stack layers IL, IL, and ILof the display element layer EML between the sub-pixels SP, SP, and SPadjacent to each other. In addition, in the two-tandem structure, each of the plurality of trenches TRC may be a structure for disconnecting the charge generation layer disposed between a lower stack layer and an upper stack layer and the lower stack layer.

1 2 1 2 3 3 3 1 2 3 In order to stably disconnect the first and second stack layers ILand ILof the display element layer EML between the sub-pixels SP, SP, and SPadjacent to each other, a height of each of the plurality of trenches TRC may be greater than a height of the pixel defining film PDL. The height of each of the plurality of trenches TRC indicates a length of each of the plurality of trenches TRC in the third direction DR. The height of the pixel defining film PDL indicates a length of the pixel defining film PDL in the third direction DR. In order to disconnect the hole transporting layers and the charge generation layers of the light emitting stack IL of the display element layer EML between the sub-pixels SP, SP, and SPadjacent to each other, other structures may be present instead of the trench TRC. In an embodiment, for example, instead of the trench TRC, a partition wall having a reverse tapered shape may be disposed on the pixel defining film PDL.

7 FIG. 1 2 3 1 1 2 3 2 1 3 3 1 2 1 2 3 In addition,illustrates an embodiment where the light emitting stack IL that emits light is disposed in all of the first light emitting area EA, the second light emitting area EA, and the third light emitting area EA, but the embodiment of the present specification is not limited thereto. In another embodiment, for example, instead of the light emitting stack IL, the first light emitting stack ILmay be disposed in the first light emitting area EAand may not be disposed in the second light emitting area EAand the third light emitting area EA. In addition, the second light emitting layer may be disposed in the second light emitting area EAand may not be disposed in the first light emitting area EAand the third light emitting area EA. In addition, the third light emitting layer may be disposed in the third light emitting area EAand may not be disposed in the first light emitting area EAand the second light emitting area EA. In this case, first to third color filters CF, CF, and CFof the optical layer OPL may be omitted.

3 1 2 3 The second electrode CAT may be disposed on the light emitting stack IL. The second electrode CAT may be disposed on the third stack layer ILin each of the plurality of trenches TRC. The second electrode CAT may include or be formed of a transparent conductive material (TCO) such as ITO or IZO capable of transmitting light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). In an embodiment where the second electrode CAT is formed of a semi-transmissive conductive material, light emission efficiency may be increased in each of the first to third sub-pixels SP, SP, and SPby micro cavities.

1 3 1 3 1 1 3 The encapsulation layer TFE may be disposed on the display element layer EML. The encapsulation layer TFE may include one or more inorganic films TFEand TFEto prevent oxygen or moisture from permeating into the display element layer EML. In an embodiment, for example, a first encapsulation inorganic film TFEmay be disposed on the second electrode CAT, and a second encapsulation inorganic film TFEmay be disposed on the first encapsulation inorganic film TFE. The first encapsulation inorganic film TFEand the second encapsulation inorganic film TFEmay be formed as or defined by multi-films in which one or more inorganic films of a silicon nitride layer (SiNx), a silicon oxynitride layer (SiON), a silicon oxide layer (SiOx), a titanium oxide layer (TiOx), and an aluminum oxide layer (AlOx) are alternately stacked.

2 2 1 3 2 2 In addition, the encapsulation layer TFE may include at least one organic film TFEto protect the display element layer EML from foreign substances such as dust. In an embodiment, for example, the encapsulation organic film TFEmay be disposed between the first encapsulation inorganic film TFEand the second encapsulation inorganic film TFE. The encapsulation organic film TFEmay be a monomer. Alternatively, the encapsulation organic film TFEmay be an organic film made of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

An adhesive layer ADL may be a layer for adhering the encapsulation layer TFE and the optical layer OPL. The adhesive layer ADL may be a double-sided adhesive member. In addition, the adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive or a transparent adhesive resin.

1 2 3 1 2 3 1 2 3 1 2 3 The optical layer OPL includes a plurality of color filters CF, CF, and CF, a plurality of lenses LNS, and a filling layer FIL. The plurality of color filters CF, CF, and CFmay include first to third color filters CF, CF, and CF. The first to third color filters CF, CF, and CFmay be disposed on the adhesive layer ADL.

1 1 1 1 1 1 The first color filter CFmay overlap the first light emitting area EAof the first sub-pixel SP. The first color filter CFmay transmit light of a first color, that is, light in a blue wavelength band. The red wavelength band may be about 370 nm to about 460 nm. Therefore, the first color filter CFmay transmit light of a first color among light emitted from the first light emitting area EA.

2 2 2 2 2 2 The second color filter CFmay overlap the second light emitting area EAof the second sub-pixel SP. The second color filter CFmay transmit light of a second color, that is, light in a green wavelength band. The green wavelength band may be about 480 nm to about 560 nm. Therefore, the second color filter CFmay transmit light of a second color among light emitted from the second light emitting area EA.

3 3 3 3 3 3 The third color filter CFmay overlap the third light emitting area EAof the third sub-pixel SP. The third color filter CFmay transmit light of a third color, that is, light in a red wavelength band. The red wavelength band may be about 600 nm to about 750 nm. Therefore, the third color filter CFmay transmit light of a third color among light emitted from the third light emitting area EA.

1 2 3 10 Each of the plurality of lenses LNS may be disposed on each of the first color filter CF, the second color filter CF, and the third color filter CF. Each of the plurality of lenses LNS may be a structure for increasing a ratio of light directed to the front of the display device. Each of the plurality of lenses LNS may have a cross-sectional shape that is convex in an upward direction.

3 The filling layer FIL may be disposed on the plurality of lenses LNS. The filling layer FIL may have a predetermined refractive index so that light travels in the third direction DRat an interface between the plurality of lenses LNS and the filling layer FIL. In addition, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic film including or made of an acryl resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

The cover layer CVL may be disposed on the filling layer FIL. The cover layer CVL may be a glass substrate or a polymer resin such as resin. In an embodiment where the cover layer CVL is a glass substrate, the cover layer CVL may be attached onto the filling layer FIL. In this case, the filling layer FIL may serve to adhere the cover layer CVL. In an embodiment where the cover layer CVL is a glass substrate, the cover layer CVL may serve as an encapsulation substrate. When the cover layer CVL is a polymer resin such as resin, the cover layer CVL may be directly applied on the filling layer FIL.

1 2 3 The polarizing plate may be disposed on one surface of the cover layer CVL. The polarizing plate may be a structure for preventing deterioration in visibility due to reflection of external light. The polarizing plate may include a linear polarizing plate and a phase retardation film. In an embodiment, for example, the phase retardation film may be a λ/4 (quarter-wave) plate, but the embodiment of the present specification is not limited thereto. However, when deterioration in visibility due to reflection of external light is sufficiently improved by the first to third color filters CF, CF, and CF, the polarizing plate may also be omitted.

8 FIG. 5 FIG. 1 1 is a schematic cross-sectional view illustrating another example of the display panel taken along line I-I′ of.

8 FIG. 7 FIG. 8 FIG. 7 FIG. 8 FIG. 7 FIG. 8 3 4 The embodiment ofis substantially the same as the embodiment ofexcept that the first electrode AND of each of the light emitting elements LE is electrically connected by being in contact with a side surface of a connection electrode ANC connected to the eighth conductive layer ML. In addition, the embodiment ofis substantially the same as the embodiment ofexcept that the trench TRC is omitted, and instead, a third pixel defining film PDLand a fourth pixel defining film PDLhave a cross-sectional structure in a shape of an caves or a mushroom shape. In description of the embodiment of, any repetitive detailed description of the same or like element as those of the embodiment ofdescribed above will be omitted.

8 FIG. 1 9 1 9 Referring to, a plurality of connection electrodes ANC may be respectively disposed on first portions AAof the ninth insulating film INS. Each of the plurality of connection electrodes ANC may be disposed on the first portion AAof the ninth insulating film INScorresponding thereto. The plurality of connection electrodes ANC may include or be formed of an alloy including at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or transparent conductive oxide. For example, the plurality of connection electrodes ANC may include titanium (Ti), titanium nitride (TiN), indium tin oxide (ITO), or indium zinc oxide (IZO), but the embodiment of the present specification is not limited thereto.

A plurality of reflective electrodes RL may be respectively disposed on the plurality of connection electrodes ANC. Each of the plurality of reflective electrodes RL may be disposed on the connection electrode ANC corresponding thereto. The plurality of reflective electrodes RL may include or be formed at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one thereof. In an embodiment, for example, each of the plurality of reflective electrodes RL may include aluminum (Al) having high reflectivity.

x A plurality of optical auxiliary films OAL may be respectively disposed on the plurality of reflective electrodes RL. Each of plurality of optical auxiliary films OAL may be disposed on the reflective electrode RL corresponding thereto. The plurality of optical auxiliary films OAL may be formed of an inorganic film including silicon oxide (SiO), but the embodiment of the present specification is not limited thereto.

1 3 2 1 2 3 A step layer STPL may be disposed on the reflective electrode RL in each of the first light emitting area EAand the third light emitting area EA, and the optical auxiliary film OAL may be disposed on the step layer STPL. In the second light emitting area EA, only the optical auxiliary film OAL may be disposed on the reflective electrode RL. The thicknesses of the optical auxiliary film OAL in the first light emitting area EA, the second light emitting area EA, and the third light emitting area EAmay be substantially the same.

1 3 2 1 2 Due to the step layer STPL, a distance between the reflective electrode RL and the first electrode AND in the first light emitting area EAand the third light emitting area EAmay be greater than a distance between the reflective electrode RL and the first electrode AND in the second light emitting area EA. The thickness of the step layer STPL and the thickness of the optical auxiliary film OAL may be set by considering the wavelength and resonance distance of light emitted from the first stack layer ILof the light emitting stack IL and the wavelength and resonance distance of light emitted from the second stack layer ILthereof.

Each of the light emitting elements LE may include a first electrode AND, a light emitting stack IL, and a second electrode CAT.

The first electrode AND of each of the light emitting elements LE may be disposed on the optical auxiliary film OAL corresponding thereto. Since the connection electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL are sequentially stacked, the first electrode AND of each of the light emitting elements LE may be disposed on upper and side surfaces of the optical auxiliary film OAL, a side surface of the reflective electrode RL, and a side surface of the connection electrode ANC. As a result, the first electrode AND of each of the light emitting elements LE may be electrically connected by being in contact with the side surface of the reflective electrode RL and the side surface of the connection electrode ANC. Therefore, since the mask process may be reduced compared to when the first electrode AND of each of the light emitting elements LE is connected to the exposed reflective electrode RL through a through hole defined through the optical auxiliary film OAL, manufacturing costs may be reduced and manufacturing efficiency may be increased.

1 9 1 8 The first electrode AND of each of the light emitting elements LE may be connected to the drain area DA or the source area SA of the pixel transistor PTR through the connection electrode ANC, the first to ninth vias VAto VA, the first to eighth conductive layers MLto ML, and the contact terminal CTE.

9 1 3 2 3 1 2 9 The ninth insulating film INSmay include a first portion AAthat overlaps the connection electrode ANC in the third direction DRand a second portion AAthat does not overlap the connection electrode ANC in the third direction DR. A thickness of the first portion AAand a thickness of the second portion AAof the ninth insulating film INSmay be substantially the same as each other.

1 9 2 1 9 1 9 Alternatively, the thickness of the first portion AAof the ninth insulating film INSmay be greater than the thickness of the second portion AA. In such an embodiment, a side surface of the first portion AAof the ninth insulating film INSmay be exposed, and the first electrode AND of each of the light emitting elements LE may be disposed on the exposed side surface of the first portion AAof the ninth insulating film INS.

The first electrode AND of each of the light emitting elements LE may include or be formed of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one thereof, or a transparent conductive oxide. For example, the first electrode AND of each of light emitting elements LE may include titanium nitride (TiN), indium tin oxide (ITO), or indium zinc oxide (IZO), but the embodiment of the present specification is not limited thereto.

1 2 3 The pixel defining film PDL may be disposed on a partial area of the first electrode AND of each of the light emitting elements LE. The pixel defining film PDL may cover an edge of the first electrode AND of each of the light emitting elements LE. The pixel defining film PDL may partition the first light emitting areas EA, the second light emitting areas EA, and the third light emitting areas EA.

1 2 3 4 The pixel defining film PDL may include first to fourth pixel defining films PDL, PDL, PDL, and PDL.

1 1 1 1 2 9 The first pixel defining film PDLmay be disposed on the first electrode AND of each of the light emitting elements LE. Specifically, the first pixel defining film PDLmay cover a portion of an upper surface of the first electrode AND disposed on the optical auxiliary film OAL. In addition, the first pixel defining film PDLmay cover the first electrode AND disposed on the side surface of the connection electrode ANC, the side surface of the reflective electrode RL, and the side surface of the optical auxiliary film OAL. The first pixel defining film PDLmay be disposed on an upper surface of the second portion AAof the ninth insulating film INS.

A planarization film PNS is a film for planarizing the steps caused by the connection electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL.

1 1 2 9 The planarization film PNS may be disposed on the first pixel defining film PDLthat covers the first electrode AND disposed on the side surface of the connection electrode ANC, the side surface of the reflective electrode RL, and the side surface of the optical auxiliary film OAL. The planarization film PNS may be disposed on the first pixel defining film PDLdisposed on the second portion AAof the ninth insulating film INS.

1 2 1 2 1 2 The planarization film PNS may be disposed between the connection electrodes ANC adjacent to each other in the first direction DRor the second direction DR. The planarization film PNS may be disposed between the reflective electrodes RL adjacent to each other in the first direction DRor the second direction DR. The planarization film PNS may be disposed between the optical auxiliary films OAL adjacent to each other in the first direction DRor the second direction DR.

2 1 3 2 1 3 1 2 While there is no step layer STPL in the second light emitting area EA, there is a step layer STPL in each of the first light emitting area EAand the third light emitting area EA. As a result, the height of the connection electrode ANC, the reflective electrode RL, and the optical auxiliary film OAL in the second light emitting area EAmay be smaller than the height of the connection electrode ANC, the reflective electrode RL, the step layer STPL, and the optical auxiliary film OAL in each of the first light emitting area EAand the third light emitting area EA. Therefore, the planarization film PNS may cover the upper surface of the first pixel defining film PDLdisposed on the upper surface of the first electrode AND disposed in the second light emitting area EA.

1 3 1 1 3 In comparison, an upper surface of the planarization film PNS may be flatly connected to the upper surface of the first electrode AND disposed in the first light emitting area EAand the third light emitting area EA. That is, the planarization film PNS may not cover the upper surface of the first pixel defining film PDLdisposed on the upper surface of the first electrode AND disposed in each of the first light emitting area EAand the third light emitting area EA.

2 1 3 2 4 3 1 3 2 4 1 1 The second pixel defining film PDLmay be disposed on the first pixel defining film PDLand the planarization film PNS, the third pixel defining film PDLmay be disposed on the second pixel defining film PDL, and the fourth pixel defining film PDLmay be disposed on the third pixel defining film PDL. The first pixel defining film PDLand the third pixel defining film PDLare formed of an inorganic film o including f silicon nitride (SiNx), while the second pixel defining film PDL, the fourth pixel defining film PDL, and the planarization film PNS may be formed of an inorganic film including silicon oxide (SiOx). As the first pixel defining film PDLis formed of a different material from the planarization film PNS, the first pixel defining film PDLmay serve as a stopper in a process of chemically and mechanically polishing the planarization film PNS.

2 2 When the planarization film PNS and the second pixel defining film PDLare identically formed of an inorganic film including silicon oxide (SiOx), the planarization film PNS and the second pixel defining film PDLmay be formed as a single film.

3 4 4 3 3 4 Since a length of the third pixel defining film PDLin one direction is smaller than a length of the fourth pixel defining film PDLin one direction, a lower surface of the fourth pixel defining film PDLmay be exposed without being covered by the third pixel defining film PDL. That is, the third pixel defining film PDLand the fourth pixel defining film PDLmay have a cross-sectional structure in a shape of an caves or a mushroom shape.

1 2 1 2 1 2 The light emitting stack IL may be disposed on the first electrodes AND and the pixel defining film PDL. The light emitting stack IL may include a first stack layer ILand a second stack layer ILthat emit different lights. When the light emitting stack IL has a two-tandem structure, one of the first stack layer ILand the second stack layer ILmay emit light including a wavelength range of one of the first light, the second light, and the third light, and the other thereof may emit light that includes the wavelength ranges of the other two lights. For example, the first stack layer ILmay emit light that includes a wavelength range of the first light and a wavelength range of the third light, and the second stack layer ILmay emit light that includes a wavelength range of the second light. Here, the first light may be light of a blue wavelength band, the second light may be light of a green wavelength band, and the third light may be light of a red wavelength band.

2 1 1 2 1 2 A charge generation layer for supplying charges to the second stack layer ILand supplying electrons to the first stack layer ILmay be disposed between the first stack layer ILand the second stack layer IL. The charge generation layer may include an n-type charge generation layer that supplies electrons to the first stack layer ILand a p-type charge generation layer that supplies holes to the second stack layer IL. The n-type charge generation layer may include a dopant of a metallic material.

1 4 3 1 3 4 1 1 2 2 2 2 1 2 3 1 2 1 2 3 8 FIG. Since the first stack layer ILis not formed on the exposed lower surface of the fourth pixel defining film PDLthat is not covered by the third pixel defining film PDL, the first stack layer ILmay be disconnected by the cross-sectional structure in the shape of an eaves or the mushroom shape by the third pixel defining film PDLand the fourth pixel defining film PDL. In this case, the first hole transporting layer of the first stack layer ILand the charge generation layer CGL disposed between the first stack layer ILand the second stack layer ILmay also be disconnected. In addition,illustrates an embodiment where the second stack layer ILis connected without being disconnected, but the second hole transporting layer of the second stack layer ILmay be disconnected, and the second electron transporting layer of the second stack layer ILmay be connected without being disconnected. Therefore, it is possible to effectively prevent leakage current from flowing between the light emitting areas EA, EA, and EAadjacent to each other through the first hole transporting layer of the first stack layer IL, the second hole transporting layer of the second stack layer IL, and the charge generation layer CGL. Therefore, it is possible to effectively prevent the light emitting stacks IL in the light emitting areas EA, EA, and EAadjacent to each other from being affected by the current and emitting light other than the originally intended light.

8 FIG. 7 FIG. 7 FIG. 1 2 3 1 2 2 3 1 2 3 9 illustrates an embodiment having the two-tandem structure in which the light emitting stack IL includes two stack layers ILand IL, but the embodiment of the present specification is not limited thereto. For example, the light emitting stack IL may have a three-tandem structure including three stack layers as illustrated in. In such an embodiment, by adjusting the height of the third pixel defining film PDL, the charge generation layer between the first stack layer ILand the second stack layer IL, and the charge generation layer between the second stack layer ILand the third stack layer ILmay be designed to be disconnected. In another embodiment, as illustrated in, a trench defined through the first pixel defining film PDL, planarization film PNS, the second pixel defining film PDL, and the third pixel defining film PDLmay be provided. In such an embodiment, the trench TRC may be defined through at least a portion of the ninth insulating film INS, but the embodiment of the present specification is not limited thereto.

9 FIG. 10 FIG. 9 FIG. is a perspective view illustrating an example of a head mounted display device.is an exploded perspective view for describing the head mounted display device of.

9 10 FIGS.and 1000 10 1 10 2 1100 1200 1210 1220 1300 1400 1510 1520 1600 Referring to, a head mounted display deviceaccording to an embodiment includes a first display device_, a second display device_, a display device accommodating portion, an accommodating portion cover, a first eyepiece, a second eyepiece, a head mounting band, a middle frame, a first optical member, a second optical member, and a control circuit board.

10 1 10 2 10 1 10 2 10 10 1 10 2 1 8 FIGS.to The first display device_provides an image to a user's left eye, and the second display device_provides an image to a user's right eye. Since each of the first display device_and the second display device_is substantially the same as the display devicedescribed with reference to, any repetitive descriptions of the first display device_and the second display device_will be omitted.

1510 10 1 1210 1520 10 2 1220 1510 1520 The first optical membermay be disposed between the first display device_and the first eyepiece. The second optical membermay be disposed between the second display device_and the second eyepiece. Each of the first optical memberand the second optical membermay include at least one convex lens.

1400 10 1 1600 10 2 1600 1400 10 1 10 2 1600 The middle framemay be disposed between the first display device_and the control circuit boardand may be disposed between the second display device_and the control circuit board. The middle frameserves to support and fix the first display device_, the second display device_, and the control circuit board.

1600 1400 1100 1600 10 1 10 2 1600 10 1 10 2 The control circuit boardmay be disposed between the middle frameand the display device accommodating portion. The control circuit boardmay be connected to the first display device_and the second display device_through a connector. The control circuit boardmay convert an image source input from the outside into digital video data DATA, and may transmit the digital video data DATA to the first display device_and the second display device_through the connector.

1600 10 1 10 2 1600 10 1 10 2 The control circuit boardmay transmit digital video data DATA corresponding to a left eye image optimized for the user's left eye to the first display device_, and may transmit digital video data DATA corresponding to a right eye image optimized for the user's right eye to the second display device_. Alternatively, the control circuit boardmay transmit the same digital video data DATA to the first display device_and the second display device_.

1100 10 1 10 2 1400 1510 1520 1600 1200 1100 1200 1210 1220 1210 1220 1210 1220 9 10 FIGS.and The display device accommodating portionserves to accommodate the first display device_, the second display device_, the middle frame, the first optical member, the second optical member, and the control circuit board. The accommodating portion coveris disposed to cover one opened surface of the display device accommodating portion. The accommodating portion covermay include a first eyepiecewhere the user's left eye is disposed and a second eyepiecewhere the user's right eye is disposed.illustrate an embodiment where the first eyepieceand the second eyepieceare separately disposed, but the embodiment of the present specification is not limited thereto. The first eyepieceand the second eyepiecemay be integrated into one.

1210 10 1 1510 1220 10 2 1520 10 1 1510 1210 10 2 1520 1220 The first eyepiecemay be aligned with the first display device_and the first optical member, and the second eyepiecemay be aligned with the second display device_and the second optical member. Therefore, the user may view an image of the first display device_magnified as a virtual image by the first optical memberthrough the first eyepiece, and may view an image of the second display device_magnified as a virtual image by the second optical memberthrough the second eyepiece.

1300 1100 1210 1220 1200 1100 1000 1300 11 FIG. The head mounting bandserves to fix the display device accommodating portionto a user's head such that the first eyepieceand the second eyepieceof the accommodating portion coverare disposed on the user's left and right eyes, respectively. In an embodiment where the display device accommodating portionis desired to be implemented in a lightweight and small size, the head mounted display devicemay include eyeglass frames as illustrated ininstead of the head mounting band.

11 FIG. is a perspective view illustrating another example of a head mounted display device.

11 FIG. 1000 1 1200 1 1000 1 10 3 1010 1020 1030 1040 1050 1060 1070 1200 1 Referring to, a head mounted display device_according to an embodiment may be a glasses-type display device in which a display device accommodating portion_is implemented in a lightweight and small size. The head mounted display device_according to an embodiment may include a display device_, a left eye lens, a right eye lens, a support frame, eyeglass frame legsand, an optical member, a light path conversion member, and a display device accommodating portion_.

1200 1 10 3 1060 1070 10 3 1060 1070 1020 10 3 1020 The display device accommodating portion_may accommodate the display device_, the optical member, and the light path conversion membertherein. As an image displayed on the display device_is magnified by the optical memberand a light path thereof is converted by the light path conversion member, the image may be provided to the user's right eye through the right eye lens. Accordingly, the user may view an augmented reality image in which a virtual image displayed on the display device_and a real image viewed through the right eye lensare combined through the right eye.

11 FIG. 1200 1 1030 1200 1 1030 10 3 1200 1 1030 10 3 illustrates an embodiment where the display device accommodating portion_is disposed at a right distal end of the support frame, but the embodiment of the present specification is not limited thereto. In an embodiment, for example, the display device accommodating portion_may be disposed at a left distal end of the support frame, and in this case, the image of the display device_may be provided to the user's left eye. Alternatively, the display device accommodating portions_may be disposed at both the left and right distal ends of the support frame. In this case, the user may view the image displayed on the display device_through both the user's left and right eyes.

12 FIG. is a schematic view illustrating a deposition device according to an embodiment.

12 FIG. 1 FIG. 7 FIG. 3000 3002 100 3002 10 11 10 11 10 3000 Referring to, an embodiment of a deposition devicemay be used to form light emitting material layers on a backplane substratein a process of manufacturing the display panel(see). In an embodiment, for example, as illustrated in, a semiconductor backplane SBP and a light emitting element backplane EBP may be disposed on the backplane substrate, and a reflective electrode layer RL and a tenth interlayer insulating film INSmay be disposed on the light emitting element backplane EBP. An eleventh interlayer insulating film INSmay be disposed on the tenth interlayer insulating film INS, electrode patterns, for example, anode electrodes AND, may be disposed on the eleventh interlayer insulating film INS, and the anode electrodes AND may be electrically connected to the reflective electrode layer RL through vias VA. The deposition devicemay be used to form a light emitting stack IL on the electrode patterns.

3000 3200 3002 2000 3200 3300 2000 3002 3002 2000 3300 3002 3002 3002 2000 3300 3310 The deposition devicemay include a deposition sourcefor providing a vapor deposition material on the backplane substrate, a deposition maskdisposed on the deposition source, and a substrate chuckthat is disposed on the deposition maskand supports the backplane substrateso that the backplane substratefaces the deposition mask. That is, the substrate chuckmay support the backplane substratein a way such that the front side of the backplane substratefaces downward, and may position the backplane substrateon the deposition maskto perform a deposition process. The substrate chuckmay be supported by a support member.

3200 2000 3300 3100 3100 3002 3100 3100 3100 3002 2000 3100 The deposition source, the deposition mask, and the substrate chuckmay be disposed within a process chamber. The process chambermay have an internal space defined therein, and a deposition process for forming a deposition material layer on the backplane substratemay be performed in the internal space of the process chamber. Although not illustrated, the process chambermay be connected to a vacuum pump (not illustrated), and the internal space of the process chambermay be created into a vacuum atmosphere by the vacuum chamber. An opening (not illustrated) for the entry and exit of the backplane substrateand the deposition maskmay be provided on one side wall of the process chamber, and may be opened and closed by a gate valve (not illustrated).

3200 3200 3002 3002 2000 3200 3002 3002 2000 A deposition material may be stored within the deposition source. The deposition sourcemay evaporate a deposition material such as an organic material, an inorganic material, a conductive material, etc. toward the backplane substrate, and the evaporated deposition material may be deposited on the backplane substratethrough the deposition mask. In an embodiment, for example, the deposition sourcemay evaporate an organic material for forming light emitting material layers on the backplane substrate, and the evaporated organic material may be deposited on electrode patterns on the backplane substratethrough the deposition mask.

13 FIG. 12 FIG. is a schematic bottom view illustrating a backplane substrate illustrated in.

13 FIG. 13 FIG. 1 FIG. 3002 3010 3020 3010 3010 1 2 3010 100 3010 1 2 1 3010 2310 2000 Referring to, the backplane substratemay include a plurality of display cell areasand a scribe lanearea disposed between the display cell areas. The display cell areasmay be disposed or arranged in a matrix form along the first direction DRand the second direction DR, as illustrated in, and each display cell areamay be individualized as a display panel(see) through a dicing process after the display manufacturing process is completed. For example, the display cell areasmay be arranged in a matrix form along a first horizontal direction DRand a second horizontal direction DRperpendicular to the first horizontal direction DR. The display cell areasmay correspond to the number and arrangement of mask cell areasof the deposition mask.

3010 11 3010 11 10 3010 3002 3300 3002 3010 3200 Each of the display cell areasmay include a semiconductor backplane SBP, a light emitting element backplane EBP disposed on the semiconductor backplane SBP, a reflective electrode layer RL disposed on the light emitting element backplane EBP, and an eleventh interlayer insulating film INSdisposed on the reflective electrode layer RL. In addition, each of the display cell areasmay include a plurality of electrode patterns, for example, a plurality of anode electrodes AND, disposed on the eleventh interlayer insulating film INS, and the anode electrodes AND may be connected to the reflective electrode layer RL through a plurality of vias VA. In such an embodiment, the electrode patterns of the display cell areasmay be disposed on the front surface of the backplane substrate, and the substrate chuckmay grip the rear surface of the backplane substratein a way such that the electrode patterns of the display cell areasface downward, i.e., toward the deposition source.

14 FIG. 15 FIG. 14 FIG. 16 FIG. 15 FIG. 2 2 is a schematic plan view illustrating a deposition mask according to an embodiment of the present disclosure.is a schematic enlarged plan view illustrating mask cell areas illustrated in.is a cross-sectional view taken along line I-I′ of.

14 16 FIGS.to 2000 2100 2200 2400 2500 Referring to, the deposition maskaccording to an embodiment of the present disclosure may include a mask frame, a membrane, a first rear inorganic film layer, and a second rear inorganic film layer.

2100 2110 2120 2110 2100 2110 2100 3 The mask framemay define cell openingsand may include lip areasdefining the cell openings. The mask framemay be provided as or defined by a single crystal silicon substrate, and the cell openingsmay be formed through a wet etching process using tetramethyl ammonium hydroxide (TMAH) or potassium hydroxide (KOH). A crystal direction of the single crystal silicon substrate provided as the mask framemay be the third direction DR.

2200 2100 2200 2310 3010 3002 2320 2310 The membranemay be disposed on the mask frame. The membranemay include mask cell areaseach corresponding to the display cell areasof the backplane substrateand a grid areaexcluding the mask cell areas.

2310 1 2 2310 1 2 1 3010 3002 14 FIG. The mask cell areasmay be disposed in a matrix form having a plurality of rows and a plurality of columns along the first direction DRand the second direction DR, as illustrated in. In an embodiment, for example, the mask cell areasmay be disposed in a matrix form along a first horizontal direction DRand a second horizontal direction DRperpendicular to the first horizontal direction DR, and may be disposed to each correspond to the display cell areasof the backplane substrate.

2320 2310 2200 2320 2100 2120 2100 The grid areamay be an area excluding the mask cell areasin the membrane. The grid areamay be disposed on an edge of the mask frameand on the lip areaof the mask frame.

2200 2210 2220 In addition, the membranemay include an inorganic film layerand a nitride layer.

2210 2100 2210 2100 2100 2210 2220 2100 2210 The inorganic film layermay be disposed on the mask frame. In some embodiments, the inorganic film layermay be disposed on the mask frameso that a lower surface thereof is in contact with an upper surface of the mask frame. The inorganic film layermay include or be made of a material having an etching selectivity with respect to the nitride layerand the mask frame. In an embodiment, for example, the inorganic film layermay include silicon oxide (SiOx).

2220 2210 2220 2210 2210 2220 The nitride layermay be disposed on the inorganic film layer. In some embodiments, the nitride layermay be disposed on the inorganic film layerso that a lower surface thereof is in contact with an upper surface of the inorganic film layer. The nitride layermay include silicon nitride (SiNx).

2310 2200 2312 2310 3200 2110 2312 2200 2110 2312 2210 2220 2110 Each mask cell areaof the membranemay include a plurality of pixel openingsthat expose the anode electrodes AND during the deposition process. The mask cell areasmay be exposed toward the deposition sourcethrough the cell openings, and the pixel openingsmay be defined through the membraneand be connected to the cell openings. In some embodiments, the pixel openingsmay be defined or formed through the inorganic film layerand the nitride layerand be connected to the cell openings.

2400 2100 2400 2100 2100 2410 2110 2400 2400 2210 2200 2400 The first rear inorganic film layermay be disposed below the mask frame. In some embodiments, the first rear inorganic film layermay be disposed below the mask frameso that an upper surface thereof is in contact with a lower surface of the mask frame. First rear openingsin communication with the cell openingsmay be defined or formed in the first rear inorganic film layer. The first rear inorganic film layermay include a same material as the inorganic film layerof the membrane. In an embodiment, for example, the first rear inorganic film layermay include silicon oxide (SiOx).

2500 2400 2500 2400 2400 2510 2110 2410 2500 2500 2220 2200 2500 The second rear inorganic film layermay be disposed below the first rear inorganic film layer. In some embodiments, the second rear inorganic film layermay be disposed below the first rear inorganic film layerso that an upper surface thereof is in contact with a lower surface of the first rear inorganic film layer. Second rear openingsin communication with the cell openingsand the first rear openingsmay be defined or formed in the second rear inorganic film layer. The second rear inorganic film layermay include a same material as the nitride layerof the membrane. In an embodiment, for example, the second rear inorganic film layermay include silicon nitride (SiNx).

17 FIG. 14 FIG. is a plan view illustrating a state in which the number of mask cell areas inis changed.

14 FIG. 2310 1 2310 2 2310 1 2310 2 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 Referring further to, in an embodiment, the number of mask cell areasdisposed in one of the plurality of rows in the first direction DRmay be equal to the number of mask cell areasdisposed in one of the plurality of columns in the second direction DR. In such an embodiment where the number of mask cell areasdisposed in one of the plurality of rows in the first direction DRand the number of mask cell areasdisposed in one of the plurality of columns in the second direction DRare equal to each other, initial stress uniformity and density uniformity may be increased. When the initial stress uniformity of the deposition maskis increased, stress may be evenly distributed on the deposition mask. As the stress is evenly distributed on the deposition mask, the stress may be effectively prevented from being concentrated on a specific portion of the deposition mask. Accordingly, global warpage that may occur in the deposition maskmay be substantially reduced. In a case where the density uniformity of the deposition maskis increased, density may be evenly distributed on the deposition mask. As the density is evenly distributed on the deposition mask, the density may be effectively prevented from being concentrated on a specific portion of the deposition mask. Accordingly, global warpage that may occur in the deposition maskmay be substantially reduced.

17 FIG. 2310 1 2310 2 2310 2 2310 1 2310 1 2310 2 Referring further to, in an embodiment, the number of mask cell areasdisposed in one of the plurality of rows in the first direction DRmay be greater than the number of mask cell areasdisposed in one of the plurality of columns in the second direction DR. The number of mask cell areasdisposed in one of the plurality of columns in the second direction DRmay be 70% or greater and 100% or less of the number of mask cell areasdisposed in one of the plurality of rows in the first direction DR. In an embodiment, for example, when the number of mask cell areasdisposed in one of the plurality of rows in the first direction DRis 10, the number of mask cell areasdisposed in one of the plurality of columns in the second direction DRmay be 7 or greater and 10 or less. This may be expressed as the following Inequality 1.

2310 2310 In Inequality 1, CX denotes the number of mask cell areasdisposed in one row, and CY denotes the number of mask cell areasdisposed in one column.

2000 2000 2000 When CX is 10 and CY is 7 to 10, Inequality 1 is satisfied. Therefore, the initial stress uniformity and density uniformity of the deposition maskmay be increased. On the other hand, when CX is 10 and CY is 6 or less, Inequality 1 is not satisfied. Therefore, as the initial stress uniformity and density uniformity of the deposition maskis decreased, the global warpage may not occur in the deposition mask.

18 FIG. 14 FIG. is an enlarged view of part A of.

18 FIG. 2310 2310 1 2310 2 2310 1 2310 2 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 Referring to, the plurality of mask cell areasmay be formed to have a same size as each other. A length CW of each mask cell areain the first direction DRmay be equal to a length CL of each mask cell areain the second direction DR. In such an embodiment the length CW of each mask cell areain the first direction DRand the length CL of each mask cell areain the second direction DRare equal to each other, initial stress uniformity and density uniformity may be increased. When the initial stress uniformity of the deposition maskis increased, stress may be evenly distributed on the deposition mask. As the stress is evenly distributed on the deposition mask, the stress may be effectively prevented from being concentrated on a specific portion of the deposition mask. Accordingly, global warpage that may occur in the deposition maskmay be substantially reduced. In a case where the density uniformity of the deposition maskis increased, density may be evenly distributed on the deposition mask. As the density is evenly distributed on the deposition mask, the density may be effectively prevented from being concentrated on a specific portion of the deposition mask. Accordingly, global warpage that may occur in the deposition maskmay be substantially reduced.

2310 1 2310 2 2310 2 2310 1 2310 1 2310 2 The length CW of the mask cell areain the first direction DRmay be longer than the length CL of the mask cell areain the second direction DR. The length CL of the mask cell areain the second direction DRmay be 70% or greater and 100% or less of the length CW of the mask cell areain the first direction DR. For example, when the length CW of the mask cell areain the first direction DRis about 10 micrometers (μm), the length CL of the mask cell areain the second direction DRmay be about 7 μm or greater and about 10 μm or less. This may be expressed as the following Inequality 2.

2310 1 2310 2 In Inequality 2, CW denotes a length of the mask cell areain the first direction DR, and CL denotes a length of the mask cell areain the second direction DR.

2000 2000 2000 When CW is about 10 μm and CL is in a range of about 7 μm to about 10 μm, Inequality 2 is satisfied. Therefore, the initial stress uniformity and density uniformity of the deposition maskmay be increased. On the other hand, when CW is about 10 μm and CL is about 6 μm or less, Inequality 2 is not satisfied. Therefore, as the initial stress uniformity and density uniformity of the deposition maskis decreased, the global warpage may not occur in the deposition mask.

19 FIG. 14 FIG. is an enlarged view of part A of.

19 FIG. 2310 1 2310 2 2310 1 2310 2 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 Referring to, in an embodiment, a length CIW of a gap between the mask cell areasin the first direction DRmay be equal to a length CIL of a gap between the mask cell areasin the second direction DR. In such an embodiment where the length CIW of the gap between the mask cell areasin the first direction DRand the length CIL of the gap between the mask cell areasin the second direction DRare equal to each other, initial stress uniformity and density uniformity may be increased. When the initial stress uniformity of the deposition maskis increased, stress may be evenly distributed on the deposition mask. As the stress is evenly distributed on the deposition mask, the stress may be prevented from being concentrated on a specific portion of the deposition mask. Accordingly, global warpage that may occur in the deposition maskmay be substantially reduced. In a case where the density uniformity of the deposition maskis increased, density may be evenly distributed on the deposition mask. As the density is evenly distributed on the deposition mask, the density may be effectively prevented from being concentrated on a specific portion of the deposition mask. Accordingly, global warpage that may occur in the deposition maskmay be substantially reduced.

2310 1 2310 2 2310 2 2310 1 2310 1 2310 2 In an embodiment, the length CIW of the gap between the mask cell areasin the first direction DRmay be longer than the length CIL of the gap between the mask cell areasin the second direction DR. The length CIL of the gap between the mask cell areasin the second direction DRmay be 70% or greater and 100% or less of the length CIW of the gap between the mask cell areasin the first direction DR. For example, when the length CIW of the length of the gap between the mask cell areasin the first direction DRis about 10 μm, the length CIL of the gap between the mask cell areasin the second direction DRmay be about 7 μm or greater and about 10 μm or less. This may be expressed as the following Inequality 3.

2310 1 2310 2 In Inequality 3, CIW denotes a length of the gap between the mask cell areasin the first direction DR, and CIL denotes a length of the gap between the mask cell areasin the second direction DR.

2000 2000 2000 When CIW is about 10 μm and CIL is in a range of about 7 μm to about 10 μm, Inequality 3 is satisfied. Therefore, the initial stress uniformity and density uniformity of the deposition maskmay be increased. On the other hand, when CIW is about 10 μm and CIL is about 6 μm or less, Inequality 3 is not satisfied. Therefore, as the initial stress uniformity and density uniformity of the deposition maskis decreased, the global warpage may not occur in the deposition mask.

20 FIG. 14 FIG. is a plan view illustrating a state in which an arrangement shape of the mask cell areas inis changed.

20 FIG. 2310 2200 2200 2 2310 2200 2200 1 2310 2200 Referring to, the number of mask cell areasdisposed in each row may gradually decrease from a row disposed on a center side (or a center portion) of the membraneto a row disposed in an outer side (or an outer portion) of the membranein the second direction DR, and the number of mask cell areasdisposed in each column may gradually decrease from a column disposed on a center side of the membraneto a column disposed in an outer side of the membranein the first direction DR. In some embodiments, the mask cell areasmay be arranged in a cross shape in the membrane.

2310 2200 1 2310 2200 4 2310 1 2310 2310 2310 4 2310 2310 1 2 4 1 2 The total length CTWL of the mask cell areason an imaginary line passing through the center side of the membraneand extending in the first direction DRmay be equal to the total length CTDL of the mask cell areason an imaginary line passing through the center side of the membraneand extending in the fourth direction DR. Here, the total length CTWL of the mask cell areason the imaginary line extending in the first direction DRmay be a length of only the pure mask cell areasexcluding the length of the gap between the mask cell areas. The total length CTDL of the mask cell areason the imaginary line extending in the fourth direction DRmay be a length of only the pure mask cell areasexcluding the length of the gap between the mask cell areas. In addition, the first direction DRmay be orthogonal to the second direction DR, and the fourth direction DRmay intersect the first direction DRor the second direction DRat an angle of about 45°.

2310 1 2310 4 2000 2000 2000 2000 2000 2000 2000 2000 2000 2000 In such an embodiment where the total length CTWL of the mask cell areason the imaginary line extending in the first direction DRand the total length CTDL of the mask cell areason the imaginary line extending in the fourth direction DRare equal to each other, initial stress uniformity and density uniformity may be increased. When the initial stress uniformity of the deposition maskis increased, stress may be evenly distributed on the deposition mask. As the stress is evenly distributed on the deposition mask, the stress may be prevented from being concentrated on a specific portion of the deposition mask. Accordingly, global warpage that may occur in the deposition maskmay be substantially reduced. In addition, when the density uniformity of the deposition maskis increased, density may be evenly distributed on the deposition mask. As the density is evenly distributed on the deposition mask, the density may be effectively prevented from being concentrated on a specific portion of the deposition mask. Accordingly, global warpage that may occur in the deposition maskmay be substantially reduced.

2310 1 2310 4 2310 4 2310 1 2310 1 2310 4 In an embodiment, the total length CTWL of the mask cell areason the imaginary line extending in the first direction DRmay be longer than the total length CTDL of the mask cell areason the imaginary line extending in the fourth direction DR. The total length CTDL of the mask cell areason the imaginary line extending in the fourth direction DRmay be 70% or greater and 100% or less of the total length CTWL of the mask cell areason the imaginary line extending in the first direction DR. When the total length CTWL of the mask cell areason the imaginary line extending in the first direction DRis about 10 μm, the total length CTDL of the mask cell areason the imaginary line extending in the fourth direction DRmay be about 7 μm or greater and about 10 μm or less. This may be expressed as the following Inequality 4.

2310 1 2310 4 In Inequality 4, CTWL denotes the total length of the mask cell areason the imaginary line extending in the first direction DR, and CTDL denotes the total length CTDL of the mask cell areason the imaginary line extending in the fourth direction DR.

2000 2000 2000 When CTWL is about 10 μm and CTDL is in a range of about 7 μm to about 10 μm, Inequality 4 is satisfied. Therefore, the initial stress uniformity and density uniformity of the deposition maskmay be increased. On the other hand, when CTWL is 10 μm and CTDL is 6 μm or less, Inequality 4 is not satisfied. Therefore, as the initial stress uniformity and density uniformity of the deposition maskis decreased, the global warpage may not occur in the deposition mask.

The display device according to an embodiment of the present disclosure can be applied to various electronic devices. The electronic device according to an embodiment of the present disclosure includes the display device described above, and may further include modules or devices having additional functions in addition to the display device.

21 FIG. is a block diagram of an electronic device according to an embodiment of the present disclosure.

21 FIG. 10000 10001 10002 10003 10004 Referring to, the electronic deviceaccording to an embodiment of the present disclosure may include a display module, a processor, a memory, and a power module.

10002 The processormay include at least one selected from a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

10003 10002 10001 10002 10003 10001 10001 The memorymay store data information to be used for the operation of the processoror the display module. When the processorexecutes an application stored in the memory, an image data signal and/or an input control signal is transmitted to the display module, and the display modulecan process the received signal and output image information through a display screen.

10004 10000 The power modulemay include a power supply module such as, for example a power adapter or a battery, and a power conversion module that converts the power supplied by the power supply module to generate power necessary for the operation of the electronic device.

10000 10001 10002 10003 10004 10000 At least one of the components of the electronic deviceaccording to an embodiment of the present disclosure may be included in the display device according to the embodiments of the present disclosure. In addition, some modules of the individual modules functionally included in one module may be included in the display device, and other modules may be provided separately from the display device. In an embodiment, for example, the display device may include the display module, and the processor, the memory, and the power modulemay be provided in the form of other devices within the electronic deviceother than the display device.

22 FIG. is a schematic diagram of an electronic device according to various embodiments of the present disclosure.

22 FIG. 10000 1 10000 1 10000 1 10000 1 10000 1 10000 2 10000 2 10000 2 10000 3 a b c d e a b c Referring to, various electronic devices to which display devices according to embodiments of the present disclosure are applied may include not only image display electronic devices such as a smart phone_, a tablet PC_, a laptop_, a TV_, and a desk monitor_, but also wearable electronic devices including display modules such as, for example smart glasses_, a head mounted display_, and a smart watch_, and vehicle electronic devices_including display modules such as a center information display (CID) and a room mirror display arranged on a dashboard, center fascia, and dashboard of an automobile.

The invention should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art.

While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the following claims.