Non-Volatile Memory Device and Storage Device

This application is a Continuation of U.S. patent application Ser. No. 18/235,678, filed on Aug. 18, 2023, which claims benefit of priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0167031, filed on Dec. 2, 2022, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties.

The present disclosure relates generally to a memory device, and more particularly, to a non-volatile memory device including sub-blocks and a storage device including the non-volatile memory device.

Non-volatile memory devices may need to meet and/or be designed according to various types of power consumption specifications. For example, when a non-volatile memory device is used in a mobile device (e.g., a mobile phone, smart phone, tablet computer, laptop computer, wearable device, Internet of Things (IoT) device, and the like), a peak power may be a limiting factor for the non-volatile memory device. Alternatively or additionally, when a non-volatile memory device is used in a storage device (e.g., a solid state drive (SSD), and the like), a maximum power consumption may be a limiting factor according to a power specification. However, power consumption of related non-volatile memory devices may tend to increase due to an increase in the throughput of a mobile device and/or a storage device. Accordingly, some operations of the related non-volatile memory devices may be disabled in order to satisfy a power constraint, and as a result, performance of the mobile device and/or the storage device may be degraded.

There exists a need for further improvements in non-volatile memory devices, as the need for increased throughput may be constrained by power consumption. Improvements are presented herein. These improvements may also be applicable to other memory devices and/or other semiconductor devices.

The present disclosure provides a non-volatile memory device and a storage device capable of potentially improving performance and controlling power consumption.

According to an aspect of the present disclosure, a storage device is provided. The storage device includes a non-volatile memory including a plurality of blocks, each block of the plurality of blocks including a plurality of independently erasable sub-blocks. The storage device further includes a storage controller configured to select an erase mode from among a plurality of erase modes including a first sub-block erase mode and a second sub-block erase mode, and control an erase operation of the non-volatile memory, according to the selected erase mode. The storage controller is further configured to select the selected erase mode according to at least one of an operation schedule and a power consumption of the non-volatile memory. Based on the selected erase mode being the first sub-block erase mode, the storage controller is configured to control a first erase operation with respect to one selected sub-block from among the plurality of independently erasable sub-blocks of a selected block from among the plurality of blocks. Based on the selected erase mode being the second sub-block erase mode, the storage controller is configured to control a second erase operation with respect to two or more selected sub-blocks from among the plurality of independently erasable sub-blocks of the selected block.

According to an aspect of the present disclosure, a storage device is provided. The storage device includes a plurality of non-volatile memories, each non-volatile memory of the plurality of non-volatile memories including a plurality of blocks, each block of the plurality of blocks including a plurality of independently erasable sub-blocks. The storage device further includes a storage controller configured to select, for each non-volatile memory of the plurality of non-volatile memories, a corresponding erase mode, according to at least one of an operation schedule and power consumption of the plurality of non-volatile memories, and control, for each non-volatile memory of the plurality of non-volatile memories, an erase operation of that non-volatile memory according to the corresponding erase mode. The storage controller is further configured to select a sub-block erase mode as the corresponding erase mode of at least one non-volatile memory of the plurality of non-volatile memories based on the power consumption being greater than or equal to a threshold value, and control the erase operation with respect to at least one sub-block from among the plurality of independently erasable sub-blocks of the at least one non-volatile memory of the plurality of non-volatile memories based on the sub-block erase mode being the corresponding erase mode of the at least one non-volatile memory.

According to an aspect of the present disclosure, a non-volatile memory device is provided. The non-volatile memory device includes a memory cell array including a plurality of blocks, each block of the plurality of blocks including a plurality of memory stacks stacked above a substrate in a vertical direction. The non-volatile memory device further includes an erase mode selector configured to select an erase mode from among a plurality of erase modes based on a command received from a storage controller, and control an erase operation with respect to the memory cell array according to the selected erase mode. The erase operation is performed on a selected block from among the plurality of blocks based on the selected erase mode being a block erase mode. The erase operation is performed on one of the plurality of memory stacks of the selected block based on the erase mode being a first sub-block erase mode. The erase operation is performed on two or more memory stacks from among the plurality of memory stacks of the selected block based on the erase mode being a second sub-block erase mode.

Additional aspects may be set forth in part in the description which follows and, in part, may be apparent from the description, and/or may be learned by practice of the presented embodiments.

The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of embodiments of the present disclosure defined by the claims and their equivalents. Various specific details are included to assist in understanding, but these details are considered to be exemplary only. Therefore, those of ordinary skill in the art may recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the disclosure. In addition, descriptions of well-known functions and structures are omitted for clarity and conciseness.

With regard to the description of the drawings, similar reference numerals may be used to refer to similar or related elements. It is to be understood that a singular form of a noun corresponding to an item may include one or more of the things, unless the relevant context clearly indicates otherwise. As used herein, each of such phrases as “A or B,” “at least one of A and B,” “at least one of A or B,” “A, B, or C,” “at least one of A, B, and C,” and “at least one of A, B, or C,” may include any one of, or all possible combinations of the items enumerated together in a corresponding one of the phrases. As used herein, such terms as “1st” and “2nd,” or “first” and “second” may be used to simply distinguish a corresponding component from another, and does not limit the components in other aspect (e.g., importance or order). It is to be understood that if an element (e.g., a first element) is referred to, with or without the term “operatively” or “communicatively”, as “coupled with,” “coupled to,” “connected with,” or “connected to” another element (e.g., a second element), it means that the element may be coupled with the other element directly (e.g., wired), wirelessly, or via a third element.

It is to be understood that when an element or layer is referred to as being “over,” “above,” “on,” “below,” “under,” “beneath,” “connected to” or “coupled to” another element or layer, it can be directly over, above, on, below, under, beneath, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly over,” “directly above,” “directly on,” “directly below,” “directly under,” “directly beneath,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

The terms “upper,” “middle”, “lower”, etc. may be replaced with terms, such as “first,” “second,” third” to be used to describe relative positions of elements. The terms “first,” “second,” third” may be used to described various elements but the elements are not limited by the terms and a “first element”may be referred to as a “second element”. Alternatively or additionally, the terms “first”, “second”, “third”, etc. may be used to distinguish components from each other and do not limit the present disclosure. For example, the terms “first”, “second”, “third”, etc. may not necessarily involve an order or a numerical meaning of any form.

Reference throughout the present disclosure to “one embodiment,” “an embodiment,” “an example embodiment,” or similar language may indicate that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present solution. Thus, the phrases “in one embodiment”, “in an embodiment,” “in an example embodiment,” and similar language throughout this disclosure may, but do not necessarily, all refer to the same embodiment.

It is to be understood that the specific order or hierarchy of blocks in the processes/flowcharts disclosed are an illustration of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of blocks in the processes/flowcharts may be rearranged. Further, some blocks may be combined or omitted. The accompanying claims present elements of the various blocks in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

Hereinafter, various embodiments of the present disclosure are described with reference to the accompanying drawings.

1 FIG. is a block diagram illustrating a host storage system (SS), according to an embodiment.

1 FIG. 4 FIG.A 10 20 10 11 12 11 12 1 2 Referring to, the host storage system SS may include a storage deviceand a host. The storage devicemay include a storage controllerand a non-volatile memory (NVM). According to some embodiments, the storage controllermay be referred to as a memory controller and/or an NVM controller. The NVMmay include a plurality of blocks BLKs, and each block BLK may include a plurality of independently erasable sub-blocks (e.g., first sub-block SUB_BLK, second sub-block SUB_BLK, hereinafter “SUB_BLK” generally). In an embodiment, a plurality of sub-blocks SUB_BLK may have different block sizes. However, the present disclosure is not limited thereto. For example, in an optional or additional embodiment, the plurality of sub-blocks SUB_BLK may have the same block size. As used herein, a block size may correspond to the number of word lines connected to each sub-block SUB_BLK. For example, the block size may correspond to the length of each sub-block SUB_BLK in a vertical direction (e.g., VD of).

12 12 12 In an embodiment, an erase operation on the NVMmay be performed in block units and/or sub-block units, according to an erase mode. For example, in a block erase mode and/or a full block erase mode, an erase operation may be independently performed on each of the plurality of blocks BLKs of NVM. That is, the erase operation may be performed in block units. For another example, in the sub-block erase mode, an erase operation may be independently performed on each of a plurality of sub-blocks of one or more blocks of the plurality of blocks BLKs of NVM. That is, the erase operation may be performed in sub-block units. In such an embodiment, a default erase mode may be the sub-block erase mode, but the present disclosure is not limited thereto. For example, the default erase mode may be the block erase mode.

12 12 12 In an optional or additional embodiment, an erase operation on the NVMmay be performed in full block units and/or sub-block units, according to an erase mode. For example, in the full block erase mode, a full block erase operation may be performed on all the blocks (e.g., the plurality of blocks BLKs) of the NVM. That is, the erase operation may be performed in full block units. For another example, in the sub-block erase mode, an erase operation may be independently performed on each of a plurality of sub-blocks of one or more blocks of the plurality of blocks BLKs of NVM. That is, the erase operation may be performed in sub-block units. In such an embodiment, the default erase mode may be the sub-block erase mode, but the present disclosure is not limited thereto. For example, the default erase mode may be the full block erase mode.

1 2 1 2 6 FIG. In an embodiment, the first and second sub-blocks SUB_BLKand SUB_BLKmay respectively correspond to first and second memory stacks (e.g., STand STof) disposed on a substrate in a vertical direction. Alternatively or additionally, the block size of the plurality of sub-blocks SUB_BLK may correspond to a stack size. For example, the size of the first memory stack may correspond to the length of the first memory stack in a vertical direction, and the size of the second memory stack may correspond to the length of the second memory stack in a vertical direction.

12 12 12 In an optional or additional embodiment, an erase operation on the NVMmay be performed in block units and/or in memory stack units, according to an erase mode. For example, in the block erase mode, an erase operation may be independently performed on each of the plurality of blocks BLKs of NVM. That is, the erase operation may be performed in block units. For another example, in the full block erase mode, an erase operation may be simultaneously performed on all the blocks (e.g., the plurality of blocks BLKs) of NVM. That is, the erase operation may be performed in full block units. For another example, in the sub-block erase mode, an erase operation may be independently performed on each of a plurality of memory stacks. That is, the erase operation may be performed in memory stack units.

In an embodiment, a sub-block erase mode may include a plurality of sub-block erase modes. For example, in a first sub-block erase mode and/or in a stack erase mode, an erase operation may be independently performed on each memory stack included in each block BLK. For another example, in a second sub-block erase mode and/or in a multi-stack erase mode, an erase operation may be independently performed on at least two memory stacks included in each block BLK. For another example, in a third sub-block erase mode and/or in a sub-stack erase mode, an erase operation may be independently performed on each of a plurality of groups included in each memory stack. For another example, in a fourth sub-block erase mode and/or in a cross stack erase mode, an erase operation may be independently performed on a plurality of groups respectively included in a plurality of memory stacks.

11 12 12 11 111 112 113 114 115 11 116 1 FIG. The storage controllermay be configured to communicate with the NVMand to manage an erase mode with respect to the NVM. For example, as shown in, the storage controllermay include a set of components, such as a processor, an erase mode manager, a host interface (I/F), a buffer memory, and an NVM interface. The set of components of the storage controllermay be communicatively coupled with each other via a bus.

116 11 116 116 11 The busmay include one or more components that may permit communication among the set of components of the storage controller. For example, the busmay be a communication bus, a cross-over bar, a network, or the like. In an embodiment, the busmay be implemented using multiple (e.g., two or more) connections between the set of components of storage controller. The present disclosure is not limited in this regard.

112 12 112 12 The erase mode managermay be configured to select at least one erase mode from among a plurality of erase modes, based on at least one of an operation schedule and a power consumption of the NVM. Alternatively or additionally, the erase mode managermay control an erase operation on the NVM, according to the selected erase mode. In an embodiment, the plurality of erase modes may include, but not be limited to, at least two of a block erase mode, a full block erase mode, and a sub-block erase mode. For example, the sub-block erase mode may include a stack erase mode and a multi-stack erase mode. For another example, the sub-block erase mode may further include a sub-stack erase mode and a cross-stack erase mode.

12 12 112 12 12 112 12 In an embodiment, when an intensive read operation and/or program (e.g., write) operation is indicated as having been performed by the NVMon the operation schedule of the NVM, the erase mode managermay select a sub-block erase mode from among a plurality of erase modes based on checking the operation schedule of the NVM. Alternatively or additionally, when an intensive read operation and/or a program operation has not been performed on the NVM, the erase mode managermay select a block erase mode and/or a full block erase mode from among a plurality of erase modes, based on checking the operation schedule of the NVM.

12 10 112 112 In another optional or additional embodiment, based on checking the power consumption of the NVMand/or the storage device, the erase mode managermay select a sub-block erase mode from among a plurality of erase modes when the power consumption is greater than or equal to a threshold value. Alternatively or additionally, the erase mode managermay select a block erase mode from among a plurality of erase modes, when the power consumption is less than the threshold value.

112 12 112 12 112 12 In an embodiment, in a low power mode in which power consumption is greater than or equal to a threshold value, the erase mode managermay select a sub-block erase mode, and accordingly, may control an erase operation on at least one sub-block of a plurality of sub-blocks SUB_BLK of a block BLK selected from the plurality of blocks BLKs included in the NVM. In an optional or additional embodiment, in a normal power mode in which the power consumption is less than the threshold value, the erase mode managermay select a block erase mode, and accordingly, may control an erase operation on a block BLK selected from the plurality of blocks BLKs included in the NVM. In an another optional or additional embodiment, in the normal power mode in which the power consumption is less than the threshold value, the erase mode managermay select a full block erase mode, and accordingly, may control an erase operation on the plurality of full blocks BLKs included in the NVM.

112 112 11 12 112 11 12 12 112 In an embodiment, the erase mode managermay perform an erase mode selection operation when a request for an erase operation occurs. For example, the erase mode managermay select one of a plurality of erase modes before performing a program operation, and the storage controllermay transfer the selected erase mode to the NVM. For another example, the erase mode managermay select one of a plurality of erase modes to secure a free block, and the storage controllermay transfer the selected erase mode to the NVM. That is, when performing an erase operation on the NVMaccording to a sub-block erase mode and a free space corresponding to a block unit is required, the erase mode managermay perform a sub-block erase operation on a plurality of blocks and/or a plurality of non-volatile memories.

112 112 11 12 112 12 112 12 In an embodiment, the erase mode managermay perform an erase mode selection operation further based on an erase time, a latency, and/or a throughput. For example, the erase mode managermay select a sub-block erase mode when an erase-program interval (EPI) with respect to a specific block exceeds a reference time so that EPIs with respect to the plurality of memory blocks BLKs may be maintained within a certain time. Alternatively or additionally, the storage controllermay transfer the selected sub-block erase mode to the NVM. For example, the erase mode managermay select a sub-block erase mode when the number of program commands exceeds a reference number in order to satisfy latency with respect to a program operation, and may transfer the selected sub-block erase mode to the NVM. For another example, the erase mode managermay select a sub-block erase mode when throughput exceeds a reference value, and may transfer the selected sub-block erase mode to the NVM.

112 112 11 112 111 12 112 According to an embodiment, the erase mode managermay be implemented in software, firmware, hardware, and/or a combination thereof. In an embodiment, the erase mode managermay be implemented in software, the storage controllermay further include a working memory into which the erase mode manageris loaded, and the processormay control an erase mode selection operation on the NVMby executing the erase mode manager. For example, the working memory may be implemented as volatile memory, such as, but not limited to, static random access memory (SRAM) or dynamic RAM (DRAM), and/or NVM, such as, but not limited to, flash memory or phase change RAM (PRAM).

112 111 12 111 12 12 12 12 In an embodiment, the erase mode managermay be implemented in a Flash Translation Layer (FTL), and the processormay control an erase mode selection operation on the NVMby executing the FTL. In such an embodiment, the processormay control data writing and/or reading operations on the NVMby executing the FTL. Alternatively or additionally, the FTL may perform various functions, such as wear-leveling and garbage collection. Wear-leveling may refer to a technique of preventing excessive deterioration of a specific block by uniformly using blocks in the NVM, and may be implemented through a firmware technique that may balance erase counts of physical blocks. Garbage collection may refer to a technique of selecting a victim sub-block from among a plurality of sub-blocks of the NVMand copying valid data in the victim sub-block to a new sub-block (e.g., a target sub-block) and then erasing the victim sub-block, in order to secure usable capacity in the NVM.

111 11 111 114 12 12 114 11 11 11 114 The processormay include a central processing unit (CPU) and/or a microprocessor, and may control all operations of the storage controller. In an embodiment, the processormay be implemented as a multi-core processor (e.g., a dual-core processor or quad-core processor). The buffer memorymay temporarily store data to be written to the NVMand/or data read from the NVM. The buffer memorymay be included in the storage controller, but may be disposed outside the storage controller. For example, the storage controllermay further include a buffer memory manager and/or a buffer memory interface for communicating with the buffer memory.

113 20 20 113 12 113 20 12 115 12 12 12 115 The host interfacemay transmit/receive packets to/from the host. A packet transmitted from the hostto the host interfacemay include a command and/or data to be written in the NVM. A packet transmitted from the host interfaceto the hostmay include a response to a command and/or data read from the NVM. The NVM interfacemay transmit data to be written in the NVMto the NVMand/or receive data read from the NVM. The NVM interfacemay be implemented to comply with one or more memory storage standard protocols, such as Toggle and Open NAND Flash Interface (ONFI).

10 20 10 10 10 10 10 20 10 The storage devicemay include storage media storing data according to a request from the host. For example, the storage devicemay include at least one of a solid state drive (SSD), an embedded memory, and a removable external memory. When the storage deviceis and/or includes an SSD, the storage devicemay be and/or include a device conforming to one or more non-volatile memory express (NVMe) standards (e.g., NVMe, Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVMe over Fabrics, and the like). When the storage deviceis and/or includes an embedded memory and/or an external memory, the storage devicemay be and/or include a device conforming to an universal flash storage (UFS) and/or an embedded multi-media card (eMMC) standard. The hostand the storage devicemay each generate and/or transmit a packet according to one or more adopted standard protocols.

20 21 22 21 22 12 12 22 10 10 21 22 In an embodiment, the hostmay include a host controllerand a host memory. The host controllermay manage an operation of storing data of a buffer area of the host memoryin the NVMand/or storing data of the NVMin the buffer area. For example, the host memorymay function as a buffer memory temporarily storing data to be transmitted to the storage deviceand/or data transmitted from the storage device. In an embodiment, the host controllermay be any one of a plurality of modules included in an application processor, and the application processor may be implemented as a System on Chip (SoC). Alternatively or additionally, the host memorymay be and/or include an embedded memory included in the application processor, and/or may be an NVM and/or a memory module disposed outside the application processor.

1 FIG. 1 FIG. 1 FIG. 1 FIG. 1 FIG. The number and arrangement of components of the host storage system SS shown inare provided as an example. In practice, there may be additional components, fewer components, different components, or differently arranged components than those shown in. Furthermore, two or more components shown inmay be implemented within a single component, or a single component shown inmay be implemented as multiple, distributed components. Alternatively or additionally, a set of (one or more) components shown inmay be integrated with each other and implemented as an integrated circuit, as software, and/or as a combination of circuits and software.

2 FIG. 2 FIG. 1 FIG. 2 FIG. 1 FIG. 2 FIG. 12 12 121 122 123 124 125 12 12 12 12 12 is a block diagram illustrating the NVMaccording to an embodiment. Referring to, the NVMmay include a memory cell array, control logic circuitry, a voltage generator, a row decoder, and a page buffer circuit. The NVMmay correspond to an implementation example of the NVMof. That is, the NVMofmay include or may be similar in many respects to the NVMdescribed above with reference to. However, the NVMofmay include additional features not mentioned above.

121 1 1 1 1 1 1 1 2 121 125 124 2 FIG. The memory cell arraymay include a plurality of memory blocks (e.g., BLKto BLKz, hereinafter “BLK” generally). Each block of the plurality of memory blocks BLK may include a plurality of pages (e.g., PGto PGc, hereinafter “PG” generally), where z and c may be positive integers greater than zero and may be variously changed according to some embodiments. For example, some pages PGto PGb among the plurality of pages PGto PGc may be included in the first sub-block SUB_BLK, and the remaining pages PGb+to PGc among the plurality of pages PGto PGc may be included in the second sub-block SUB_BLK, wherein b may be a positive integer less than c. For example, a memory block and/or a sub-block may be a unit of erase, and/or a page may be a unit of program and read. As shown in, the memory cell arraymay be connected to the page buffer circuitthrough bit lines BL, and/or may be connected to the row decoderthrough word lines WL, string selection lines SSL, and ground selection lines GSL.

121 In an embodiment, the memory cell arraymay be and/or may include a three-dimensional (3D) memory cell array. The 3D memory cell array may be and/or include a plurality of NAND strings. Each NAND string may include memory cells which may be respectively connected to word lines WL vertically stacked on a substrate. U.S. Pat. Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S. Pat. No. 9,536,970 disclose semiconductor memory devices, the disclosures of which are incorporated by reference herein in their entireties.

121 10 121 In an optional or additional embodiment, the memory cell arraymay be and/or include a flash memory, and the flash memory may include a two-dimensional (2D) NAND memory array and/or a 3D (vertical) NAND (VNAND) memory array. Alternatively or additionally, the storage devicemay include other types of NVMs. For example, the memory cell arraymay include magnetic RAM (MRAM), spin-transfer torque MRAM, conductive bridging RAM (CBRAM), ferroelectric RAM (FeRAM), PRAM, resistive RAM, and the like.

122 12 122 122 122 1221 1221 121 11 1221 122 1221 1221 122 The control logic circuitrymay generally control various operations within the NVM. That is, the control logic circuitrymay output various control signals in response to a command CMD and/or an address ADDR. For example, the control logic circuitrymay output a voltage control signal CTRL_vol, a row address X_ADDR, and a column address Y_ADDR. In an embodiment, the control logic circuitrymay include an erase mode selector. The erase mode selectormay select an erase mode with respect to the memory cell arraybased on the command CMD received from the storage controller. For example, the command CMD may correspond to an erase command, and the erase command may include information about an erase mode. For another example, the command CMD may correspond to a dedicated command instructing an erase mode, that is, an erase mode command. However, the present disclosure is not limited thereto. In some embodiments, the erase mode selectormay be disposed outside the control logic circuitry. For example, the erase mode selectormay be included in a command decoder. For another example, the erase mode selectormay be disposed between the command decoder and the control logic circuitry.

123 123 The voltage generatormay generate various types of voltages for performing program, read, and/or erase operations based on the voltage control signal CTRL_vol. For example, the voltage generatormay generate a program voltage, a read voltage, a program verify voltage, an erase voltage, and the like, as a word line voltage VWL.

124 124 124 The row decodermay select one of a plurality of word lines WL and/or one of a plurality of string selection lines SSL in response to the row address X_ADDR. For example, during a program operation, the row decodermay apply a program voltage and a program verify voltage to the selected word line WL. For another example, during a read operation, the row decodermay apply a read voltage to the selected word line WL.

125 125 The page buffer circuitmay select at least one bit line from among the bit lines BL in response to the column address Y_ADDR. The page buffer circuitmay operate as a write driver and/or a sense amplifier according to an operation mode.

3 FIG. is a circuit diagram illustrating a memory block BLK, according to an embodiment.

3 FIG. 2 FIG. 11 33 11 Referring to, the memory block BLK may include or may be similar in many respects to one of the plurality of memory blocks BLK described above with reference to, and may include additional features not mentioned above. The memory block BLK may include NAND strings NSto NS. Each NAND string (e.g., NS) may include a string selection transistor SST, a plurality of memory cells MCs, and a ground selection transistor GST, which may be connected to each other in series. The transistors SST and GST and the memory cells MCs may be included in each NAND string and may form a stacked structure in a vertical direction on a substrate.

1 2 3 1 2 3 4 5 6 7 8 11 21 31 1 12 22 32 2 13 23 33 3 In an embodiment, bit lines (e.g., first bit line BL, second bit line BL, and third bit line BL, hereinafter “BL” generally) may extend in a first direction. Alternatively or additionally, word lines (e.g., first word line WL, second word line WL, third word line WL, fourth word line WL, fifth word line WL, sixth word line WL, seventh word line WL, and eighth word line WL) may extend in a second direction. In an embodiment, the NAND strings NS, NS, and NSmay be positioned between the first bit line BLand the common source line CSL, the NAND strings NS, NS, and NSmay be positioned between the second bit line BLand the common source line CSL, and the NAND strings NS, NS, and NSmay be positioned between the third bit line BLand the common source line CSL.

1 2 3 1 8 1 2 3 The string selection transistor SST may be connected to a corresponding string selection line (e.g., first string selection line SSL, second string selection line SSL, and third string selection line SSL). The memory cells MCs may be respectively connected to the word lines (e.g., WLto WL). The ground selection transistor GST may be connected to a corresponding ground selection line (e.g., first ground selection line GSL, second ground selection line GSL, and third ground selection line GSL). The string selection transistor SST may be connected to a corresponding bit line BL, and the ground selection transistor GST may be connected to the common source line CSL. In such embodiments, the number of NAND strings, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of string selection lines may be variously changed according to some embodiments and/or design constraints.

4 FIG.A is a perspective view illustrating a memory block BLKa, according to an embodiment.

4 FIG.A 2 FIG. 1 3 2 Referring to, the memory block BLKa may correspond to one of the plurality of memory blocks BLK of. The memory block BLKa may include a memory stack ST extending in a vertical direction VD on the upper portion of a substrate SUB. For example, the memory block BLKa may include the single memory stack ST between the substrate SUB and the bit lines BLto BL. Common source lines CSL may be disposed on the substrate SUB, and insulating layers IL extending long in a second horizontal direction HDon a region of the substrate SUB between two adjacent common source lines CSL may be sequentially provided in the vertical direction VD, and spaced apart by a specific distance in the vertical direction VD. Pillars P penetrating the insulating layers IL in the vertical direction VD may be provided on a region of the substrate SUB between two adjacent common source lines CSL. A surface layer S of each pillar P may include a first type silicon material and may function as a channel region. In an embodiment, an inner layer I of each pillar P may include an insulating material, such as silicon oxide or an air gap.

1 8 1 3 1 2 In a region between two adjacent common source lines CSL, a charge storage layer CS may be provided along the insulating layers IL, the pillars P, and the exposed surface of the substrate SUB. The charge storage layer CS may include a gate insulating layer, a charge trap layer, and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. Alternatively or additionally, in a region between two adjacent common source lines CSL, a gate electrode GE such as the selection lines GSL and SSL and the word lines WLto WLmay be provided on the exposed surface of the charge storage layer CS. Drains DR may be respectively provided on the plurality of pillars P. The bit lines BLto BLelongating in the first horizontal direction HDand spaced apart from each other by a specific distance in the second horizontal direction HDmay be provided on the drains DR.

4 FIG.B is a perspective view illustrating a memory block BLKb, according to an embodiment.

4 FIG.B 2 FIG. 4 FIG.A 2 4 FIGS.andA Referring to, the memory block BLKb may include or may be similar in many respects to at least one of the plurality of memory blocks BLK ofand the memory block BLKa of, and may include additional features not mentioned above. As such, descriptions given above with reference tomay also be applied to the memory block BLKb.

1 2 1 2 1 3 1 2 1 3 In an embodiment, the memory block BLKb may include a first memory stack STand a second memory stack STstacked on the substrate SUB in the vertical direction VD. For example, the memory block BLKb may include two memory stacks (e.g., first and second memory stacks STand ST) between the substrate SUB and the bit lines BLto BL. That is, the memory block BLKb may have a multi-stack structure (e.g., a 2-stack structure). In an embodiment, the vertical lengths of the first and second memory stacks STand STmay be different from each other. However, the present disclosure is not limited thereto. For example, according to some embodiments, the memory block BLKb may include three or more memory stacks between the substrate SUB and the bit lines BLto BL.

5 FIG. 1 2 FIGS.and 50 50 12 schematically illustrates an NVM, according to an embodiment. The NVMmay include or may be similar in many respects to the NVMdescribed above with reference to, and may include additional features not mentioned above.

5 FIG. 4 FIG.A 4 FIG.A 3 FIG. 50 1 50 11 Referring to, the NVMmay include the common source line CSL and the bit line BL extending in the first horizontal direction HDand the memory stack ST extending in the vertical direction VD. That is, the memory stack ST may be connected to the bit line BL through the drain DR. For example, the NVMmay correspond to an example ofin which the memory stack ST may correspond to the pillar P of, and the first cell string NSof.

50 1 1 In an embodiment, the NVMmay further include a plurality of word lines (e.g., WLto WLn, where n is a positive integer greater than zero) stacked in the vertical direction VD. Alternatively or additionally, at least one ground selection line GSL may be provided between the common source line CSL and the word line WL, and at least one string selection line SSL may be disposed between the bit line BL and the word line WLn. In an optional or additional embodiment, an erase control line (e.g., GIDL_SS) may be further disposed between the string selection line SSL and the bit line BL, and an erase control line (e.g., GIDL_GS) may be further disposed between the ground selection line GSL and the common source line CSL.

1 1 2 1 1 2 1 1 1 2 1 2 In an embodiment, the plurality of word lines WLto WLn may be grouped into a plurality of groups including a first word line group WGRand a second word line group WGR. The first word line group WGRmay include word lines WLto WLd relatively close to a substrate, and the second word line group WGRmay include word lines WLd+to WLn relatively far from the substrate. Here, d is a positive integer between 1 and n. For example, according to an embodiment, the plurality of word lines WLto WLn may be grouped into three or more groups. In an optional or additional embodiment, the number of word lines included in the first word line group WGRand the number of word lines included in the second word line group WGRmay be different from each other. For example, the number of word lines included in the first word line group WGRmay be greater than the number of word lines included in the second word line group WGR. That is, d may be greater than n/2.

1 5 FIGS.and 1 1 1 1 2 2 11 12 11 1 2 11 1 2 11 10 Referring totogether, the word lines WLto WLd included in the first word line group WGRmay be connected to the first sub-block SUB_BLK, and the word lines WLd+to WLn included in the second word line group WGRmay be connected to the second sub-block SUB_BLK. The storage controllermay select one of a plurality of erase modes according to at least one of an operation schedule and a power consumption of the NVM. In the block erase mode, the storage controllermay perform an erase operation on the block BLK including the first and second sub-blocks SUB_BLKand SUB_BLK. In the sub-block erase mode, the storage controllermay perform an erase operation on the first sub-block SUB_BLKand/or on the second sub-block SUB_BLK. Power consumption resulting from the erase operation according to the sub-block erase mode may be lower than power consumption resulting from the erase operation according to the block erase mode. Accordingly, in the low power mode, the storage controllermay adjust power consumption by controlling the sub-block erase operation and simultaneously prevent performance degradation of the storage device.

6 FIG. 5 FIG. 60 60 50 schematically illustrates an NVMaccording to an embodiment. The NVMmay include or may be similar in many respects to a modified example of the NVMof, and may include additional features not mentioned above. Consequently, a redundant description thereof may be omitted.

6 FIG. 4 FIG.B 4 FIG.B 60 1 1 2 1 2 1 60 1 2 1 2 Referring to, the NVMmay include the common source line CSL and the bit line BL extending in the first horizontal direction HDand the first memory stack STand the second memory stack STextending in the vertical direction VD. That is, the first memory stack STmay be disposed on the upper portion of the common source line CSL, and the second memory stack STmay be disposed on the upper portion of the first memory stack STand connected to the bit line BL through the drain DR. For example, the NVMmay correspond to an example of, and the first memory stack STand the second memory stack STmay respectively correspond to the first memory stack STand the second memory stack STof.

60 1 2 1 2 1 1 2 2 Alternatively or additionally, the NVMmay include a first center dummy word line CDLand a second center dummy word line CDLcorresponding to a junction portion of the first and second memory stacks STand ST. However, the present disclosure is not limited thereto. For example, the number of center dummy word lines corresponding to the junction portion may be variously changed according to some embodiments. According to some optional or additional embodiments, a center dummy word line may not be disposed. In an embodiment, the first memory stack STmay be connected to the first word line group WGR, and the second memory stack STmay be connected to the second word line group WGR.

1 6 FIGS.and 1 1 1 1 2 2 11 60 11 1 2 11 1 2 11 10 Referring totogether, the word lines WLto WLd included in the first word line group WGRmay be connected to the first sub-block SUB_BLK, and the word lines WLd+to WLn included in the second word line group WGRmay be connected to the second sub-block SUB_BLK. The storage controllermay select one of a plurality of erase modes according to at least one of an operation schedule or power consumption of the NVM. In the block erase mode, the storage controllermay perform an erase operation on the block BLK including the first and second memory stacks STand ST. In the stack erase mode, the storage controllermay perform an erase operation on the first memory stack STand/or the second memory stack ST. Power consumption resulting from an erase operation according to the stack erase mode may be lower than power consumption resulting from an erase operation according to the block erase mode. Accordingly, in the low power mode, the storage controllermay adjust power consumption by controlling the stack erase operation and simultaneously prevent performance degradation of the storage device.

7 FIG. 6 FIG. 70 70 60 schematically illustrates an NVMaccording to an embodiment. The NVMmay include or may be similar in many respects to a modified example of the NVMof, and may include additional features not mentioned above. Consequently, a redundant description thereof may be omitted.

7 FIG. 70 1 2 3 1 2 1 3 2 70 1 2 1 2 3 4 2 3 Referring to, the NVMmay include memory stacks (e.g. first memory stack ST, second memory stack ST, and third memory stack ST) extending in the vertical direction VD. That is, the first memory stack STmay be disposed on the upper portion of the common source line CSL, the second memory stack STmay be disposed on the upper portion of the first memory stack ST, and the third memory stack STmay be disposed on the upper portion of the second memory stack STand may be connected to the bit line BL through the drain DR. Alternatively or additionally, the NVMmay include first and second center dummy word lines CDLand CDLcorresponding to a junction portion of the first and second memory stacks STand STand third and fourth center dummy word lines CDLand CDLcorresponding to a junction portion of the second and third memory stacks STand ST.

1 1 2 2 3 3 1 1 2 1 3 1 1 2 3 In an embodiment, the first memory stack STmay be connected to the first word line group WGR, the second memory stack STmay be connected to the second word line group WGR, and the third memory stack STmay be connected to the third word line group WGR. The first word line group WGRmay include word lines WLto WLd, the second word line group WGRmay include word lines WLd+to WLe, and the third word line group WGRmay include word lines WLe+to WLn, where e is a positive integer between d and n. In some embodiments, word lines connected to at least one of the first to third memory stacks ST, ST, and STmay be grouped into a plurality of groups, and an erase operation may be independently performed for each group.

1 7 FIGS.and 1 1 1 1 2 2 1 3 11 70 11 1 2 3 11 1 2 3 11 1 2 3 11 10 Referring totogether, each block BLK may further include a third sub-block, and the word lines WLto WLd included in the first word line group WGRmay be connected to the first sub-block SUB_BLK, the word lines WLd+to WLe included in the second word line group WGRmay be connected to the second sub-block SUB_BLK, and the word lines WLe+to WLn included in the third word line group WGRmay be connected to the third sub-block. The storage controllermay select one of a plurality of erase modes according to at least one of an operation schedule or power consumption of the NVM. In the block erase mode, the storage controllermay perform an erase operation on the block BLK including the first to third memory stacks ST, ST, and ST. In the stack erase mode, the storage controllermay perform an erase operation on the first memory stack ST, the second memory stack ST, or the third memory stack ST. In the multi-stack erase mode, the storage controllermay perform an erase operation on two of the first to third memory stacks ST, ST, and ST. Consequently, power consumption resulting from an erase operation according to the stack erase mode may be lower than power consumption resulting from an erase operation according to the block erase mode. Alternatively or additionally, power consumption resulting from an erase operation according to the stack erase mode may be lower than power consumption resulting from an erase operation according to the multi-stack erase mode. Accordingly, in the low power mode, the storage controllermay adjust power consumption by controlling the stack erase operation and/or the multi-stack erase operation and simultaneously prevent performance degradation of the storage device.

In some embodiments, the NVM may include four or more memory stacks including first to fourth memory stacks extending in the vertical direction VD. For example, in the multi-stack erase mode, the NVM may simultaneously perform an erase operation on at least two memory stacks from among the four or more memory stacks. For example, in the two-stack erase mode, the NVM may simultaneously erase the first and fourth memory stacks, may simultaneously erase the second and third memory stacks, may simultaneously erase the second and fourth memory stacks, may simultaneously erase the first and third memory stacks, may simultaneously erase the first and second memory stacks, and/or may simultaneously erase the third and fourth memory stacks. For another example, in the three-stack erase mode, the NVM may simultaneously erase the first, second and fourth memory stacks, may simultaneously erase the second to fourth memory stacks, and/or may simultaneously erase the first, third, and fourth memory stacks.

8 FIG. 80 is a block diagram illustrating a storage device, according to an embodiment.

8 FIG. 1 FIG. 80 11 12 10 a a Referring to, the storage devicemay include a storage controllerand an NVM, and may include or may be similar in many respects to the storage devicedescribed above with reference to, and may include additional features not mentioned above.

12 1 2 3 1 2 3 1 2 3 1 2 3 a 7 FIG. The NVMmay include a plurality of blocks BLKs. Each block BLK may include a plurality of memory stacks including the first to third memory stacks ST, ST, and ST. Each of the first to third memory stacks ST, ST, and STmay include a plurality of memory cells arranged in a vertical direction. For example, the first to third memory stacks ST, ST, and STmay be respectively connected to the first to third word line groups WGR, WGR, and WGRof.

11 1121 1122 1123 1121 1122 1123 112 1121 1122 1123 11 111 a a 1 FIG. 1 FIG. The storage controllermay include an erase operation request unit, a power consumption estimator, and an erase mode selector. For example, the erase operation request unit, the power consumption estimator, and the erase mode selectormay be included in the erase mode managerof, but the present disclosure is not limited thereto. For example, the erase operation request unit, the power consumption estimator, and the erase mode selectormay be loaded into an operational memory of the storage controller, such as SRAM or DRAM, and executed by a processor (e.g., processorof).

1121 12 20 11 1121 11 20 11 a a a a The erase operation request unitmay request an erase operation with respect to the NVMaccording to a request received from the hostand/or a background operation of the storage controller. In an embodiment, the erase operation request unitmay check a command queue in which commands received from the storage controllerare queued, and request an erase operation based on the commands queued in the command queue. For example, the request received from the hostmay include a write request, a read request, and/or an erase request. For another example, a background operation of the storage controllermay include a garbage collection operation.

1121 12 20 1121 12 20 1121 12 12 1121 12 a a a a a In an embodiment, the erase operation request unitmay request an erase operation on the NVMbefore performing a program operation according to the write request received from the host. In an optional or additional embodiment, the erase operation request unitmay request an erase operation on the NVMaccording to the erase request received from the host. In another optional or additional embodiment, the erase operation request unitmay request an erase operation on the NVMin order to secure a free block in the NVM. In another optional or additional embodiment, the erase operation request unitmay request an erase operation on the NVMaccording to the garbage collection operation.

1122 1122 1121 80 12 1122 80 12 1122 80 12 a a a The power consumption estimatormay estimate power consumption when an erase operation request occurs. That is, the power consumption estimatormay estimate power consumption when an erase operation request is received from the erase operation request unit. For example, the power consumption may include power consumption of the storage device, power consumption of the NVM, current power consumption, future power consumption, and the like. However, the present disclosure is not limited thereto. For example, in some embodiments, the power consumption estimatormay estimate the amount of heat generated by the storage device, the amount of heat generated by the NVM, the amount of currently generated heat, the amount of heat generated in the future, and the like. Alternatively or additionally, in some embodiments, the power consumption estimatormay estimate the temperature of the storage device, the temperature of the NVM, the current temperature, the future temperature, and the like.

1122 12 1122 12 11 1122 12 1122 a a a a In an embodiment, the power consumption estimatormay check an operation schedule of the NVMand estimate power consumption based on the checked operation schedule. For example, the power consumption estimatormay check the operation schedule of the NVMfrom the command queue of the storage controller. Alternatively or additionally, the power consumption estimatormay estimate power consumption based on the type and/or number of commands queued in the command queue. For example, when an intensive read operation and/or program operation is performed on the NVM, the power consumption estimatormay determine that the power consumption is high (e.g., greater than or equal to a threshold value).

1123 1123 1122 1123 1123 12 a. The erase mode selectormay select one of a plurality of erase modes based on power consumption. For example, when an erase operation request occurs, the erase mode selectormay compare the amount of power consumption received from the power consumption estimatorwith a threshold value, and select one of a plurality of erase modes according to a comparison result. The erase mode selectormay select a full block erase mode or a block erase mode when power consumption is smaller than a threshold value. In the block erase mode, the erase mode selectormay control an erase operation on a selected block among the plurality of blocks BLKs of the NVM

1123 1123 1 2 3 12 1123 1 2 3 12 a a. Alternatively or additionally, the erase mode selectormay select a sub-block erase mode when the power consumption is greater than or equal to a threshold value. When the sub-block erase mode is the stack erase mode, the erase mode selectormay control an erase operation on one of the first to third memory stacks ST, ST, and STincluded in the selected block of the NVM. When the sub-block erase mode is the multi-stack erase mode, the erase mode selectormay control an erase operation on two of the first to third memory stacks ST, ST, and STincluded in the selected block of the NVM

11 12 11 12 11 12 a a a a a a As described above, the storage controllermay determine a power mode as a normal power mode or a low power mode by checking the operation schedule and power consumption of the NVM. The storage controllermay select a block erase mode in the normal power mode and control an erase operation on the NVMaccording to the selected block erase mode. Alternatively or additionally, the storage controllermay select a sub-block erase mode in the low power mode and control an erase operation on the NVMaccording to the selected sub-block erase mode.

11 12 11 12 12 10 a a a a a a. For example, the storage controllermay select the sub-block erase mode instead of the block erase mode in the low power mode in which the power consumption is greater than or equal to the threshold value, and control an erase operation on at least one sub-block or memory stack included in the NVMaccording to the selected sub-block erase mode. As described above, the storage controllermay determine the NVMnot to be in an idle state in the low power mode and may apply power throttling to perform a sub-block erase operation on some memory chips, memory dies, and/or memory planes of the NVM, thereby improving performance of the storage device

9 FIG. 10 FIG.A 10 FIG.B 100 100 a b is a flowchart illustrating a method of operating a storage device, according to an embodiment.shows a block erase modeaccording to an embodiment, andshows a sub-block erase modeaccording to an embodiment.

9 10 FIGS.toB 8 FIG. 8 FIG. 900 900 80 Referring totogether, the operating method, according to the present disclosure, may correspond to a method of operating a storage device when an erase operation on an NVM is requested. For example, the operating methodmay include operations performed time-sequentially by the storage deviceof, and the descriptions given above with reference tomay also be applied to the present description.

100 11 110 11 1 1 1 80 a a 8 FIG. In operation S, the storage controllermay check power consumption as described with reference to. In operation S, the storage controllermay determine whether the power consumption is greater than or equal to a first threshold value TH. For example, the first threshold value THmay be previously determined. Alternatively or additionally, the first threshold value THmay be changed during operation of the storage device.

1 110 120 11 100 100 12 12 3 1 2 3 100 12 1 2 1 2 3 100 a b b a a b a b. As a result of determination, when the power consumption is greater than or equal to the first threshold value TH(YES in operation S), in operation S, the storage controllermay select the sub-block erase mode, and according to the sub-block erase mode, may control an erase operation on the NVMfor each sub-block. For example, the NVMmay perform an erase operation on the third memory stack STamong the first to third memory stacks ST, ST, and STaccording to the sub-block erase mode. However, the present disclosure is not limited thereto, and the NVMmay perform an erase operation on the first memory stack STand/or the second memory stack STamong the first to third memory stacks ST, ST, and STaccording to the sub-block erase mode

1 110 130 11 100 100 12 12 1 2 3 100 1 130 11 12 a a a a a a a a Alternatively or additionally, as a result of determination, when the power consumption is less than the first threshold value TH(NO in operation S), in operation S, the storage controllermay select the block erase mode, and according to the block erase mode, may control an erase operation on the NVMfor each block. For example, the NVMmay perform an erase operation on a block including the first to third memory stacks ST, ST, and STaccording to the block erase mode. In some embodiments, as a result of determination, when the power consumption is less than the first threshold value TH, in operation S, the storage controllermay select a full block erase mode, and according to the full block erase mode, may control an erase operation on the NVMfor the full block.

11 FIG. 12 FIG.A 12 FIG.B 120 120 a b is a flowchart illustrating a method of operating a storage device, according to an embodiment.shows a first sub-block erase modeaccording to an embodiment, andshows a second sub-block erase modeaccording to an embodiment.

11 12 FIGS.toB 9 FIG. 1150 900 Referring totogether, the operation method, according to the present disclosure, may correspond to a modified example of the operation methodof, and a redundant description thereof may be omitted.

140 11 2 2 1 2 2 80 a In operation S, the storage controllermay determine whether power consumption is greater than or equal to a second threshold value TH. In an embodiment, the second threshold value THmay be greater than the first threshold value TH. For example, the second threshold value THmay be previously determined. Alternatively or additionally, the second threshold value THmay be changed during operation of the storage device.

2 140 150 11 120 120 12 120 12 1 120 12 2 3 120 a a a a a a a a a. As a result of the determination, when the power consumption is greater than or equal to the second threshold value TH(YES in operation S), in operation S, the storage controllermay select the first sub-block erase mode, and according to the first sub-block erase mode, may control an erase operation on the NVMfor each sub-block. In an embodiment, the first sub-block erase modemay correspond to a stack erase mode. For example, the NVMmay perform an erase operation on the first memory stack STaccording to the first sub-block erase mode. However, the present disclosure is not limited thereto. For example, the NVMmay perform an erase operation on the second memory stack STand/or the third memory stack STaccording to the first sub-block erase mode

2 140 160 11 120 120 12 120 12 2 3 120 12 1 3 1 2 120 a b b a b a b a b. Alternatively or additionally, as a result of the determination, when the power consumption is less than the second threshold value TH(NO in operation S), in operation S, the storage controllermay select the second sub-block erase mode, and according to the second sub-block erase mode, may control an erase operation on the NVMfor a plurality of sub-blocks. In an embodiment, the second sub-block erase modemay correspond to a multi-stack erase mode. For example, the NVMmay perform an erase operation on the second and third memory stacks STand STaccording to the second sub-block erase mode. However, the present disclosure is not limited thereto. For example, the NVMmay perform an erase operation on the first and third memory stacks STand STand/or the first and second memory stacks STand ST, according to the second sub-block erase mode

13 FIG. 14 FIG.A 14 FIG.B 140 140 a b is a flowchart illustrating a method of operating a storage device, according to an embodiment.shows a third sub-block erase modeaccording to an embodiment, andshows a fourth sub-block erase modeaccording to an embodiment.

13 14 FIGS.toB 11 FIG. 1300 1150 Referring totogether, the operation method, according to the present disclosure, may correspond to a modified example of the operation methodof, and a redundant description thereof may be omitted.

170 11 3 3 2 3 3 80 a In operation S, the storage controllermay determine whether the power consumption is greater than or equal to a third threshold value TH. In an embodiment, the third threshold value THmay be greater than the second threshold value TH. In an optional or additional embodiment, the third threshold value THmay be previously determined. Alternatively or additionally, the third threshold value THmay be changed during operation of the storage device.

3 170 180 11 140 140 12 140 12 3 140 12 2 1 140 a a a a a a a a a. As a result of the determination, when the power consumption is greater than or equal to the third threshold value TH(YES in operation S), in operation S, the storage controllermay select the third sub-block erase mode, and according to the third sub-block erase mode, may control an erase operation on the NVMfor each group in a memory stack. In an embodiment, the third sub-block erase modemay correspond to a sub-stack erase mode. For example, the NVMmay perform an erase operation on at least one group included in the third memory stack STaccording to the third sub-block erase mode. However, the present disclosure is not limited thereto. For example, the NVMmay perform an erase operation on at least one group included in the second memory stack STand/or at least one group included in the first memory stack ST, according to the third sub-block erase mode

3 170 190 11 140 140 12 140 12 2 3 140 12 1 3 1 2 140 a b b a b a b a b. Alternatively or additionally, as a result of the determination, when the power consumption is less than the third threshold TH(NO in operation S), in operation S, the storage controllermay select the fourth sub-block erase mode, and according to the fourth sub-block erase mode, may control an erase operation on the NVMfor each group included in each of different memory stacks. In an embodiment, the fourth sub-block erase modemay correspond to a cross-stack erase mode. For example, the NVMmay perform an erase operation on groups included in each of the second and third memory stacks STand STaccording to the fourth sub-block erase mode. However, the present disclosure is not limited thereto. For example, the NVMmay perform an erase operation on groups included in each of the first and third memory stacks STand STand/or groups included in each of the first and second memory stacks STand ST, according to the fourth sub-block erase mode

15 FIG. 150 is a block diagram illustrating a storage device, according to an embodiment.

15 FIG. 8 FIG. 8 14 FIGS.toB 150 11 12 150 80 150 a b Referring to, the storage devicemay include the storage controllerand the NVM. The storage devicemay include or may be similar in many respects to a modified example of the storage deviceof, and may include additional features not mentioned above. Consequently, detailed descriptions given above with reference tomay also be applied to the storage device.

12 1 2 1 1211 1212 1213 2 1214 1215 1216 b The NVMmay include a plurality of memory groups including first and second memory groups MGand MG. According to some embodiments, a plurality of memory groups may be referred to as a plurality of NVMs. The first memory group MGmay include a plurality of memory stacks including first to third memory stacks,, and, and the second memory group MGmay include a plurality of memory stacks including first to third memory stacks,, and.

11 1 2 1 2 11 1 2 12 11 a a b a The storage controllermay select erase modes respectively corresponding to the first and second memory groups MGand MG, and independently perform an erase operation on the first and second memory groups MGand MG. For example, the storage controllermay control an erase operation on the first memory group MGaccording to a first erase mode and an erase operation on the second memory group MGaccording to a second erase mode. That is, when an erase operation is performed on the NVMaccording to the sub-block erase mode, and a free space corresponding to a block unit is required, the storage controllermay perform a sub-block erase operation on a plurality of blocks and/or a plurality of memory groups.

1 2 11 1 2 11 a a In an embodiment, the first and second memory groups MGand MGmay respectively correspond to first and second memory chips. Alternatively or additionally, the storage controllermay control an erase operation for each memory chip according to erase modes respectively corresponding to the first and second memory chips. In an optional or additional embodiment, the first and second memory groups MGand MGmay respectively correspond to first and second memory dies, and the storage controllermay control an erase operation for each memory die according to erase modes respectively corresponding to the first and second memory dies. In such an embodiment, the memory chip may include a plurality of memory dies.

1 2 11 a For another example, the first and second memory groups MGand MGmay respectively correspond to first and second memory planes, and the storage controllermay control an erase mode for each memory plane according to erase modes respectively corresponding to the first and second memory planes. In such an example, the memory die may include a plurality of memory planes, and operations on the plurality of memory planes may be independently performed.

16 FIG. 160 illustrates a storage devicecontrolling an erase mode for each memory die, according to an embodiment.

16 FIG. 15 FIG. 15 FIG. 160 161 162 161 11 162 12 a b Referring to, the storage devicemay include a storage controllerand an NVM. The storage controllermay include or may be similar in many respects to an example of the storage controllerof, and the NVMmay include or may be similar in many respects to an example of the NVMof.

162 1 8 1 8 1 4 161 1 5 8 161 2 15 FIG. In an embodiment, the NVMmay include first to eighth memory dies DIEto DIE. In such an embodiment, the first to eighth memory dies DIEto DIEmay correspond to an example of the plurality of memory groups of. For example, the first to fourth memory dies DIEto DIEmay communicate with the storage controllerthrough a first channel CH, and the fifth to eighth memory dies DIEto DIEmay communicate with the storage controllerthrough a second channel CH.

1 4 6 8 161 162 161 5 5 For example, when a read operation RD_op is performed on the first to fourth memory dies DIEto DIEand the sixth to eighth memory dies DIEto DIE, the storage controllermay determine that an intensive read operation is performed on the volatile memory. In such an example, the storage controllermay determine the erase mode of the fifth memory die DIEas a sub-block erase mode SUB-BLK ERS, and may perform an erase operation on at least one sub-block of a selected block included in the fifth memory die DIE.

1 4 6 8 161 162 161 5 5 However, the present disclosure is not limited thereto. For example, when a program operation is performed on the first to fourth memory dies DIEto DIEand the sixth to eighth memory dies DIEto DIE, the storage controllermay determine that an intensive program operation is performed on the volatile memory. In such an example, the storage controllermay determine the erase mode of the fifth memory die DIEas the sub-block erase mode SUB-BLK ERS, and may perform an erase operation on at least one sub-block of the selected block included in the fifth memory die DIE.

17 FIG. 170 illustrates a storage devicecontrolling an erase mode for each memory die, according to an embodiment.

17 FIG. 16 FIG. 170 171 172 170 160 Referring to, the storage devicemay include a storage controllerand an NVM. The storage devicemay include or may be similar in many respects to a modified example of the storage deviceof, and may include additional features not mentioned above. Consequently, a redundant description thereof may be omitted.

1 4 7 8 171 172 171 5 5 171 6 6 In an embodiment, when the read operation RD_op is performed on the first to fourth memory dies DIEto DIEand the seventh and eighth memory dies DIEand DIE, the storage controllermay determine that an intensive read operation is performed on the NVM. In such an embodiment, the storage controllermay determine the erase mode of the fifth memory die DIEas the sub-block erase mode SUB-BLK ERS, and may perform an erase operation on at least one sub-block of a selected block included in the fifth memory die DIE. Alternatively or additionally, the storage controllermay determine the erase mode of the sixth memory die DIEas a full block erase mode FULL-BLK ERS and/or a block erase mode, and may perform an erase operation on a selected block and/or full blocks included in the sixth memory die DIE.

18 FIG. 180 illustrates a storage devicecontrolling an erase mode for each memory chip, according to an embodiment.

18 FIG. 15 FIG. 15 FIG. 180 181 182 181 11 182 12 a b Referring to, the storage devicemay include a storage controllerand an NVM. The storage controllermay include or may be similar in many respects to an example of the storage controllerof, and the NVMmay include or may be similar in many respects to an example of the NVMof, and may include additional features not mentioned above.

182 1 2 1 2 1 181 1 2 181 2 1 1 4 2 5 8 15 FIG. In an embodiment, the NVMmay include a first memory chip CHIPand a second memory chip CHIP. In such an embodiment, the first and second memory chips CHIPand CHIPmay correspond to an example of the plurality of memory groups of. For example, the first memory chip CHIPmay communicate with the storage controllerthrough the first channel CH, and the second memory chip CHIPmay communicate with the storage controllerthrough the second channel CH. For another example, the first memory chip CHIPmay include the first to fourth memory dies DIEto DIE, and the second memory chip CHIPmay include the fifth to eighth memory dies DIEto DIE.

1 1 4 1 181 182 1 181 2 5 8 2 When an intensive read operation or program operation is performed on the first memory chip CHIP(e.g., when the read operation RD_op is performed on the first to fourth memory dies DIEto DIEof the first memory chip CHIP), the storage controllermay determine that an intensive read operation is performed on the NVM(e.g., the first memory chip CHIP). In such an example, the storage controllermay determine the erase mode of the second memory chip CHIPas the sub-block erase mode SUB-BLK ERS, and may control an erase operation with respect to the fifth to eighth memory dies DIEto DIEincluded in the second memory chip CHIPfor each sub-block.

1 4 1 181 182 1 181 2 5 8 2 However, the present disclosure is not limited thereto. For example, when a program operation is performed on the first to fourth memory dies DIEto DIEof the first memory chip CHIP, the storage controllermay determine that an intensive program operation is performed on the NVM(e.g., the first memory chip CHIP). In such an example, the storage controllermay determine the erase mode of the second memory chip CHIPas the sub-block erase mode SUB-BLK ERS, and may control an erase operation with respect to the fifth to eighth memory dies DIEto DIEincluded in the second memory chip CHIPfor each sub-block.

19 FIG. 190 illustrates a storage devicecontrolling an erase mode for each memory chip, according to example embodiments.

19 FIG. 18 FIG. 190 191 192 190 180 Referring to, the storage devicemay include a storage controllerand an NVM. The storage devicemay include or may be similar in many respects to a modified example of the storage deviceof, and may include additional features not mentioned above. Consequently, a redundant description thereof may be omitted.

3 4 1 191 1 2 191 1 2 1 191 5 8 2 In an embodiment, when the read operation RD_op or a program operation is performed on the third and fourth memory dies DIEand DIEof the first memory chip CHIP, the storage controllermay determine the full block erase mode FULL-BLK ERS and/or a block erase mode with respect to the first memory chip CHIP, and may determine the sub-block erase mode SUB-BLK ERS with respect to the second memory chip CHIP. Accordingly, the storage controllermay control an erase operation with respect to the first and second memory dies DIEand DIEof the first memory chip CHIPfor each block. Alternatively or additionally, the storage controllermay control an erase operation with respect to the fifth to eighth memory dies DIEto DIEof the second memory chip CHIPfor each sub-block.

20 FIG. 200 illustrates a storage devicecontrolling an erase mode for each memory plane, according to an embodiment.

20 FIG. 15 FIG. 15 FIG. 200 201 202 201 11 202 12 a b Referring to, the storage devicemay include a storage controllerand an NVM. The storage controllermay include or may be similar in many respects to an example of the storage controllerof, and the NVMmay include or may be similar in many respects to an example of the NVMof, and may include additional features not mentioned above.

202 1 8 1 8 1 2 1 2 1 4 201 1 5 8 201 2 15 FIG. In an embodiment, the NVMmay include the first to eighth memory dies DIEto DIE, and each of the first to eighth memory dies DIEto DIEmay include a first memory plane PLand a second memory plane PL. In such an embodiment, the first and second memory planes PLand PLmay correspond to an example of the plurality of memory groups of. For example, the first to fourth memory dies DIEto DIEmay communicate with the storage controllerthrough the first channel CH, and the fifth to eighth memory dies DIEto DIEmay communicate with the storage controllerthrough the second channel CH.

1 2 2 201 2 5 201 1 1 When a read operation and/or a program operation is performed on one of the first and second memory planes PLand PL(e.g., when the read operation RD_op is performed on the second memory plane PL), the storage controllermay determine that an intensive read operation is performed on the second memory plane PLof the fifth memory die DIE. In such an example, the storage controllermay determine the erase mode of the first memory plane PLas the sub-block erase mode SUB-BLK ERS, and may control the erase operation with respect to the first memory plane PLfor each sub-block.

21 FIG. 210 illustrates a storage devicecontrolling an erase mode for each memory plane, according to an embodiment.

21 FIG. 20 FIG. 210 211 212 210 200 Referring to, a storage devicemay include a storage controllerand an NVM. The storage devicemay include or may be similar in many respects to a modified example of the storage deviceof, and may include additional features not mentioned above. Consequently, a redundant description thereof may be omitted.

1 6 8 211 1 2 5 211 1 5 2 5 211 1 5 211 2 5 In an embodiment, when the read operation RD_op is performed on the first to fourth memory dies DIEto DI4 and the sixth to eighth memory dies DIEto DIE, the storage controllermay respectively determine erase modes corresponding to the first and second memory planes PLand PLof the fifth memory dies DIE. For example, the storage controllermay determine the sub-block erase mode SUB-BLK ERS with respect to the first memory plane PLof the fifth memory die DIE, and the full block erase mode FULL-BLK ERS and/or a block erase mode with respect to the second memory plane PLof the fifth memory die DIE. Accordingly, the storage controllermay control an erase operation with respect to the first memory plane PLof the fifth memory die DIEfor each sub-block. Alternatively or additionally, the storage controllermay control an erase operation with respect to the second memory plane PLof the fifth memory die DIEfor each block.

22 FIG. is a flowchart illustrating a method of operating a storage device, according to an embodiment.

22 FIG. 1 FIG. 1 21 FIGS.to 11 12 Referring to, the operating method, according to the present disclosure, may be performed by, for example, the storage controllerand the NVMof. The detailed descriptions given above with reference tomay also be applied to the present embodiment, and redundant descriptions may be omitted.

200 11 210 11 220 11 230 11 240 11 12 270 12 280 12 11 In operation S, the storage controllermay generate an erase operation request. In operation S, the storage controllermay check power consumption. In operation S, the storage controllermay select an erase mode. In operation S, the storage controllermay generate an erase command E_CMD. In operation S, the storage controllermay transmit the erase command E_CMD including erase mode information EM to the NVM. In operation S, the NVMmay perform an erase operation based on an erase mode in response to the erase command E_CMD. In operation S, the NVMmay transmit a response indicating completion of the erase operation to the storage controller.

23 FIG. is a flowchart illustrating a method of operating a storage device, according to an embodiment.

23 FIG. 1 FIG. 22 FIG. 1 22 FIGS.to 11 12 Referring to, the operating method, according to the present disclosure, may be performed, for example, by the storage controllerand the NVMof, and may include or may be similar in many respects to a modified example of the operating method of. Accordingly, the contents described above with reference tomay also be applied to the present embodiment, and redundant descriptions may be omitted.

200 11 210 11 220 11 235 11 245 11 12 250 11 260 11 12 270 12 280 12 11 In operation S, the storage controllermay generate an erase operation request. In operation S, the storage controllermay check power consumption. In operation S, the storage controllermay select an erase mode. In operation S, the storage controllermay generate the erase command E_CMD. In operation S, the storage controllermay transmit the erase command E_CMD to the NVM. In operation S, the storage controllermay generate an erase mode command EM_CMD. In operation S, the storage controllermay transmit the erase mode command EM_CMD to the NVM. In operation S, the NVMmay perform an erase operation based on an erase mode in response to the erase command E_CMD. In operation S, the NVMmay transmit a response indicating completion of the erase operation to the storage controller.

24 FIG. 24 FIG. 24 FIG. 1000 1000 1000 is a diagram of a systemto which a storage device may be applied, according to an embodiment. The systemofmay be and/or may include, but not be limited to, a mobile system, such as a portable communication terminal (e.g., a mobile phone), a smartphone, a tablet, a personal computer (PC), a wearable device, a healthcare device, an Internet of things (IoT) device, or the like. However, the systemofmay not be limited to the mobile system and may be and/or include another electronic device such as, but not be limited to, a PC, a laptop computer, a server, a media player, an automotive device (e.g., a navigation device), or the like.

24 FIG. 1000 1100 1200 1200 1300 1300 1000 1410 1420 1430 1440 1450 1460 1470 1480 a b a b Referring to, the systemmay include a main processor, memories (e.g.,and), and storage devices (e.g.,and). Alternatively or additionally, the systemmay include at least one of an image capturing device, a user input device, a sensor, a communication device, a display, a speaker, a power supplying device, and a connecting interface.

1100 1000 1100 1000 1100 The main processormay control the operations of the system. Alternatively or additionally, the main processormay control operations of other components included in the system. The main processormay be implemented as a general-purpose processor, a dedicated processor, and/or an application processor.

1100 1110 1120 1200 1200 1300 1300 1100 1130 1100 a b a b The main processormay include at least one CPU core, and/or further include a controllerconfigured to control the memoriesandand/or the storage devicesand. In some embodiments, the main processormay further include an accelerator 1130, which may be and/or may include a dedicated circuit for a high-speed data operation, such as, but not limited to, an artificial intelligence (AI) data operation. For example, the acceleratormay include a graphics processing unit (GPU), a neural processing unit (NPU) and/or a data processing unit (DPU) and/or be implemented as a chip that may be physically separate from the other components of the main processor.

1200 1200 1000 1200 1200 1200 1200 1100 a b a b a b The memoriesandmay be used as main memory devices of the system. Each of the memoriesandmay include a volatile memory, such as, but not be limited to, SRAM and/or DRAM, and/or non-volatile memory, such as, but not be limited to, a flash memory, PRAM, and/or resistive RAM (ReRAM). In some embodiments, the memoriesandmay be implemented in the same package as the main processor.

1300 1300 1200 1200 1300 1300 1310 1310 1320 1320 1310 1310 1320 1320 1320 1320 a b a b a b a b a b a b a b a b The storage devicesandmay serve as non-volatile storage devices configured to store data regardless of whether power has been supplied thereto, and may have a larger storage capacity than the memoriesand. The storage devicesandmay respectively include storage controllersandand flash memoriesand(e.g., NVMs) configured to store data via the control of the storage controllersand. Although the flash memoriesandmay include flash memories having a 2D structure and/or a 3D V-NAND structure, the flash memoriesandmay include other types of NVMs, such as, but not limited to, PRAM and/or ReRAM.

1300 1300 1100 1000 1100 1300 1300 1000 1480 1300 1300 a b a b a b The storage devicesandmay be physically separated from the main processorand be included in the systemand/or implemented in the same package as the main processor. Alternatively or additionally, the storage devicesandmay have types of solid-state devices (SSDs) and/or memory cards and may be removably combined with other components of the systemthrough an interface, such as a connecting interface. The storage devicesandmay be devices to which a memory storage standard protocol, such as, but not limited to, a UFS protocol, an eMMC protocol, or an NVMe protocol, may be applied, without being limited thereto.

1410 1410 The image capturing devicemay capture still images and/or moving images. The image capturing devicemay include, but not limited to, a camera, a camcorder, and/or a webcam.

1420 1000 The user input devicemay receive various types of data input by a user of the systemand may include, but not limited to, a touch pad, a keypad, a keyboard, a mouse, and/or a microphone.

1430 1000 1430 The sensormay detect various types of physical quantities, which may be obtained from the outside of the system, and convert the detected physical quantities into electric signals. The sensormay include, but not limited to, a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, a gyroscope sensor, and/or the like.

1440 1000 1440 The communication devicemay transmit and/or receive signals between other devices outside the systemaccording to various communication protocols. The communication devicemay include, but not limited to, an antenna, a transceiver, a modem, and/or the like.

1450 1460 1000 The displayand the speakermay serve as output devices configured to output visual information and auditory information, respectively, to the user of the system.

1470 1000 1000 The power supplying devicemay convert power supplied from a battery (not shown) embedded in the systemand/or an external power source, and supply the converted power to each of components of the system.

1480 1000 1000 1000 1480 1394 The connecting interfacemay provide connections between the systemand external devices, which may be connected to the systemand may be capable of transmitting and/or receiving data to and/or from the system. The connecting interfacemay be implemented by using various interface schemes, such as, but not limited to, advanced technology attachment (ATA), serial ATA (SATA), external SATA (e-SATA), small computer small interface (SCSI), serial attached SCSI (SAS), PCI, PCIe, NVMe, Institute of Electrical and Electronics Engineers (IEEE)(FireWire), a universal serial bus (USB) interface, a secure digital (SD) card interface, a multi-media card (MMC) interface, an eMMC interface, a UFS interface, an embedded UFS (eUFS) interface, a compact flash (CF) card interface, and the like.

While the present disclosure has been particularly shown and described with reference to embodiments thereof, it is to be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.