Flip-Flops with Multiple Data Retention Paths

The present disclosure relates to flip-flop circuits and, more particularly, to embodiments of a low-power, reduced-area, flip-flop circuit suitable for both high and low frequency clock-controlled operation.

Various different types of circuit structures (e.g., memory circuits, counters, shift registers, etc.) employ data flip-flops. Data flip-flops are also known in the art as delay flip-flops, D-type flip-flops, or D flip-flops and are hereinafter referred to as D flip-flops. D flip-flops are circuits configured to receive a data input (D), to temporarily store the data, and to subsequently output a data output (Q) that reflects D and/or an inverted data output (Qb) that is inverted with respect to D. D flip-flop processing is controlled by a clock input (CK) and is typically edge triggered. For example, a D flip-flop may be configured so that Q switches to reflect the current value of D only when CK transitions from low to high. Thus, as CK transitions from low to high, Q will switch to reflect the current value D. As CK transitions back from high to low, Q should maintain the current value of D. D flip-flops are relatively large (e.g., include twenty-four transistors), consume a significant amount of power, and require the use of a constant frequency CK and plus multiple versions of CK (i.e., multiple phases of CK). Recently, D flip-flops have been developed that rely on a single phase CK and that are also smaller in area, faster and consume less power than conventional D flip-flops. However, these D flip-flops require CK to be dynamic (e.g., toggling at a constant frequency) to avoid loss of data. That is, if CK is static for some extended period of time, stored data may be lost.

Disclosed embodiments of a flip-flop can include a first stage and a second stage. The first stage can have a first intermediate node. The second stage can be connected to the first stage and can include a second intermediate node and a third intermediate node. The second stage can further include a pair of node-controlled transistors, which are connected in series between a voltage rail and the second intermediate node. The first intermediate node of the first stage and the third intermediate node of the second stage can be connected to gates of different ones of the node-controlled transistors in the pair.

More specifically, in some embodiments disclosed herein, a flip-flop can include a first stage and a second stage. The first stage can include a first intermediate node. The second stage can be connected to the first stage and can include a second intermediate node and a third intermediate node. The second stage can further include a pair of node-controlled transistors (e.g., P-type field effect transistors (PFETs)), which are connected in series between a positive voltage rail and the second intermediate node. The first intermediate node of the first stage and the third intermediate node of the second stage can be connected to gates of different ones of the node-controlled transistors in the pair.

In other embodiments disclosed herein, a flip-flop can include a first stage and a second stage. The first stage can include a first intermediate node. The second stage can be connected to the first stage and can include a second intermediate node and a third intermediate node. The second stage can further include a pair of node-controlled transistors (e.g., N-type field effect transistors (NFETs)), which are connected in series between the second intermediate node and a ground rail. The first intermediate node of the first stage and the third intermediate node of the second stage can be connected to gates of different ones of the node-controlled transistors in the pair.

It should be noted that all aspects, examples, and features of disclosed embodiments mentioned in the summary above can be combined in any technically possible way. That is, two or more aspects of any of the disclosed embodiments, including those described in this summary section, may be combined to form implementations not specifically described herein. The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features, objects and advantages will be apparent from the description and drawings, and from the claims.

As mentioned above, D flip-flops are circuits configured to receive a data input (D), to temporarily store the data, and to subsequently output a data output (Q) that reflects D and/or an inverted data output (Qb) that is inverted with respect to D. D flip-flop processing is controlled by a clock input (CK) and is typically edge triggered. For example, a D flip-flop may be configured so that Q switches to reflect the current value of D only when CK transitions from low to high. Thus, as CK transitions from low to high, Q will switch to reflect the current value D. As CK transitions back from high to low, Q should maintain the current value of D. D flip-flops are relatively large (e.g., include twenty-four transistors), consume a significant amount of power, and require the use of a constant frequency CK and plus multiple versions of CK (i.e., multiple phases of CK). Recently, D flip-flops have been developed that rely on a single phase CK and that are also smaller in area, faster and consume less power than conventional D flip-flops. However, these D flip-flops require CK to be dynamic (e.g., toggling at a constant frequency) to avoid loss of data. That is, if CK is static for some extended period of time, stored data may be lost.

In view of the foregoing, disclosed herein are embodiments of a D flip-flop, which is smaller in area, faster, and consumes less power than a conventional D flip-flop and which is further configured with a combination of data retentions paths (including a feedforward path, a feedback path, and a feedback loop) to avoid data loss if/when a clock signal that controls flip-flop operation is static for some extended period of time and a data input signal (D) changes states. More specifically, in the disclosed embodiments, the D flip-flop includes first and second stages. The first stage can include, among other components, a first intermediate node (also referred to herein as a pre-charge node). The second stage can be connected to the first stage and can include, among other components, a second intermediate node (also referred to herein as a data transfer node) and a third intermediate node (also referred to herein as a data retention node). The second stage can also include a pair of transistors, which are connected in series between the second intermediate node and either a positive voltage rail or a ground rail (depending upon the embodiment), and which are controlled by voltage levels of signals on the first and third intermediate nodes. That is, the first and third intermediate nodes can be connected to the gates of different ones of the transistors in the pair in order to provide both feedforward and feedback paths for maintaining the voltage level of the signal on the second intermediate node when a clock signal controlling flip-flop operation is static and the second intermediate node is floating.

Optionally, the second stage can also include a feedback loop (including an inverter and a multi-phase clock-controlled tri-state logic device connected in series from and back to the third intermediate node) for maintaining the voltage level of a signal on the third intermediate node when the clock signal is static and the third intermediate node is floating. It should be noted that in the disclosed embodiments, operation of the D flip-flop can be controlled by a single-phase clock signal, except in the feedback loop where the multiphase clock-controlled tri-state logic device is controlled by both clock and inverted clock signals, as discussed in greater detail below.

1 FIG. 100 100 1 2 1 More particularly,is a schematic diagram illustrating an embodiment of a D flip-flop. D flip-flopcan include a first stage (S) (also referred to herein as an input stage or primary stage) and a second stage (S) (also referred to herein as an output stage or secondary stage) connected to S.

1 115 1 110 110 111 112 113 199 198 111 111 113 113 115 112 112 101 110 116 112 113 112 113 1 116 1 g g g Scan include a data input node, which is electrically connected to receive a data input (D). Scan further include a first single phase clock-controlled tri-state logic device(herein after referred to as first SPCTSL). For purposes of this disclosure, a single phase clock-controlled tri-state logic device is a tri-state logic device that outputs an output signal, which is high (i.e., logic 1, such as at VDD), low (i.e., logic 0, such as at ground or 0.0V), or floating depending on the states of a single clock signal and an input signal. A multiphase clock-controlled tri-state logic device is a tri-state logic device that outputs an output signal, which is high (i.e., logic 1), low (i.e., logic 0), or floating depending on the states of at least two clock signals (e.g., an clock signal and an inverted clock signal) and an input signal. First SPCTSLcan include a stack of first transistors including a first P-type field effect transistor (PFET), an additional first PFET, and a first N-type field effect transistor (NFET), which are electrically connected in series between a positive voltage railat a positive supply voltage (VDD) level and a ground rail(e.g., at 0.0 volts (V)). In some embodiments, VDD can be 0.8V. Alternatively, VDD could be at any other suitable positive supply voltage level (e.g., given the processing technology node at which the flip-flop is designed). Gateof first PFETand gateof first NFETcan be electrically connected to data input nodeto receive D. Gateof additional first PFETcan be electrically connected to receive a clock signal (CKM) from a clock signal generator(also referred to herein as a clock generation circuit), as discussed in greater detail below. First SPCTSLcan further include a first intermediate nodeat the junction between additional first PFETand first NFET(i.e., at the electrical connection between additional first PFETand first NFET). A first intermediate signal (I) can be output at first intermediate node. The state of Ican be high, low, or floating depending upon the states of D and CKM.

2 120 120 121 123 124 199 198 121 121 124 124 123 123 116 1 120 126 121 123 121 123 2 126 2 1 g g g Scan include a second single phase clock-controlled tri-state logic device(hereinafter referred to as second SPCTSL). Second SPCTSLcan include a stack of second transistors including a second PFET, a second NFET, and an additional second NFET, which are electrically connected in series between positive voltage railand ground rail. Gateof second PFETand gateof additional second NFETcan be electrically connected to receive CKM. Gateof second NFETcan be electrically connected to first intermediate nodeto receive I. Second SPCTSLcan further include a second intermediate nodeat the junction between second PFETand second NFET(i.e., at the electrical connection between second PFETand second NFET). A second intermediate signal (I) can be output at second intermediate nodeand the state of Ican be high, low, or floating depending upon the states of Iand CKM.

2 130 130 131 133 134 199 198 131 131 134 134 126 2 133 133 130 136 131 133 131 133 3 136 3 2 g g g Scan further include a third single phase clock-controlled tri-state logic device(hereinafter referred to as third SPCTSL). Third SPCTSLcan include a third PFET, a third NFET, and an additional third NFET, which are electrically connected in series between positive voltage railand ground rail. Gateof third PFETand gateof additional third NFETcan be electrically connected to second intermediate nodeto receive I. Gateof third NFETcan be electrically connected to receive CKM. Third SPCTSLcan further include a third intermediate nodeat the junction between third PFETand third NFET(i.e., at the electrical connection between third PFETand third NFET). A third intermediate signal (I) can be output at third intermediate nodeand the state of Ican be high, low, or floating depending upon the states of Iand CKM.

2 140 140 141 142 199 126 141 141 136 3 192 136 141 126 142 142 116 1 191 116 142 126 192 191 1 3 141 142 2 126 g g Scan further include a stackof fourth transistors. Stackcan include a fourth PFETand an additional fourth PFET, which are electrically connected in series between positive voltage railand second intermediate node. Gateof fourth PFETcan be electrically connected to third intermediate nodeto receive I, thereby creating a feedback pathfrom third intermediate nodeto fourth PFETto assist in maintaining a high voltage level on second intermediate nodewhen necessary. Furthermore, gateof additional fourth PFETcan be electrically connected to first intermediate nodeto receive I, thereby creating a feedforward pathfrom first intermediate nodeto additional fourth PFETto further assist in maintaining a high voltage level on second intermediate nodewhen necessary. For example, given the feedback pathand feedforward pathmentioned above, when Iand Iare both at low volage levels, fourth PFETand additional fourth PFETwill both be on (i.e., conductive) to keep the voltage level on Ihigh if second intermediate nodeis floating, as discussed in greater detail below.

2 150 160 136 136 170 136 Scan further include an inverterand a multiphase clock-controlled tri-state logic device(hereinafter referred to as MPCTSL), which are electrically connected in series with third intermediate nodeand further arranged in a loop back to third intermediate node(as discussed in greater detail below) and/or an additional inverter, which is also electrically connected in series with third intermediate node.

2 150 150 151 153 199 198 151 151 153 153 136 3 150 156 151 153 151 153 150 156 100 170 4 170 100 4 3 160 161 162 163 164 199 198 161 161 164 164 156 4 162 162 163 163 160 166 162 163 162 163 166 4 166 136 193 3 g g g g g g Specifically, Scan include an inverter. Invertercan include a fifth PFETand a fifth NFET, which are electrically connected in series between positive voltage railand ground rail. A gateof fifth PFETand a gateof fifth NFETcan each be electrically connected to third intermediate nodeto receive I. Invertercan further include a node(which is a data output node or a fourth intermediate node) at the junction between fifth PFETand fifth NFET(i.e., at the electrical connection between fifth PFETand fifth NFET). The output signal of inverterat nodecan be either the data output signal (Q) of D flip-flopin the absence of an additional inverteror a fourth intermediate signal (I) when additional inverteris included in D flip-flopfor generating Q (as discussed below). In any case, Q (or I, which has the same state as Q) will be low when Iis high and vice versa. MPCTSLcan include a stack of sixth transistors including a sixth PFET, an additional sixth PFET, a sixth NFET, and an additional sixth NFET, which are electrically connected in series between positive voltage railand ground rail. Gateof sixth PFETand gateof additional sixth NFETcan be electrically connected to nodeto receive Q (or I). Furthermore, gateof additional sixth PFETcan be electrically connected to receive CKM, whereas gateof sixth NFETcan be electrically connected to receive an inverted clock signal (CKN). CKN can be inverted relative to CKM and, particularly, can has the same properties in terms of frequency, etc., but in an opposite polarity relative to CKM. MPCTSLcan further include a sixth intermediate nodeat the junction between additional sixth PFETand sixth NFET(i.e., at the electrical connection between additional sixth PFETand sixth NFET). A feedback signal (Ifb) can be output at sixth intermediate nodeand the state of Ifb can be high, low, or floating depending upon the states of Q (or I), CKM and CKN. Sixth intermediate nodecan be electrically connected to back to third intermediate node, thereby forming a feedback loopfor maintaining Ieither high or low when CKM is low and CKN is high.

170 171 173 199 198 171 171 173 173 136 3 170 176 171 173 171 173 176 4 3 3 g g Additional invertercan include a seventh PFETand a seventh NFET, which are electrically connected in series between positive voltage railand ground rail. Gateof seventh PFETand gateof seventh NFETcan each be electrically connected to third intermediate nodeto receive I. Additional invertercan further include a data output nodeat the junction between seventh PFETand seventh NFET(i.e., at the electrical connection between seventh PFETand seventh NFET). A data output signal (Q) can be output at data output nodeand the state of Q will be the same as I. Specifically, Q will depend upon the state of I(i.e., when Iis high, Q will be low and vice versa).

100 193 101 101 102 103 102 103 100 101 100 1 FIG. Thus, in D flip-flopdescribed above and illustrated in, operation is primarily controlled by one clock signal (i.e., CKM) and only operation of feedback loopis controlled by two clock signals (i.e., CKM and CKN). CKM and CKN can be generated by a clock signal generator. Clock signal generatorcan, for example, include a pair of series-connected invertersand. Invertercan be connected to receive a system clock signal (CK) and can invert CK to output CKN. Invertercan be connected to receive CKN and can invert CKN to output CKM. Thus, CKN is inverted relative to both CK and CKM. Since D flip-floponly requires CKM and CKN to operate, clock signal generatoris relatively small. That is, it has fewer inverters and/or delay buffers than clock signal generators used for other D flip-flops that require more than two different clock phases to operate. Additionally, since there are a relatively small number of transistors in D flip-flopcontrolled by these clock signals (e.g., only one transistor controlled by CKN and only five transistor controlled by CKM), clock driver size can be reduced.

2 FIG. 1 FIG. 2 FIG. 2 FIG. 100 111 113 112 1 116 1 123 124 126 121 126 2 2 131 3 2 134 133 136 136 3 3 4 is a table illustrating different possible states of nodes with D flip-flopupon power up. Referring toin combination with, if CKM and D are both low at power up, then first PFETwill be on, first NFETwill be off, and additional first PFETwill be on. Thus, Iat first intermediate nodewill be pulled up. When Iis high, second NFETwill turn on. However, since CKM is low, additional second NFETwill be off and, thus, will prevent the voltage level on second intermediate nodefrom being pulled down. Additionally, second PFETwill be turned on and will pull up the voltage level on second intermediate nodeso Iwill be high. When Iis high, third PFETwill be off and will prevent the voltage level on third intermediate node Ifrom being pulled up. Furthermore, when Iis high, additional third NFETwill be on. However, since CKM is low, third NFETwill be off and will prevent the voltage level on third intermediate nodefrom being pulled down. Thus, the voltage level at third intermediate nodewill be floating and Ishould maintain the same state as it had at power down, as indicated by an ‘x’ in the table of. Since Imaintains the same state it had at power down, so will Q (I).

112 111 116 113 116 1 1 121 126 2 136 3 4 If CKM is low and D is high at power up, then additional first PFETwill be on, but first PFETwill be off and will prevent the voltage level on first intermediate nodefrom being pulled up. Additionally, first NFETwill be on, pulling down the voltage level on first intermediate node. Thus, Iwill be low. When Iis low and CKM is also low, second PFETwill turn on and pull up the voltage level on second intermediate node. When Iis high and CKM is low, third intermediate nodewill be floating. So, as discussed above, Iand Q (I) should maintain the states (high or low) that they had before power down.

111 112 116 113 116 116 126 136 1 2 3 4 If CKM is high and D is low at power up, then first PFETwill be on, but additional first PFETwill be off and will prevent the voltage level on first intermediate nodefrom being pulled up. Additionally, first NFETwill be off and will prevent the voltage level on first intermediate nodefrom being pulled down. Thus, first intermediate node, second intermediate node, and third intermediate nodewill all be floating and I, I, Iand Q (I) will maintain the states (high or low) that they had before power down.

111 112 116 113 116 1 121 126 124 123 1 126 126 2 3 4 If CKM is high and D is also high at power up, then first PFETand additional first PFETwill both be off and will prevent the voltage level on first intermediate nodefrom being pulled up. First NFETwill be on and will pull the voltage level on first intermediate nodedown to ground. When CKM is high and Iis low, second PFETwill be off and will prevent the voltage level on the second intermediate nodefrom being pulled up. Additionally, additional second NFETwill be on because CKM is high. However, second NFETwill be off because Iis low and will prevent the voltage level on second intermediate nodefrom being pulled down. Thus, second intermediate nodewill be floating and I, Iand Q (I) will maintain the states (high or low) that they had before power down.

3 FIG. 1 1 is a table illustrating four examples A-D of multiple possible states of D and I-Q when CKM is low and how those states change when CKM transitions from low to high and further illustrating another four examples E-H of possible states of D and I-Q when CKM is high and how those states will change when CKM transitions from high to low.

4 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 As illustrated in examples A-D, Q (I) will either remain unchanged or will change so that it is the same as D during any transition of CKM from low to high. For example, in example A, if CKM and D are currently low and Iis high, Iis high, Iis low, and Q is high, transitioning of CKM from low to high (i.e., the rising edge of CKM) will cause Ito stay high, Ito go low, Ito go high, and Q to go low. Thus, Q changes to reflect the same state as D. In example B, if CKM and D are currently low, and Iis high, Iis high, Iis high, and Q is low, transitioning of CKM from low to high will cause Ito stay high, Ito go low, Ito stay high, and Q to stay low. Thus, Q remains unchanged to reflect the same state as D. In example C, if CKM is currently low and D is currently high and if Iis low, Iis high, Iis low, and Q is high, transitioning of CKM from low to high will cause Ito stay low, Ito stay high, Ito stay low, and Q to stay high. Thus, Q remains unchanged to reflect the same state as D. In example D, if CKM is currently low and D is high, and if Iis low, Iis high, Iis high, and Q is low, transitioning of CKM from low to high will cause Ito stay low, Ito stay high, Ito go low, and Q to go high. Thus, Q changes to reflect the same state as D.

4 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 As illustrated in examples E-H, when CKM transitions from high to low Q (I) remains unchanged regardless of the state of D. In example E, if CKM is currently high and D is currently low and I, Iand Iare high and Q is low, transitioning of CKM from high to low (i.e., the falling edge of CKM) will not cause changes in any of these nodes (i.e., I, I, and Iwill stay high and Q will stay low). Thus, Q is held. In example F, if CKM is currently high and D is currently low and Iand Iare high, Iis low and Q is high, transitioning of CKM from high to low will again not cause changes in any of these nodes (i.e., Iand Istay high, Istays low and Q stays high). Thus, Q is held. In example G, if CKM and D are both currently high and if Iis low, Iand Iare high, and Q is low, transitioning of CKM from high to low will again not cause changes in any of these nodes (i.e., Istays low, Iand Istay high, and Q stays low). Thus, Q is held. In example H, if CKM and D are both currently high, and if Iis low, Iis high, Iis low, and Q is high, transitioning of CKM from high to low will again not cause changes in any of these nodes (i.e., Istays low, Istays high, Istays low, and Q stays high). Thus, Q is held.

4 FIG. 1 FIG. 5 FIG. 1 FIG. 1 FIG. 5 FIG. 100 100 100 191 192 193 2 3 126 136 191 192 193 is a timing diagram illustrating that, for D flip-flopof, changes in Q reflect changes in D only at the rising edges of a high frequency CKM (e.g., a 100 MHz CKM).is a timing diagram illustrating that, for D flip-flopof, changes in Q similarly reflect changes in D at the rising edges of a low frequency CKM (e.g., a 1 KHz CKM). It should be noted that in D flip-flopof, the combination of feedforward path, feedback path, and feedback loopeffectively prevent data loss if/when CKM is static for some extended period of time (i.e., in the absence of clock edges for a prolonged period) by ensuring that Iand Iretain their current states if/when second intermediate nodeand/or, respectively, are floating. Thus, the combination of feedforward path, feedback path, and feedback loopensure that Q inonly switches on the rising edge of CKM.

136 193 3 136 1 116 1 121 123 124 2 126 2 126 136 3 193 3 4 160 4 162 161 164 166 162 161 3 136 3 4 160 4 161 163 164 166 163 164 3 136 For example, as mentioned above, third intermediate nodeis also referred to herein as a data retention node. Feedback loopensures that Idoes not change states when third intermediate nodeis floating. Specifically, when D goes or is high and CKM is low, Ion first intermediate nodewill be low. When Iis low and CKM is low, second PFETwill be on and both second NFETand additional second NFETwill be off. Therefore, Ion second intermediate nodewill go high. If Ion second intermediate nodeis high and CKM is low, third intermediate nodeis floating and Iis maintained in its current state by feedback loop. For example, if Iis high it will remain high. This is because Q (I) is low and, within MPCTSL, when Q (I) is low, CKM is low, and CKN is high, additional sixth PFETand sixth PFETwill both be on and additional sixth NFETwill be off. Thus, Ifb on sixth intermediate nodewill be pulled up by additional sixth PFETand sixth PFETand will, in turn, pull up Ion third intermediate node. Contrarily, if Iis low, it will remain low. This is because Q (I) is high and, within MPCTSL, when Q (I) is high, CKM is low, and CKN is high, sixth PFETwill be off and sixth NFETand additional sixth NFETwill be on. Thus, Ifb on sixth intermediate nodewill be pulled down through sixth NFETand additional sixth NFETand will, in turn pull down Ion third intermediate node.

111 112 113 1 116 1 121 123 124 121 126 124 1 2 126 2 126 136 3 193 193 166 When D goes or is low and CKM is low, first PFETand additional first PFETwill be on and first NFETwill be off. Therefore, Ion first intermediate nodewill go high. If Iis high and CKM is low, then second PFETand second NFETwill both be on but additional second NFETwill be off. Therefore, second PFETcan pull the voltage level on the second intermediate nodeup and the additional second NFETwill prevent the voltage level thereon from being pulled down. So, regardless of whether Iis high or low, when CKM is low, Ion second intermediate nodewill be high. As mentioned above, if Ion second intermediate nodeis high and CKM is low, third intermediate nodewould be floating and Iwould be kept in its current state (high or low) by feedback loop, in the same manner as described above. It should be noted that feedback loopwill be off (i.e., sixth intermediate nodewill be floating) when CKM is high and CKN is low.

126 191 192 2 2 126 1 136 3 3 113 116 1 116 121 123 126 2 3 3 141 142 191 192 126 2 3 FIG. 3 FIG. Also, as mentioned above, second intermediate nodeis also referred to herein as a data transfer node. Feedforward pathand feedback pathensure that Idoes not change states under certain conditions and, particularly, when CKM transitions from low to high and D is high. For example, as mentioned above, when CKM is low, Ion second intermediate nodewill be high regardless of the state of Iand third intermediate nodewill be floating, so Imay be low and Q may be the same as D (as in example C in the table of) or Imay be high and Q may be different than D (as in example D in the table of). If CKM goes high when D is high, then first NFETwill remain on and continue to pull down the voltage level on first intermediate node. Thus, Ion first intermediate nodewill be low. As a result, second PFETand second NFETwill both be off, so second intermediate nodewill be floating. So, to ensure that Istays high when Iis low in order to prevent Ifrom changing states and, more particularly, to ensure that Q stays high to reflect D, fourth PFETand additional fourth PFETof feedforward pathand feedback pathwill both turn on to pull up the voltage level on second intermediate nodeand ensure Istays high.

6 FIG. 6 FIG. 600 600 100 640 600 1 2 1 is a schematic diagram illustrating an alternative embodiment of a D flip-flop. D flip-flopis similar to D flip-flopwith minor variations including, but not limited to, the fact that the stackof fourth transistors are NFETs instead of PFETs. Specifically, referring to, D flip-flopcan include a first stage (S) (also referred to herein as an input stage or primary stage) and a second stage (S) (also referred to herein as an output stage or secondary stage) connected to S.

1 615 1 610 610 611 613 614 699 698 611 611 614 614 615 613 613 601 610 616 611 613 611 613 1 616 1 g g g Scan include a data input node, which is electrically connected to receive a data input (D). Scan further include a first single phase clock-controlled tri-state logic device(herein after referred to as first SPCTSL). As mentioned above, a single phase clock-controlled tri-state logic device is a tri-state logic device that outputs an output signal, which is high (i.e., logic 1, such as at VDD), low (i.e., logic 0, such as at ground or 0.0V), or floating and which depends on the states of a single clock signal and an input signal. A multiphase clock-controlled tri-state logic device is a tri-state logic device that outputs an output signal, which is high (i.e., logic 1), low (i.e., logic 0), or floating and which depends on the states of at least two clock signals (e.g., an clock signal and an inverted clock signal) and an input signal. First SPCTSLcan include a stack of first transistors including a first PFET, a first NFET, and an additional first NFET, which are electrically connected in series between a positive voltage railat a positive supply voltage (VDD) level and a ground rail(e.g., at 0.0 volts (V)). In some embodiments, VDD can be 0.8V. Alternatively, VDD could be at any other suitable positive supply voltage level (e.g., given the processing technology node at which the flip-flop is designed). Gateof first PFETand gateof additional first NFETcan be electrically connected to data input nodeto receive D. Gateof first NFETcan be electrically connected to receive a clock signal (CKN) from a clock signal generator(also referred to herein as a clock generation circuit), as discussed in greater detail below. First SPCTSLcan further include a first intermediate nodeat the junction between first PFETand first NFET(i.e., at the electrical connection between first PFETand first NFET). A first intermediate signal (I) can be output at first intermediate node. The state of Ican be high, low, or floating depending upon the states of D and CKN.

2 620 620 621 622 623 699 698 621 621 623 623 622 622 616 1 620 626 622 623 622 623 2 626 2 1 g g g Scan include a second single phase clock-controlled tri-state logic device(hereinafter referred to as second SPCTSL). Second SPCTSLcan include a stack of second transistors including a second PFET, an additional second PFET, and a second NFET, which are electrically connected in series between positive voltage railand ground rail. Gateof second PFETand gateof second NFETcan be electrically connected to receive CKN. Gateof additional second PFETcan be electrically connected to first intermediate nodeto receive I. Second SPCTSLcan further include a second intermediate nodeat the junction between additional second PFETand second NFET(i.e., at the electrical connection between additional second PFETand second NFET). A second intermediate signal (I) can be output at second intermediate nodeand the state of Ican be high, low, or floating depending upon the states of Iand CKN.

2 630 630 631 632 633 699 698 631 631 633 633 626 2 632 632 630 636 632 633 632 633 3 636 3 2 g g g Scan further include a third single phase clock-controlled tri-state logic device(hereinafter referred to as third SPCTSL). Third SPCTSLcan include a third PFET, an additional third PFET, and a third NFET, which are electrically connected in series between positive voltage railand ground rail. Gateof third PFETand gateof third NFETcan be electrically connected to second intermediate nodeto receive I. Gateof additional third PFETcan be electrically connected to receive CKN. Third SPCTSLcan further include a third intermediate nodeat the junction between additional third PFETand third NFET(i.e., at the electrical connection between additional third PFETand third NFET). A third intermediate signal (I) can be output at third intermediate nodeand the state of Ican be high, low, or floating depending upon the states of Iand CKN.

2 640 640 643 644 626 698 644 644 636 3 692 636 644 626 643 643 616 1 691 616 643 626 692 691 1 3 643 644 2 626 g g Scan further include a stackof fourth transistors. Stackcan include a fourth NFETand an additional fourth NFET, which are electrically connected in series between second intermediate nodeand ground rail. Gateof additional fourth NFETcan be electrically connected to third intermediate nodeto receive I, thereby creating a feedback pathfrom third intermediate nodeto additional fourth NFETto assist in maintaining a low voltage level on second intermediate nodewhen necessary. Furthermore, gateof fourth NFETcan be electrically connected to first intermediate nodeto receive I, thereby creating a feedforward pathfrom first intermediate nodeto fourth NFETto further assist in maintaining a low voltage level on second intermediate nodewhen necessary. For example, given the feedback pathand feedforward pathmentioned above, when Iand Iare both at high volage levels, fourth NFETand additional fourth NFETwill both be on (i.e., conductive) to keep the voltage level on Ilow if second intermediate nodeis floating.

2 650 660 636 636 670 636 2 650 650 651 653 699 698 651 651 653 653 636 3 650 656 651 653 651 653 650 656 600 670 4 670 600 4 3 660 661 662 663 664 699 698 661 661 664 664 656 4 662 662 663 663 660 666 662 663 662 663 666 4 666 636 693 3 g g g g g g Scan further include an inverterand a multiphase clock-controlled tri-state logic device(hereinafter referred to as MPCTSL), which are electrically connected in series with third intermediate nodeand arranged in a loop back to third intermediate node(as discussed in greater detail below) and/or an additional inverter, which is also electrically connected in series with third intermediate node. Specifically, Scan include an inverter. Invertercan include a fifth PFETand a fifth NFET, which are electrically connected in series between positive voltage railand ground rail. A gateof fifth PFETand a gateof fifth NFETcan each be electrically connected to third intermediate nodeto receive I. Invertercan further include a nodeat the junction between fifth PFETand fifth NFET(i.e., at the electrical connection between fifth PFETand fifth NFET). The output signal of inverterat nodecan be either the data output signal (Q) of D flip-flopin the absence of an additional inverteror a fourth intermediate signal (I) if additional inverteris included in D flip-flopfor generating Q (as discussed below). In any case, Q (or I, which has the same state as Q) will be low when Iis high and vice versa. MPCTSLcan include a stack of sixth transistors including a sixth PFET, an additional sixth PFET, a sixth NFET, and an additional sixth NFET, which are electrically connected in series between positive voltage railand ground rail. Gateof sixth PFETand gateof additional sixth NFETcan be electrically connected to nodeto receive Q (or I). Furthermore, gateof additional sixth PFETcan be electrically connected to receive CK, whereas gateof sixth NFETcan be electrically connected to receive another clock signal (CK). CKN can be inverted relative to CK and, particularly, can has the same properties in terms of frequency, etc., but in an opposite polarity relative to CK. MPCTSLcan further include a sixth intermediate nodeat the junction between additional sixth PFETand sixth NFET(i.e., at the electrical connection between additional sixth PFETand sixth NFET). A feedback signal (Ifb) can be output at sixth intermediate nodeand the state of Ifb can be high, low, or floating depending upon the states of Q (or I), CK and CKN. Sixth intermediate nodecan be electrically connected back to third intermediate node, thereby forming a feedback loopfor maintaining Ieither high or low when CK is low and CKN is high.

670 671 673 699 698 671 671 673 673 636 3 670 676 671 673 671 673 676 4 3 3 g g Additional invertercan include a seventh PFETand a seventh NFET, which are electrically connected in series between positive voltage railand ground rail. Gateof seventh PFETand gateof seventh NFETcan each be electrically connected to third intermediate nodeto receive I. Additional invertercan further include a data output nodeat the junction between seventh PFETand seventh NFET(i.e., at the electrical connection between seventh PFETand seventh NFET). A data output signal (Q) can be output at data output nodeand the state of Q will be the same as I. Specifically, it will depend upon the state of I(i.e., when Iis high, Q will be low and vice versa).

600 693 601 601 602 602 600 601 600 6 FIG. Thus, in D flip-flopdescribed above and illustrated in, operation is primarily controlled by one clock signal (i.e., CKN) and only operation of feedback loopis controlled by two clock signals (i.e., CK and CKN). CKN can be generated by a clock signal generator. Clock signal generatorcan, for example, include a single inverter. Invertercan be connected to receive CK (e.g., a system clock signal) and can invert CK to output CKN. Since D flip-floponly requires CK and CKN to operate, clock signal generatoris relatively small. That is, it doesn't need as many inverters and/or delay buffers than clock signal generators used for other D flip-flops that require more than two different clock phases to operation. Additionally, since there are a relatively small number of transistors in D flip-flopcontrolled by these clock signals (e.g., only one transistor controlled by CK and only five transistors controlled by CKN), clock driver size can be reduced.

600 100 4 600 691 692 693 2 3 626 636 691 692 693 1 FIG. 6 FIG. It should be understood that D flip-flopoperates similarly to D flip-flopof. That is, when CKN transitions from low to high, Q (I) will either change or stay the same so as to reflect D. However, when CKN transitions from high to low, Q will be held in the same state, regardless of the state of D. Furthermore, in D flip-flopof, the combination of feedforward path, feedback path, and feedback loopeffectively prevent data loss if/when CKN is static for some extended period of time (i.e., in the absence of clock edges for a prolonged period) by ensuring that Iand Iretain their current states if/when second intermediate nodeand/or, respectively, are floating. Thus, the combination of feedforward path, feedback pathand feedback loopensure that Q only switches on the rising edge of CKN.

It should be understood that in the embodiments described above a field effect transistor (FET) is a semiconductor device including a channel region between source/drain regions, a primary gate (also referred to in the art as a front gate) adjacent to the channel region, and, optionally, a secondary gate (also referred to in the art as a back gate) adjacent to the channel region opposite the primary gate. A P-type FET (PFET) can include P-type source/drain regions at a relatively high conductivity level (e.g., P+ source/drain regions) and a channel region that is either an intrinsic (i.e., undoped) channel region or an N-type channel region at a relatively low conductivity level (e.g., a N-channel region). An N-type FET (NFET) can include N-type source/drain regions at a relatively high conductivity level (e.g., N+ source/drain regions) and a channel region that is either an intrinsic (i.e., undoped) channel region or a P-type channel region at a relatively low conductivity level (e.g., a P-channel region). Various different types of FET structures are known in the art and could be incorporated into the disclosed circuit structures. For example, the FETs mentioned above could be bulk semiconductor devices or semiconductor-on-insulator devices, planar semiconductor devices or non-planar semiconductor devices, single gate devices or dual-gate devices, single gate finger devices or multiple gate finger devices, etc.

100 100 600 100 600 1 600 FIG.or 6 FIG. 1 FIG. 6 FIG. In some embodiments, the FETs of the disclosed D flip-flopofofcould be formed using an advanced semiconductor-on-insulator technology processing platform such that they are either fully-depleted semiconductor-on-insulator FETs (e.g., a fully-depleted SOI (FDSOI) FET) or partially-depleted semiconductor-on-insulator FETs (e.g., a partially-depleted SOI (PDSOI) FET). Those skilled in the art will recognize that one advantage of advanced semiconductor-on-insulator technology processing platforms is that FETs can be formed on an insulator layer above a particular type of well region (e.g., an N-type well region (Nwell) or a P-type well region (Pwell)) in order to achieve different types of NFETs or PFETs with different threshold voltages (VTs). For example, for a super low threshold voltage (SLVT) or low threshold voltage (LVT) FET, an NFET can be formed above an Nwell and a PFET can be formed above a Pwell. For a regular threshold voltage (RVT) or high threshold voltage (HVT) FET, an NFET can be formed above a Pwell and a PFET can be formed above an Nwell. Whether the FETs are SLVT or LVT FETs or whether they are RVT or HVT FETs will depend upon the design (e.g., device size, etc.) and process specifications (e.g., dopant concentrations, etc.). In some embodiments, the FETs within D flip-flopofor D flip-flopofcan be all RVT or HVT FETs. That is, with D flip-flop,, PFETs can be above Nwells and NFETs can be above Pwells.

It should be understood that in the method and structures described above, a semiconductor material refers to a material whose conducting properties can be altered by doping with an impurity. Example semiconductor materials include, but are not limited to, silicon-based semiconductor materials (e.g., silicon, silicon germanium, silicon germanium carbide, silicon carbide, etc.) and III-V compound semiconductors (i.e., compounds obtained by combining group III elements, such as aluminum (Al), gallium (Ga), or indium (In), with group V elements, such as nitrogen (N), phosphorous (P), arsenic (As) or antimony (Sb)) (e.g., GaN, InP, GaAs, or GaP). A pure semiconductor material and, more particularly, a semiconductor material that is not doped with an impurity for the purposes of increasing conductivity (i.e., an undoped semiconductor material) is referred to in the art as an intrinsic semiconductor. A semiconductor material that is doped with an impurity for the purposes of increasing conductivity (i.e., a doped semiconductor material) is referred to in the art as an extrinsic semiconductor and will be more conductive than an intrinsic semiconductor made of the same base material. That is, extrinsic silicon will be more conductive than intrinsic silicon; extrinsic silicon germanium will be more conductive than intrinsic silicon germanium; and so on. Furthermore, it should be understood that different impurities (i.e., different dopants) can be used to achieve different conductivity types (e.g., P-type conductivity and N-type conductivity) and that the dopants may vary depending upon the different semiconductor materials used. For example, a silicon-based semiconductor material (e.g., silicon, silicon germanium, etc.) is typically doped with a Group III dopant, such as boron (B) or indium (In), to achieve P-type conductivity, whereas a silicon-based semiconductor material is typically doped with a Group V dopant, such as arsenic (As), phosphorous (P) or antimony (Sb), to achieve N-type conductivity. A gallium nitride (GaN)-based semiconductor material is typically doped with magnesium (Mg) to achieve P-type conductivity and with silicon (Si) or oxygen to achieve N-type conductivity. Those skilled in the art will also recognize that different conductivity levels will depend upon the relative concentration levels of the dopant(s) in a given semiconductor region.

It should be understood that the terminology used herein is for the purpose of describing the disclosed structures and methods and is not intended to be limiting. For example, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Additionally, as used herein, the terms “comprises,” “comprising,” “includes,” and/or “including” specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Furthermore, as used herein, terms such as “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” “upper,” “lower,” “under,” “below,” “underlying,” “over,” “overlying,” “parallel,” “perpendicular,” etc., are intended to describe relative locations as they are oriented and illustrated in the drawings (unless otherwise indicated) and terms such as “touching,” “in direct contact,” “abutting,” “directly adjacent to,” “immediately adjacent to,” etc., are intended to indicate that at least one element physically contacts another element (without other elements separating the described elements). The term “laterally” is used herein to describe the relative locations of elements and, more particularly, to indicate that an element is positioned to the side of another element as opposed to above or below the other element, as those elements are oriented and illustrated in the drawings. For example, an element that is positioned laterally adjacent to another element will be beside the other element, an element that is positioned laterally immediately adjacent to another element will be directly beside the other element, and an element that laterally surrounds another element will be adjacent to and border the outer sidewalls of the other element. The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed.

The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

The descriptions of the various disclosed embodiments have been presented for purposes of illustration but are not intended to be exhaustive or limiting. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosed embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.