Gate to Source/Drain Contact Links Implemented in Metallization Layer Contacting Device Layer

Coupling terminals of a transistor, for example, diode-connecting a transistor, may conventionally be done within a device layer or up in an interconnect stack, potentially well away from the transistor. Making these connections within a device layer may involve extra patterning and removing material from delicate structures in constrained spaces. Making these connections up in an interconnect stack may employ excessive routing.

New techniques and structures are needed to improve transistor diode connections in integrated circuit devices.

In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. The various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter.

References within this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present description. Therefore, the use of the phrase “one embodiment” or “in an embodiment” does not necessarily refer to the same embodiment. In addition, the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled.

The terms “over,” “to,” “between,” and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer “over” or “on” another layer or bonded “to” another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers.

The terms “coupled” and “connected,” along with their derivatives, may be used herein to describe structural relationships between components. These terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may be used to indicate that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause-and-effect relationship, an electrical relationship, a functional relationship, etc.).

The term “circuit” or “module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term “signal” may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”

The vertical orientation is in the z-direction and recitations of “top,” “bottom,” “above,” and “below” refer to relative positions in the z-dimension with the usual meaning. However, embodiments are not necessarily limited to the orientations or configurations illustrated in the figure.

The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10% of a target value (unless specifically specified). Unless otherwise specified in the specific context of use, the term “predominantly” means more than 50%, or more than half. For example, a composition that is predominantly a first constituent means more than half of the composition is the first constituent. The term “primarily” means the most, or greatest, part. For example, a composition that is primarily a first constituent means the composition has more of the first constituent than any other constituent. A composition that is primarily first and second constituents means the composition has more of the first and second constituents than any other constituent.

Unless otherwise specified the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects to which are being referred and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

For the purposes of the present disclosure, phrases “A and/or B” and “A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

Views labeled “cross-sectional,” “profile,” and “plan” correspond to orthogonal planes within a cartesian coordinate system. Thus, cross-sectional and profile views are taken in the x-z and y-z planes, and plan views are taken in the x-y plane. Typically, profile views in the x-z plane are cross-sectional views. Where appropriate, drawings are labeled with axes to indicate the orientation of the figure.

Structures and techniques are disclosed to improve linking structures and processing efficiencies in integrated circuit (IC) devices having diode-connected transistors.

Diode-connected transistors are employed for a variety of purposes, including as diodes, but also as large resistors and in current mirrors, which also have a multitude of applications. While a MOS (metal-oxide-semiconductor) FET (field-effect transistor) may be diode connected by electrically tying the gate to the drain, the drain and source bodies are often physically symmetrical in FETs, so the described techniques and structures may be utilized for gate-source connections as well. Transistor terminals may be electrically coupled conventionally, up in an interconnect stack over the transistor (for example, at met0, met1, etc.), but excessive routing may have electrical drawbacks (e.g., increased parasitics, etc.) and add avoidable complexity. Alternatively, other electrical connections may be made by etching into a gate electrode and source or drain contact metal in a device layer, but such patterning wastes processing resources (e.g., by adding extra masking, etc.) and may raise risks of reliability issues (e.g., by etching through one or more material layers in very constrained and critical spaces). The techniques and structures described herein conserve processing operations without these reliability risks.

Transistors may be diode connected by coupling gate electrodes with source and/or drain contacts in a metallization level immediately above a device layer, but below a conventional interconnect stack. Processing operations may be conserved by utilizing a metallization level otherwise dedicated to coupling source and drain contacts between neighboring transistors. A gate-drain (or gate-source) metallization link may be deposited directly on an upper surface of a transistor (and the gate electrode and source or drain contact). This direct interfacing of a metallization plane and the contact plane may minimize both reliability issues and mask operations, producing robust structures while efficiently utilizing processing resources.

1 1 1 1 1 FIGS.A,B,C,D, andE 1 FIG.A 1 FIG.B 1 1 FIG.C-E 1 1 FIGS.A andB 100 141 125 131 132 134 143 147 101 101 150 195 140 130 101 100 101 101 141 142 125 131 132 100 101 101 141 142 131 132 101 134 143 145 illustrate isometric, plan, and cross-sectional profile views of an IC devicehaving linking bodiescoupling gate electrodesand source or drain contact metals,at contact and metallization planes,at an upper surfaceof diode-connected transistor structures, in accordance with some embodiments. Transistor structuremay be coupled with an interconnect leveland interconnect networkby a metallization leveldirectly on a contact levelof or on transistor structure.shows a cross-sectional profile view A-A′ of devicethrough a row of transistor structures, including diode-connected structureswith metal bodies,on gate electrodesand source and drain metals,.illustrates a cross-sectional profile view B-B′ of devicethrough a second row of transistor structures, coupled to the first row of transistor structuresby linking bodiesand/oron source and drain metals,in each row of structures.show isometric and plan views of (and above) contact and metallization planes,,, including the orientations of profile views A-A′ and B-B′ of.

100 101 199 101 101 110 120 110 101 125 120 199 101 Apparatus or deviceincludes transistor structuresover substrate. Transistor structure(e.g., structureA) includes source and drain bodiesand a channel structurebetween and coupling source and drain bodies. StructureA includes a gate electrodeover channel structure. Substratemay include or support multiple transistor structures, for example, over subfins extending up from a crystalline layer of a semiconductor or insulator material.

130 140 101 130 130 101 130 140 125 132 131 132 110 110 131 110 110 Contact levelprovides structures and surfaces for interfacing between metallization leveland transistor structures. Contact levelmay be above (or the uppermost levelof) a device layer including transistor structures. Contact levelis below metallization leveland includes gate electrode, source contact metal, and drain contact metal. Source contact metalis on source bodyB and over source bodyB, and drain contact metalis on drain bodyA and over drain bodyA.

125 120 130 125 120 120 120 125 120 120 120 1 FIG.A 1 FIG.A Gate electrodeextends up over channel structure(e.g., in the z-direction) and into contact level. Gate electrodeis over channel structure(e.g., in the z-direction) and to both sides of channel structure(e.g., in both y-directions, in front of and behind the x- z viewing plane of). In the exemplary embodiment of, which has nanoribbon stacks as structures, electrodeis within, through, or between channel structures, for example, extending between individual nanoribbons (e.g., extending in the y-directions over one nanoribbon in a channel structureand under another nanoribbon in the same channel structure).

130 134 137 132 137 131 127 125 134 120 134 130 143 140 130 140 141 142 125 131 132 134 143 130 140 134 143 140 130 Contact levelhas an upper, top plane. Upper surfaceof source contact metal, upper surfaceof drain contact metal, and upper surfaceof gate electrodeare coplanar in contact planeabove the channel structure. The contact planeof contact levelinterfaces with the metallization planeof metallization level. The interfacing of contact and metallization levels,(and, e.g., of bodies,with electrodesand metals,) at contact and metallization planes,refers to the direct contact of levels,at planes,, without any intervening levels or structures. Metallization levelis directly on contact level.

140 130 134 143 132 131 125 140 141 142 143 145 148 141 148 142 143 120 147 141 147 142 145 120 143 120 1 2 1 Metallization levelinterfaces with contact level(at contact and metallization planes,), interfacing with each of source contact metal, drain contact metal, and gate electrode. Metallization levelincludes first and second metal bodies,between a lower, bottom planeand an upper, top plane. A lower surfaceof metal bodyand lower surfaceof metal bodyare substantially coplanar in bottom metallization planeat a first height Habove channel structure. An upper surfaceof metal bodyand upper surfaceof metal bodyare substantially coplanar in top metallization planeat a second height Habove the channel structureand above the first height Hof metallization planeabove channel structure.

141 125 110 141 140 143 134 125 131 132 142 140 143 134 131 132 141 142 131 132 101 141 142 120 131 132 101 120 1 FIG.A First metal bodycouples gate electrodeto one of source or drain bodies. First metal bodyin levelinterfaces at metallization plane(and contact plane) with gate electrodeand one of drain and source contact metals,. Second metal bodyin levelinterfaces at metallization plane(and contact plane) with the other of drain and source contact metals,. In some embodiments, either or both of bodies,interface with other drain and/or source contact metals,in other transistor structures. For example, metal bodiesand/ormay extend in the y-direction, orthogonal to a longitudinal direction of channel structures, and contact drain and/or source contact metals,in transistor structureswith channel structuresparallel to those described at.

1 FIG.A 1 FIG.A 141 125 131 142 132 110 101 195 110 110 131 132 101 In the exemplary embodiment of, bodycontacts gate electrodeand drain metal, and bodycontacts source metal. Drain and source bodiesin FET structuresare often symmetrical and may be determined by electrical connections (e.g., to a power supply via interconnect network), so the labels provided for any specific embodiment, e.g., of(for example, drain and source bodiesA,B and metals,in transistor structureA), should not be understood as limiting for these or other embodiments, e.g., which may have different or undetermined electrical connections.

141 142 149 140 130 140 149 149 149 140 149 143 140 149 149 149 149 130 101 149 141 142 162 149 149 149 149 149 Metal bodies,are in a dielectric layerin metallization level, over contact level. Metallization levelmay include multiple dielectric layers, such as dielectric layersB,C at a bottom of level(e.g., with dielectric layerC on metallization plane). For example, metallization levelmay include dielectric layersB,C as etch-stop layersB,C over contact leveland a device layer including transistor structures. The bulk or majority of dielectric layermay advantageously be of a low-K (low-permittivity) dielectric material, e.g., to electrically insulate metallic bodies,from each other, via, etc. Etch-stop layersB,C may advantageously be of low-K dielectric materials, but etch-stop layersB,C may provide etch selectivities and may have higher permittivities than the bulk or majority of dielectric layer.

141 142 141 142 141 142 141 142 141 142 149 141 142 140 Metal bodies,may include any suitable materials, including non-metals. In many embodiments, bodies,include one or more of tungsten, molybdenum, cobalt, ruthenium, copper, gold, tantalum, aluminum, nickel, or other metals, including in alloys. Bodies,may include other electrically conductive materials, including non-metals. In some embodiments, bodies,include nitrides of metals, e.g., tantalum and titanium. In some embodiments, bodies,include multiple materials, for example, with one or more conformal metal layers (e.g., barrier and/or seed layers) on sidewalls of dielectric layeras a liner around a different bulk or fill metal within or surrounded by the liner. In many embodiments, bodies,have identical compositions, e.g., due to concurrent depositions into metallization level.

141 125 131 141 142 131 132 145 141 142 131 132 101 141 142 125 131 132 141 142 141 142 125 131 132 141 142 125 131 132 141 142 125 131 132 125 131 132 125 131 132 Metal bodyis on, and continuous between, gate electrodeand drain contact metal. Metal bodies,are continuous between drain and source contact metals,and upper plane. In embodiments with one or both of bodies,interfacing with drain and/or source contact metals,in other transistor structures, bodies,are on, and continuous between, gate electrodeand drain and/or source contact metals,. In some embodiments, bodies,have multiple metal layers, one or both of bodies,interface with gate electrodeand contact metalsor, and the interfacing bodyoris continuous between gate electrodeand contact metaland/or. For example, although there may be an interface (e.g., a seam) between the layers of the interfacing bodyor, each of the layers spans and is continuous between the electrodeand contact metaland/or(e.g., with the interface also spanning between electrodeand metaland/or). There is no seam or interface between electrodeand metaland/or.

141 142 100 102 141 142 125 132 141 125 141 142 141 125 1 2 1 Bodies,may be oriented (e.g., sized and spaced) to optimize performance of device, e.g., to ensure sufficient interface area while minimizing parasitic capacitances. In many embodiments, as in the example of magnified view, a first distance Dseparating metal bodies,is greater than a second distance Dseparating gate electrodeand source contact metal. Bodyis large enough to overlap electrodesufficiently, but increased space (e.g., distance D) is left between bodies,(e.g., relative to a bodycompletely covering electrode).

101 101 141 144 146 141 144 146 144 125 131 101 146 141 131 132 110 101 1 1 FIGS.A andB 1 FIG.A 1 FIG.B 1 FIG.B 1 FIG.A 1 FIG.B In the exemplary embodiment of transistor structuresA,B in, bodyincludes first portion(as shown in) and a second portion (e.g., portionshown in). Bodyis continuous between portions,, as described. First portionextends in the x-directions between gate electrodeand drain contact metalof structureA. As will be described at, second portionof bodyextends in the y-directions (e.g., behind the viewing plane of, into the x-z viewing plane of) and contacts a drain or source contact metal,on a drain or source bodyof another transistor structureB.

131 132 110 131 132 110 101 150 195 101 131 132 141 142 141 142 131 132 131 132 141 142 131 132 131 132 133 Contact metals,may be conductive (e.g., metal) materials or structures that contact source or drain bodies. Contact metals,may couple regions(and transistor structures) to interconnect leveland network, e.g., over transistor structures. Contact metals,may include any suitable material(s), including non-metals, for example, as described of metal bodies,. In some embodiments, bodies,have a first composition different than a second composition of contact metals,, but metals,may have a composition substantially the same as a composition of bodies,. For example, in many embodiments, metals,include the same one or more of tungsten, molybdenum, cobalt, ruthenium, copper, gold, tantalum, aluminum, nickel, or other metals or non-metals, including in alloys, nitrides, etc., in a bulk of contact metals,, but with additional layerof a different metal.

131 132 136 136 110 139 135 136 131 132 133 110 110 133 139 131 132 139 139 139 2 In many embodiments, metals,include multiple materials, for example, with one or more conformal metal layers(e.g., barrier and/or seed layers) on source or drain bodiesor sidewalls of dielectric layeras a liner around a different bulk or fill metalwithin or surrounded by layer. In many embodiments, metals,include an interfacing layeron source or drain bodiesthat is or includes an alloy of a metal (e.g., as previously listed) and a semiconductor material of a body(e.g., a silicide layer). Dielectric layersmay be on sidewalls of metals,. Dielectric layersmay advantageously include a low-K dielectric material, such as a silicon oxide (e.g., silicon dioxide, SiO). Dielectric layersmay provide an etch selectivity, for example, with adjacent structures or materials during processing. In some embodiments, dielectric layersinclude a silicon nitride, a silicon oxynitride, etc., either with or without carbon.

159 150 149 140 141 142 159 159 145 150 159 159 150 159 140 141 142 149 159 162 163 159 159 159 Dielectric layeris in interconnect leveland over dielectric layerand metallization level, and bodies,interface with layer(e.g., layerB) at plane. Interconnect levelmay include multiple dielectric layers, such as dielectric layerB at a bottom of level(e.g., with dielectric layerB on metallization level, including bodies,and dielectric layer). The bulk or majority of dielectric layermay advantageously be of a low-K dielectric material, e.g., to electrically insulate vias,from each other. Etch-stop layerB may advantageously be of a low-K dielectric material, but etch-stop layerB may provide etch selectivities and may have higher permittivities than the bulk or majority of dielectric layer.

162 163 101 195 162 163 150 150 150 195 163 159 150 142 145 163 159 142 162 149 159 140 150 125 143 125 101 141 142 162 149 159 125 101 2 1 Vias,couple transistor structurewith interconnect network. Vias,are in interconnect leveland through at least interconnect level, which is a lowest levelof interconnect network. First viaextends through dielectric layerand interconnect leveland interfaces with metal bodyat upper metallization plane. First viaextends through dielectric layerto the second height Hand contacts metal body. Second viaextends through dielectric layers,and levels,and interfaces with an uncoupled gate electrodeat lower metallization plane, e.g., an electrodeof another transistor structureand not in contact with a metal bodyor. Second viaextends through dielectric layers,to first height Hand contacts a gate electrodeof the adjacent transistor structure.

162 163 141 142 162 163 141 142 163 162 162 163 141 142 162 163 162 163 166 166 149 159 165 166 Vias,may include any suitable materials, including non-metals, for example, as described of metal bodies,. Viamay have a composition the same as, or different from, a composition of via. In some embodiments, bodies,have a first composition different than a second composition of first and second vias,, but one or both of vias,may have a composition the same as, or different from, a composition of bodies,. For example, in many embodiments, vias,include one or more of tungsten, molybdenum, cobalt, ruthenium, copper, gold, tantalum, aluminum, nickel, or other metals or non-metals, including in alloys, nitrides, etc. In many embodiments, vias,include multiple materials, for example, with one or more conformal metal layers(e.g., barrier and/or seed layers) on sidewalls of dielectric layerand/oras a liner around a different bulk or fill metalwithin or surrounded by layer.

130 140 134 143 145 141 142 143 131 132 134 143 141 142 131 132 141 142 131 132 134 143 141 142 143 125 134 143 141 142 125 134 143 141 142 131 132 125 134 143 Interfaces between contact and metallization levels,may be demonstrated by metal-metal, metal-dielectric, dielectric-dielectric interfaces at planes,,. For example, in some embodiments, metal bodies,at and above metallization planehave a first composition different than a second composition of drain and source contact metals,below contact plane(and metallization plane). In some such embodiments, a seam is detectable (e.g., visibly or otherwise in cross-section) between bodies,and metals,, where contiguous bodies,and metals,abut at interface planes,. In many embodiments, metal bodies,at and above metallization planehave a composition different than a composition of the gate electrodebelow contact plane(and metallization plane). In some such embodiments, a seam is detectable between abutting bodies,and electrodeat interface planes,. Interfaces between metal bodies,and contact metals,or electrodemay include metallic bonding at abutting planes,.

141 142 131 132 141 142 131 132 141 142 131 132 141 142 125 141 142 131 132 134 143 134 143 134 143 134 143 141 142 131 132 125 134 143 141 142 131 132 125 Interfaces (e.g., metal-metal interfaces) may be detectable between metal bodies,and contact metals,having a same composition. In some embodiments, metal bodies,have a same composition as drain and source contact metals,. If not visibly, a seam between bodies,and metals,is often still detectable (e.g., in cross-section) by other analyses. In some embodiments, metal bodies,have a same composition as at least a portion of gate electrode. Even in embodiments having abutting metal bodies,and contact metals,and difficult to detect seams (e.g., along metallically bonded interface planes,with a same composition above and below planes,), planes,may be detected by overhangs or underhangs. For example, interface planes,may be apparent where an overhang of bodyorextends beyond (e.g., in an x-direction) a sidewall of contact metal,or gate electrode. Interface planes,may also be apparent at an underhang, where a sidewall of bodyoris over contact metal,or gate electrode.

141 142 131 132 125 141 125 134 143 126 125 134 141 126 127 134 136 131 132 134 141 142 131 132 134 143 136 134 141 142 141 142 131 132 125 134 143 141 142 131 132 125 1 FIG.A Metal-metal interfaces may be detectable even when a bulk of metal bodies,match a bulk of contact metals,or gate electrode. For example, in embodiments with bulks of bodyand electrodehaving matching compositions, an interface may be detectable at planes,where a liner metalof electrodeterminates at planeand body. In other embodiments, liner metalterminates below surfaceand plane. In the exemplary embodiment of, liner metalof contact metals,terminates below plane, but in other embodiments, e.g., with bulks of bodies,and metals,having matching compositions, an interface may be detectable at planes,where a liner metalterminates at planeand bodyor. In some embodiments, a bulk of metal bodies,match a bulk of contact metals,or gate electrode, and an interface is detectable at planes,where a liner metal (not shown) of,abuts metals,or electrode.

130 140 150 134 143 145 145 147 141 142 159 159 141 142 159 150 149 140 134 143 141 142 123 139 131 132 125 149 149 127 123 127 125 134 127 125 123 141 142 141 124 125 134 143 127 124 127 125 124 127 134 Interfaces between levels,,may be demonstrated by metal-dielectric interfaces at planes,,. For example, upper metallization planemay be apparent at interfaces of coplanar upper surfacesof metal bodies,with dielectric layer(e.g., layerB) over bodies,. Dielectric layeris in interconnect leveland over dielectric layerand metallization level. Interface planes,may be detectable at a meeting of either or both of bodies,with either or both of dielectric layers,and/or at a meeting of any of contact metals,or gate electrodewith dielectric layer(e.g., layerC). Upper surfaceof dielectric layermay be coplanar with upper surfaceof gate electrode, and contact planeand upper surfaceof electrodemay be defined or distinguished by an interfacing of layerat body(or). In some embodiments, a meeting of bodywith gate dielectric layeron gate electrodemakes apparent interface planes,(e.g., where upper surfaceof gate dielectric layeris coplanar with upper surfaceof electrode). In other embodiments, layerterminates below surfaceand plane.

130 140 134 143 145 145 147 149 159 159 150 140 147 149 147 141 147 142 145 140 134 143 123 139 149 149 149 124 134 143 124 127 134 Interfaces between contact and metallization levels,may be demonstrated by dielectric-dielectric interfaces at planes,,. For example, interface planemay be apparent at interfaces of upper surfaceof dielectric layerwith dielectric layer(e.g., layerB) of interconnect levelover metallization level. Upper surfaceof dielectric layeris coplanar with upper surfaceof metal bodyand upper surfaceof metal bodyin top planeof metallization level. Interface planes,may be detectable at a meeting of either or both of dielectric layers,with dielectric layer(e.g., layerC). In some embodiments, a meeting of dielectric layerwith gate dielectric layermakes apparent interface planes,. In other embodiments, layerterminates below surfaceand plane.

101 195 150 140 110 110 120 110 120 120 110 Transistor structuresof either conductivity type (e.g., n- or p-type) may be coupled to a power supply through interconnect network(including interconnect level) by metallization level. Drain and source bodiesare of semiconductor material doped with donor or acceptor impurities (n-or p-type dopants), e.g., having increased charge-carrier availabilities and associated conductivities. Bodiesare electrically and physically coupled to opposite ends of channel structures. Drain and source bodiesmay be polycrystalline or substantially monocrystalline, e.g., having long-range order at least adjacent ends of channel structuresand (for example, in embodiments having nanoribbon channel structures) merging or joining into a unitary body with few grain boundaries. Bodiesmay include one or more electrically active impurities in a Group IV semiconductor material (e.g., silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn) alloy).

120 120 1 FIG.A Channel structuresmay be of any suitable material and structure. In the exemplary embodiment of, structuresare stacks of silicon nanoribbons, but other embodiments may have other aspect ratios (such as of nanowires or nanosheets), structures (such as fins, etc.), or materials (such as Ge, SiGe, two-dimensional (2D) materials (e.g., transition metal dichalcogenides, TMDs), etc.

125 126 124 125 Gate electrodelayeron gate dielectric layermay include at least one of a p-type work function metal (WFM) or an n-type WFM, depending on whether the transistor is a PMOS or an NMOS transistor. In some embodiments, gate electrodeis a stack of two or more metal layers, where one or more metal layers are WFM layers and at least one metal layer is a fill metal layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A p-type metal layer will enable the formation of a PMOS gate electrode with a work function that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as aluminum carbide, hafnium carbide, zirconium carbide, titanium carbide, and tantalum carbide. An n-type metal layer will enable the formation of an NMOS gate electrode with a work function that is between about 3.9 eV and about 4.2 eV.

124 120 125 124 124 124 124 120 125 2 Gate dielectric layerprovides electrical insulation between channel structuresand gate electrode. Layermay have more than one layer. Layermay be of any suitable material(s). The one or more layers of dielectric layermay include a silicon oxide, silicon dioxide (e.g., SiO), a silicon oxynitride, etc. Advantageously, gate layerincludes a high-permittivity (“high-K”) dielectric, which may improve transconductance and so electrostatic control of channel structuresby electrode. A high-k dielectric material may include one or more of various elements, such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc, including in oxides of these elements and combinations of these elements. Any other suitable materials may be deployed.

122 120 120 125 110 123 125 110 125 131 132 122 123 122 123 122 123 1 FIG.A 2 Gate spacersprovide electrical insulation between channel structures(in the case of nanoribbon channel structuresof) and between gate electrodeand source and drain bodies. Gate spacer layersprovide electrical insulation between gate electrodeand source and drain bodiesand between gate electrodeand contact metals,. Dimple spacerand spacer layersmay be of or include the same or different dielectric material(s). Spacerand spacer layersmay include a silicon oxide, silicon dioxide (e.g., SiO), a silicon nitride, a silicon oxynitride, etc., either with or without carbon. Any other suitable materials may be deployed. Advantageously, spacerand spacer layersinclude a low-K dielectric.

195 150 140 150 195 101 130 162 163 Interconnect networkincludes layers (such as interconnect level) with interconnections or wires that provide electrical routing, generally formed of metal or other electrically conductive material. Adjacent interconnect layers may be formed of different materials and by different methods. Metallization leveland interconnect leveland networkare over a device layer that includes transistor structuresand contact level. Adjacent metallization and interconnect layers are interconnected by vias, e.g., like vias,, that may be characterized as part of the metallization layers or between the metallization layers.

195 195 195 195 195 195 159 In the illustrated example, networkmay be a front-side interconnect networkincluding M0, V0, M1, M2/V1, M3/V2, M4/V3, and M4-M12 metallization layers. However, networkmay include any number of metallization layers such as eight or more metallization layers. Similarly, a back-side networkmay include BM0, BM1, BM2, and BM3. However, networkmay include any number of metallization layers such as two to five metallization layers. Metallization in networkis embedded within dielectric materials (such as layer).

199 199 199 199 199 199 101 199 199 2 3 Substratemay include any suitable material or materials. Any suitable semiconductor or other material can be used. Substratemay be any suitable substrate, such as a wafer, die, etc. Substratemay include a crystalline material that transistors can be formed out of or over, such as monocrystalline or polycrystalline Si, Ge, SiGe, a III-V alloy material (e.g., gallium arsenide (GaAs)), a silicon carbide (SiC), a sapphire (AlO), or any combination thereof. In some embodiments, substrateincludes crystalline silicon and subsequent components are also silicon. In some embodiments, a crystalline material of substrateis removed (e.g., by grinding) from a back-side of transistor structuresand replaced with an isolation material. Substratemay be a silicon-on-insulator (SOI) substrate. Substratemay also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in IC substrates.

1 FIG.B 1 FIG.A 1 FIG.B 1 FIG.A 101 100 101 101 101 141 142 131 132 101 129 110 131 132 141 142 illustrates a row of transistor structuresin an x-z plane of device, parallel to the row of structuresdescribed at, with at least one of structuresincoupled to one of structuresinby a linking bodyoron drain and/or source metals,in each row of structures. A dielectric isolationis between some of source or drain bodies. At least one of drain and source contact metals,is not interfaced with a metal body,.

101 101 141 144 146 141 144 146 144 125 131 146 131 110 101 1 1 FIGS.A andB 1 FIG.A 1 FIG.A 1 FIG.B 1 1 FIGS.A andB In the exemplary embodiment of transistor structuresA,B in, bodyincludes first portion(as described at) and second portion. Bodyis continuous between portions,. As described at, first portionextends in the x-directions between gate electrodeand drain contact metal. In, second portion(extending in the y-directions between the x-z viewing planes of) contacts drain contact metalon drain bodyA of transistor structureB.

1 FIG.C 1 1 FIGS.A andB 1 1 FIGS.A andB 1 1 FIGS.A andB 134 100 103 134 103 103 101 101 shows isometric and plan views of contact planein deviceas if sectioned through by x-y, y-z, and x-z viewing planes, including the orientations of profile views A-A′ and B-B′ of. Dashed outlines of x-y sectionin both the isometric and plan views provide further reference to, and aids comparison of, the views. Note that more of planeis visible in the plan view than the isometric view, beyond section. Note also that some of profile views A-A′ and B-B′ ofare beyond section. Dashed ovals indicate areas over transistor structuresA,B along cross-sectional views A-A′ and B-B′ of.

125 127 131 132 137 134 139 125 131 132 139 125 131 132 101 Gate electrodes(e.g., upper surfaces) and drain and source contact metals,(e.g., upper surfaces) are revealed at x-y contact plane. Dielectric layeris between electrodesand contact metals,extending in the y-directions. Dielectric layeris between some pairs of electrodesand some pairs of contact metals,, for example, separating or isolating adjacent transistor structures.

100 125 120 125 129 103 125 The sectioning of devicereveals a y-z plane through a track of gate electrodes. Channel structuresextend in the x-directions through gate electrodes. Dielectric isolationis visible in the y-z plane (along an edge of section) in place of some electrodes, including on view B-B′.

100 125 131 132 110 129 131 132 The sectioning of deviceincludes an x-z plane through gate electrodesand at least one drain or source contact metalor(but not the associated drain or source body). A dielectric isolationis visible in the x-z plane in place of (or between) some of contact metals,.

1 FIG.D 1 1 FIGS.A andB 1 1 FIGS.A andB 145 100 103 101 101 illustrates isometric and plan views of upper metallization planein deviceas if sectioned through by x-y, y-z, and x-z viewing planes, including the orientations of profile views A-A′ and B-B′ of. Dashed outlines of x-y sectionare in both the isometric and plan views. Dashed ovals indicate areas over transistor structuresA,B along cross-sectional views A-A′ and B-B′ of.

141 142 145 140 149 141 142 144 141 120 146 141 131 132 131 132 101 141 101 101 131 101 101 146 141 101 101 144 125 131 101 101 Upper surfaces of metal bodies,are revealed at x-y metallization planeat a top of metallization level. Dielectric layeris between bodies,extending mostly in the y-directions. First portionsof bodiesextend in the x-directions (e.g., parallel to and over channel structures). Second portionsof bodiesextend in the y-directions, e.g., parallel to and on contact metals,, in some cases coupling contact metals,in different transistor structures. For example, at least one bodyis over transistor structuresA,B (e.g., on metalsof structuresA,B), with portionof bodyextending in the y-directions between structuresA,B and with portionsextending in the x-directions (e.g., on and coupling gate electrodesand metalswithin each of structuresA,B).

162 145 140 162 140 162 125 125 Viasare revealed at planeat a top of metallization level(e.g., at a midpoint of viasextending down from interconnect level and network, into and through level). Viasare over gate electrodes(e.g., on and coupling electrodes).

100 141 142 149 140 149 149 140 The sectioning of deviceincludes a y-z plane and an x-z plane through metal bodies,and dielectric layerin metallization level, which includes dielectric layersB,C at a bottom of metallization level.

1 FIG.E 1 1 FIGS.A andB 1 1 FIGS.A andB 150 100 101 101 shows an isometric view of a top of interconnect levelin deviceas if sectioned through by x-y, y-z, and x-z viewing planes, including the orientations of profile views A-A′ and B-B′ of. Dashed ovals indicate areas over transistor structuresA,B along cross-sectional views A-A′ and B-B′ of.

162 163 150 159 150 140 163 195 150 141 142 141 142 162 195 150 140 125 125 Vias,are visible at an x-y plane over interconnect level. Dielectric layeris in level, over metallization level. Viaextends down from interconnect networkand through interconnect levelto bodies,(e.g., touching down on and coupling bodies,). Viaextends down from interconnect networkand through interconnect leveland metallization levelto gate electrodes(e.g., touching down on and coupling electrodes).

100 141 142 149 159 140 150 150 159 150 The sectioning of deviceincludes a y-z plane and an x-z plane through metal bodies,and dielectric layers,in levels,. Interconnect levelincludes dielectric layersB at a bottom of level.

2 FIG. 2 FIG. 2 FIG. 2 FIG. 200 200 210 260 200 is a flow chart of methodsfor forming a metallization level with linking bodies on gate electrodes and drain and source contacts, in accordance with some embodiments. Methodsinclude operations-. Some operations shown inare optional. Additional operations may be included.shows an example sequence, but the operations can be done in other orders as well, and some operations may be omitted. Some operations can also be performed multiple times before other operations are performed. For example, multiple openings may be patterned in a first dielectric layer before covering the first dielectric layer with a second dielectric layer. Some operations may be included within other operations so that the number of operations illustratedis not a limitation of the methods.

3 3 3 3 3 3 FIGS.A,B,C,D,E, andF 3 3 FIG.A-F 2 FIG. 100 141 142 140 125 131 132 130 200 illustrate isometric and plan views of IC devicehaving metal bodies,in metallization leveldirectly on gate electrodesand contact metals,in contact level, at various stages of manufacture, in accordance with some embodiments.show possible examples of intermediate structures during an embodiment of a practice of methodsof.

2 FIG. 1 FIG.A 200 210 199 Returning to, methodsbegin at operationwith planarizing an upper surface of a transistor structure. The transistor structure may be received on or in a substrate, such as an IC die or wafer, e.g., much as described of substrateat. The transistor structure may be planarized by any suitable means. In many embodiments, the upper surface of the transistor structure is planarized by a CMP (chemical-mechanical planarization or polish) of the substrate. The planarizing (e.g., polishing) may reduce down and smooth out any structures and materials on the upper surface of the substrate and transistor structure. The transistor structure may include a gate electrode (for example, over a channel structure, such as a stack of nanoribbons, nanowires, etc., or a fin), source and drain bodies (e.g., coupled to ends of the channel structure), contacts (e.g., metallization on the source and drain), etc. Planarizing the upper surface of the transistor structure may planarize upper surfaces of source and drain contacts and the gate electrode to approximately level, e.g., a same height, for example, all on a same, planarized upper surface of the transistor structure.

3 FIG.A 1 FIG.C 127 137 125 131 132 101 100 210 101 101 101 127 125 137 131 132 134 139 125 131 132 127 137 125 131 132 220 101 101 101 illustrates coplanar upper surfaces,of gate electrodesand drain and source contact metals,in transistor structuresin a workpiece or IC device, in accordance with some embodiments, for example, following a performance of planarizing operation. Dashed ovals indicate areas over transistor structuresA,B. Transistor structuresmay be much as described at(etc.), with upper surfacesof electrodesand upper surfacesof metals,planarized (e.g., polished) to a same level or height at contact plane. Dielectric layersprovide electrical isolation, for example, between gate electrodesand drain and source contact metals,. Upper surfaces,of electrodesand metals,are prepared for operations, etc., for example, to link and couple transistor structuresA,B (and other structureson the x-z planes of profile views A-A′ and B-B′).

2 FIG. 200 220 Returning to, methodscontinue at operationwith covering a transistor structure with a dielectric layer. A dielectric material may be deposited as a layer over the entire substrate or over selected portions, including on upper surfaces of the gate electrode and of source and drain contacts. The dielectric material may be deposited by any suitable means. In many embodiments, the dielectric material is a low-K dielectric, e.g., to provide good electrical isolation and so to minimize parasitic capacitances between conductive structures. In some embodiments, the dielectric layer is one of multiple dielectric layers deposited over the transistor structure. In some such embodiments, the dielectric layer is a relatively thick, low-K dielectric layer over one or more relatively thin layers that provide etch selectivities (e.g., etch-stop layers that may have somewhat higher permittivities). In some such embodiments, the low-K dielectric layer includes oxygen (e.g., in an oxide, such as an oxide of silicon), and the layer(s) providing etch selectivities include(s) nitrogen (e.g., in a nitride, such as a nitride of silicon).

The dielectric material may be deposited by any suitable means, such as by a chemical vapor deposition (CVD). In some embodiments, multiple dielectric layers are deposited by different means, for example, a thermally grown low-K dielectric layer over an etch-stop layer deposited by an ALD (atomic layer deposition).

3 FIG.B 149 149 149 101 100 220 149 149 149 149 149 149 230 101 illustrates first dielectric layer(and layersB,C) over transistor structuresin a workpiece or IC device, in accordance with some embodiments, for example, following a performance of covering operation. Dielectric layersB,C may be etch-stop layersB,C, while dielectric layerhas a lower dielectric permittivity. Dielectric layersare prepared for operations, etc., for example, to link and couple transistor structures.

2 FIG. 200 230 Returning to, methodscontinue by patterning one or more openings in the dielectric layer at operation. The openings may be formed in selected locations, for example, to expose certain structures below the dielectric layer for subsequent coupling with a deposited metal. Holes or gaps may be opened in the dielectric layer over the gate electrode and the source and drain contacts. In many embodiments, gaps are opened in the dielectric layer(s) over gate electrodes and source and drain contacts of multiple transistors. In many embodiments, patterning the one or more openings in the dielectric layer forms an opening with orthogonal portions. For example, a first portion of the opening may extend in a first direction over both the gate electrode and a source or drain contact, and a second portion of the opening may extend in a second, orthogonal direction over a source or drain contact of a second transistor structure. The opening may have multiple perpendicular first and/or second portions. For example, openings may have a single second portion extending over contacts of multiple transistor structures with first portions of the opening branching off orthogonally from over contacts of multiple transistor structures to uncover corresponding gate electrodes.

The openings may be patterned by any suitable means, e.g., photolithographically. For example, a litho mask complex may be deposited, selectively exposed (e.g., in a pattern), and used to remove patterned portions of the dielectric layer, leaving openings exposing structures to be coupled by a metal deposited in the opening(s). In some embodiments (e.g., embodiments with multiple dielectric layers deposited over a planarized upper surface of the transistor structure), multiple etches are employed to expose the underlying structures.

3 FIG.C 341 342 344 346 149 101 100 230 341 342 149 149 149 125 131 132 341 342 341 342 141 142 344 346 341 144 146 141 341 342 149 240 101 341 141 125 131 132 163 195 342 142 101 163 195 illustrates openings,(including orthogonal portions,) through dielectric layerover transistor structuresin a workpiece or IC device, in accordance with some embodiments, for example, following a performance of patterning operation. Openings,are through dielectric layers,B,C, and gate electrodesand contact metals,are exposed in openings,. Openings,may be filled to form corresponding bodies,. Orthogonal portions,of openingsmay be filled to form corresponding portions,of bodies. Openings,in layersare prepared for operations, etc., for example, to link and couple transistor structures. For example, openingsmay be filled with metal(s) to form a linking body(e.g., for linking gate electrodesand contact metals,and for contacting by a viafor coupling to network), and openingsmay be filled with the same metal(s) to form a body(e.g., for linking contact metals in adjacent transistor structuresand for contacting by a viafor coupling to network).

2 FIG. 200 240 Returning to, methodscontinue at operationwith depositing a metal in the opening. The deposited metal may be any suitable material and may be deposited by any suitable means. The deposited metal may be deposited on and couple with any gate electrode(s) and source or drain contact(s) exposed by the opening(s). For example, the deposited metal may couple with a gate electrode, couple with a source or drain contact in the same transistor structure and exposed by a same opening in the dielectric layer, and couple the gate electrode and source or drain contact (e.g., to each other by the deposited metal). The metal may be deposited in the opening(s), on an upper (e.g., planarized) surface of the transistor structure, and on the dielectric layer (and/or litho mask(s)) over the transistor structure, for example, with a lower edge or surface of the metal above any gate electrodes, source and drain bodies, and source and drain contacts of the transistor structure.

In embodiments having an opening extending over contacts of multiple transistor structures, depositing the metal in the opening couples the multiple transistor structures. The deposited metal may couple with source or drain contacts exposed by the openings and with any gate electrode(s) exposed by the opening, and the previously exposed contacts and electrode(s) may be covered and coupled by the deposited metal. In many embodiments, the deposited metal is planarized, e.g., down to the dielectric layer, removing any excess metal and leaving a planarized upper surface of the substrate with deposited metal exposed within a layer of dielectric.

141 142 131 132 135 136 1 FIG.A The metal may be deposited by any suitable means. In some embodiments, a barrier and/or seed metal is first deposited (e.g., in a thin, conformal layer, for example, by an ALD) on the first dielectric layer and exposed electrode and contact metals (e.g., in a thin, conformal layer, for example, by an ALD). A bulk or fill second metal may then be deposited on (e.g., grown from) the first metal, for example, a different metal deposited by different means. The metal(s) may be as described of bodies,(and metals,, including metaland layer) at.

3 FIG.D 141 142 125 131 132 101 100 240 140 141 142 149 149 149 145 140 141 142 149 142 131 132 141 125 131 132 141 144 146 162 149 141 142 149 250 141 142 149 101 illustrates metal bodies,linking gate electrodesand contact metals,in transistor structuresin a workpiece or IC device, in accordance with some embodiments, for example, following a performance of depositing operation. Metallization levelinclude metal bodies,and dielectric layers,B,C. Upper metallization planeis at a top of leveland bodies,and layer. Metal bodiesare over and on contact metals,, and metal bodiesare over and on gate electrodesand contact metals,. Metal bodiesinclude orthogonal portions,. (Notably, no viasare yet through layer.) Metal bodies,and dielectric layerare prepared for operations, etc., for example, to cover bodies,and layerand to couple transistor structures.

2 FIG. 200 250 Returning to, methodscontinue with covering the dielectric layer and the deposited metal with another dielectric layer at operation. This second dielectric may be deposited as a layer of the same or a different dielectric material, over the entire substrate or at least over the first dielectric layer and the deposited metal. The dielectric material may be any suitable material and may be deposited by any suitable means. In many embodiments, the dielectric material is a low-K dielectric material. In some embodiments, multiple dielectric layers are deposited over the first dielectric layer. In some such embodiments, one or more etch-stop layers are first deposited over the metals and first dielectric layer, and a low-K dielectric layer is then deposited over the etch-stop layer(s) to provide electrical isolation.

3 FIG.E 159 141 142 149 101 100 250 159 140 141 142 149 159 159 159 101 260 101 illustrates second dielectric layerover metal bodies,and first dielectric layeron transistor structuresin a workpiece or IC device, in accordance with some embodiments, for example, following a performance of covering operation. LayerC is on metallization level(including bodies,and layer), and layeris on layerC. Dielectric layerand transistor structuresare prepared for operations, for example, to couple transistor structures.

2 FIG. 200 260 240 Returning to, methodscontinue at operationby coupling the transistor structure, for example, to an interconnect network over the transistor structure. In many embodiments, the transistor structure is coupled by forming a via through at least the second dielectric layer. In many embodiments, the transistor structure is coupled by forming a via through the first and second dielectric layers. In many embodiments, the transistor structure is coupled by forming first vias through the second dielectric layer (e.g., down to and contacting a metal deposited at operation) and second vias through the first and second dielectric layers (e.g., down to and contacting a gate electrode). In some embodiments, a via is formed through both of the first and second dielectric layers and contacts a source or drain contact.

240 162 163 166 165 230 240 240 1 FIG.A The via(s) may be of any suitable material(s) and may be formed by any suitable means. For example, a via may be formed of one or more suitable metals, much as described of the metal(s) at operationor of vias,described at(including barrier and/or seed layersand bulk or fill metal). The via may be formed by, firstly, opening cavities or holes in and through one or both of the first and second dielectric layers over the transistor structure and, secondly, by depositing one or more metals at least in the openings, much as described by operations,. Notably, the via openings may extend more deeply and through more dielectric layers, and the vias may contact gate electrodes, source or drain contacts, or tops of the metals deposited at operation.

3 FIG.F 162 163 140 150 101 100 260 150 159 159 163 159 159 150 142 162 149 149 149 159 159 140 150 141 195 140 150 101 162 163 101 195 101 195 395 195 illustrates vias,through interconnect levels,to transistor structuresin IC device, in accordance with some embodiments, for example, following a performance of coupling operation. Interconnect levelincludes dielectric layers,B. Viasextend through layers,B and interconnect leveland contact bodies, and viasextend through layers,B,C,,B and levels,and contact bodies. Interconnect networkmay be formed over metallization level(and may include level) and may couple transistor structuresby vias,. Transistor structuresmay be coupled to a power supply (not shown) by network. Transistor structuresand networkmay be coupled to the power supply (not shown) by an optional backside interconnect network, opposite network.

100 399 399 199 101 199 399 101 399 IC devicemay include or be coupled to a substrate or other host component. Host componentmay be a package substrate, an interposer, an IC die, etc. For example, substratemay be an IC die that includes transistor structures, substratemay be coupled (e.g., soldered or otherwise bonded) to host component, and transistor structuremay be coupled to a power supply (not shown) through host component.

399 399 100 399 100 100 399 399 100 399 399 399 399 Host componentis a planar platform and may include dielectric and metallization structures. Host componentmechanically supports and electrically couples one or more IC devices. At least one side of host componentincludes substrate interconnect interfaces for bonding to one or more IC devices. IC devicemay be direct bonded, e.g., hybrid bonded, to host componentor otherwise bonded, e.g., by optional solder bumps. The opposite side of host componentmay include similar interfaces, e.g., copper pads for socketing and/or solder bumps for bonding deviceto a host component, such as a printed circuit board (PCB). Host componentmay be any host component with substrate interconnect interfaces, such as a package host componentor interposer, etc. Host componentmay itself be a die. In many embodiments, host componentincludes organic dielectric(s), such as a resin or other polymer, between metallization layers.

4 FIG. 406 406 450 illustrates a diagram of an example data server machineemploying an IC device having a metallization layer on a transistor, linking a gate electrode and a source or drain contact, in accordance with some embodiments. Server machinemay be any commercial server, for example, including any number of high-performance computing platforms disposed within a rack and networked together for electronic data processing, which in the exemplary embodiment includes one or more deviceshaving a metallization layer on a transistor, linking a gate electrode and a source or drain contact.

406 415 450 450 410 410 420 450 450 450 450 399 430 425 435 425 430 435 450 Also as shown, server machineincludes a battery and/or power supplyto provide power to devices, and to provide, in some embodiments, power delivery functions such as power regulation. Devicesmay be deployed as part of a package-level integrated system. Integrated systemis further illustrated in the expanded view. In the exemplary embodiment, devices(labeled “Memory/Processor”) includes at least one memory chip (e.g., random-access memory (RAM)), and/or at least one processor chip (e.g., a microprocessor, a multi-core microprocessor, or graphics processor, or the like) having the characteristics discussed herein. In an embodiment, deviceis a microprocessor including a static RAM (SRAM) cache memory. As shown, devicemay be an IC device having a metallization layer on a transistor, linking a gate electrode and a source or drain contact, as discussed herein. Devicemay be further coupled to (e.g., communicatively coupled to) a board, an interposer, or other substrate or host componentalong with, one or more of a power management IC (PMIC), RF (wireless) IC (RFIC)including a wideband RF (wireless) transmitter and/or receiver (TX/RX) (e.g., including a digital baseband and an analog front end module further includes a power amplifier on a transmit path and a low noise amplifier on a receive path), and a controllerthereof. In some embodiments, RFIC, PMIC, controller, and deviceinclude having a metallization layer on a transistor, linking a gate electrode and a source or drain contact.

5 FIG. 5 FIG. 5 FIG. 500 500 500 500 500 500 500 503 503 500 504 505 509 510 511 504 505 509 510 511 is a block diagram of an example computing device, in accordance with some embodiments. For example, one or more components of computing devicemay include any of the devices or structures discussed herein. A number of components are illustrated inas being included in computing device, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in computing devicemay be attached to one or more printed circuit boards (e.g., a motherboard). In some embodiments, various ones of these components may be fabricated onto a single system-on-a-chip (SoC) die. Additionally, in various embodiments, computing devicemay not include one or more of the components illustrated in, but computing devicemay include interface circuitry for coupling to the one or more components. For example, computing devicemay not include a display device, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which display devicemay be coupled. In another set of examples, computing devicemay not include an audio output device, other output device, global positioning system (GPS) device, audio input device, or other input device, but may include audio output device interface circuitry, other output device interface circuitry, GPS device interface circuitry, audio input device interface circuitry, audio input device interface circuitry, to which audio output device, other output device, GPS device, audio input device, or other input devicemay be coupled.

500 501 501 521 522 523 524 525 526 527 528 Computing devicemay include a processing device(e.g., one or more processing devices). As used herein, the term “processing device” or “processor” indicates a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. Processing devicemay include a memory, a communication device, a refrigeration device, a battery/power regulation device, logic, interconnects(i.e., optionally including redistribution layers (RDL) or metal-insulator-metal (MIM) devices), a heat regulation device, and a hardware security device.

501 Processing devicemay include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.

500 502 502 501 Computing devicemay include a memory, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random-access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, memoryincludes memory that shares a die with processing device. This memory may be used as cache memory and may include embedded dynamic random-access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).

500 506 506 501 500 Computing devicemay include a heat regulation/refrigeration device. Heat regulation/refrigeration devicemay maintain processing device(and/or other components of computing device) at a predetermined low temperature during operation.

500 507 507 500 In some embodiments, computing devicemay include a communication chip(e.g., one or more communication chips). For example, the communication chipmay be configured for managing wireless communications for the transfer of data to and from computing device. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

507 507 507 507 507 500 513 Communication chipmay implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. Communication chipmay operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. Communication chipmay operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communication chipmay operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. Communication chipmay operate in accordance with other wireless protocols in other embodiments. Computing devicemay include an antennato facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

507 507 507 507 507 507 In some embodiments, communication chipmay manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, communication chipmay include multiple communication chips. For instance, a first communication chipmay be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chipmay be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chipmay be dedicated to wireless communications, and a second communication chipmay be dedicated to wired communications.

500 508 508 500 500 Computing devicemay include battery/power circuitry. Battery/power circuitrymay include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of computing deviceto an energy source separate from computing device(e.g., AC line power).

500 503 503 Computing devicemay include a display device(or corresponding interface circuitry, as discussed above). Display devicemay include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

500 504 504 Computing devicemay include an audio output device(or corresponding interface circuitry, as discussed above). Audio output devicemay include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

500 510 510 Computing devicemay include an audio input device(or corresponding interface circuitry, as discussed above). Audio input devicemay include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

500 509 509 500 Computing devicemay include a GPS device(or corresponding interface circuitry, as discussed above). GPS devicemay be in communication with a satellite-based system and may receive a location of computing device, as known in the art.

500 505 505 Computing devicemay include other output device(or corresponding interface circuitry, as discussed above). Examples of the other output devicemay include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

500 511 511 Computing devicemay include other input device(or corresponding interface circuitry, as discussed above). Examples of the other input devicemay include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

500 512 512 500 Computing devicemay include a security interface device. Security interface devicemay include any device that provides security measures for computing devicesuch as intrusion detection, biometric validation, security encode or decode, access list management, malware detection, or spyware detection.

500 Computing device, or a subset of its components, may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.

1 5 FIG.A- The subject matter of the present description is not necessarily limited to specific applications illustrated in. The subject matter may be applied to other deposition applications, as well as any appropriate manufacturing application, as will be understood to those skilled in the art.

The following examples pertain to further embodiments, and specifics in the examples may be used anywhere in one or more embodiments.

In one or more first embodiments, an apparatus includes a transistor structure including a source body, a drain body, and a gate electrode over a channel structure, a source contact metal on the source body and a drain contact metal on the drain body, a first metal body in a metallization level, the metallization level interfacing with the source contact metal, the drain contact metal, and the gate electrode, the first metal body on and continuous between the gate electrode and one of the source contact metal or the drain contact metal, and a second metal body in the metallization level, the second metal body on the other of the source contact metal and the drain contact metal.

In one or more second embodiments, further to the first embodiments, the source contact metal, the drain contact metal, and the gate electrode are in a contact level below the metallization level, a lower surface of the first metal body and a lower surface of the second metal body are substantially coplanar in a metallization plane, and an upper surface of the source contact metal, an upper surface of the drain contact metal, and an upper surface of the gate electrode are substantially coplanar in a contact plane above the channel structure, the contact plane interfacing with the metallization plane.

In one or more third embodiments, further to the first or second embodiments, the transistor structure is a first transistor structure, the gate electrode is a first gate electrode, the metallization plane is a first metallization plane, the first and second metal bodies are in a first dielectric layer in the metallization level and over the contact level, a second dielectric layer is over the first dielectric layer and the metallization level, an upper surface of the first metal body and an upper surface of the second metal body are substantially coplanar in a second metallization plane, a first via extends through the second dielectric layer and interfaces with the second metal body at the second metallization plane, and a second via extends through the first and second dielectric layers and interfaces with a second gate electrode of a second transistor structure at the first metallization plane.

In one or more fourth embodiments, further to the first through third embodiments, the first and second metal bodies have a first composition different than a second composition of the first and second vias.

In one or more fifth embodiments, further to the first through fourth embodiments, the first and second metal bodies have a first composition different than a second composition of the source contact metal and the drain contact metal or a third composition of the gate electrode.

In one or more sixth embodiments, further to the first through fifth embodiments, the first composition of the first and second metal bodies is substantially the same as the second composition of the source contact metal and the drain contact metal.

In one or more seventh embodiments, further to the first through sixth embodiments, the first metal body includes first and second portions, the first portion extends in a first direction between the gate electrode and the one of the source contact metal or the drain contact metal, and the second portion of the first metal body extends in a second direction orthogonal to the first direction.

In one or more eighth embodiments, further to the first through seventh embodiments, the transistor structure is a first transistor structure, the source body is a first source body, and the drain body is a first drain body, the source contact metal is a first source contact metal, and the drain contact metal is a first drain contact metal, and the second portion of the first metal body extending in the second direction contacts a second source contact metal or a second drain contact metal on a second source or drain body of a second transistor structure.

In one or more ninth embodiments, further to the first through eighth embodiments, a first distance separating the first and second metal bodies is greater than a second distance separating the gate electrode and the other of the source contact metal and the drain contact metal.

In one or more tenth embodiments, an apparatus includes a transistor structure including a source body, a drain body, and a gate electrode over a channel structure, a source contact metal on the source body and a drain contact metal on the drain body, wherein an upper surface of the source contact metal, an upper surface of the drain contact metal, and an upper surface of the gate electrode are substantially coplanar above the channel structure, and first and second metal bodies in a dielectric layer over the transistor structure, the first metal body in contact with the gate electrode and one of the source contact metal or the drain contact metal, the first metal body continuous between the gate electrode and one of the source contact metal or the drain contact metal, the second metal body in contact with the other of the source contact metal and the drain contact metal.

In one or more eleventh embodiments, further to the tenth embodiments, lower surfaces of the first and second metal bodies are substantially coplanar at a first height above the channel structure, and upper surfaces of the first and second metal bodies are substantially coplanar at a second height above the channel structure.

In one or more twelfth embodiments, further to the tenth or eleventh embodiments, the transistor structure is a first transistor structure, the gate electrode is a first gate electrode, the dielectric layer is a first dielectric layer, a second dielectric layer is over the first dielectric layer, a first via extends through the second dielectric layer to the second height and contacts the second metal body, and a second via extends through the first and second dielectric layers to the first height and contacts a second gate electrode of a second transistor structure.

In one or more thirteenth embodiments, further to the tenth through twelfth embodiments, the first metal body includes first and second portions, the first metal body continuous between the first and second portions, the first portion extends in a first direction between the gate electrode and the one of the source contact metal or the drain contact metal, and the second portion of the first metal body extends in a second direction orthogonal to the first direction.

In one or more fourteenth embodiments, further to the tenth through thirteenth embodiments, the source body is a first source body, the source contact metal is a first source contact metal, the drain body is a first drain body, the drain contact metal is a first drain contact metal, and the second portion contacts a second source contact metal or a second drain contact metal on a second source or drain body of a third transistor structure.

In one or more fifteenth embodiments, further to the tenth through fourteenth embodiments, an integrated circuit (IC) die includes the transistor structure, the IC die is coupled to a substrate, and the transistor structure is coupled to a power supply through the substrate.

In one or more sixteenth embodiments, a method includes covering a transistor structure with a first dielectric layer, the first dielectric layer on a gate electrode and a source or drain contact, the transistor structure including the gate electrode, the source or drain contact, and a source or drain body under the source or drain contact, the source or drain contact on the source or drain body, patterning an opening in the first dielectric layer over the gate electrode and the source or drain contact, depositing a metal in the opening, wherein the metal on the gate electrode and the source or drain contact, and a lower edge of the metal is above the gate electrode and the source or drain contact, and covering the first dielectric layer and the metal with a second dielectric layer.

In one or more seventeenth embodiments, further to the sixteenth embodiments, the method also includes planarizing a first upper surface of the transistor structure, wherein the covering the transistor structure with the first dielectric layer deposits a dielectric material on a second upper surface of the gate electrode and a third upper surface of the source or drain contact, and the second upper surface of the gate electrode and the third upper surface of the source or drain contact are approximately level at a height.

In one or more eighteenth embodiments, further to the sixteenth or seventeenth embodiments, the method also includes coupling the transistor structure by forming a via through at least the second dielectric layer.

In one or more nineteenth embodiments, further to the sixteenth through eighteenth embodiments, the via is a first via, the transistor structure is a first transistor structure, the gate electrode is a first gate electrode, the coupling the transistor structure forms the first via through the second dielectric layer, the first via contacting the source or drain contact, and the method also includes forming a second via through the first and second dielectric layers, the second via contacting a second gate electrode of a second transistor structure.

In one or more twentieth embodiments, further to the sixteenth through nineteenth embodiments, the transistor structure is a first transistor structure, the source or drain contact is a first source or drain contact, the patterning the opening in the first dielectric layer forms orthogonal first and second portions of the opening, the first portion over the gate electrode and the source or drain contact and extending in a first direction, and the second portion extending in a second direction over a second source or drain contact of a second transistor structure, the second direction orthogonal with the first direction, and the depositing the metal in the opening couples the first and second transistor structures.

The disclosure can be practiced with modification and alteration, and the scope of the appended claims is not limited to the embodiments so described. For example, the above embodiments may include specific combinations of features. However, the above embodiments are not limiting in this regard and, in various implementations, the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The scope of the patent rights should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.