Power Grid Architecture

The present application claims priority to U.S. Provisional App. No. 63/699,893, entitled “Power Grid Architecture,” filed Sep. 27, 2024, the disclosure of which is incorporated by reference herein in its entirety.

Embodiments described herein relate to power and signal routing for semiconductor devices. More particularly, embodiments described herein relate to implementations for power grid routing through power switches between a power supply and functional circuits.

Power switch circuits are important in large scale integrations of integrated circuits (such as very-large scale integrations (VLSIs)). For instance, power switches are implemented to convert true power supply voltages (e.g., true VDD or TVDD) provided by power supplies to virtual power supply voltages that are tailored for specific devices. In many instances, power switch devices are placed between functional circuits in a core logic region of a device and the power supply source. The connectivity involving devices with power switches includes routings for TVDD, VVDD (e.g., the converted power supply voltage), and VSS (e.g., the ground supply voltage). These routings may involve long paths that utilize large amounts of resources in the power switch region and the core logic region around the functional circuits. Accordingly, there are both electrical and mechanical reasons for optimizing the utilization of physical resources when implementing the various routings for TVDD, VVDD, and VSS.

Although the embodiments disclosed herein are susceptible to various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and are described herein in detail. It should be understood, however, that drawings and detailed description thereto are not intended to limit the scope of the claims to the particular forms disclosed. On the contrary, this application is intended to cover all modifications, equivalents and alternatives falling within the spirit and scope of the disclosure of the present application as defined by the appended claims.

The present disclosure is directed to the implementation of connectivity between power supply sources, power switch circuits, and functional circuits in integrated circuit devices. Specifically, the connectivity involves routings of the actual power supply voltage (referred to, herein, as “true power supply voltage” or “TVDD”) from a power supply source to power switches, routings of lower supply voltages (referred to, herein, as “virtual power supply voltages” or “VVDDs”) from the power switches to specific functional circuits, and routings of ground supply voltage (referred to, herein, as “ground supply voltage” or “VSS”) from the power supply source to the functional circuits.

As used herein, the term “routing” refers to any combination of metal vias, metal wires, metal traces, terminals, etc. that provide a path/route between two structures. Additional embodiments may be contemplated where the metal in “routing” is replaced with an alternative conductive material. For instance, the metal in “routing” may be replaced with a superconductor material, a semiconductor material, or a non-metal conductor. Routings may be part of a “power grid” or a “power network” for a particular voltage. For instance, a power grid/network for TVDD includes the various routings for TVDD between the power supply source and the power switches.

Power switch circuits are implemented in many current iterations of VLSI (“very large scale integration”) devices. For low power VLSI devices, power switch circuits are essential in converting higher power supply voltages to lower operating voltages for specific circuits (such as functional circuits) in the VLSI. For instance, power switch circuits may convert the actual power supply voltage (“TVDD”) from a power supply source to a lower supply voltage (“VVDD”) that is usable for operation of a specific circuit (e.g., a specific functional circuit) in a core logic region of a device.

1 FIG. 1 FIG. 100 100 110 120 120 130 140 130 150 130 150 140 100 depicts a schematic side-view representation of an implementation of power switches in an integrated circuit device, according to some embodiments. Integrated circuit devicemay be, for example, a VLSI device. In the illustrated embodiment, integrated circuit deviceincludes power supply sourceand transistor region. Transistor regionincludes core logic regionand power switch (PSW) region. In some embodiments, core logic regionmay be referred to as a switched logic region or a gated logic region. Functional circuitsmay be positioned in core logic region. Functional circuitsmay include various active circuits that receive converted power supply voltages (e.g., VVDD) from power switches in power switch region. Examples of functional circuits include, but are not limited to, switched logic circuits or gated logic circuits. It should be noted that the various regions of deviceare shown schematically and that no specific position of one region relative to another region is implied by the placements of the regions in.

1 FIG. 2 FIG. 140 120 100 130 150 140 140 210 120 200 210 As shown in, power switch regionis located in transistor regionof devicealong with core logic regionand functional circuits. In various embodiments, power switch regionincludes a plurality of power switch circuits.depicts a side-view representation of a power switch region in a transistor region above a substrate, according to some embodiments. In the illustrated embodiment, power switch regionincludes a plurality of power switches (PSWs)A-J formed in transistor regionabove substrate. Power switchesmay be, for example, FET (field-effect transistor) power switches or other types of integrated circuit power switches capable of switching or converting voltages.

2 FIG. 210 200 120 210 200 210 200 120 120 140 140 200 In certain embodiments, as shown in, power switchesA-J are an array of power switches aligned in a horizontal dimension above substratein transistor region. For instance, power switchesA-J may be aligned linearly in the horizontal dimension above substrate. Power switchesA-J may be positioned at any distance above substratein transistor region. In some embodiments, transistor regionmay include multiple power regionswith each power region having multiple power switches. The multiple power regionsmay be spaced at different heights and in different horizontal positions relative to substrate.

210 140 110 150 130 110 150 210 1 FIG. In various embodiments, power switch circuitsin power switch regionmay convert TVDD (the true power supply voltage from power supply source) to one or more VVDDs (virtual power supply voltages specific to functional circuitsin core logic region). Meanwhile, as shown in, the ground supply voltage (VSS) may be provided directly from power supply sourceto functional circuitswithout any change in the voltage. In some embodiments, the ground supply voltage (VSS) may also be routed to power switch circuits, as described herein.

140 130 120 100 160 170 180 115 110 120 115 160 170 180 115 120 140 120 120 With both power switch regionand core logic regionpositioned in transistor regionof device, there are various pathways of routings for each of the three power networks—TVDD power network, VVDD power network, and VSS power network—through the transistor region. In certain embodiments, metal routing(e.g., layers of metal routing) is positioned between power supply sourceand transistor region. Metal routingmay include the various layers or sets of layers of power network routing for TVDD, VVDD, and VSS. In certain embodiments, metal routingis located in topside (e.g., BEOL) metal layers above transistor region. While power switch regionmay represent only a small amount of the resources in the transistor region (e.g., 2-5%), connectivity involving the power networks, which are associated with the power switches, may occupy valuable resources within transistor region. Thus, efficient utilization of resources for the power networks may provide additional area in transistor regionfor other utilizations.

3 4 FIGS.A-B The present disclosure recognizes that various connectivity designs may be implemented to efficiently route power network resources through the transistor region of an integrated circuit device having power switches. In various embodiments, efficiently routing the power network resources involves selection of different types of routing in various metal layers associated with the routing. Examples of different types of routing utilized herein include pillar routing and mesh routing, which are described in detail below with reference to.

Efficiently routing the power network resources through the transistor region may provide additional area for other resources in the transistor region. For instance, resources may be available for as additional routings (e.g., signal routings) or the placement of additional components or circuits. Adding capability for additional resources beyond power network resources may improve freedom and flexibility in the design of the VLSI device or improve the operational capacity of the VLSI device. The opened up capability may be utilized, for example, to increase the number of other types of transistors or circuit elements, allowing for more complex or powerful devices. In some instances, the design of integrated circuits may include more optimized routing strategies for signals in the devices with more efficient power network routing. Manufacturing may also be more efficient in certain instances with optimized design strategies.

Certain embodiments disclosed herein have three broad elements: 1) a transistor region with a core logic region and a power switch region; 2) three sets of one or more metal layers positioned above the transistor region for routing of power network resources to the core logic region or the power switch region, and 3) selection of various types of pillar routing and mesh routing in the sets of metal layers based on the power network and the destination of the routing in the power network.

140 130 150 In various embodiments directed to TVDD routing, TVDD routing for connections is provided to power switch regiononly with no connections to core logic regionor functional circuit. In certain embodiments, for the power switch connections, the first set of metal layers (e.g., the set closest to the transistor region and the power switch) has pillar routing in the last metal layer furthest from the transistor region with the rest of the layers having mesh routing. In various embodiments, the TVDD routing includes combinations of mesh and pillar routing in the second and third sets of one or more metal layers above the first set of metal layers.

140 130 150 In various embodiments directed to VVDD routing, VVDD routing includes only the first set of metal layers (e.g., the set closest to the transistor region) and has connections to both power switch regionand core logic regionand functional circuitsin the core logic region. In certain embodiments, the first set of metal layers (e.g., the set closest to the transistor region and the power switch) has mesh routing in the last metal layer furthest from the transistor region where the mesh routing provides a connection between the routing above power switch region connected to the power switch and the routing above the core logic region connected to the functional circuits. In various embodiments, the VVDD routing above the power switch region includes only mesh routing while the VVDD routing above the core logic region includes some pillar routing.

140 130 150 In various embodiments directed to VSS routing, VSS routing has connections to both power switch regionand core logic regionand functional circuitsin the core logic region from the power supply source. In certain embodiments, a lowest metal layer in the second set of metal layers (e.g., the metal layer in the second set closest to the transistor region) and the last metal layer furthest from the transistor region both have mesh routing. In some embodiments, the second set of metal layers includes at least two metal layers with pillar routing between the lowest and last metal layers. The first set of metal layers may include mesh routing connected to the transistor region along with a combination of pillar and mesh routing or pillar only routing. In certain embodiments, the lowest metal layer in the third set of metal layers (furthest set from transistor region) includes mesh routing for distributing ground supply voltage.

As used herein, the term “pillar routing” refers to routing (e.g., metal structures) in a metal layer that primarily transfers current vertically through the metal layer. For instance, pillar routing may be structurally and functionally similar to a via through an insulating layer where the via transfers current vertically through the insulating layer. In some instances, pillar routing may be referred to as pillar pattern metallization or vertical routing.

3 FIG.A 3 FIG.A 300 310 310 310 320 320 310 310 310 depicts a side-view representation of pillar routing, according to some embodiments. In the illustrated embodiment, pillar routingis shown for each of metal layerA, metal layerB, and metal layerC. ViasA andB interconnect metal structures in the metal layers through intermediate insulating layers (not shown). As shown in, current (solid line arrow) primarily transfers up or down between the pillar routes (e.g., metal structures) of metal layerA, metal layerB, and metal layerC.

310 310 310 310 310 320 320 310 310 310 3 FIG.A In certain embodiments, metal structures in the metal layers with pillar routing (such as metal layerA, metal layerB, and metal layerC) have horizontal dimensions (e.g., length or width) that are designed to be, at most, a minimum amount necessary for landing a specified number (e.g., n) of vias going down or up from the pillar routing. For example, as shown in, the metal structures in metal layerA and metal layerC may have lengths (dashed line arrow) that are a minimum needed to land four vias with the length of a via (e.g., length of viaA or viaB). Accordingly, metal layerA and metal layerC are designed to have metal structures with a maximum length of four via lengths. As another example, metal layerB may have metal structures with a length that is a minimum needed to land two vias and thus the metal layer is designed to have metal structures with a maximum length of two via lengths.

3 FIG.B 3 FIG.B 3 FIG.B 310 320 310 330 320 330 330 310 330 320 330 320 310 300 330 depicts a top plan view representation of pillar routing, according to some embodiments. In the illustrated embodiment, a single metal layer (e.g., metal layerA) and a single layer of vias (e.g., vias) is shown. Metal layerA includes a layer of pillar routesconnected to a layer of viasA. Pillar routesare metal structures that, as described above, have lengths dimensioned as minimum lengths for landing a specified number of vias routing above or below the metal structures. With the limited lengths of pillar routes, as shown, in, the pillar routes will primarily transfer current up or down through metal layerA. For instance, one pillar routetransfers current up or down through vias (e.g., viaA) connected to the pillar route. Whiledepicts a grid of pillar routesand viasA, it should be understood that the layout of metal layerA may include any number of pillar routes placed in any arrangement depending on the desired design of pillar routing. For instance, as one example, some pillar routesmay be removed to provide more spacing between remaining pillar routes.

As used herein, the term “mesh routing” refers to routing (e.g., metal structures) in a metal layer that transfers current both vertically through the metal layer and across the metal layer over a wide distance horizontally (e.g., a wide horizontal area). Accordingly, mesh routing may transfer current over greater horizontal distances than vertical distance. For instance, while mesh routing transfer current vertically through the metal layer, mesh routing typically has much larger horizontal dimensions (e.g., length and width) than vertical dimensions (e.g., height). Thus, mesh routing transfers current more significantly (e.g., over longer distances) in the horizontal dimensions than in the vertical dimension. In some instances, mesh routing may be referred to as mesh pattern metallization or interconnect metallization. Generally speaking, mesh routing encompasses more resource utilization than pillar routing due to the wider distribution of metal over the horizontal dimensions.

4 FIG.A 4 FIG.A 400 410 410 410 420 420 410 410 420 420 410 410 410 depicts a side-view representation of mesh routing, according to some embodiments. In the illustrated embodiment, mesh routingis shown for metal layerA and metal layerC while metal layerB includes pillar routing. ViasA andB interconnect metal structures in the metal layers through intermediate insulating layers (not shown). As shown in, current (solid line arrow) primarily transfers horizontally in the mesh routing metal layers—horizontally through metal structures in metal layerA and metal layerC. ViasA,B and metal layerB (e.g., pillar routing) provide vertical transfer of current between metal layerA and metal layerC.

410 410 410 410 410 420 410 420 410 420 410 410 420 410 4 FIG.A 4 FIG.A In certain embodiments, mesh routing transfers current across a horizontal area that covers an area of a logic block or design block in a device. For instance, metal layerA may transfer current horizontally across an entire block length (dashed line arrow), as shown in. Accordingly, metal layerA distributes current across the area of the entire block. Metal layerC may also distribute current across the area of the block. Thus, one possible current path in the illustrated embodiment ofmay be, starting in on the left side of metal layer—across metal layerA′ to the right, down viaA′, down metal layerB′, down viaB′, across metal layerC to the left, up viaB, up metal layerB (which is same metal layer asB′ but a separate pillar), and up viaA back to metal layerA.

4 FIG.B 410 420 410 430 420 430 400 410 430 440 depicts a top plan view representation of mesh routing, according to some embodiments. In the illustrated embodiment, a single metal layer (e.g., metal layerA) and a single layer of vias (e.g., viasA) is shown. Metal layerA includes a layer of mesh routesA-E connected to a layer of viasA. Mesh routesA-E are, for example, metal structures that have lengths approximately spanning dimensions of the logic block. It should be understood that mesh routingmay include any number of mesh routes in metal layerA. Additionally, some embodiments may be contemplated where one or more of mesh routesare interconnected. For instance, cross-connector(dashed line) may be placed between one or more mesh routes to interconnect the routes.

4 FIG.B 400 430 420 430 420 400 420 430 410 As shown in, mesh routingincludes mesh routesthat primarily transfer current horizontally across the metal layer with any number of viasA connected to the mesh routes. As with mesh routes, the number and arrangement of viasA may vary depending on the design needs for mesh routing. For instance, the number of viasA connecting to a mesh route (e.g., mesh routeA) may vary depending on the desired transfer of current vertically to/from metal layerA.

5 16 FIGS.- 510 520 530 510 520 530 530 530 Various embodiments of routing of power network resources to a core logic region or a power switch region of a transistor region are now described with reference to. The embodiments described herein generally reference routing through three different sets of one or more metal layers—a first set of one or more metal layers, a second set of one or more metal layers, and a third set of one or more metal layers. Unless otherwise explicitly indicated, it should be understood that the number of metal layers in each set—,,—may vary. For instance, only a single metal layer (A) is depicted for the third set of metal layersbut it should be understood that the third set of metal layers may include any number of additional metal layers.

5 16 FIGS.- 5 FIG. 550 550 510 Additionally, it should be understood that unless specifically indicated, pillar routing or mesh routing may be used interchangeably where appropriate in the disclosed embodiments. For instance, pillar routing or mesh routing may be used interchangeably in instances where neither routing is specifically called for in the disclosed embodiments.further include basic representations of viasfor interconnection through insulating layers (not shown). It should be understood that any number of vias between metal layers may be implemented as desired or available. For example, multiple viasmay be placed between metal layers with mesh routing to further interconnect the metal layers and improve electrical conductivity between the metal layers. Additionally, in some depictions, vias are not shown between metal layers with pillar routing for simplicity in the drawings. As one example, metal layerE, in, includes pillar routing where the via that would be vertically above the metal layer is included as part of the depiction of the metal layer.

5 FIG. 5 16 FIGS.- 5 FIG. 500 210 140 530 530 210 510 510 550 210 510 510 140 120 depicts a side-view representation of TVDD routing over a power switch region of a device, according to some embodiments. Note that in, pillar routing in metal layers is indicated by the metal layer having no pattern while mesh routing in the metal layers is indicated by the metal layer having a dotted pattern. In the illustrated embodiment of, TVDD routingincludes routing between a power supply source and power switchin power switch region. Routing to the power supply source may include, for example, additional metal layers above metal layerA in third set of metal layers. Connection to power switchmay be made by metal layerA. Metal layerA may include, for example, a pin or other connection terminal connecting viaabove the metal layer to power switch. In some embodiments, metal layerA is a lowest metal layer in first set of metal layers(e.g., a metal layer vertically closest to power switch regionin transistor region).

510 500 510 510 510 510 140 510 510 510 510 510 510 520 520 Going up from metal layerA, in various embodiments, TVDD routingincludes mesh routing in metal layersB,C,D. Then, in the last metal layer of first set of metal layersfurthest from power switch region(e.g., metal layerE), pillar routing is implemented. Mesh routing may be used in the intermediate metal layers of first metal layers(e.g., metal layersB,C,D) to provide high interconnectivity between the metal layers while pillar routing is used in the uppermost/last metal layerE of the first set of metal layers to provide specific contact to a first metal layer in the next set of metal layers—metal layerA in second set of metal layers.

520 520 520 500 140 600 130 600 130 600 130 150 130 6 FIG. 6 FIG. In certain embodiments, the first metal layer in second set of metal layers(e.g., metal layerA) uses mesh routing. Utilizing mesh routing in metal layerA interconnects TVDD routingabove power switch regionto TVDD routingabove core logic region(shown in).depicts a side-view representation of TVDD routingover core logic regionof a device, according to some embodiments. Note that TVDD routingis absent any routing in the first set of metal layers above core logic region. No routing is needed in this instance since TVDD is not connected to any structures (e.g., any functional circuits) in core logic region.

520 530 500 600 520 520 520 520 520 520 520 5 6 FIGS.and From metal layerA upwards to metal layerA, both TVDD routingand TVDD routing, shown in, may be substantially identical in structure, as described together herein. In certain embodiments, second set of metal layersincludes primarily pillar routing in metal layers. For instance, in the illustrated embodiment, metal layersB-F andH may be layers of pillar routing while metal layersG,I,J are layers of mesh routing. The use of primarily pillar routing in second set of metal layersreduces the amount of routing resources in the second set of metal layers used for TVDD routing and enables additional space for other resources (e.g., signal routing or devices positioned in the topside metal layers).

530 530 530 520 520 520 520 130 140 The lowest metal layer,A, in third set of metal layersmay be mesh routing. Between the mesh routing in metal layerA and the mesh routing in any of the second set of metal layers—e.g., metal layersA,G,I,J, TVDD routing can be distributed between above core logic regionand power switch regionto allow increased TVDD capacity or lower resistance through higher metal usage.

7 FIG. 8 FIG. 7 FIG. 8 FIG. 700 800 510 140 130 510 210 150 depicts a side-view representation of VVDD routing over a power switch region of a device, according to some embodiments.depicts a side-view representation of VVDD routing over a core logic region of a device, according to some embodiments. In various embodiments, VVDD routing, shown in, and VVDD routing, shown in, are limited to first set of metal layersas the VVDD routing stays within the first set of metal layers for direct routing between power switch regionand core logic region. The direct routing provided in first set of metal layersprovides VVDD voltage directly from power switchto functional circuits.

7 FIG. 700 210 510 510 550 210 510 700 510 510 510 120 In certain embodiments, as shown in, VVDD routingincludes a connection to power switchfor VVDD made by metal layerA. Metal layerA may include, for example, a pin or other connection terminal connecting viaabove the metal layer to power switch. Above metal layerA, VVDD routingmay include all or primarily mesh routing in metal layersB-D with metal layerD being the uppermost metal layer in first set of metal layers (e.g., the furthest metal layer in the first set from transistor region).

700 800 800 510 0 510 510 510 510 510 0 150 130 510 510 510 0 510 510 700 140 8 FIG. Using mesh routing increases the capacity for VVDD routingand allows transfer of VVDD to the metal layers above core logic region for VVDD routingthrough the mesh routing. In certain embodiments, as shown in, VVDD routingincludes primarily mesh routing (e.g., metal layers-,C,D) with some pillar routing in metal layersA,B. Metal layer-may be a connection layer to functional circuitsin core logic regionthat provides distributed, high capacity connection for VVDD to the functional circuits. Pillar routing in metal layersA,B may thus provide directed connections to metal layer-while mesh routing in metal layersC,D provides connected mesh with the same metal layers in VVDD routingabove power switch region.

9 10 FIGS.and 9 FIG. 10 FIG. 9 FIG. 10 FIG. 900 140 700 1000 130 800 510 510 0 510 510 depict a possible alternative embodiment of VVDD routing.depicts another side-view representation of VVDD routing over a power switch region of a device.depicts another side-view representation of VVDD routing over a core logic region of a device, according to some embodiments. In certain embodiments, VVDD routingabove power switch region, shown inis substantially similar to VVDD routing. VVDD routingabove core logic region, shown in, may, however, have an increased amount of pillar routing compared to VVDD routingwith all pillar routing in metal layersA-C between the lowest metal layer-and the uppermost metal layerD. The use of more pillar routing may be implemented to allow more space for additional resources in first set of metal layers.

11 FIG. 12 FIG. 11 FIG. 12 FIG. 210 140 150 130 530 520 530 520 520 520 510 1100 1200 510 510 510 510 0 210 150 depicts a side-view representation of VSS routing over a power switch region of a device, according to some embodiments.depicts a side-view representation of VSS routing over a core logic region of a device, according to some embodiments. In various embodiments, VSS routing connects to both power switchesin power switch regionand functional circuitsin core logic region. In the illustrated embodiments ofand, third set of metal layersand second set of metal layershave substantially identical arrangements of mesh routing and pillar routing. For instance, metal layerA is mesh routing, metal layersF-J are mesh routing, metal layersB-E are pillar routing, and metal layerA is mesh routing. Additionally, first set of metal layersin both VSS routingand VSS routingmay be substantially identical to each other with metal layersC-E being mesh routing and metal layersA-B being pillar routing. Metal layer-may be used for connections to power switchor functional circuits, as described herein.

13 FIG. 1300 510 510 510 130 510 depicts a side-view representation of an alternative embodiment of VSS routing over a power switch region of a device. In the illustrated embodiment, VSS routinghas substantially all mesh routing in first set of metal layers(e.g., metal layersB-E are mesh routing) over power switch regionwith metal layerA being a connection layer that may include mesh routing or other types of connection.

14 FIG. 1400 510 510 510 510 0 150 depicts a side-view representation of an alternative embodiment of VSS routing over a core logic region of a device. In some embodiments, VSS routinghas primarily pillar routing in first set of metal layers(e.g., metal layersA-E are pillar routing). Metal layer-is a connection layer to functional circuits. The use of primarily pillar routing increases space for additional resources, as described herein.

15 16 FIGS.and 15 FIG. 13 FIG. 16 FIG. 14 FIG. 1500 1300 1600 520 520 520 520 510 1400 1600 depict a possible alternative embodiment of VSS routing.depicts a side-view representation of VSS routingover a power switch region of a device that is substantially similar to VSS routingin.depicts a side-view representation of another alternative embodiment of VSS routing over a core logic region of a device. In the illustrated embodiment, VSS routingis primarily pillar routing in second set of metal layerswith metal layerA being mesh routing and remaining metal layersB-F being pillar routing. First set of metal layersis also primarily pillar routing (similar to VSS routing, shown in). Accordingly, VSS routingincludes more pillar routing and further increased space for other resources in the topside metal layers.

17 25 FIGS.- 5 16 FIGS.- 17 25 FIGS.- 3 4 FIGS.A andA 17 25 FIGS.- 5 16 FIGS.- 17 25 FIGS.- 17 25 FIGS.- depict cross-sectional side-view representations of various possible steps in an exemplary embodiment of a method for manufacturing the various routing structures with mesh routings and pillar routings shown in. Note thatare shown along cross-sectional views similar tofor showing results of manufacturing (e.g., process) steps to form various embodiments of mesh routing and pillar routing. For instance, the cross-sectional side-view representations inillustrate possible structural results of manufacturing steps for forming mesh routing on a substrate, pillar routing on a substrate, mesh routing on mesh routing, mesh routing on pillar routing, pillar routing on mesh routing, and pillar routing on pillar routing. The various routing structures depicted inmay be constructed based on the principals of the individual manufacturing steps for mesh routings and pillar routings shown in. Furthermore, it is noted thatdepict cross-sectional side-view representations of intermediate structural results (e.g., structural end results for mesh routing or pillar routing layers in a layer-by-layer manufacturing process) of manufacturing steps involved in forming the full routing structures described herein.

17 25 FIGS.- In various embodiments, one or more semiconductor manufacturing processing steps are implemented to form the intermediate structural results or structural end results depicted in. Examples of semiconductor manufacturing processing steps include, but are not limited to, wafer fabrication, etching (e.g., material removal), photolithography processing, deposition (e.g., material deposition), planarization (e.g., chemical mechanical planarization), ion implantation (e.g., doping), packaging, and packaging test (e.g., end product testing). Etching may include any of various etching techniques such as, but not limited to, wet etching, dry etching, plasma etching, and laser etching. Photolithography processing may include steps for mask deposition, irradiation (e.g., patterning), pattern transfer (including any related etching, deposition, or ion implantation steps), and mask removal (if necessary). Material deposition may include deposition processes such as, but not limited to, physical deposition, chemical deposition, chemical vapor deposition, evaporation, diffusion, spin coating, and electron beam deposition.

17 25 FIGS.- 17 25 FIGS.- Any of the various semiconductor manufacturing processing steps mentioned above along with any related semiconductor manufacturing processing steps not explicitly disclosed may be implemented to arrive at the structures depicted inwith the understanding that those skilled in the art would be able to determine a set of appropriate semiconductor manufacturing processing steps for implementing the depicted structures based on the present disclosure. Additionally, at some points throughout the present disclosure, semiconductor manufacturing processing steps may be explicitly recited in relation to specific structures. In such instances, it is understood that variations beyond the explicitly recited semiconductor manufacturing processing steps may be possible as known to those skilled in the art. Thus, whiledepict one exemplary embodiment for step-by-step manufacturing of devices described herein, additional embodiments for manufacturing devices described herein may be contemplated with modifications or alternatives that fall within the spirit or scope of the present disclosure where such modification or alternatives may include variations on the disclosed semiconductor manufacturing processing steps.

17 FIG. 1700 510 0 is a cross-sectional side-view representation of a beginning manufacturing step for forming routing on a substrate, according to some embodiments. In the illustrated embodiment, substratemay be any substrate on which the routing structures described herein may be formed. Examples include, but are not limited to, a semiconductor substrate, a metal connection layer (e.g., a metal layer connecting to circuits such as metal layer-, described herein), a layer of terminals connecting to circuits, and a dielectric layer.

1710 1700 1710 1700 1700 1720 1710 1720 1710 17 FIG. In certain embodiments, insulation layeris formed on substrate. Insulation layermay be, for example, a dielectric layer or other electrically insulating layer formed on substrate. As shown in, manufacturing/processing to form routing on substratemay begin with forming viasthrough insulation layer. Viasmay be formed, for example, by forming openings in insulationand filling the openings with material (e.g., electrically conductive material) for the vias.

18 FIG. 18 FIG. 410 1710 410 430 430 1720 1720 1720 430 is a cross-sectional side-view representation of a manufacturing step for forming mesh routing on a substrate, according to some embodiments. In the illustrated embodiment, metal layeris formed on insulation layer. Metal layerincludes mesh route. In certain embodiments, mesh routeis a metal structure that has at least one horizontal dimension (e.g., length) that spans a corresponding horizontal dimension (e.g., length) of a logic block and couples to multiple viasacross its length. For instance, as shown in, the logic block may span between viaand via′ and mesh routecorrespondingly spans across both the vias.

430 1810 1810 1810 430 430 410 1810 In various embodiments, mesh routeis enclosed (e.g., encapsulated) in insulation layer. Insulation layermay be a dielectric layer or other electrically insulating layer. In some embodiments, insulation layeris formed first and then mesh routeis formed in the insulation layer by forming openings in the insulation layer and then depositing metal in the openings. In some embodiments, mesh route(and metal layer) is formed first and then insulation layeris formed around (e.g., formed to encapsulate) the mesh route.

19 FIG. 19 FIG. 310 1710 310 330 330 330 1720 is a cross-sectional side-view representation of a manufacturing step for forming pillar routing on a substrate, according to some embodiments. In the illustrated embodiment, metal layeris formed on insulation layer. Metal layerincludes pillar routes. In certain embodiments, pillar routesare metal structures that have horizontal dimensions (e.g., length or width) that are designed to be, at most, a minimum amount necessary for landing a specified number of vias going down or up from the pillar routes. For instance, as shown in, pillar routeshave lengths designed to be a minimum amount for landing multiple vias.

330 1910 1910 1910 330 330 310 1910 In various embodiments, pillar routesare enclosed in insulation layer. Insulation layermay be a dielectric layer or other electrically insulating layer. In some embodiments, insulation layeris formed first and then pillar routesare formed in the insulation layer by forming openings in the insulation layer and then depositing metal in the openings. In some embodiments, pillar routes(and metal layer) are formed first and then insulation layeris formed around (e.g., formed to encapsulate) the pillar routes.

20 FIG. 20 FIG. 2010 2020 430 410 2010 410 2020 2020 1720 1710 2020 1720 is a cross-sectional side-view representation of a manufacturing step for forming vias on mesh routing, according to some embodiments. In the illustrated embodiment, insulation layerwith viasis formed on mesh routeand metal layer. In certain embodiments, insulation layeris formed on metal layerfirst and then viasare formed in the insulation layer by forming openings and depositing via material (e.g., electrically conductive material) in the openings. In some embodiments, as shown in, viasare aligned with viasin the underlying insulation layer. Additional embodiments may be contemplated where viasare not aligned with vias.

2010 2020 410 430 430 410 2110 21 FIG. 20 FIG. With insulation layerand viasformed on metal layerand mesh route(e.g., mesh routing), embodiments may be contemplated where either additional mesh routing is formed on the insulation layer and vias above the mesh routing or pillar routing is formed on the insulation layer and vias above the mesh routing.is a cross-sectional side-view representation of a manufacturing step for forming mesh routing on mesh routing, according to some embodiments. In the illustrated embodiment, mesh route′ of metal layer′ and insulation layerare formed on the structure shown in.

430 2110 2110 430 430 410 2110 2020 430 430 410 410 In various embodiments, mesh route′ is enclosed by insulation layer, which may be a dielectric layer or other electrically insulating layer. In some embodiments, insulation layeris formed first and then mesh route′ is formed in the insulation layer as described herein. In some embodiments, mesh route′ (and metal layer′) is formed first and then insulation layerencapsulates the mesh route. In various embodiments, multiple viasconnect mesh routeto mesh route′, which distributes current transfer over a wide distance horizontally between both metal layerand metal layer′.

22 FIG. 20 FIG. 330 310 2210 330 2210 2210 330 330 310 2210 330 2020 330 2020 2010 2210 430 is a cross-sectional side-view representation of a manufacturing step for forming pillar routing on mesh routing, according to some embodiments. In the illustrated embodiment, pillar routes′ of metal layer′ and insulation layerare formed on the structure shown in. In various embodiments, pillar routes′ are enclosed by insulation layer, which may be a dielectric layer or other electrically insulating layer. In some embodiments, insulation layeris formed first and then pillar routes′ are formed in the insulation layer as described herein. In some embodiments, pillar routes′ (and metal layer′) are formed first and then insulation layerencapsulates the pillar routes. In certain embodiments, pillar routes′ are aligned with viasin the underlying layer. Pillar routes′ and viasmay be aligned to provide substantially vertical current transfer through insulation layersandfrom the underlying mesh route.

23 FIG. 2310 2320 330 310 2320 330 2320 330 310 2310 is a cross-sectional side-view representation of a manufacturing step for forming vias on pillar routing, according to some embodiments. In the illustrated embodiment, insulation layerwith viasis formed on pillar routesand metal layer. In certain embodiments, viasare aligned with pillar routes. Alignment between viasand pillar routesmaintains electrical contiguity between metal layerand any metal layer formed above insulation layer.

2310 310 2320 2310 2320 310 330 In certain embodiments, insulation layeris formed on metal layerfirst and then viasare formed in the insulation layer by forming openings and depositing via material (e.g., electrically conductive material) in the openings. With insulation layerand viasformed on metal layerand pillar routes(e.g., the pillar routing), embodiments may be contemplated where either additional pillar routing is formed on the insulation layer and vias above the pillar routing or mesh routing is formed on the insulation layer and vias above the pillar routing.

24 FIG. 23 FIG. 330 310 2410 330 2410 2410 330 330 310 2410 330 2320 330 330 1710 1910 2310 2410 is a cross-sectional side-view representation of a manufacturing step for forming pillar routing on pillar routing, according to some embodiments. In the illustrated embodiment, pillar routes′ of metal layer′ and insulation layerare formed on the structure shown in. In various embodiments, pillar routes′ are enclosed by insulation layer, which may be a dielectric layer or other electrically insulating layer. In some embodiments, insulation layeris formed first and then pillar routes′ are formed in the insulation layer as described herein. In some embodiments, pillar routes′ (and metal layer′) are formed first and then insulation layerencapsulates the pillar routes. In certain embodiments, pillar routes′ are aligned with viasin the underlying layer. Accordingly, pillar routes′ are aligned with pillar routesand the structure may provide substantially vertical current transfer through the various insulation layers (e.g., through insulation layers,,, and).

25 FIG. 23 FIG. 430 410 2510 430 2510 2510 430 430 410 2510 430 2320 330 430 330 310 410 2320 330 430 is a cross-sectional side-view representation of a manufacturing step for forming mesh routing on pillar routing, according to some embodiments. In the illustrated embodiment, mesh route′ of metal layer′ and insulation layerare formed on the structure shown in. In various embodiments, mesh route′ is enclosed by insulation layer, which may be a dielectric layer or other electrically insulating layer. In some embodiments, insulation layeris formed first and then mesh route′ is formed in the insulation layer as described herein. In some embodiments, mesh route′ (and metal layer′) is formed first and then insulation layerencapsulates the mesh route. In various embodiments, mesh route′ connects to multiple vias, which are connected to individual pillar routes. Accordingly, mesh route′ may electrically connect together the individual pillar routesin metal layerand distribute current transfer over a wide distance horizontally in metal layer′. Embodiments may be contemplated, however, where one or more of viasare removed to inhibit electrical connection between pillar routesby mesh route′.

17 26 FIGS.- 5 6 FIGS.- 7 10 FIGS.- 11 16 FIGS.- 500 700 900 1000 1100 1200 1300 1400 1500 1600 Note that similar steps for forming any of the mesh routing, pillar routing, or via structures described herein may be implemented based on the illustrated steps shown in. Further, it should be noted that these steps may also form the basis of any process for forming a routing structure that has various combinations of mesh routing and pillar routing. For instance, the steps described may form the basis for forming any of the disclosed TVDD routings(shown in), VVDD routings//(shown in), or VSS routings/////(shown in).

26 FIG. 2600 2600 2606 2606 2606 2602 2604 2608 Turning next to, a block diagram of one embodiment of a systemis shown that may incorporate and/or otherwise utilize the methods and mechanisms described herein. In the illustrated embodiment, the systemincludes at least one instance of a system on chip (SoC)which may include multiple types of processing units, such as a central processing unit (CPU), a graphics processing unit (GPU), or otherwise, a communication fabric, and interfaces to memories and input/output devices. In some embodiments, one or more processors in SoCincludes multiple execution lanes and an instruction issue queue. In various embodiments, SoCis coupled to external memory, peripherals, and power supply.

2608 2606 2602 2604 2608 2606 2602 A power supplyis also provided which supplies the supply voltages to SoCas well as one or more supply voltages to the memoryand/or the peripherals. In various embodiments, power supplyrepresents a battery (e.g., a rechargeable battery in a smart phone, laptop or tablet computer, or other device). In some embodiments, more than one instance of SoCis included (and more than one external memoryis included as well).

2602 The memoryis any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of the SDRAMs such as mDDR3, etc., and/or low power versions of the SDRAMs such as LPDDR2, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are coupled onto a circuit board to form memory modules such as single inline memory modules (SIMMs), dual inline memory modules (DIMMs), etc. Alternatively, the devices are mounted with a SoC or an integrated circuit in a chip-on-chip configuration, a package-on-package configuration, or a multi-chip module configuration.

2604 2600 2604 2604 2604 The peripheralsinclude any desired circuitry, depending on the type of system. For example, in one embodiment, peripheralsincludes devices for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular, global positioning system, etc. In some embodiments, the peripheralsalso include additional storage, including RAM storage, solid state storage, or disk storage. The peripheralsinclude user interface devices such as a display screen, including touch display screens or multitouch display screens, keyboard or other input devices, microphones, speakers, etc.

2600 2600 2610 2620 2630 2640 2650 2660 As illustrated, systemis shown to have application in a wide range of areas. For example, systemmay be utilized as part of the chips, circuitry, components, etc., of a desktop computer, laptop computer, tablet computer, cellular or mobile phone, or television(or set-top box coupled to a television). Also illustrated is a smartwatch and health monitoring device. In some embodiments, smartwatch may include a variety of general-purpose computing related functions. For example, smartwatch may provide access to email, cellphone service, a user calendar, and so on. In various embodiments, a health monitoring device may be a dedicated medical device or otherwise include dedicated health related functionality. For example, a health monitoring device may monitor a user's vital signs, track proximity of a user to other users for the purpose of epidemiological social distancing, contact tracing, provide communication to an emergency service in the event of a health crisis, and so on. In various embodiments, the above-mentioned smartwatch may or may not include some or any health monitoring related functions. Other wearable devices are contemplated as well, such as devices worn around the neck, devices that are implantable in the human body, glasses designed to provide an augmented and/or virtual reality experience, and so on.

2600 2670 2600 2680 2600 2690 2600 2600 26 FIG. 26 FIG. Systemmay further be used as part of a cloud-based service(s). For example, the previously mentioned devices, and/or other devices, may access computing resources in the cloud (i.e., remotely located hardware and/or software resources). Still further, systemmay be utilized in one or more devices of a homeother than those previously mentioned. For example, appliances within the home may monitor and detect conditions that warrant attention. For example, various devices within the home (e.g., a refrigerator, a cooling system, etc.) may monitor the status of the device and provide an alert to the homeowner (or, for example, a repair facility) should a particular event be detected. Alternatively, a thermostat may monitor the temperature in the home and may automate adjustments to a heating/cooling system based on a history of responses to various conditions by the homeowner. Also illustrated inis the application of systemto various modes of transportation. For example, systemmay be used in the control and/or entertainment systems of aircraft, trains, buses, cars for hire, private automobiles, waterborne vessels from private boats to cruise liners, scooters (for rent or owned), and so on. In various cases, systemmay be used to provide automated guidance (e.g., self-driving vehicles), general systems control, and otherwise. These any many other embodiments are possible and are contemplated. It is noted that the devices and applications illustrated inare illustrative only and are not intended to be limiting. Other devices are possible and are contemplated.

The present disclosure includes references to “an “embodiment” or groups of “embodiments” (e.g., “some embodiments” or “various embodiments”). Embodiments are different implementations or instances of the disclosed concepts. References to “an embodiment,” “one embodiment,” “a particular embodiment,” and the like do not necessarily refer to the same embodiment. A large number of possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of the disclosure.

This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all implementations of these embodiments will necessarily manifest any or all of the potential advantages. Whether an advantage is realized for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. In fact, there are a number of reasons why an implementation that falls within the scope of the claims might not exhibit some or all of any disclosed advantages. For example, a particular implementation might include other circuitry outside the scope of the disclosure that, in conjunction with one of the disclosed embodiments, negates or diminishes one or more the disclosed advantages. Furthermore, suboptimal design execution of a particular implementation (e.g., implementation techniques or tools) could also negate or diminish disclosed advantages. Even assuming a skilled implementation, realization of advantages may still depend upon other factors such as the environmental circumstances in which the implementation is deployed. For example, inputs supplied to a particular implementation may prevent one or more problems addressed in this disclosure from arising on a particular occasion, with the result that the benefit of its solution may not be realized. Given the existence of possible factors external to this disclosure, it is expressly intended that any potential advantages described herein are not to be construed as claim limitations that must be met to demonstrate infringement. Rather, identification of such potential advantages is intended to illustrate the type(s) of improvement available to designers having the benefit of this disclosure. That such advantages are described permissively (e.g., stating that a particular advantage “may arise”) is not intended to convey doubt about whether such advantages can in fact be realized, but rather to recognize the technical reality that realization of such advantages often depends on additional factors.

Unless stated otherwise, embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of claims that are drafted based on this disclosure, even where only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative rather than restrictive, absent any statements in the disclosure to the contrary. The application is thus intended to permit claims covering disclosed embodiments, as well as such alternatives, modifications, and equivalents that would be apparent to a person skilled in the art having the benefit of this disclosure.

For example, features in this application may be combined in any suitable manner. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of other dependent claims where appropriate, including claims that depend from other independent claims. Similarly, features from respective independent claims may be combined where appropriate.

Accordingly, while the appended dependent claims may be drafted such that each depends on a single other claim, additional dependencies are also contemplated. Any combinations of features in the dependent that are consistent with this disclosure are contemplated and may be claimed in this or another application. In short, combinations are not limited to those specifically enumerated in the appended claims.

Where appropriate, it is also contemplated that claims drafted in one format or statutory type (e.g., apparatus) are intended to support corresponding claims of another format or statutory type (e.g., method).

Because this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. Public notice is hereby given that the following paragraphs, as well as definitions provided throughout the disclosure, are to be used in determining how to interpret claims that are drafted based on this disclosure.

References to a singular form of an item (i.e., a noun or noun phrase preceded by “a,” “an,” or “the”) are, unless context clearly dictates otherwise, intended to mean “one or more.” Reference to “an item” in a claim thus does not, without accompanying context, preclude additional instances of the item. A “plurality” of items refers to a set of two or more of the items.

The word “may” is used herein in a permissive sense (i.e., having the potential to, being able to) and not in a mandatory sense (i.e., must).

The terms “comprising” and “including,” and forms thereof, are open-ended and mean “including, but not limited to.”

When the term “or” is used in this disclosure with respect to a list of options, it will generally be understood to be used in the inclusive sense unless the context provides otherwise. Thus, a recitation of “x or y” is equivalent to “x or y, or both,” and thus covers 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, a phrase such as “either x or y, but not both” makes clear that “or” is being used in the exclusive sense.

A recitation of “w, x, y, or z, or any combination thereof” or “at least one of . . . w, x, y, and z” is intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrasings cover any single element of the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase “at least one of ... w, x, y, and z” thus refers to at least one element of the set [w, x, y, z], thereby covering all possible combinations in this list of elements. This phrase is not to be interpreted to require that there is at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

Various “labels” may precede nouns or noun phrases in this disclosure. Unless context provides otherwise, different labels used for a feature (e.g., “first circuit,” “second circuit,” “particular circuit,” “given circuit,” etc.) refer to different instances of the feature. Additionally, the labels “first,” “second,” and “third” when applied to a feature do not imply any type of ordering (e.g., spatial, temporal, logical, etc.), unless stated otherwise.

The phrase “based on” is used to describe one or more factors that affect a determination. This term does not foreclose the possibility that additional factors may affect the determination. That is, a determination may be solely based on specified factors or based on the specified factors as well as other, unspecified factors. Consider the phrase “determine A based on B.” This phrase specifies that B is a factor that is used to determine A or that affects the determination of A. This phrase does not foreclose that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover an embodiment in which A is determined based solely on B. As used herein, the phrase “based on” is synonymous with the phrase “based at least in part on.”

The phrases “in response to” and “responsive to” describe one or more factors that trigger an effect. This phrase does not foreclose the possibility that additional factors may affect or otherwise trigger the effect, either jointly with the specified factors or independent from the specified factors. That is, an effect may be solely in response to those factors, or may be in response to the specified factors as well as other, unspecified factors. Consider the phrase “perform A in response to B.” This phrase specifies that B is a factor that triggers the performance of A, or that triggers a particular result for A. This phrase does not foreclose that performing A may also be in response to some other factor, such as C. This phrase also does not foreclose that performing A may be jointly in response to B and C. This phrase is also intended to cover an embodiment in which A is performed solely in response to B. As used herein, the phrase “responsive to” is synonymous with the phrase “responsive at least in part to.” Similarly, the phrase “in response to” is synonymous with the phrase “at least in part in response to.”

Within this disclosure, different entities (which may variously be referred to as “units,” “circuits,” other components, etc.) may be described or claimed as “configured” to perform one or more tasks or operations. This formulation—[entity] configured to [perform one or more tasks]—is used herein to refer to structure (i.e., something physical). More specifically, this formulation is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure can be said to be “configured to” perform some task even if the structure is not currently being operated. Thus, an entity described or recited as being “configured to” perform some task refers to something physical, such as a device, circuit, a system having a processor unit and a memory storing program instructions executable to implement the task, etc. This phrase is not used herein to refer to something intangible.

In some cases, various units/circuits/components may be described herein as performing a set of task or operations. It is understood that those entities are “configured to” perform those tasks/operations, even if not specifically noted.

The term “configured to” is not intended to mean “configurable to.” An unprogrammed FPGA, for example, would not be considered to be “configured to” perform a particular function. This unprogrammed FPGA may be “configurable to” perform that function, however. After appropriate programming, the FPGA may then be said to be “configured to” perform the particular function.

For purposes of United States patent applications based on this disclosure, reciting in a claim that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112(f) for that claim element. Should Applicant wish to invoke Section 112(f) during prosecution of a United States patent application based on this disclosure, it will recite claim elements using the “means for” [performing a function] construct.

Different “circuits” may be described in this disclosure. These circuits or “circuitry” constitute hardware that includes various types of circuit elements, such as combinatorial logic, clocked storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memory (e.g., random-access memory, embedded dynamic random-access memory), programmable logic arrays, and so on. Circuitry may be custom designed, or taken from standard libraries. In various implementations, circuitry can, as appropriate, include digital components, analog components, or a combination of both. Certain types of circuits may be commonly referred to as “units” (e.g., a decode unit, an arithmetic logic unit (ALU), functional unit, memory management unit (MMU), etc.). Such units also refer to circuits or circuitry.

The disclosed circuits/units/components and other elements illustrated in the drawings and described herein thus include hardware elements such as those described in the preceding paragraph. In many instances, the internal arrangement of hardware elements within a particular circuit may be specified by describing the function of that circuit. For example, a particular “decode unit” may be described as performing the function of “processing an opcode of an instruction and routing that instruction to one or more of a plurality of functional units,” which means that the decode unit is “configured to” perform this function. This specification of function is sufficient, to those skilled in the computer arts, to connote a set of possible structures for the circuit.

In various embodiments, as discussed in the preceding paragraph, circuits, units, and other elements defined by the functions or operations that they are configured to implement, The arrangement and such circuits/units/components with respect to each other and the manner in which they interact form a microarchitectural definition of the hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitectural definition. Thus, the microarchitectural definition is recognized by those of skill in the art as structure from which many physical implementations may be derived, all of which fall into the broader structure described by the microarchitectural definition. That is, a skilled artisan presented with the microarchitectural definition supplied in accordance with this disclosure may, without undue experimentation and with the application of ordinary skill, implement the structure by coding the description of the circuits/units/components in a hardware description language (HDL) such as Verilog or VHDL. The HDL description is often expressed in a fashion that may appear to be functional. But to those of skill in the art in this field, this HDL description is the manner that is used transform the structure of a circuit, unit, or component to the next level of implementational detail. Such an HDL description may take the form of behavioral code (which is typically not synthesizable), register transfer language (RTL) code (which, in contrast to behavioral code, is typically synthesizable), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL description may subsequently be synthesized against a library of cells designed for a given integrated circuit fabrication technology, and may be modified for timing, power, and other reasons to result in a final design database that is transmitted to a foundry to generate masks and ultimately produce the integrated circuit. Some hardware circuits or portions thereof may also be custom-designed in a schematic editor and captured into the integrated circuit design along with synthesized circuitry. The integrated circuits may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.) and interconnect between the transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuits, and/or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized to a programmable logic array such as a field programmable gate array (FPGA) and may be implemented in the FPGA. This decoupling between the design of a group of circuits and the subsequent low-level implementation of these circuits commonly results in the scenario in which the circuit or logic designer never specifies a particular set of structures for the low-level implementation beyond a description of what the circuit is configured to do, as this process is performed at a different stage of the circuit implementation process.

The fact that many different low-level combinations of circuit elements may be used to implement the same specification of a circuit results in a large number of equivalent structures for that circuit. As noted, these low-level circuit implementations may vary according to changes in the fabrication technology, the foundry selected to manufacture the integrated circuit, the library of cells provided for a particular project, etc. In many cases, the choices made by different design tools or methodologies to produce these different implementations may be arbitrary.

Moreover, it is common for a single implementation of a particular functional specification of a circuit to include, for a given embodiment, a large number of devices (e.g., millions of transistors). Accordingly, the sheer volume of this information makes it impractical to provide a full recitation of the low-level structure used to implement a single embodiment, let alone the vast array of equivalent possible implementations. For this reason, the present disclosure describes structure of circuits using the functional shorthand commonly employed in the industry.