Semiconductor Package and Method of Manufacturing Semiconductor Package

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Many integrated circuits are typically manufactured on a single semiconductor wafer. The dies of the wafer may be processed and packaged at the wafer level, and various technologies have been developed for wafer level packaging.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

A package and the method of forming the same are provided in accordance with various embodiments. The intermediate stages of forming the package are illustrated in accordance with some embodiments. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It is appreciated that although the formation of System-on-Integrated-Chips (SoIC) packages is used as examples to explain the concept of the embodiments of the present disclosure, the embodiments of the present disclosure are readily applicable to other packages.

1 FIG. 9 FIG. 1 FIG. 110 101 110 110 110 110 110 101 102 101 101 110 102 101 102 toillustrates a cross sectional views of intermediate stages in the manufacturing of a semiconductor package according to some embodiments of the present disclosure. Referring to, in some embodiments, a wafer (or a substrate)is provided over a carrier. In some embodiments, the wafermay include a plurality of dies, with some details of one of diesillustrated. In one embodiment, each of the diesmay be a system on chip (SOC), or the like. In other embodiment, the wafermay be an interposer wafer, which is free from active devices such as transistors and/or diodes. The interposer wafer may be free from passive devices such as capacitors, inductors, resistors, or the like, or may include passive devices. In some embodiments, the carriermay be a glass carrier. In some embodiments, a de-bonding layermay be provided over the carrierfor bonding the carrierand the wafer. In one embodiment, the de-bonding layeris a light-to heat-conversion (LTHC) release layer, for example. The materials of the carrierand the de-bonding layerare not limited in this disclosure.

110 111 111 111 111 111 In accordance with some embodiments of the present disclosure, the waferincludes semiconductor substrateand the features formed over semiconductor substrate. The semiconductor substratemay be formed of crystalline silicon, crystalline germanium, crystalline silicon germanium, and/or a III-V compound semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and the like. The semiconductor substratemay also be formed of other rigid materials such as glass, silicon oxide, silicon carbide, or the like. In some embodiments, the semiconductor substratemay also be a bulk silicon substrate.

113 111 113 113 111 In one embodiments, at least one dielectric layeris formed over the semiconductor substrate. In accordance with some embodiments of the present disclosure, the dielectric layeris formed of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxy-carbide, or the like. In accordance with some embodiments, the dielectric layeris formed of silicon oxide, a thermal oxidation may be performed on semiconductor substrateto form oxide layer.

111 113 115 115 115 32 1 FIG. In some embodiments, over the semiconductor substrate(and the dielectric layer) resides interconnect structure. It is noted thatillustrates the interconnect structureschematically, and the disclosure is not limited thereto. In some embodiments, the interconnect structureincludes metal lines/contacts, which are formed in dielectric layers. The dielectric layers are alternatively referred to as Inter-Metal Dielectric (IMD) layers hereinafter. In accordance with some embodiments of the present disclosure, at least the lower layers of dielectric layers are formed of low-k dielectric materials, which may have dielectric constants (k-value) lower than about 3.0. The dielectric layers may be formed of Black Diamond (a registered trademark of Applied Materials), a carbon-containing low-k dielectric material, Hydrogen SilsesQuioxane (HSQ), MethylSilsesQuioxane (MSQ), or the like. In accordance with alternative embodiments of the present disclosure, some or all of dielectric layers are formed of non-low-k dielectric materials such as silicon oxide, silicon carbide (SiC), silicon carbo-nitride (SiCN), silicon oxy-carbo-nitride (SiOCN), or the like. In accordance with some embodiments of the present disclosure, the formation of dielectric layersincludes depositing a porogen-containing dielectric material, and then performing a curing process to drive out the porogen, and hence the remaining dielectric layers are porous. Etch stop layers (not shown), which may be formed of silicon carbide, silicon nitride, or the like, are formed between IMD layers, and are not shown for simplicity.

115 In accordance with some embodiments of the present disclosure, the interconnect structureincludes a plurality of metal layers that are interconnected through vias. The metal layers may be formed of copper or copper alloys, and they can also be formed of other metals. The formation process may include single damascene process and dual damascene process. In an example of the single damascene process, a trench is first formed in one of dielectric layers, followed by filling the trench with a conductive material. A planarization process such as a Chemical Mechanical Polish (CMP) process is then performed to remove the excess portions of the conductive material higher than the top surface of the IMD layer, leaving a metal line in the trench. In a dual damascene process, both a trench and a via opening are formed in an IMD layer, with the via opening underlying and connected to the trench. The conductive material is then filled into the trench and the via opening to form a metal line and a via, respectively.

112 111 112 115 112 111 111 111 112 112 112 In some embodiments, a plurality of through vias (or through substrate vias (TSVs))are formed to extend through the semiconductor substrate. The TSVsare electrically connected to the interconnect structure. The TSVsmay be formed by forming openings in the semiconductor substrateand filling the openings with electrically conductive material(s). In one embodiment, the openings may extend into the semiconductor substratewithout extending through the substrate. In some embodiments, the conductive material filled the TSVsmay include copper, although other suitable materials such as aluminum, tungsten, alloys, doped polysilicon, combinations thereof, and the like, may alternatively be utilized. The conductive material may be formed by depositing a seed layer and then electroplating copper onto the seed layer, filling and overfilling the openings for the TSV. A planarization process, such as CMP, may be performed next to remove excess portions of the conductive material disposed outside the openings for the TSV.

110 116 116 116 116 In some embodiments, the waferfurther includes surface dielectric layerformed at its top surface. The surface dielectric layeris formed of a non-low-k dielectric material such as silicon oxide. The surface dielectric layeris alternatively referred to as a passivation layer since it has the function of isolating the underlying low-k dielectric layers (if any) from the adverse effect of moisture and detrimental chemicals. The surface dielectric layermay also have a composite structure including more than one layer, which may be formed of silicon oxide, silicon nitride, Undoped Silicate Glass (USG), or the like.

114 1168 112 114 114 116 114 114 In some embodiments, a plurality of bond padsare formed in surface dielectric layerand are electrically connected to the TSVs. In accordance with some embodiments of the present disclosure, the bond padsare formed through a single damascene process, and may also include barrier layers and a copper-containing material formed over the respective barrier layers. In accordance with alternative embodiments of the present disclosure, the bond padsare formed through a dual damascene process. The top surface dielectric layerand the bond padsare planarized so that their top surfaces are coplanar, which may be resulted due to the CMP in the formation of the bond pads.

120 110 120 120 120 120 120 2 FIG. Next, a plurality of device diesare bonded over the wafer, as shown in. In accordance with some embodiments of the present disclosure, each of device diesmay also include memory dies. In some embodiments, each of device diesmay be a Central Processing Unit (CPU) die, a Micro Control Unit (MCU) die, an input-output (IO) die, a BaseBand (BB) die, an Application processor (AP) die, or the like. In addition, the device diesmay be different types of dies selected from the above-listed types. Also, one of device diesmay be a digital circuit die, while the other may be an analog circuit die. The device diesin combination function as a system. Splitting the functions and circuits of a system into different dies may optimize the formation of these dies, and may achieve the reduction of manufacturing cost.

120 121 122 120 120 123 120 123 The device diesmay include semiconductor substrates, respectively, which may be silicon substrates. In some embodiments, integrated circuit devices, which may include active devices such as transistors and/or diodes, and passive devices such as capacitors, resistors, or the like are formed in the device dies. Also, the device diesinclude interconnect structures, respectively, for connecting to the active devices and passive devices in the device dies. The interconnect structuresinclude metal lines and vias.

120 124 114 110 124 120 116 110 120 In some embodiments, each of the device diesincludes a plurality of bond pads. In one embodiment, the bonding may be achieved through hybrid bonding. For example, the bond padsof the waferare bonded to the bond padsof the device diesthrough metal-to-metal direct bonding. In accordance with some embodiments of the present disclosure, the metal-to-metal direct bonding includes a copper-to-copper direct bonding. Furthermore, the dielectric layersof the waferare bonded to the dielectric layers of the device diesthrough fusion bonding.

120 116 114 120 110 120 120 To achieve the hybrid bonding, the device diesare first pre-bonded to the dielectric layerand bond padsby lightly pressing the device diesagainst the wafer. Although two device diesare illustrated, the hybrid bonding may be performed at wafer level, and a plurality of device die groups identical to the illustrated die group (which include device dies) are pre-bonded, and arranged as rows and columns.

120 114 124 124 114 After all the device diesare pre-bonded, an anneal is performed to cause the inter-diffusion of the metals in the bond padsand the corresponding overlying bond pads. The annealing temperature may be in the range between about 200° and about 400° C., and may be in the range between about 300° and about 400° C. in accordance with some embodiments. The annealing time may be in the range between about 1.5 hours and about 3.0 hours, and may be in the range between about 1.5 hours and about 2.5 hours in accordance with some embodiments. The bond padsare bonded to the corresponding bond padsthrough direct metal bonding caused by metal inter-diffusion.

116 120 116 110 120 The dielectric layeris also bonded to the dielectric layers of the device dies, with bonds formed therebetween. For example, the atoms (such as oxygen atoms) in one of the dielectric layers form chemical or covalence bonds with the atoms (such as silicon atoms) in the other one of dielectric layers. The resulting bonds between the dielectric layersof the waferand the dielectric layers of the device diesare dielectric-to-dielectric bonds.

120 110 114 124 120 110 120 110 In an alternative embodiment, the device diesmay be bonded to the waferthrough a plurality of external connectors disposed between the bond padsand the bond pads. In such embodiments, an underfill material may be formed between the device diesand the waferto at least encapsulate the external connectors after the device diesare attached to the wafer.

3 FIG. 3 FIG. 130 110 120 130 130 130 130 110 120 130 110 120 130 a a a a a a a 2 2 3 Referring to, an encapsulating materialis provided over the waferfor encapsulating the device die. In some embodiments, the encapsulating materialmay be an oxide, such as silicon oxide, and is formed by a suitable formation method such as PCV, CVD, or the like. Although oxide is used as an example of the encapsulating material, the encapsulating materialmay be formed of other suitable materials, such as polymer, molding compound, molding underfill, epoxy, and/or resin. Accordingly, the encapsulating materialmay be conformally covering upper surfaces of the waferand the device dieswith a uniform thickness as shown in. In the embodiment, an upper surface of the encapsulating materialis a non-planar surface, which conforms to the profile of the waferand the device dies. In one embodiment, the encapsulating materialmay include base material, which may be a polymer, a resin, an epoxy, or the like, and filler particles in the base material. The base material may be a carbon-based polymer. The filler particles may be the particles of a dielectric material(s) such as SiO, AlO, silica, the compound of iron (Fe), the compound of sodium (Na), or the like, and may have spherical shapes. Also, the spherical filler particles may have the same or different diameters. The disclosure is not limited thereto.

3 FIG. 4 FIG. 130 130 120 2 130 1 120 130 120 130 120 130 a Then, referring toand, a (first) thinning process is performed over the encapsulating material, so that the encapsulating materialbeing thinned and flattened reveals the back surface of the device dies. In some embodiments, the thinning process includes chemical mechanical polishing (CMP) process. After the thinning process is performed, a height hof the encapsulating materialis substantially lower than a maximum height hof each of the device dies. Accordingly, the back surface of the encapsulating materialis lower than the back surface of the device die, so as to cause a step difference at an interface between the encapsulating materialand the device die, and a valley portion (i.e., concave) corresponds to the encapsulating material.

121 120 1211 121 120 1211 120 150 4 FIG. 6 FIG. a In addition, a dishing effect occurs in the thinning process, which causes the center portion of the substrateof the devices dieis formed into a concave dish-shape by the difference in polishing rates on the back surfaceof the substratesof the device dies. Accordingly, the back surfaceof the device dieincludes a dish-shape concave as shown in. As such, difficulties arise in the later bonding process, so a filling material (e.g., the filling materialshown in) is usually provided for compensating the step difference causing by thinning process. Oxide is generally used as the filling material since it is formed by chemical vapor deposition (CVD) for depositing in greater thickness. However, the filling material formed of oxide possesses low thermal conductivity of approximately 1.3 W/m.K, which would significantly reduce the heat dissipation efficiency of the semiconductor package.

5 FIG. 140 120 130 140 140 140 120 130 140 T Accordingly, referring to, in some embodiments, after the thinning process, a thermal conductive layeris conformally deposited over the device diesand the encapsulating material. In some embodiments, the material of the thermal conductive layerincludes aluminum nitride, silicon carbide, silicon nitride, or the like, and can be formed by physical vapor deposition (PVD) process, or chemical vapor deposition (CVD) process, etc. The thermal conductivity of the thermal conductive layeris at least greater than about 50 W/m.K. In the present embodiment, the thermal conductive layerincludes aluminum nitride (AlN) and is formed by PVD process, so as to conformally covering the device diesand the encapsulating materialwith uniform thickness. Aluminium nitride (AlN) is a solid nitride of aluminium, which is an electrical insulator with high thermal conductivity of up to 321 W/(m.K). Silicon carbide (SiC) can be formed by CVD process with greater thickness, and has high thermal conductivity of 120 W/(m.K), and a pure SiC mono-crystals exhibit a room temperature thermal conductivity (K) of 490 W/(m.K). In some embodiments, a thickness of the thermal conductive layeris substantially equal to or smaller than about 3 kA.112

140 1 120 120 2 120 140 1 1 130 140 120 140 Accordingly, there is at least one step difference at an upper surface of the thermal conductive layer. For example, one of the step difference (i.e., valley portions C) is at a location corresponding to an interface between the encapsulating materialand the device dies, and one of the step difference (i.e., concaves C) is at a location corresponding to the back surfaces of the device dies. In other words, the profile of the thermal conductive layerincludes valley portions C, wherein the location of the valley portion Ccorresponds to the encapsulating materialwith lower height. In addition, the thermal conductive layerconformally covering an inner surface of the concaves at the back surfaces of the device dies. In the present embodiments, the thermal conductive layercompletely fills the concaves.

6 FIG. 150 140 1 2 140 140 150 150 130 150 150 150 140 a a a a a 2 2 3 Then, referring to, a filling materialis provided over the thermal conductive layerfor filling the step difference (i.e., the valley portions Cand the concaves C) of the thermal conductive layer. The thermal conductivity of the thermal conductive layeris higher than the thermal conductivity of the filling material, so as to improve the heat dissipation efficiency of the semiconductor package. In the present embodiments, the material of the filling materialmay be the same as that of the encapsulating material, which includes oxide, such as silicon oxide, and is formed by CVD, or the like. In other embodiments, the filling materialmay also be formed of other suitable materials, such as polymer, molding compound, molding underfill, epoxy, and/or resin. In one embodiment, the filling materialmay include base material, which may be a polymer, a resin, an epoxy, or the like, and filler particles in the base material. The base material may be a carbon-based polymer. The filler particles may be the particles of a dielectric material(s) such as SiO, AlO, silica, the compound of iron (Fe), the compound of sodium (Na), or the like, and may have spherical shapes. Also, the spherical filler particles may have the same or different diameters. The disclosure is not limited thereto. At this stage, the filling materialcompletely covers a non-planar upper surface of the thermal conductive layer.

6 FIG. 7 FIG. 150 140 140 150 150 140 1 2 120 140 a Then, referring toand, another (second) thinning process is performed over the filling materialuntil the thermal conductive layeris revealed. Accordingly, after the second thinning process, the upper surface of the thermal conductive layeris substantially coplanar with an upper surface of the filling material, so as to provide a planar bonding surface for the later bonding process. In the embodiment, the filling materialcompensates the step difference on the non-planar upper surface of the thermal conductive layerand fills the valley portions C, while the concaves Con the back surface of the device diesare filled by the thermal conductive layer.

8 FIG. 7 FIG. 104 140 150 103 104 104 104 103 104 140 150 104 Then, referring to, a carrieris bonded to the thermal conductive layerand the filling materialthrough a bonding layer. In some embodiments, the resulting structure shown inis not thick enough, so the carrier(i.e., a supporting substrate) is bonded to the resulting structure to provide mechanical strength. In some embodiments, the carriermay be a blank substrate formed of a homogenous material such as silicon, and no devices are formed on/in the carrier. In accordance with some embodiments, the bonding layermay be an adhesive film such as a thermal interface material (TIM), or the like. In other embodiments, the carriermay be bonded to the thermal conductive layerand the filling materialthrough fusion bonding. In an example of the attachment, an oxide layer, such as a silicon oxide layer, may be formed on the surface of the carrier, for example, through thermal oxidation, for performing fusion bonding.

9 FIG. 8 FIG. 9 FIG. 101 101 102 102 101 160 110 110 110 160 160 100 110 110 120 100 Then, referring to, the resulting structure shown inis separated from the carrier. That is, the carrierare removed along with the de-bonding layer. In some embodiments, the de-bonding layeris irradiated by an UV laser such that the overlying structure is peeled from the carrier. Then, the structure may be turned upside down, and a plurality of conductive terminalsare mounted over the exposed wafer, so as to electrically connect the wafer. In some embodiments, a plurality of dies, such as IPD dies, IVR dies, memory dies or the like, may also be mounted on the wafer. In some embodiments, a plurality of under-ball metallurgy (UBM) patterns are formed under the conductive terminalsfor ball mount. In some embodiments, after the conductive terminalsare formed, a singulation process is performed to form a plurality of semiconductor packages. Accordingly, the waferis diced into a plurality of (first) dieswhere the device diesare bonded over. At this point, a semiconductor packageshown inis fabricated.

140 130 120 150 140 120 104 140 150 120 110 140 104 104 With such configuration, the thermal conductive layer, which has higher thermal conductivity than the filling material, conformally covering the step difference between the encapsulating materialand the device dies, and then providing the filling materialto compensate the step difference at the upper surface of the thermal conductive layer. As such, the device diescan be thermally coupled to the carrierthrough the thermal conductive layerinstead of the filling materialwith low thermal conductivity. Therefore, the heat generated by the device diesand/or the diecan be sequentially conducted to the thermal conductive layer, the bonding layer, and then to the carrier, so as to be dissipated to exterior environment and improve the heat dissipation of the semiconductor package.

10 FIG.A 10 FIG.A 9 FIG. 10 FIG.A 100 100 100 100 2 140 150 1211 120 2 2 140 140 2 140 2 150 2 140 150 2 1211 120 a a illustrates a partial cross sectional view of the semiconductor package according to some embodiments of the present disclosure. The semiconductor packageillustrated inis similar to the semiconductor packageillustrated in, hence the same reference numerals are used to refer to the same and liked parts, and its detailed description will be omitted herein. The difference between the semiconductor packageand the semiconductor packageis the concave Cbeing filled by both the thermal conductive layerand the filling material. Referring to, in some embodiments, the back surfaceof the device dieincludes a concave Ccaused by the CMP process. In the present embodiment, the depth of the concave Cmay be slightly greater than the thickness of the thermal conductive layer, so that when the thermal conductive layerconformally covers an inner surface of the concave C, the thermal conductive layermay not be able to completely fill the concave C, and the filling materialdeposited later on fills the rest part of the concave C. That is, the thermal conductive layerand the filling materialtogether fill the concave Cat the back surfaceof the device die.

150 2 1211 1211 140 104 150 120 104 140 120 140 104 In this embodiment, the filling materialmerely covers the concave Cat the central portion of the back surfaceand the peripheral portion of the back surfaceis still covered by the thermal conductive layerand directly bonded to the carrierwithout the filling materialinterposed in between. Therefore, the device diescan still be thermally coupled to the carrierthrough the thermal conductive layer, and the heat generated by the device diescan be conducted through the thermal conductive layerto the carrierand be dissipated to the exterior environment. It is noted that “central” and “peripheral” herein may not be interpreted literally but rather be deemed as spatially relative terms, which are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.

10 FIG.B 10 FIG.B 10 FIG.B 100 100 100 2 120 140 150 1 130 140 1211 120 2 2 140 140 2 140 2 150 2 140 150 2 1211 120 b a illustrates a partial cross sectional view of the semiconductor package according to some embodiments of the present disclosure. The semiconductor packageillustrated inis similar to the semiconductor packages shown in the previous embodiments, hence the same reference numerals are used to refer to the same and liked parts, and its detailed description will be omitted herein. The difference between the semiconductor packageand the semiconductor packageis that the concaves Cat the back of the device diesare filled by both the thermal conductive layerand the filling materialwhile the valley portions Ccorresponding to the encapsulating materialare completely filled by the thermal conductive layer. Referring to, in some embodiments, the back surfaceof the device dieincludes a concave Ccaused by the CMP process. In the present embodiment, the depth of the concave Cmay be slightly greater than the thickness of the thermal conductive layer, so that when the thermal conductive layerconformally covers an inner surface of the concave C, the thermal conductive layermay not be able to completely fill the concave C, and the filling materialdeposited later on fills the rest part of the concave C. That is, the thermal conductive layerand the filling materialtogether fill the concave Cat the back surfaceof the device die.

1 140 140 2 140 2 1 150 2 140 150 2 1211 120 140 1 150 In the present embodiment, the depth of the valley portions Cmay be substantially equal to or smaller than the thickness of the thermal conductive layer, so that when the thermal conductive layerconformally covers an inner surface of the concave C, the thermal conductive layermay not be able to completely fill the concave C, but be able to completely fill the valley portions C, so that the filling materialdeposited later on fills the rest part of the concave C. That is, the thermal conductive layerand the filling materialtogether fill the concave Cat the back surfaceof the device diewhile the thermal conductive layercompletely fills the valley portions Cwithout the filling material.

10 FIG.C 10 FIG.C 100 100 140 1 2 140 1 130 2 120 c c illustrates a partial cross sectional view of the semiconductor package according to some embodiments of the present disclosure. The semiconductor packageillustrated inis similar to the semiconductor packages shown in the previous embodiments, hence the same reference numerals are used to refer to the same and liked parts, and its detailed description will be omitted herein. The difference between the semiconductor packageand the previous semiconductor packages is that the thermal conductive layercompletely fills the valley portions Cand the concaves Cwithout any filling material. In the embodiments, the material of the thermal conductive layermay include silicon carbide, silicon nitride, or the like, which can be formed by CVD process with greater thickness, so as to completely fill the valley portions Ccorresponding to the encapsulating materialand the concaves Cat the back surface of the device dies.

11 FIG. 15 FIG. 11 FIG. 15 FIG. 1 FIG. 10 FIG. 100 d toillustrates a cross sectional views of intermediate stages in the manufacturing of a semiconductor package according to some embodiments of the present disclosure. It is noted that the semiconductor packageand the manufacturing process thereof shown intocontains many features same as or similar to the previous embodiments disclosed earlier withto. For purpose of clarity and simplicity, detail description of same or similar features may be omitted, and the same or similar reference numbers denote the same or like components.

11 FIG. 11 FIG. 5 FIG. 140 120 130 170 140 170 140 170 170 150 170 140 150 Referring to, in the present embodiment, the step shown inis performed after the step the thermal conductive layeris formed, i.e., the step shown in. After the thermal conductive layer is conformally deposited over the device diesand the encapsulating material, a polishing stop layeris conformally deposited over the thermal conductive layer, so that the polishing stop layerconformally covers the non-planar upper surface of the thermal conductive layer. In some embodiments, the material of the polishing stop layerincludes silicon carbide, silicon nitride, or the like, and can be formed by physical vapor deposition (PVD) process, or chemical vapor deposition (CVD) process, etc. The thermal conductivity of the polishing stop layeris also greater than the thermal conductivity of the filling material. In some embodiments, the thermal conductivity of the polishing stop layermay be smaller than or substantially equal to that of the thermal conductive layerand is greater than the thermal conductivity of the filling material.

140 140 140 170 140 170 140 150 140 In some embodiments, the production cost of the thermal conductive layer(e.g., AlN layer) is pretty high and the thickness of the thermal conductive layeris usually thinner than 3 ka, so it is easy to polishing off the thermal conductive layerduring the later on thinning (CMP) process. The polishing stop layerprovides an adequate hard stop over the thermal conductive layer. Therefore, by adding the polishing stop layerbetween the thermal conductive layerand the filling materialcan protect the thermal conductive layerfrom being damage or even removed during the CMP process.

170 140 170 1 120 120 2 120 140 170 Since the polishing stop layeris conformally deposited over the thermal conductive layer, there is at least one step difference at an upper surface of the polishing stop layer. For example, one of the step difference (i.e., valley portions C′) is at a location corresponding to an interface between the encapsulating materialand the device dies, and one of the step difference (i.e., concaves C′) is at a location corresponding to the back surfaces of the device dies. In the present embodiments, the thermal conductive layerand the polishing stop layercompletely fills the concaves at the back surfaces of the device dies.

12 FIG. 150 170 1 2 170 150 130 150 150 150 170 a a a a a 2 2 3 Then, referring to, a filling materialis provided over the polishing stop layerfor filling the step difference (i.e., the valley portions C′ and the concaves C′) of the polishing stop layer. In the present embodiments, the material of the filling materialmay be the same as that of the encapsulating material, which includes oxide, such as silicon oxide, and is formed by CVD, or the like. In other embodiments, the filling materialmay also be formed of other suitable materials, such as polymer, molding compound, molding underfill, epoxy, and/or resin. In one embodiment, the filling materialmay include base material, which may be a polymer, a resin, an epoxy, or the like, and filler particles in the base material. The base material may be a carbon-based polymer. The filler particles may be the particles of a dielectric material(s) such as SiO, AlO, silica, the compound of iron (Fe), the compound of sodium (Na), or the like, and may have spherical shapes. Also, the spherical filler particles may have the same or different diameters. The disclosure is not limited thereto. At this stage, the filling materialcompletely covers a non-planar upper surface of the polishing stop layer.

12 FIG. 13 FIG. 150 170 170 150 150 170 1 2 a Then, referring toand, a thinning process is performed over the filling materialuntil it reaches and stops at the polishing stop layer. Accordingly, after the thinning process, the upper surface of the polishing stop layeris substantially coplanar with an upper surface of the filling material, so as to provide a planar bonding surface for the later bonding process. In the embodiment, the filling materialcompensates the step difference on the non-planar upper surface of the polishing stop layerand fills the valley portions C′ and the concaves C′.

14 FIG. 104 170 150 103 120 130 104 104 103 104 170 150 104 Then, referring to, the carrieris bonded to the polishing stop layerand the filling materialthrough a bonding layerto provide mechanical strength to the device diesand the encapsulating material. In some embodiments, the carriermay be a blank substrate formed of a homogenous material such as silicon, and no devices are formed on/in the carrier. In accordance with some embodiments, the bonding layermay be an adhesive film such as a thermal interface material (TIM), or the like. In other embodiments, the carriermay be bonded to the polishing stop layerand the filling materialthrough fusion bonding. In an example of the attachment, an oxide layer, such as a silicon oxide layer, may be formed on the surface of the carrier, for example, through thermal oxidation, for performing fusion bonding.

15 FIG. 14 FIG. 15 FIG. 101 101 102 102 101 160 110 110 110 160 160 100 110 110 120 100 d d Then, referring to, the resulting structure shown inis separated from the carrier. That is, the carrierare removed along with the de-bonding layer. In some embodiments, the de-bonding layeris irradiated by an UV laser such that the overlying structure is peeled from the carrier. Then, the structure may be turned upside down, and a plurality of conductive terminalsare mounted over the exposed wafer, so as to electrically connect the wafer. In some embodiments, a plurality of dies, such as IPD dies, IVR dies, memory dies or the like, may also be mounted on the wafer. In some embodiments, a plurality of under-ball metallurgy (UBM) patterns are formed under the conductive terminalsfor ball mount. In some embodiments, after the conductive terminalsare formed, a singulation process is performed to form a plurality of semiconductor packages. Accordingly, the waferis diced into a plurality of (first) dieswhere the device diesare bonded over. At this point, a semiconductor packageshown inis fabricated.

Based on the above discussions, it can be seen that the present disclosure offers various advantages. It is understood, however, that not all advantages are necessarily discussed herein, and other embodiments may offer different advantages, and that no particular advantage is required for all embodiments.

Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

In accordance with some embodiments of the disclosure, a semiconductor package includes a substrate, a device die, an encapsulating material, a thermal conductive layer, a filling material, and a carrier. The device die is disposed over the substrate. The encapsulating material is disposed over the substrate and laterally encapsulates the device die. The thermal conductive layer conformally covers the device die and the encapsulating material, wherein a profile of the thermal conductive layer comprises a valley portion. The filling material is disposed over the thermal conductive layer and fills the valley portion, wherein a thermal conductivity of the thermal conductive layer is higher than a thermal conductivity of the filling material. The carrier is bonded to the thermal conductive layer and the filling material. In one embodiment, a back surface of the encapsulating material is lower than a back surface of the device die, and the location of the valley portion corresponds to the encapsulating material. In one embodiment, a back surface of the device die comprises a concave, and the thermal conductive layer fills the concave. In one embodiment, a back surface of the device die comprises a concave, and the thermal conductive layer conformally covering an inner surface of the concave and the filling material fills the concave. In one embodiment, an upper surface of the thermal conductive layer is substantially coplanar with an upper surface of the filling material. In one embodiment, the thermal conductive layer comprises aluminum nitride, silicon carbide, or silicon nitride. In one embodiment, the semiconductor package further includes a polishing stop layer conformally covering an upper surface of the thermal conductive layer and disposed between the thermal conductive layer and the filling material. In one embodiment, the substrate comprises a plurality of through vias extending through the substrate. In one embodiment, the carrier is bonded to the thermal conductive layer and the filling material through a bonding layer.

In accordance with some embodiments of the disclosure, a semiconductor package includes a first die, a second die, an encapsulating material, a thermal conductive layer, a filling material, and a carrier. The second die is disposed over the first die. The encapsulating material is over the first die and laterally encapsulating the second die. The thermal conductive layer conformally covers the second die and the encapsulating material, wherein there is a step difference at an upper surface of the thermal conductive layer. The filling material is disposed over the thermal conductive layer for compensating the step difference, wherein a thermal conductivity of the thermal conductive layer is higher than a thermal conductivity of the filling material. The carrier is bonded to the thermal conductive layer and the filling material. In one embodiment, the step difference is at a location corresponding to an interface between the encapsulating material and the device die. In one embodiment, the step difference is at a location corresponding to a back surface of the device die. In one embodiment, the upper surface of the thermal conductive layer is substantially coplanar with an upper surface of the filling material. In one embodiment, the semiconductor package further includes a polishing stop layer conformally covering the upper surface of the thermal conductive layer and disposed between the thermal conductive layer and the filling material. In one embodiment, an upper surface of the polishing stop layer is substantially coplanar with an upper surface of the filling material. In one embodiment, the polishing stop layer comprises silicon carbide, or silicon nitride.

In accordance with some embodiments of the disclosure, a manufacturing method of a semiconductor package includes the following steps. A wafer is provided. A device die is bonded over the wafer. An encapsulating material is provided over the wafer for encapsulating the device die. A first thinning process is performed over the encapsulating material for revealing a back surface of the device die. A thermal conductive layer conformally deposits over the device die and the encapsulates material, wherein a profile of the thermal conductive layer includes a valley portion. A filling material is provided over the thermal conductive layer for filling the valley portion, wherein a thermal conductivity of the thermal conductive layer is higher than a thermal conductivity of the filling material. A second thinning process is performed over the filling material. A carrier is bonded to the thermal conductive layer and the filling material. In one embodiment, the thermal conductive layer is formed by physical vapor deposition. In one embodiment, the semiconductor package further includes: conformally depositing a polishing stop layer over the thermal conductive layer. In one embodiment, the carrier is bonded to the thermal conductive layer and the filling material through a bonding layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.