Semiconductor Device

The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2024-0120882 filed in the Korean Intellectual Property Office on Sep. 5, 2024, which is incorporated herein by reference in its entirety.

The embodiments of the present disclosure relate to a semiconductor device with a hybrid bonding structure.

The degree of integration of semiconductor devices continues to improve in order to achieve high capacity and miniaturization. As part of the effort to improve integration, a structure has been proposed in which components included in a semiconductor device are not manufactured on a single chip, but rather manufactured on multiple chips, and then the chips are joined using hybrid bonding.

Embodiments of the disclosure may provide a semiconductor device with improved reliability of hybrid bonding.

Embodiments of the disclosure may provide a semiconductor device including a first chip including a first bonding pad and a first insulating layer, and a second chip disposed on the first chip, and including a second bonding pad bonded to the first bonding pad and a second insulating layer bonded to the first insulating layer, wherein a bonding interface between the first insulating layer and the second insulating layer includes a first step portion disposed around a bonding interface between the first bonding pad and the second bonding pad.

Embodiments of the disclosure may provide a semiconductor device including a first chip including a first bonding pad and a first insulating layer having an opening exposing the first bonding pad, and a second chip including a second bonding pad bonded to the first bonding pad and a second insulating layer bonded to the first insulating layer, wherein the second insulating layer includes a protrusion having a side wall bonded to a side wall of the opening in the first insulating layer.

According to embodiments of the present disclosure, it is possible to improve the reliability of hybrid bonding by suppressing the formation of bridges between adjacent bonding pads and delamination of bonded chips.

Hereinafter, various embodiments of the present disclosure will be described in detail with reference to accompanying drawings. The specific structural or functional descriptions of embodiments are provided as examples to explain the concepts disclosed herein. The embodiments or examples according to the concepts of the present disclosure may be implemented in various forms, and the scope of the present disclosure is not limited to the embodiments or examples described herein.

The same hatching shown throughout the drawings may indicate corresponding or identical areas in the drawings, and does not indicate materials associated with the corresponding areas.

When one element is described as being “connected” or “coupled” to another element, the elements may be directly connected or directly coupled, or may be connected or coupled through one or more intermediate elements between the elements. When two elements are described as being “directly connected” or “directly coupled,” one element is directly connected or directly coupled to the other element without any intermediate element between the two elements.

When one element is described as being disposed “over” or “under” another element, the elements may be in direct contact with each other, or an intermediate element may be disposed between the elements.

Terms such as “vertical,” “horizontal,” “upper,” “lower,”, “up”, “down”, “top,” “bottom,” “front,” “back,” “side,” “left and right,” “column,” “row,” “level,” and other relative spatial relationships or directions are used only for the purpose of ease of description or reference to the drawings, and are not limiting to any specific meaning. Other spatial relationships or directions not shown in the drawings or described in the specification are also possible within the scope of the present specification.

Terms such as “first” and “second” may be used to distinguish different elements and do not imply size, order, priority, quantity, or importance of the elements. For example, in some embodiments, a first element may be referred to as a second element, and in other embodiments, a second element may be referred to as a first element.

When an element included in embodiments in the present specification is described in the singular form, the element may be interpreted to include a plurality of elements performing the same or similar functions.

1 FIG. 2 FIG. 1 FIG. is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure, andis an exploded view of a portion of.

1 FIG. 100 200 Referring to, a semiconductor device may include a first chipand a second chipthat are hybrid bonded.

100 200 Each of the first chipand the second chipmay include various types of electronic devices. The electronic devices may include, for example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a system Large Scale Integration (LSI), an image sensor such as a CMOS Imaging Sensor (CIS), a Micro Electro Mechanical System (MEMS), an active device, a passive device, etc.

100 200 In some embodiments, each of the first chipand the second chipmay be at least one of a Dynamic Random Access Memory (DRAM) chip, a Static Random Access Memory (SRAM) chip, a flash memory chip, an Electrically Erasable and Programmable Read Only Memory (EEPROM) chip, a Phase change Random Access Memory (PRAM) chip, a Magnetic Random Access Memory (MRAM) chip, or a Resistive Random Access Memory (RRAM) chip.

100 110 120 120 110 110 The first chipmay include first bonding padsand a first insulating layer. The first insulating layermay surround each of the first bonding padsand insulate adjacent first bonding padsfrom each other.

200 210 220 220 210 210 The second chipmay include second bonding padsand a second insulating layer. The second insulating layermay surround each of the second bonding padsand insulate adjacent second bonding padsfrom each other.

110 210 The first and second bonding padsandmay include a metal. The metal may include, for example, copper (Cu), aluminum (Al), silver (Ag), cobalt (Co), ruthenium (Ru), or an alloy thereof.

120 220 120 220 The first and second insulating layersandmay include an oxide film and a nitride film. For example, the first and second insulating layersandmay include silicon oxide (SiO2), carbon-doped silicon oxide (C-doped SiO2), silicon nitride (SiN), silicon carbon nitride (SiCN), a polymer, etc.

110 210 110 210 110 210 The first bonding padand the second bonding padmay be bonded to each other to form a metal bonding interface MB. The metal bonding interface MB may be a boundary between the first bonding padand the second bonding pad, and the first bonding padand the second bonding padmay be in contact with and bonded to each other at the metal bonding interface MB.

120 220 120 220 120 220 The first insulating layerand the second insulating layermay be bonded to each other to form an insulating bonding interface IB. The insulating bonding interface IB may be a boundary between the first insulating layerand the second insulating layer, and the first insulating layerand the second insulating layermay be in contact with and bonded to each other at the insulating bonding interface IB.

The insulating bonding interface IB may have a step portion SP around the metal bonding interface MB. In one embodiment, the step portion SP may surround the metal bonding interface MB.

2 FIG. 120 110 120 2 Referring to, in an exploded view of a metal bonding interface MB and surrounding step portions SP, the first insulating layermay have an opening OP exposing the first bonding padon a second surfaceA.

110 110 110 120 2 120 110 120 1 120 120 2 120 1 120 2 In an embodiment, the opening OP may have a larger area than the first bonding pad. The opening OP may have a larger width than the first bonding pad. The opening OP exposes the first bonding pad, the second surfaceAof the first insulating layeraround the first bonding pad, and a side wallSof the first insulating layer, which connects the second surfaceAand a first surfaceA, which is offset from the second surfaceA.

220 220 1 210 220 220 3 220 1 220 3 220 220 1 220 4 220 3 220 2 220 3 220 4 The second insulating layermay include a protrusionPsurrounding the second bonding pad. The second insulating layermay have a third surfaceA, and the protrusionPmay protrude from the third surfaceAof the second insulating layer. The protrusionPmay have a fourth surfaceAoffset from the third surfaceA, and a side wallSconnecting the third surfaceAand the fourth surfaceA.

110 210 120 1 120 220 3 220 120 2 120 220 4 220 120 1 120 220 2 220 1 FIG. 1 FIG. An upper surface of the first bonding padand a lower surface of the second bonding padmay be bonded to each other, thereby forming a metal bonding interface MB of. The first surfaceAof the first insulating layerand the third surfaceAof the second insulating layermay be bonded to each other, the second surfaceAof the first insulating layerand the fourth surfaceAof the second insulating layermay be bonded to each other, and the side wallSof the first insulating layerand the side wallSof the second insulating layermay be bonded to each other, thereby forming an insulating bonding interface IB of.

The metal included in the first and second bonding pads may be ionized, and the ions may migrate along the bonding interface between the first chip and the second chip to form a bridge between adjacent bonding pads.

1 FIG. According to an embodiment of the present disclosure, the insulating bonding interface IB has a step portion (SP in) around the metal bonding interface MB, so a distance of a migration path may increase. Furthermore, the structure of the migration path for the metal ions is more complicated. As a result, formation of a metal ion bridge between adjacent bonding pads is suppressed.

1 FIG. 100 200 100 200 100 200 In addition, the insulating bonding interface (IB in) includes a step portion SP, and compared to a case where the insulating bonding interface is planar, the bonding area between the first chipand the second chipincreases and the bonding strength between the first chipand the second chipmay be improved. Consequently, delamination between the first chipand the second chipcan be reduced.

3 14 FIGS.to 1 2 FIGS.and For the sake of simplicity, in the embodiments described below with reference to, content overlapping with that described with reference towill be briefly described or omitted.

3 4 FIGS.to are cross-sectional views of semiconductor devices according to embodiments of the present disclosure.

3 FIG. 120 110 120 110 120 110 110 Referring to, an opening OP in a first insulating layermay have a smaller area than the first bonding padembedded in the first insulating layer. The opening OP may have a smaller width than the first bonding pad. The first insulating layermay expose a center area of the first bonding padand cover an edge area of the first bonding pad.

210 211 212 211 211 210 120 211 210 212 210 211 210 212 210 211 210 The second bonding padmay include a first portionand a second portionon the first portion. The first portionof the second bonding padmay have a smaller area relative to the opening OP of the first insulating layer. The first portionof the second bonding padmay have a smaller width relative to the opening OP. The second portionof the second bonding padmay have a larger area than the first portionof the second bonding pad. The second portionof the second bonding padmay have a larger width than the first portionof the second bonding pad.

220 1 220 211 210 211 210 110 220 1 220 110 220 4 220 1 110 The protrusionPof the second insulating layermay surround the first portionof the second bonding pad. The first portionof the second bonding padmay be bonded to the first bonding pad. The protrusionPof the second insulating layermay vertically overlap with the first bonding pad, and a fourth surfaceAof the protrusionPmay contact an upper surface of the first bonding pad.

4 FIG. 210 120 210 Referring to, a second bonding padmay have a smaller area than the opening OP of a first insulating layer. The second bonding padmay have a smaller width than the opening OP.

220 1 220 210 210 110 220 1 220 110 220 4 220 1 110 A protrusionPof a second insulating layermay surround a side surface of the second bonding pad. The second bonding padmay be bonded to a first bonding pad. The protrusionPof the second insulating layermay vertically overlap with the first bonding pad, and the fourth surfaceAof the protrusionPmay contact an upper surface of the first bonding pad.

5 FIG. 6 FIG. 5 FIG. is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure, andis a perspective view of first and second bonding pads of.

5 6 FIGS.and 110 110 1 210 210 1 110 1 110 210 110 Referring to, a first bonding padmay have a recessed portionRor a concavity from an upper surface, and a second bonding padmay have a convex or protruding portionP, which is coupled with the recessed portionRof the first bonding pad. The lower surface of the second bonding padand the lower surface of the first bonding padmay be bonded to each other.

110 1 110 110 1 120 110 1 120 110 1 110 1 5 6 FIGS.and The recessed portionRmay be disposed in a center area of the first bonding pad. The recessed portionRmay be spaced apart from the first insulating layer, i.e., the surfaces of the recessed portionRmay not contact the first insulating layer. Although the recessed portionRhas a rectangular planar structure in, the shape of the recessed portionRis not limited thereto.

210 1 110 1 210 1 210 210 1 220 210 1 220 The convex portionPmay have a structure with a lower surface that is symmetrical to the surfaces common to recessed portionR. The convex portionPmay be disposed in a center area of the second bonding pad. The convex portionPmay be spaced apart from the second insulating layer, i.e., the surfaces of the convex portionPmay not contact the second insulating layer.

7 FIG. 8 FIG. 7 FIG. is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure, andis a perspective view of first and second bonding pads of.

7 8 FIGS.and 110 110 2 210 210 2 110 2 110 Referring to, a first bonding padwith an upper surface may have a plurality of recessed portionsRthat are recessed from the upper surface, and a second bonding padmay have protrusionsP, which have lower surfaces that are coupled with the recessed portionsRof the first bonding pad.

110 2 110 2 110 110 2 120 A recessed portionRmay have a line shape extending in one direction. In an embodiment, the recessed portionRmay extend across the first bonding pad, and both ends of the recessed portionRmay be connected to the first insulating layer.

210 2 110 2 210 2 210 210 2 220 The protrusionPmay have a structure symmetrical to the recessed portionR. The protrusionPmay cross the second bonding pad, and both ends of the protrusionPmay be connected to the second insulating layer.

9 FIG. 10 FIG. 9 FIG. is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure, andis a perspective view of first and second bonding pads of.

9 10 FIGS.and 110 110 1 110 1 130 110 1 110 110 120 130 120 Referring to, a first bonding padmay have a first slitSon an upper surface. The first slitSmay be filled with a first insulating pattern. In an embodiment, the first slitSmay extend across the first bonding padin one direction, and both ends of the first slitS may be connected to a first insulating layer. Both ends of the first insulating patternmay be in contact with the first insulating layer.

210 210 2 210 2 110 1 A second bonding padmay have a second slitSon a lower surface. The second slitsSmay have a structure symmetrical to the first slitsS.

210 2 230 210 2 210 210 2 220 230 220 The second slitsSmay be filled with a second insulating pattern. In an embodiment, the second slitSmay extend across the second bonding padin one direction, and both ends of the second slitSmay be connected to a second insulating layer. Both ends of the second insulating patternmay be in contact with the second insulating layer.

130 230 130 230 The first and second insulating patternsandmay include an oxide film and a nitride film. For example, the first and second insulating patternsandmay include silicon oxide (SiO2), carbon-doped silicon oxide (C-doped SiO2), silicon nitride (SiN), silicon carbon nitride (SiCN), a polymer, etc.

130 230 130 230 The first insulating patternand the second insulating patternmay vertically overlap each other, and an upper surface of the first insulating patternand a lower surface of the second insulating patternmay be bonded to each other.

130 230 110 210 130 230 100 200 100 200 The bonding strength between the first insulating patternand the second insulating patternmay be greater than the bonding strength between the first bonding padand the second bonding pad. The increased bonding strength between the first insulating patternand the second insulating patternimproves the overall adhesive strength between the first chipand the second chip, so delamination between the first chipand the second chipcan be suppressed or reduced.

11 FIG. 12 FIG. 11 FIG. is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure, andis a perspective view of first and second bonding pads of.

11 FIG. 12 FIG. 110 110 110 110 130 110 110 110 120 130 120 Referring toand, a first bonding padmay have a first slitS on an upper surface. The first slitS may have a line shape extending in a first direction FD. The first slitS may be filled with a first insulating pattern. In an embodiment, the first slitS may extend across the first bonding padin the first direction FD, and both ends of the first slitS may be connected to a first insulating layer. Both ends of the first insulating patternmay be in contact with the first insulating layer.

210 210 210 210 230 A second bonding padmay have a second slitS′ on a lower surface. The second slitS′ may have a line shape extending in a second direction SD intersecting the first direction FD. The second slitS′ may be filled with a second insulating pattern′.

210 210 210 220 230 220 In an embodiment, the second slitS′ may extend across the second bonding padin the second direction SD, and both ends of the second slitS′ may be connected to a second insulating layer. Both ends of the second insulating pattern′ may be in contact with the second insulating layer.

130 230 130 230 The first insulating patternand the second insulating pattern′ may intersect each other and vertically overlap with each other at an intersection point. At the intersection point, the first insulating patternand the second insulating pad′ may be bonded to each other.

13 FIG. is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

13 FIG. 110 110 210 210 Referring to, a first bonding padmay have a first step portionSP on an upper surface. A second bonding padmay have a second step portionSP on a lower surface.

110 210 210 110 110 210 110 210 The first step portionSP and the second step portionSP may have structures that are symmetrical to each other. For example, the height difference between horizontal surfaces of a protrusion and a recessed portion of the second step portionSP may be the same as the height difference between horizontal surfaces of a protrusion and a recessed portion of the first step portionSP. The protrusion of the first step portionSP may be bonded to the recessed portion of the second step portionSP, and the recessed portion of the first step portionSP may be bonded to the protrusion of the second step portionSP.

14 FIG. is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

14 FIG. 120 120 220 220 2 120 220 2 220 1 Referring to, a first insulating layermay have a recessed portionR around an opening OP. A second insulating layermay have a convex portionPprotruding from a lower surface of a recessed portionR. The convex portionPmay be disposed around the protrusionP.

120 220 2 By configuring a recessed portionR and a convex portionP, the length of a migration path for metal ions may be further increased, and the structure of the migration path may be further complicated. Accordingly, the formation of bridges between adjacent bonding pads may be further suppressed.

The semiconductor devices according to the embodiments described above may be a vertical NAND flash memory device. However, in other embodiments, the semiconductor device may be multi-die, chiplet type semiconductor devices.

15 FIG. 15 FIG. is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.illustrates a semiconductor device as a vertical NAND flash memory.

15 FIG. 100 200 Referring to, a first chipmay be a peripheral circuit chip, and a second chipmay be a memory chip.

100 10 11 110 120 12 The first chipmay include a first substrate, a peripheral circuit, a first bonding pad, a first insulating layer, and a first wiring structure.

11 10 11 11 11 The peripheral circuitmay be disposed on the first substrate. The peripheral circuitmay control the operation of a memory cell array MCA. The peripheral circuitmay include, for example, a row decoder, a page buffer circuit, control logic, and a voltage generator, but the circuit is not limited thereto. The peripheral circuitmay include a plurality of individual elements. The individual elements may include transistors.

120 10 11 110 120 110 120 The first insulating layermay be disposed on the first substrate, and may cover the peripheral circuit. The first bonding padmay be disposed in the first insulating layer. An upper surface of the first bonding padmay be exposed to an upper surface of the first insulating layer.

12 11 110 12 12 120 12 120 12 12 The first wiring structuremay electrically connect the peripheral circuitto a first bonding pad. The first wiring structuremay include a plurality of first conductive linesA arranged at different vertical levels within the first insulating layerand a first viaB vertically extending within the first insulating layer. The first viaB may electrically connect the plurality of first conductive linesA that are arranged at different vertical levels.

200 20 21 23 24 25 26 210 220 The second chipmay include an insulating structure, a conductive plate, a gate stack, a contact, a cell plug, a second wiring structure (), a second bonding pad, and a second insulating layer.

20 21 20 21 The insulating structuremay have a lower surface and an upper surface facing each other. The conductive platemay be disposed on a lower surface of the insulating structure. The conductive platemay include a metal material, a semiconductor material, or a combination thereof.

23 23 23 21 23 23 23 a b a a b The gate stackmay include a plurality of gate electrode layersand a plurality of interlayer insulating layersalternately stacked on the lower surface of the conductive plate. The gate electrode layersmay include a conductive material. For example, the gate electrode layersmay include tungsten (W). The interlayer insulating layersmay include silicon oxide.

23 23 23 24 23 a a a a The gate electrode layersmay include word lines. The gate electrode layersmay further include at least one source select line and at least one drain select line. The gate electrode layersmay extend in different lengths to form a step structure. Contactsmay be connected on the step structure to the gate electrode layers.

25 23 21 A plurality of cell plugsmay extend vertically through the gate stackto the conductive plate.

25 25 25 25 25 25 Each of the cell plugsmay include a channel layer and a cell gate insulating layer. The cell gate insulating layer may have a straw or cylinder shell shape that surrounds the outer wall of the channel layer. The cell gate insulating layer may include a tunnel insulating film, a charge storage film, and a blocking film that are sequentially laminated from the outer wall of the channel layer. In some embodiments, the cell gate insulating layer may have an Oxide-Nitride-Oxide (ONO) stacked structure in which an oxide film, a nitride film, and an oxide film are sequentially stacked. Memory cells may be configured in portions where word lines surround the cell plug. A source select transistor may be configured in a portion where a source select line surrounds the cell plug. A drain select transistor may be configured in a portion where a drain select line surrounds the cell plug. A drain select transistor, a plurality of memory cells, and a source select transistor arranged along one cell plugmay constitute one cell string. There may be provided a plurality of cell strings corresponding to a plurality of cell plugs. The plurality of cell strings may constitute the memory cell array MCA.

26 26 220 26 220 26 26 The second wiring structuremay include a plurality of second conductive linesA arranged at different vertical levels within the second insulating layerand a plurality of second viasB extending vertically within the second insulating layer. The plurality of second viasB may electrically connect between the plurality of second conductive linesA arranged at different vertical levels.

24 25 210 26 Each of the contactsand the cell plugsmay be connected to the second bonding padthrough the second wiring structure.

30 20 200 40 20 30 30 210 27 27 20 220 30 210 The semiconductor device may further include an external connection paddisposed on the insulating structureof the second chip, and a passivation layerdisposed on the insulating structureand having an opening exposing the external connection pad. The external connection padmay be connected to the second bonding padthrough a through via. The through viamay vertically penetrate the insulating structureand the second insulating layerto form a vertical connection wiring electrically connecting the external connection padand the second bonding pad.

110 100 210 200 120 100 220 200 The first bonding padof the first chipand the second bonding padof the second chipmay be bonded to each other to form a metal bonding interface MB. The first insulating layerof the first chipand the second insulating layerof the second chipmay be bonded to each other to form an insulating bonding interface IB. The insulating bonding interface IB may have a step portion SP that surrounds the metal bonding interface MB.

15 FIG. Although a semiconductor device ofincludes one memory chip and one peripheral circuit chip, embodiments are not limited thereto. As another example, a semiconductor device may include two or more memory chips or two or more peripheral circuit chips. As another example, at least one of the semiconductor chips included in the semiconductor device may have a Peri-Under-Cell (PUC) structure including a peripheral circuit area and a memory cell area built up on the peripheral circuit area.

The above description and the accompanying drawings provide an example of the technical idea of the present disclosure for illustrative purposes only. Various modifications, additions and substitutions to the described embodiments will be readily apparent to those skilled in the art without departing from the spirit and scope of the present disclosure. In addition, since the embodiments disclosed in this disclosure are not intended to limit the technical ideas of this disclosure but to explain the technical ideas of this disclosure, the scope of the technical ideas of this disclosure is not limited by these embodiments. The protection scope of this disclosure should be interpreted by the claims below, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of the rights of this disclosure.