Methods and Apparatus to Update Firmware Using Bulk Register Access

This patent application claims the benefit of and priority to Indian Provisional Patent Application No. 202441080769 filed Oct. 23, 2024, which is hereby incorporated herein by reference in its entirety.

The present disclosure relates generally to an electronic system and method, and, in particular embodiments, to methods and apparatus to update firmware using bulk register access.

Firmware provides digital systems with an instruction set representing different operations. Digital systems execute a series of instructions to implement, e.g., relatively complex operations. Some digital systems support firmware updates via a communication interface with a host device. During a firmware update, a host device provides a digital system with configuration data containing the firmware update. The digital system completes the firmware update by writing the firmware update to chunks of memory corresponding to the firmware. Devices supporting firmware updates allow designers to fix bugs, add features, etc.

In accordance to an embodiment, a device includes: memory circuitry having a first memory portion and a second memory portion, the first memory portion corresponding to a first range of memory addresses, the second memory portion corresponding to a second range of memory addresses, where the first range of memory addresses are non-consecutive to the second range of memory addresses; and a controller coupled to the memory circuitry, the controller configured to: request first data; after requesting the first data, receive the first data in a packet having a first data set and a second data set, the first data set including a first chunk start address corresponding to an address of the first range of memory addresses, the second data set including a second chunk start address corresponding to an address of the second range of memory address; write data of the first data set to the first memory portion using the first chunk start address; and write data of the second data set to the second memory portion using the second chunk start address.

In accordance to an embodiment, a method includes: requesting, by a first device, first data using a first protocol; after requesting the first data, receiving, by the first device, a packet including the first data using the first protocol, the first data having a first data set and a second data set, the first data set including peripheral data, the second data set including a chunk start address corresponding to an address of a first portion of memory; writing, by the first device, a first portion of the first data set to a second portion of memory; after writing the first portion of the first data set, providing, by the first device, the peripheral data to a second device using a second protocol; after writing the first portion of the first data set, writing, by the first device, a second portion of the first data set to the second portion of memory; and after writing the second portion of the first data set, writing data of the second data set to the first portion of memory using the chunk start address of the second data set.

In accordance to an embodiment, a device includes: memory circuitry having a first memory portion, a second memory portion, and a third memory portion, the first memory portion corresponding to a first range of memory addresses, the second memory portion corresponding to a second range of memory addresses, the third memory portion corresponding to a third range of memory addresses, where the first and second ranges of memory addresses are consecutive addresses, and where the second and third ranges of memory addresses are consecutive addresses; and a controller coupled to the memory circuitry, the controller configured to: request configuration data; after requesting the configuration data, receive the configuration data having a first data set and a second data set, the first data set including a first memory address in the first range of memory addresses, the second data set including a second memory address of in the third range of memory addresses; write data of the first data set to the first memory portion using the first memory address; and write data of the second data set to the third memory portion using the second memory address.

In accordance to an embodiment, an electronic device includes: a primary device; a secondary device; and an audio device coupled to the primary device and the secondary device, the audio device configured to: receive an update using a first communication protocol, the update having a first data set and a second data set, the update corresponding to operations of the secondary device; write data of the first data set to a first portion of memory, the first portion of memory corresponding to first operations of the secondary device; and write data of the second data set to a second portion of memory, the second portion of memory corresponding to second operations of the secondary device, the first and second portions of memory have non-consecutive memory addresses.

Corresponding numerals and symbols in different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate relevant aspects of preferred embodiments and are not necessarily drawn to scale.

The making and using of the embodiments disclosed are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosure, and do not limit the scope of the disclosure.

The description below illustrates various specific details to provide an in-depth understanding of several example embodiments according to the description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials and the like. In some cases, known structures, materials or operations are not shown or described in detail so as not to obscure the different aspects of the embodiments. References to “an embodiment” in this description indicate that a particular configuration, structure or feature described in relation to the embodiment is included in at least one embodiment. Consequently, phrases such as “in one embodiment” that may appear at different points of the present description do not necessarily refer exactly to the same embodiment. Furthermore, specific formations, structures or features may be combined in any appropriate manner in one or more embodiments.

Several aspects of the disclosure are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the disclosure. The present disclosure is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events.

Firmware provides digital systems with an instruction set representing different operations. Digital systems execute a series of instructions to implement, e.g., relatively complex operations. Some digital systems support firmware updates via a communication interface with a host device. During a firmware update, a host device provides a digital system with configuration data containing the firmware update. The digital system completes the firmware update by writing the firmware update to chunks of memory corresponding to the firmware. Devices supporting firmware updates allow designers to fix bugs, add features, etc.

In some systems, device manufacturers provide firmware updates to devices in the form of a file or file set containing configuration data (also referred to as update data). An updating device begins the firmware update process by receiving access to the configuration data. In some examples, the updating device uses a file download (FDL) process to receive the configuration data from a host device. For example, some devices use an over-the-air (OTA) connection to an FDL server or device to receive the configuration data. In other examples, the updating device uses a direct connection to a host device, which stores the file or file set containing the configuration data. The updating device uses a communication protocol to receive the configuration data via a data stream from the host device. Some communication protocols, such as SoundWire, provide the configuration data using a process of bulk register access (BRA). BRA is a process of providing the configuration data responsive to one or more BRA call commands (BRA_CALL) from the updating device. A BRA call command (BRA_CALL) is a request from the updating device to receive access to a file containing the configuration data. In some examples, such as firmware updates using configuration data from a set of files, the updating device generates a series of BRA call commands (BRA_CALL) to access configuration data in each file of the file set.

In operation, the updating device stores the original firmware image in chunks of memory (also referred to as portions of memory). A chunk of memory is a set of consecutive memory addresses corresponding to a given function of the firmware image. After determining the host device has a file to update the firmware in one or more chunks of memory, the device generates a BRA call command (BRA_CALL) to update the portion of the firmware image in a first chunk of memory. The BRA call command (BRA_CALL) identifies a file in the host device to provide to the device. The host device generates a BRA data stream (BRA_DATA) to provide the configuration data of the file responsive to the BRA call command (BRA_CALL). The BRA data stream (BRA_DATA) provides the updating device access to the configuration data.

The updating device updates the firmware by writing portions of the configuration data to consecutive addresses of the corresponding chunk of memory. However, if the firmware update includes configuration data corresponding to non-consecutive memory addresses, such as in non-consecutive chunks of memory, the updating device has to generate another BRA call command (BRA_CALL) to receive the next portion of the update. The additional BRA call command(s) (BRA_CALL) corresponds to an additional file of a file set containing the additional configuration. In such examples, the additional file of the file set corresponds to a different chunk of memory. The updating device continues to generate additional BRA call commands (BRA_CALL) until the host device provides the configuration data from all files of the file set. In such operations, the generation of additional BRA call commands (BRA_CALL) substantially increases the duration of the firmware update.

Some embodiments relate to methods and apparatus to update firmware using bulk register access (BRA) across non-consecutive memory addresses and, therefore, across different memory chunks. In some embodiments, a secondary device includes FDL circuitry and FDL decoder circuitry to decode context of a firmware update from configuration data. The FDL circuitry generates a BRA call command (BRA_CALL) responsive to a determination that a host device has a file including configuration data (also referred to as update data). In such examples, the configuration data includes a packet header, first data set, and second data set. The packet header provides context for the BRA data stream (BRA_DATA) or, more generally, the configuration data. For example, the packet header may include a payload length, which corresponds to the length of the configuration data. The first data set includes a first chunk header and chunk data. The example chunk header provides context of the chunk data. For example, the chunk header may include a chunk start address, which identifies a location in memory to write the chunk data. The chunk data represents the firmware update of the portion of memory corresponding to the chunk start address.

Similar to the first data set, the second data set includes a second chunk header and second chunk data. The second chunk header specifies a chunk start address to write the second chunk data. In example operations, the FDL decoder circuitry identifies the chunk headers from the BRA data stream. The FDL decoder circuitry writes the chunk data to the portions of memory specified by the chunk headers. In such example operations, the chunk headers allow the FDL decoder circuitry to write chunk data to different portions of memory without additional BRA call commands (BRA_CALL). Advantageously, in some embodiments, the FDL decoder circuitry decreases the duration of firmware updates by reducing the number of BRA call commands. Advantageously, in some embodiments, as further described herein, the FDL decoder circuitry allows the configuration data to support additional firmware update operations, such as Cyclic Redundancy Checks (CRCs), secondary interface writes, etc.

1 FIG. 1 FIG. 1 FIG. 100 100 105 110 115 120 125 130 100 105 110 100 100 125 130 is a block diagram of an example audio system. In the example of, the audio systemincludes a host device, an audio device, a first bridge device, a second bridge device, a speaker, and a microphone. The example audio systemofis an example of a SoundWire Device Class for Audio (SDCA) system, which implements SoundWire controls for audio functions. For example, the host deviceand the audio devicecommunicate using SoundWire signaling protocols. Alternatively, the audio systemmay implement an alternative set of controls, such as inter-integrated circuit (I2C), improved inter-integrated circuitry (I3C), serial peripheral interface (SPI), SLIMBus, Bluetooth, etc. In example operations, the audio systemproduces soundwaves using the speakerand receives soundwaves using the microphone.

105 110 105 110 105 110 105 110 105 110 105 110 105 105 135 140 1 FIG. The host device(also referred to as a primary device) is communicatively coupled to the audio device. In some examples, the host deviceand the audio deviceare coupled by a bus including a clock signal (CLK) and a data signal (DATA). In such examples, the communication protocols allow the host deviceand the audio deviceto exchange commands using the data signal (DATA). For example, as part of a firmware update, the host devicereceives a BRA call command (BRA_CALL) from the audio device. In such examples, the host deviceprovides BRA data stream (BRA_DATA) responsive to the BRA call command (BRA_CALL). The BRA call command (BRA_CALL) is a request from the audio devicefor the host deviceto provide a relatively large portion of data. The audio devicerequests configuration data using the BRA call command (BRA_CALL). The host deviceprovides the relatively large portion of data as the BRA data stream (BRA_DATA). The example host deviceofincludes example memory circuitryand example interface circuitry.

105 135 145 145 145 110 145 1 FIG. 2 7 9 FIGS.,, and In example operations of the host device, the memory circuitrystores example configuration data. The configuration datais a compiled set of instructions representing at least a portion of a firmware image. In the example of, the configuration datahas update data corresponding to operations of the audio devicean update to an active firmware image. Examples of the configuration dataare further illustrated and described in connection with.

105 140 110 140 140 In such example operations of the host device, the interface circuitryimplements a communication protocol to interface with the audio deviceusing the clock signal (CLK) and the data signal (DATA). In some examples, the interface circuitryimplements the SoundWire protocol. Alternatively, the interface circuitrymay implement another communication protocol, such as I2C, I3C, SPI, etc.

110 105 110 115 120 110 115 120 110 105 115 120 110 115 120 105 110 150 155 160 165 170 1 FIG. The audio deviceis communicatively coupled to the host deviceby a first communication protocol. The audio deviceis communicatively coupled to bridge devices,by a second communication protocol. In some examples, the audio devicesupports audio operations with the bridge devices,despite having support for the first communication protocol. For example, the audio deviceuses the SoundWire protocol to communicate with the host deviceand the I2C protocol to communicate with the bridge devices,. In such examples, the audio devicedoes not need the bridge devices,to support SoundWire protocols to exchange data with the host device. The example audio deviceofincludes first example interface circuitry, an example controller, example audio channel(s), example memory circuitry, and second example interface circuitry.

110 150 105 150 150 150 155 160 170 150 105 In example operations of the audio device, the interface circuitryimplements the first communication protocol to interface with the host device. In some examples, the interface circuitryimplements the SoundWire protocol, which uses the clock signal (CLK) and the data signal (DATA) to exchange data. Alternatively, the interface circuitrymay implement another communication protocol, such as I2C, I3C, SPI, etc. The interface circuitrysequences use of the data signal (DATA) to provide data to the controller, the audio channel(s), and the interface circuitry. The interface circuitrysequences use of the data signal (DATA) to provide commands, such as the BRA call command (BRA_CALL), to the host device.

110 155 165 155 165 155 175 180 175 175 150 180 145 180 145 145 165 180 110 145 165 175 180 1 FIG. 4 5 FIGS.and In such example operations of the audio device, the controllerperforms operations to update firmware in the memory circuitry. For example, the controlleris configured to write data to the memory circuitry. The example controllerofincludes example FDL circuitryand example FDL decoder circuitry. The FDL circuitrygenerates the BRA call command (BRA_CALL) to initiate a firmware update. The FDL circuitryprovides the BRA data stream (BRA_DATA) from the interface circuitryto the FDL decoder circuitry. In some examples, the BRA data stream (BRA_DATA) is a data stream representative of the configuration data, which represents an updated firmware image. The FDL decoder circuitrydecodes the configuration datato determine context data of the firmware update. For example, the configuration dataincludes a chunk header identifying a start memory address in the memory circuitry. In such examples, the FDL decoder circuitryupdates the firmware of the audio deviceby writing a portion of the configuration datato the memory circuitry. Examples of the FDL circuitryand the FDL decoder circuitryare further illustrated and described in connection with.

110 165 165 185 190 165 185 190 185 190 185 190 110 185 125 190 130 180 185 190 1 FIG. In example operations of the audio device, the memory circuitrystores a firmware image. In the example of, the memory circuitryincludes a first portion of memoryand a second portion of memory. However, in practice the memory circuitrycan include any number of portions of memory. In some examples, the portions of memory,are referred to as a chunk of memory, a block of memory, memory portion, etc. The portions of memory,form a firmware image. In some examples, the portions of memory,store portions of the firmware image that correspond to different functions of the audio device. For example, the portion of memoryincludes instructions to produce ultrasonic signals (signals having frequencies beyond the audible spectrum) for the speakerand the portion of memoryincludes instructions to determine distances using received ultrasonic signals from the microphone. During a firmware update, the FDL decoder circuitrycan write to any of the portions of memory,to update the corresponding operations.

160 110 1 160 2 160 160 105 150 115 120 In example operations, the audio channel(s)are analog components that allow the audio deviceto be directly coupled to a speaker or microphone. For example, a first audio channel (CH) of the audio channelsincludes a digital-to-analog converter (DAC) to drive a speaker and a second audio channel (CH) of the audio channelsincludes an analog-to-digital converter (ADC) to receive audio from a microphone. In some examples, the audio channel(s)exchange audio data with the host devicevia the interface circuitry. Similarly, the bridge devices,include circuitry to support audio generating and capturing audio signals.

170 115 120 170 170 170 115 120 In example operations, the interface circuitryimplements the second communication protocol to interface with the bridge devices,. In some examples, the interface circuitryimplements I2C. Alternatively, the interface circuitrymay implement another communication protocol, such as SoundWire, I3C, SPI, etc. The interface circuitrysequences use of a data signal to exchange data with the bridge devices,.

2 FIG. 1 FIG. 2 FIG. 145 145 205 210 215 100 105 145 110 180 155 145 205 210 215 is a block diagram of an example of the configuration dataoffor a firmware update. In the example of, the configuration dataincludes a packet header, a first data set, and a second data set. In example operations of the audio system, the host deviceprovides the configuration datausing the BRA data stream (BRA_DATA) responsive to a BRA call command (BRA_CALL) from the audio device. In such example operations, the FDL decoder circuitryor, more generally, the controllerdecodes the configuration datato identify the packet headerand the data sets,.

205 145 145 205 220 225 220 180 145 220 220 145 185 190 220 155 145 145 220 2 FIG. 7 FIG. The packet headeris a first portion of the configuration data, which provides context to the update data of the configuration data. The example packet headerofincludes an example number of functionsand an example payload length. The number of functions(Num_Functions) represents the number of operations that the FDL decoder circuitrywill perform during the firmware update of the configuration data. In some examples, the number of functionsrepresents the number of portions of memory being updated. For example, if the number of functionsis two, the configuration dataincludes data sets for two chunks of memory, such as the portions of memory,. In other examples, the number of functionsrepresents the number of operations the controllerwill perform during the firmware update of the configuration data. For example, if the configuration dataincludes Cyclic Redundancy Check (CRC) data, such as in, the number of functionsis increased to include CRCs.

225 145 225 225 225 225 225 225 225 2 FIG. The payload length(Payload_Length) is a payload length field that represents the length of the BRA data stream (BRA_DATA) or, more generally, the configuration data. In some examples, such as in, the payload lengthis a value that exceeds the maximum value of a single word (e.g., eight bits, sixteen bits, etc.). In such examples, a plurality of words represent the payload length. For example, wordsA,B,C each store a portion of the payload length(Payload_Length[23:0]). Alternatively, the payload length(Payload_Length) may include any number of words.

210 145 185 190 210 230 235 230 235 230 240 245 240 235 240 235 240 240 240 235 185 2 FIG. 2 FIG. 0 The data setis a second portion of the configuration data, which provides update data for a portion of memory, such as one of the portions of memory,. The example data setofincludes an example chunk headerand example chunk data. The chunk headerprovides context to the chunk data. The example chunk headerofincludes an example chunk data lengthand an example chunk start address. The chunk data length(Chunk_Length) represents the length of the chunk data. In some examples, the chunk lengthcorresponds to a number of words that form the chunk data. In other examples, the chunk lengthcorresponds to a number of bits that form the chunk data. In both examples, the chunk lengthdoes not need to correspond to a total length of a corresponding portion of memory. For example, the chunk lengthmay indicate the chunk datais smaller than the total length of the portion of memory.

245 165 245 235 245 245 235 185 245 185 225 245 245 245 245 245 245 0 0 The chunk start address(CHNK_Addr[23:0]) represents a memory address in the memory circuitry. In example operation, the chunk start addressidentifies a location in the memory address to begin writing the chunk data. In some examples, the chunk start addressidentifies a memory address that is not the start memory address of a portion of memory. Instead, the chunk start addresscan correspond to a memory location within the portion of memory. For example, if the chunk datais only updating a portion of the portion of memory, the chunk start addresscan be between the start and end addresses of the portion of memory. Similar to the payload length, in some examples, a plurality of words represents the chunk start address. For example, wordsA,B,C each store a portion of the chunk start address(CHNK_Addr[23:0]). The chunk start addressmay include any number of words.

215 145 185 190 215 250 255 250 255 250 260 265 260 255 260 255 260 260 260 255 190 2 FIG. 2 FIG. N The data setis a third portion of the configuration data, which provides update data for another portion of memory, such as one of the portions of memory,. The example data setofincludes an example chunk headerand example chunk data. The chunk headerprovides context to the chunk data. The example chunk headerofincludes an example chunk data lengthand an example chunk start address. The chunk length(Chunk_Length) represents the length of the chunk data. In some examples, the chunk lengthcorresponds to a number of words that form the chunk data. In other examples, the chunk lengthcorresponds to a number of bits that form the chunk data. In both examples, the chunk lengthdoes not need to correspond to a total length of a corresponding portion of memory. For example, the chunk lengthmay indicate the chunk datais smaller than the total length of the portion of memory.

265 165 265 255 265 265 255 190 265 190 225 265 265 265 265 265 265 N N The chunk start address(CHNK_Addr[23:0]) represents a memory address in the memory circuitry. In example operations, the chunk start addressidentifies a location in the memory address to begin writing the chunk data. In some examples, the chunk start addressidentifies a memory address that is not the start memory address of a portion of memory. Instead, the chunk start addresscan correspond to a memory location within the portion of memory. For example, if the chunk datais only updating a portion of the portion of memory, the chunk start addresscan be between the start and end addresses of the portion of memory. Similar to the payload length, in some examples, the chunk start addressis represented by a plurality of words. For example, wordsA,B,C each store a portion of the chunk start address(CHNK_Addr[23:0]). The chunk start addressmay include any number of words.

3 FIG. 3 FIG. 3 FIG. 300 180 165 165 185 190 310 310 185 190 185 185 300 180 210 185 190 230 250 180 165 1 0 N 0 N is a timing diagramof example operations of the FDL decoder circuitryto update firmware in the memory circuitry. In the example of, the memory circuitryincludes the portions of memory,and a third portion of memory. The example portion of memory(CHNK) ofspans a range of memory addresses between an end address of the portion of memory(CHNK) and a start address of the portion of memory(CHNK). In some examples, the portion of memoryincludes memory addresses being consecutive addresses to the memory addresses of the portion of memory. The timing diagramillustrates the operations of the FDL decoder circuitrywhen the data setcorresponds to the portion of memory(CHNK) and the data set corresponds to the portion of memory(CHNK). Advantageously, the chunk headers,allow the FDL decoder circuitryto update non-consecutive portions of the memory circuitrywithout additional BRA call commands.

0 1 0 1 N 175 330 105 145 330 185 310 190 At a first time 320 (T), the FDL circuitrygenerates a BRA call command (BRA_CALL) to initialize a firmware update. At a second time(T), the host devicestarts providing the BRA data stream (BRA_DATA) responsive to the BRA call command (BRA_CALL). The BRA data stream (BRA_DATA) corresponds to the configuration data. At the time, the portion of memorycontains first original chunk data (ORG_CHNK_DATA[n:0]), the portion of memorycontains second original chunk data (ORG_CHNK_DATA[d:0]), and the portion of memorycontains third original chunk data (ORG_CHNK_DATA[m:0]).

330 340 180 235 185 180 245 185 235 245 185 245 185 340 185 235 310 190 2 0 2 0 1 N 3 FIG. Between the second timeand a third time(T), the FDL decoder circuitrywrites the chunk data(CHNK_DATA[n:0]) to the portion of memory. In such example operations, the FDL decoder circuitryuses the start addressto identify an address in the portion of memoryto start writing the chunk data. In the example of, the start addresscorresponds to a start address of the portion of memory. However, in other examples, the start addresscorresponds to any address inside the range of memory addresses corresponding to the portion of memory. After the third time(T), the portion of memorycontains the chunk data(CHNK_DATA[n:0]), the portion of memorycontains the original chunk data (ORG_CHNK_DATA[d:0]), and the portion of memorycontains the original chunk data (ORG_CHNK_DATA[m:0]).

340 350 180 255 190 180 265 190 255 265 190 265 190 350 185 235 310 190 255 N N N 0 1 N 3 FIG. Between the third timeand a fourth time(T), the FDL decoder circuitrywrites the chunk data(CHNK_DATA[m:0]) to the portion of memory. In such example operations, the FDL decoder circuitryuses the start addressto identify an address in the portion of memoryto start writing the chunk data. In the example of, the start addresscorresponds to a start address of the portion of memory. Alternatively, in some other examples, the start addresscorresponds to an address inside the range of memory addresses corresponding to the portion of memory. After the fourth time(T), the portion of memorycontains the chunk data(CHNK_DATA[n:0]), the portion of memorycontains the original chunk data (ORG_CHNK_DATA[d:0]), and the portion of memorycontains chunk data(CHNK_DATA[m:0]).

340 350 230 250 180 165 Advantageously, between the times,, the chunk headers,allow the FDL decoder circuitryto update discontinuous portions of the memory circuitrywithout additional BRA call commands. Advantageously, reducing the number of BRA call commands reduces duration of the firmware update.

4 FIG. 1 FIG. 4 FIG. 4 FIG. 4 FIG. 4 FIG. 4 FIG. 4 FIG. 175 175 175 410 420 430 is a block diagram of an example implementation of the FDL circuitryof. The FDL circuitry ofmay be instantiated (e.g., creating an instance of, bring into being for any length of time, materialize, implement, etc.) by programmable circuitry such as a Central Processor Unit (CPU) executing first instructions, a field programmable gate array, a programmable logic device (PLD), a generic array logic (GAL) device, a programmable array logic (PAL) device, a complex programmable logic device (CPLD), a simple programmable logic device (SPLD), a microcontroller (MCU), a programmable system on chip (PSoC), etc. Also or alternatively, the FDL circuitryofmay be instantiated (e.g., creating an instance of, bring into being for any length of time, materialize, implement, etc.) by (i) an Application Specific Integrated Circuit (ASIC) or (ii) a Field Programmable Gate Array (FPGA) structured or configured in response to execution of second instructions to perform operations corresponding to the first instructions. Some or all of the circuitry ofmay, thus, be instantiated at the same or different times. Some or all of the circuitry ofmay be instantiated, for example, in one or more threads executing concurrently on hardware or in series on hardware. Moreover, in some examples, some or all of the circuitry ofmay be implemented by microprocessor circuitry executing instructions or FPGA circuitry performing operations to implement one or more virtual machines or containers. In the example of, the FDL circuitryincludes example BRA call circuitry, example BRA write circuitry, and example CRC circuitry.

410 410 150 410 105 145 410 165 410 6 8 11 FIGS.,, and The BRA call circuitrygenerates a BRA call command (BRA_CALL). In example operations, the BRA call circuitryprovides the BRA call command (BRA_CALL) to the interface circuitryto start a firmware update. In some examples, the BRA call circuitrydetermines a firmware update is to occur responsive to a file download (FDL) status indication. In such examples, the host devicemay provide the FDL indication in response to receiving the configuration data. The BRA call circuitrymay use the FDL indication to determine the portions of the memory circuitrythat correspond to the update. In some examples, the BRA call circuitryis instantiated by ASIC or programmable circuitry executing BRA call instructions to perform operations such as those represented by the flowcharts of.

420 180 420 150 420 180 420 6 8 11 FIGS.,, and The BRA write circuitryprovides the BRA data stream (BRA_DATA) to the FDL decoder circuitry. In some examples, the BRA write circuitrybuffers the BRA data stream (BRA_DATA) from the interface circuitry. In other examples, the BRA write circuitryprovides the FDL decoder circuitryaccess to the BRA data stream (BRA_DATA) responsive to writing the BRA data stream (BRA_DATA) to a temporary memory location. In some examples, the BRA write circuitryis instantiated by ASIC or programmable circuitry executing BRA write instructions to perform operations such as those represented by the flowcharts of.

430 180 165 430 430 165 430 8 FIG. The CRC circuitrycalculates a real-time CRC value as the FDL decoder circuitrywrites to the memory circuitry. In some examples, the CRC circuitrycompares the calculated CRC value to a CRC value from the BRA data stream (BRA_DATA). In such examples, the CRC circuitryverifies the write to the memory circuitrywas successful responsive to the calculated CRC value matching the received CRC value. In some examples, the CRC circuitryis instantiated by ASIC or programmable circuitry executing CRC instructions to perform operations such as those represented by the flowchart of.

5 FIG. 1 FIG. 5 FIG. 5 FIG. 5 FIG. 5 FIG. 5 FIG. 5 FIG. 180 180 180 180 510 520 530 540 550 560 is a block diagram of an example implementation of the FDL decoder circuitryof. The FDL decoder circuitryofmay be instantiated (e.g., creating an instance of, bring into being for any length of time, materialize, implement, etc.) by programmable circuitry such as a Central Processor Unit (CPU) executing first instructions, a field programmable gate array, a programmable logic device (PLD), a generic array logic (GAL) device, a programmable array logic (PAL) device, a complex programmable logic device (CPLD), a simple programmable logic device (SPLD), a microcontroller (MCU), a programmable system on chip (PSoC), etc. Also or alternatively, the FDL decoder circuitryofmay be instantiated (e.g., creating an instance of, bring into being for any length of time, materialize, implement, etc.) by (i) an Application Specific Integrated Circuit (ASIC) or (ii) a Field Programmable Gate Array (FPGA) structured or configured in response to execution of second instructions to perform operations corresponding to the first instructions. Some or all of the circuitry ofmay, thus, be instantiated at the same or different times. Some or all of the circuitry ofmay be instantiated, for example, in one or more threads executing concurrently on hardware or in series on hardware. Moreover, in some examples, some or all of the circuitry ofmay be implemented by microprocessor circuitry executing instructions or FPGA circuitry performing operations to implement one or more virtual machines or containers. In the example of, the FDL decoder circuitryincludes example FDL interface circuitry, example packet header circuitry, example chunk header circuitry, example chunk write circuitry, example interface manager circuitry, and an example datastore.

510 175 510 560 510 145 560 510 6 8 11 FIGS.,, and The FDL interface circuitryreceives the BRA data stream (BRA_DATA) from the FDL circuitry. In some examples, the FDL interface circuitrystores portions of the BRA data stream (BRA_DATA) in the datastore. In such examples, the FDL interface circuitryforms portions of the configuration datain the datastore. In some examples, the FDL interface circuitryis instantiated by ASIC or programmable circuitry executing FDL interface instructions to perform operations such as those represented by the flowcharts of.

520 205 145 520 145 205 145 520 220 225 520 205 540 520 220 225 520 205 180 520 2 FIG. 6 8 11 FIGS.,, and The packet header circuitryidentifies the packet headerof the configuration data. The packet header circuitrydetermines the context of the configuration datausing the packet header. In some examples, such as in the configuration dataof, the packet header circuitrydetermines the number of functionsand the payload length. In example operations, the packet header circuitryuses data of the packet headerto track the BRA data stream (BRA_DATA) and the operations of the chunk write circuitry. For example, the packet header circuitrycan use the number of functionsand the payload lengthto confirm a successful firmware update. In other examples, the packet header circuitrymay provide data from the packet headerto another component of the FDL decoder circuitry. In some examples, the packet header circuitryis instantiated by ASIC or programmable circuitry executing packet header instructions to perform operations such as those represented by the flowcharts of.

530 230 250 145 530 235 255 530 260 265 250 530 260 265 540 530 6 8 11 FIGS.,, and The chunk header circuitryidentifies the chunk headers,of the configuration data. The chunk header circuitrydetermines context of subsequent chunk data, such as the chunk data,, using the corresponding chunk header. For example, the chunk header circuitrydetermines the chunk lengthand the chunk start addressfrom the chunk header. In example operations, the chunk header circuitryprovides the chunk lengthand the chunk start addressto the chunk write circuitry. In some examples, the chunk header circuitryis instantiated by ASIC or programmable circuitry executing chunk header instructions to perform operations such as those represented by the flowcharts of.

540 235 255 145 540 240 260 245 265 530 540 235 255 240 260 245 265 540 6 8 11 FIGS.,, and The chunk write circuitryidentifies the chunk data,of the configuration data. The chunk write circuitryreceives the chunk lengths,and the chunk start addresses,from the chunk header circuitry. In example operations, the chunk write circuitrywrites the chunk data,using the chunk lengths,and the chunk start addresses,. In some examples, the chunk write circuitryis instantiated by ASIC or programmable circuitry executing chunk write instructions to perform operations such as those represented by the flowcharts of.

550 550 550 170 550 145 115 120 170 115 120 550 9 FIG. 6 8 11 FIGS.,, and The interface manager circuitryidentifies peripheral data in the BRA data stream (BRA_DATA). In some examples, the interface manager circuitrychecks for peripheral data after a fixed number of words of the BRA data stream (BRA_DATA). The interface manager circuitryprovides the peripheral data to the interface circuitry. In some examples, such as in, the interface manager circuitryallows the configuration datato contain commands for the bridge devices,. In such examples, the interface circuitrymay provide commands to the bridge devices,during the firmware update. In some examples, the interface manager circuitryis instantiated by ASIC or programmable circuitry executing interface manager instructions to perform operations such as those represented by the flowcharts of.

6 FIG. 1 4 FIGS.and 1 5 FIGS.and 1 FIG. 2 FIG. 600 600 175 180 100 145 is a flowchart of embodiment method, according to an embodiment of the present disclosure. Methodmay be executed, instantiated, or performed using an example implementation of the FDL circuitryofand the FDL decoder circuitryofto update the firmware of the audio systemofusing the configuration dataof.

600 610 410 410 105 410 105 110 410 105 145 110 410 105 410 610 610 Methodbegin at Blockat which the BRA call circuitrydetermines if there is a firmware update. In example operations, the BRA call circuitryreads an FDL status of the host device. In some examples, the BRA call circuitrycompares the FDL status of the host deviceto an FDL index of a current firmware of the audio device. In such examples, the BRA call circuitrydetermines that the host devicehas the configuration datafor updating the firmware of the audio deviceresponsive to the comparison. In other examples, the BRA call circuitrymay receive an indication or periodically check if a firmware update is available in the host device. If the BRA call circuitrydetermines that there is no firmware update (e.g., Blockreturns a result of NO), control proceeds to return to Block.

410 610 410 615 410 110 410 110 410 110 410 105 145 410 145 105 410 145 105 If the BRA call circuitrydetermines that there is a firmware update (e.g., Blockreturns a result of YES), the BRA call circuitryprovides a write command for bulk register access (BRA). (Block). In example operations, the BRA call circuitrywaits for the audio deviceto be ready for a firmware update. In some examples, the BRA call circuitrydetermines the audio deviceis ready for a firmware update responsive to discontinuing audio operations. In such examples, the BRA call circuitrymay wait for a break in audio operations or generate an interrupt (e.g., alert, alarm, etc.) to halt operations of the audio device. In such example operations, the BRA call circuitryprovides a BRA call command (BRA_CALL) to the host deviceto initialize the transfer of the configuration data. The BRA call circuitryprovides the BRA call command (BRA_CALL) to request the configuration datafrom the host device. Alternatively, the BRA call circuitrymay use an alternative procedure for initiating a transfer of the configuration datafrom the host device.

510 620 105 145 510 145 510 205 560 510 510 205 520 510 145 180 The FDL interface circuitryreceives a firmware update file. (Block). In example operations, the host devicedrives the BRA data stream (BRA_DATA) responsive to the BRA call command. In such example operations, the BRA data stream (BRA_DATA) is a data stream representation of the configuration data. In some examples, the FDL interface circuitrybuffers the BRA data stream (BRA_DATA) to construct portions of the configuration data. For example, the FDL interface circuitryconstructs the packet headerresponsive to buffering the first four words of the BRA data stream (BRA_DATA) in the datastore. In other examples, the FDL interface circuitrybuffers the BRA data stream (BRA_DATA) by providing portions of the BRA data stream (BRA_DATA) to different locations. For example, the FDL interface circuitryprovides the portions of the BRA data stream (BRA_DATA) corresponding to the packet headerto the packet header circuitry. Advantageously, the FDL interface circuitrymakes portions of the configuration dataaccessible to different components of the FDL decoder circuitry.

520 625 520 205 520 225 205 520 225 520 225 225 225 225 520 225 180 180 225 The packet header circuitrydetermines a packet length. (Block). In example operations, the packet header circuitryidentifies the packet header. In such examples, the packet header circuitrydetermines the payload lengthfrom the packet header. In some examples, the packet header circuitrydetermines the payload lengthby combining multiple sequential words of the BRA data stream (BRA_DATA). For example, the packet header circuitrydetermines a twenty-four bit representation of the payload length(Payload_Length[23:0]) by combining the wordsA,B,C. Advantageously, the packet header circuitrymakes the payload lengthaccessible to the FDL decoder circuitry. Advantageously, the FDL decoder circuitrymay use the payload lengthto determine the end of the BRA data stream (BRA_DATA).

530 630 530 230 530 240 230 530 240 210 240 235 530 240 180 180 240 235 0 The chunk header circuitrydetermines a first chunk length. (Block). In example operations, the chunk header circuitryidentifies the chunk header. In such examples, the chunk header circuitrydetermines the chunk length(CHNK_Length) from the chunk header. For example, the chunk header circuitrydetermines the chunk lengthcorresponds to the first word of the data set. In such example operations, the chunk lengthrepresents the length of the chunk data. Advantageously, the chunk header circuitrymakes the chunk lengthaccessible to the FDL decoder circuitry. Advantageously, the FDL decoder circuitrymay use the chunk lengthto determine the length of the chunk data.

530 635 530 230 530 245 230 530 245 245 245 245 210 245 165 235 530 245 180 180 245 165 235 The chunk header circuitrydetermines a first chunk address. (Block). In example operations, the chunk header circuitryidentifies the chunk header. In such examples, the chunk header circuitrydetermines the chunk start addressfrom the chunk header. For example, the chunk header circuitrydetermines the chunk start addresscorresponds to the wordsA,B,C of the data set. In such example operations, the chunk start addressrepresents an address in the memory circuitryto begin writing the chunk data. Advantageously, the chunk header circuitrymakes the chunk start addressaccessible to the FDL decoder circuitry. Advantageously, the FDL decoder circuitrymay use the chunk start addressto identify a location in the memory circuitryto write the chunk data.

540 640 540 235 245 165 540 235 165 540 235 245 240 165 210 The chunk write circuitrywrites chunk data using the chunk length and address. (Block). In example operations, the chunk write circuitrybegins to write the chunk datato the chunk start addressin the memory circuitry. In such example operations, the chunk write circuitrycontinues writing the chunk datato consecutive addresses of the memory circuitry. In some examples, the chunk write circuitrycompletes the write the chunk dataafter writing data from the chunk start addressplus the chunk length. In such examples, the consecutive addresses of the memory circuitrycorrespond to the update of a portion of memory using the data set.

520 645 520 220 225 145 540 235 520 220 225 520 520 645 610 The packet header circuitrydetermines if there is another chunk to update. (Block). In example operations, the packet header circuitryuses at least one of the number of functionsor the payload lengthto determine if the configuration dataincludes another data set. For example, after the chunk write circuitrywrites the chunk data, the packet header circuitrycompares the number of performed functions or the current length of the BRA data stream (BRA_DATA) to the number of functionsor the payload length. In such examples, the packet header circuitrydetermines if there is another portion of memory to update responsive to the comparison. If the packet header circuitrydetermines there is not another chunk to update (e.g., Blockreturns a result of NO), control proceeds to return to Block.

520 645 530 650 530 250 530 260 250 530 260 215 260 255 530 260 180 180 260 255 N If the packet header circuitrydetermines there is another chunk to update (e.g., Blockreturns a result of YES), the chunk header circuitrydetermines another chunk length. (Block). In example operations, the chunk header circuitryidentifies the chunk header. In such examples, the chunk header circuitrydetermines the chunk length(CHNK_Length) from the chunk header. For example, the chunk header circuitrydetermines the chunk lengthcorresponds to the first word of the data set. In such example operations, the chunk lengthrepresents the length of the chunk data. Advantageously, the chunk header circuitrymakes the chunk lengthaccessible to the FDL decoder circuitry. Advantageously, the FDL decoder circuitrymay use the chunk lengthto determine the length of the chunk data.

530 655 530 250 530 265 250 530 265 265 265 265 215 265 165 255 530 265 180 180 265 165 255 640 540 255 The chunk header circuitrydetermines another chunk address. (Block). In example operations, the chunk header circuitryidentifies the chunk header. In such examples, the chunk header circuitrydetermines the chunk start addressfrom the chunk header. For example, the chunk header circuitrydetermines the chunk start addresscorresponds to the wordsA,B,C of the data set. In such example operations, the chunk start addressrepresents an address in the memory circuitryto begin writing the chunk data. Advantageously, the chunk header circuitrymakes the chunk start addressaccessible to the FDL decoder circuitry. Advantageously, the FDL decoder circuitrymay use the chunk start addressto identify a location in the memory circuitryto write the chunk data. Control proceeds to return to Block. However, unlike in the example described above, the chunk write circuitrywrites the chunk data.

6 FIG. 1 4 FIGS.and 1 5 FIGS.and 1 FIG. 175 180 100 Example methods are described with reference to the flowchart illustrated in. However, many other methods of implementing the FDL circuitryofand the FDL decoder circuitryofor, more generally, the audio systemofmay also be used in this description. For example, the order of execution of the blocks may be changed, or some of the blocks described may be changed, eliminated, or combined. Similarly, additional operations may be included in the manufacturing process before, in between, or after the blocks shown in the illustrated examples.

7 FIG. 1 2 FIGS.and 7 FIG. 700 700 145 700 705 710 715 100 105 700 180 155 700 705 710 715 is a block diagram of example configuration data, according to an embodiment of the present disclosure. Configuration datais another example of the configuration dataof. In the example of, the configuration dataincludes a packet header, a first data set, and a second data set. In example operations of the audio system, the host deviceprovides the configuration datausing the BRA data stream (BRA_DATA). In such example operations, the FDL decoder circuitryor, more generally, the controllerdecodes the configuration datato identify the packet headerand the data sets,.

705 145 700 705 720 720 180 700 720 220 705 225 7 FIG. The packet headeris a portion of the configuration datathat provides context to the configuration data. The example packet headerofincludes an example number of functions. The number of functions(Num_Functions) represents the number of operations that the FDL decoder circuitrywill perform during the firmware update of the configuration data. The number of functionsis another example of the number of functions. Advantageously, the CRCs described herein allow the packet headerto not include a payload length, such as the payload length.

710 700 710 185 190 310 710 725 730 735 725 730 725 740 740 165 740 245 265 725 240 260 7 FIG. 7 FIG. 0 The data setis a second portion of the configuration data. The data setprovides update data for a portion of memory, such as the portions of memory,,. The example data setofincludes an example chunk header, example chunk data, and example CRC data. The chunk headerprovides context to the chunk data. The example chunk headerofincludes an example chunk start address. The chunk start address(CHNK_Addr[23:0]) represents a memory address in the memory circuitry. The chunk start addressis another example of the chunk start addresses,. Advantageously, the CRCs described herein allow the chunk headerto not include a chunk length, such as the chunk lengths,.

735 730 735 745 750 755 760 745 760 730 745 730 175 730 745 175 730 745 7 FIG. 8 FIG. The CRC dataprovides context to the CRCs of the transmission and writing of the chunk data. The example CRC dataofincludes a first example CRC value, first example default data, second example default data, and a second example CRC value. The CRC values,represent check values for the chunk data. In some examples, a function produces the CRC valueas a product of the chunk data. In example operations, as further described in connection with, the FDL circuitryverifies the BRA data stream (BRA_DATA) accurately provides the chunk databy comparing a real-time CRC value to the CRC value. In such examples, the FDL circuitrydetects the end of the chunk dataresponsive to the real-time CRC value matching the CRC value.

750 755 745 760 750 755 175 730 175 745 730 175 750 755 750 755 The default data,(also referred to as fixed data packet(s)) provides additional context for the CRCs of the CRC values,. The default data,is fixed values that allow the FDL circuitryto verify the end of the chunk data. In example operations, if the FDL circuitrymay calculate a real-time CRC value that matches the CRC value, but the BRA data stream (BRA_DATA) has only provided a portion of the chunk data. In such example operations, the FDL circuitryidentifies the accidental match by comparing the subsequent data words to the expected values of the default data,. Advantageously, the default data,provides reference values to verify the accuracy of the CRC.

715 700 715 185 190 310 715 765 770 775 765 770 765 780 780 165 780 245 265 740 765 240 260 7 FIG. 7 FIG. N The data setis a third portion of the configuration data. The data setprovides update data for a portion of memory, such as the portions of memory,,. The example data setofincludes an example chunk header, example chunk data, and example CRC data. The chunk headerprovides context to the chunk data. The example chunk headerofincludes an example chuck start address. The chunk start address(CHNK_Addr[23:0]) represents a memory address in the memory circuitry. The chunk start addressis another example of the chunk start addresses,,. Advantageously, the CRCs described herein allow the chunk headerto not include a chunk length, such as the chunk lengths,.

775 770 775 750 755 785 790 785 790 770 785 770 175 770 785 790 175 730 785 175 750 755 7 FIG. 8 FIG. The CRC dataprovides context to the CRCs of the transmission and writing of the chunk data. The example CRC dataofincludes the default data,, a first example CRC value, and a second example CRC value. The CRC values,represent check values for the chunk data. In some examples, a function produces the CRC valueas a product of the chunk data. In example operations, as further described in connection with, the FDL circuitryverifies the BRA data stream (BRA_DATA) accurately provides the chunk databy comparing a real-time CRC value to the CRC values,. In such examples, the FDL circuitrydetects the end of the chunk dataresponsive to the real-time CRC value matching the CRC value. Advantageously, the FDL circuitryuses the default data,to reduce a likelihood of accidentally matching CRC values.

8 FIG. 1 4 FIGS.and 1 5 FIGS.and 1 FIG. 7 FIG. 800 800 175 180 100 700 is a flowchart of embodiment method, according to an embodiment of the present disclosure. Methodmay be executed, instantiated, or performed using an example implementation of the FDL circuitryofand the FDL decoder circuitryofto update the firmware of the audio systemofusing the configuration dataof.

800 610 615 620 635 175 180 700 805 6 FIG. Methodbegin with the example operations of Blocks,,,of. In such example operations, the FDL circuitryand the FDL decoder circuitrygenerate a BRA call command (BRA_CALL) and begin receiving the configuration dataas the BRA data stream (BRA_DATA). Control proceeds to Block.

430 805 430 700 430 700 430 The CRC circuitrybegins calculating a real-time CRC value. (Block). In example operations, the CRC circuitryimplements a function to calculate a real-time CRC value as the BRA data stream (BRA_DATA) provides portions of the configuration data. In some examples, the CRC circuitrydetermines the real-time CRC value for portions of the configuration data. In other examples, the CRC circuitrydetermines a global real-time CRC value by using the CRC function since the beginning of the BRA data stream (BRA_DATA).

540 810 540 730 740 540 730 The chunk write circuitrybegins writing chunk data using the start address. (Block). In example operations, the chunk write circuitrybegins to write the chunk datato the chunk start address. In such example operations, the chunk write circuitrycontinues writing the chunk datato consecutive memory addresses.

430 815 430 430 430 730 430 745 430 745 560 430 815 815 The CRC circuitrydetermines if the CRC of the data write to the chunk matches a first CRC value. (Block). In example operations, the CRC circuitryuses the CRC function to update the real-time CRC value as the BRA data stream (BRA_DATA) continues. In such example operations, the CRC circuitrycompares the real-time CRC value to a subsequent packet(s) of the BRA data stream (BRA_DATA). In some examples, the CRC circuitrydetects the end of the chunk dataresponsive to the subsequent packet(s) being equal to the real-time CRC value. In such examples, the CRC circuitryidentifies the subsequent packet(s) as the CRC value. In other examples, the CRC circuitrydetermines the CRC valuefrom the datastore. If the CRC circuitrydetermines the CRC of the data write to the chunk does not match the first CRC value (e.g., Blockreturns a result of NO), control proceeds to return to Block.

430 815 430 820 430 750 755 745 430 430 750 755 750 755 430 745 430 820 815 If the CRC circuitrydetermines the CRC of the data write to the chunk does match the first CRC value (e.g., Blockreturns a result of YES), the CRC circuitrydetermines if the next data words match fixed CRC data. (Block). In example operations, after the real-time CRC value matches the subsequent packet(s), the CRC circuitryuses the default data,to confirm the subsequent packet(s) are the CRC value. In some examples, the CRC circuitrycompares subsequent packets of the BRA data stream (BRA_DATA) to expected reference values (also referred to as reference data packet(s)). If the subsequent packet(s) match the reference values, the CRC circuitryidentifies the packets as the default data,. Advantageously, the default data,allows the CRC circuitryto verify the real-time CRC value matches the CRC value. If the CRC circuitrydetermines the next data words do not match the fixed CRC data (e.g., Blockreturns a result of NO), control proceeds to return to Block.

430 820 430 825 745 750 755 430 730 760 430 760 710 430 745 760 730 165 430 825 815 430 825 645 655 If the CRC circuitrydetermines the next data words match the fixed CRC data (e.g., Blockreturns a result of YES), the CRC circuitrydetermines if the current CRC value matches a second CRC value. (Block). In example operations, after confirming the real-time CRC value matches the CRC valueusing the default data,, the CRC circuitryverifies the reception of the chunk databy comparing the real-time CRC value to the CRC value. In such example operations, the CRC circuitryuses the additional CRC of the CRC valueto confirm transmission of the data set. In some examples, the CRC circuitrymay use the CRC values,to verify a successful write of the chunk datato the memory circuitry. If the CRC circuitrydetermines the current CRC value does not match the second CRC value (e.g., Blockreturns a result of NO), control proceeds to return to Block. If the CRC circuitrydetermines the current CRC value does match the second CRC value (e.g., Blockreturns a result of YES), control proceeds with the operations of Blocks,.

8 FIG. 1 4 FIGS.and 1 5 FIGS.and 1 FIG. 7 FIG. 175 180 100 700 Example methods are described with reference to the flowchart illustrated in. However, many other methods of implementing the FDL circuitryofand the FDL decoder circuitryofto update the audio systemofusing the configuration dataofmay also be used in this description. For example, the order of execution of the blocks may be changed, or some of the blocks described may be changed, eliminated, or combined. Similarly, additional operations may be included in the manufacturing process before, in between, or after the blocks shown in the illustrated examples.

9 FIG. 1 2 7 FIGS.,, and 9 FIG. 2 FIG. 900 900 145 700 900 205 905 910 100 105 900 180 155 900 205 905 910 205 900 900 is a block diagram of example configuration data, according to an embodiment of the present disclosure. Configuration datais yet another example of the configuration data,of. In the example of, the configuration dataincludes the packet header, a first data set, and a second data set. In example operations of the audio system, the host deviceprovides the configuration datausing the BRA data stream (BRA_DATA). In such example operations, the FDL decoder circuitryor, more generally, the controllerdecodes the configuration datato identify the packet headerand the data sets,. As further described in connection with, the packet headeris a first portion of the configuration data, which provides context for the update data of the configuration data.

905 900 185 190 905 210 215 710 715 905 230 915 9 FIG. The data setis a second portion of the configuration data, which provides update data for a portion of memory, such as one of the portions of memory,. The data setis another example of the data sets,,,. The example data setofincludes the chunk headerand example chunk data.

915 235 255 730 770 235 255 730 770 915 920 925 930 920 930 230 925 915 920 930 915 925 915 900 925 900 925 915 925 920 930 9 FIG. 9 FIG. The chunk datais another example of the chunk data,,,. Unlike the chunk data,,,, the example chunk dataofincludes a first example portion of chunk data, example peripheral data, and a second example portion of chunk data. The portions of chunk data,contain update data of a portion of memory specified in the chunk header. In some examples, such as in, the peripheral datadivides the chunk datainto the portions of chunk data,. In such examples, the chunk datamay include any number of instances of the peripheral datadividing the chunk datainto any number of portions. Also, in some examples, the configuration datamay be structured to include an instance of the peripheral datain regular intervales. For example, the configuration dataincludes an instance of the peripheral dataafter every two-hundred words of the chunk data. In such examples, the instances of the peripheral dataset the maximum length of each of the portions of chunk data,to two-hundred words.

925 925 170 115 120 925 170 925 935 940 945 935 115 120 940 115 120 935 945 940 925 170 115 120 925 9 FIG. 9 FIG. The peripheral datarepresents peripheral device commands for devices coupled to the secondary device being updated. For example, the peripheral datacorresponds to commands from the interface circuitryto one or more of the bridge devices,. In some such examples, the peripheral datais set to produce commands using communication protocol of the interface circuitry, such as I2C, SPI, I3C, etc. The example peripheral dataofincludes an example peripheral device address, an example peripheral register address, and example peripheral write data. The peripheral device addressrepresents the one or more of the bridge devices,receiving the peripheral command. The peripheral register addresscorresponds to a register of the one or more bridge devices,of the peripheral device address. The peripheral write datais data to store in the register of the register address. In the example of, the peripheral dataillustrates an example of the interface circuitrycommunicating with the bridge devices,using inter-integrated circuit (I2C) protocol. However, the peripheral datamay be modified to support an alternative communication protocol, such as SPI, I3C, etc.

910 900 185 190 910 210 215 710 715 905 910 250 950 915 950 955 960 965 955 965 920 930 920 930 955 965 250 9 FIG. 9 FIG. The data setis a third portion of the configuration data, which provides update data for a portion of memory, such as one of the portions of memory,. The data setis another example of the data sets,,,,. The example data setofincludes the chunk headerand example chunk data. Similar to the chunk data, the example chunk dataofincludes a first example portion of chunk data, example peripheral data, and a second example portion of chunk data. The portions of chunk data,are examples of the portions of chunk data,. Unlike the portions of chunk data,, the portions of chunk data,correspond to the portion of memory of the chunk header.

925 960 115 120 960 970 975 980 960 170 115 120 9 FIG. 9 FIG. Similar to the peripheral data, the peripheral datais another command for one or more of the bridge devices,. The example peripheral dataofincludes an example peripheral device address, an example peripheral register address, and example peripheral write data. In the example of, the peripheral datais structured for I2C communications between the interface circuitryand the bridge devices,.

925 960 915 950 180 115 120 180 920 965 170 925 960 900 110 115 120 Advantageously, encoding the peripheral data,into the chunk data,allows the FDL decoder circuitryto update the bridge devices,during a firmware update. Advantageously, the FDL decoder circuitrycan continue to receive and write the portions of chunk data,during the write operations of the interface circuitry. Advantageously, including the peripheral data,in the configuration datareduces the total time to update the firmware of the audio deviceand the bridge devices,.

10 10 FIGS.A andB 1 5 FIGS.and 9 FIG. 10 10 FIGS.A andB 3 FIG. 1000 180 165 900 165 185 190 310 185 190 310 185 190 310 185 310 180 230 250 725 765 165 are a timing diagramof example operations of the FDL decoder circuitryofto update firmware in the memory circuitryusing the configuration dataof, according to an embodiment of the present disclosure. In the example of, the memory circuitryincludes the portions of memory,,. As further described in connection with, each respective one of the portions of memory,,span a plurality of consecutive memory addresses. However, in some examples, start or end memory addresses of the portions of memory,,are non-consecutive in relation to each other. For example, a portion of memory can separate the last address of the portion of memoryand the start address of the portion of memory. Advantageously, the FDL decoder circuitrycan use the chunk headers,,,to update non-consecutive memory addresses of the memory circuitrywithout an additional BRA call command (BRA_CALL).

1010 175 1020 105 900 1020 185 310 190 0 1 0 1 N At a first time(T), the FDL circuitrygenerates a BRA call command (BRA_CALL) to start a firmware update. At a second time(T), the host devicestarts providing the BRA data stream (BRA_DATA) responsive to the BRA call command (BRA_CALL). The BRA data stream (BRA_DATA) provides the update data corresponding to the configuration data. At the time, the portion of memorycontains first original chunk data (ORG_CHNK_DATA[n:0]), the portion of memorycontains second original chunk data (ORG_CHNK_DATA[d:0]), and the portion of memorycontains third original chunk data (ORG_CHNK_DATA[m:0]).

1020 1030 180 920 185 180 245 185 915 920 180 925 180 925 170 115 120 925 170 180 930 165 1030 185 920 930 310 190 2 2 0 1 N 9 FIG. Between the second timeand a third time(T), the FDL decoder circuitrywrites the first portion of chunk datato the portion of memory. In such example operations, the FDL decoder circuitryuses the start addressto identify an address in the portion of memoryto start writing the chunk data. In the example of, after receiving the portion of chunk data, the FDL decoder circuitryreceives the peripheral data. The FDL decoder circuitryprovides the peripheral datato the interface circuitryto begin updating the configuration of one or more of the bridge devices,. After providing the peripheral datato the interface circuitry, the FDL decoder circuitrycontinues by writing the portion of chunk datato the memory circuitry. After the third time(T), the portion of memorycontains the portions of chunk data,(CHNK_DATA[n:0]), the portion of memorycontains the original chunk data (ORG_CHNK_DATA[d:0]), and the portion of memorycontains the original chunk data (ORG_CHNK_DATA[m:0]).

1030 1040 180 955 190 180 265 190 950 955 180 960 180 960 170 115 120 960 170 180 965 165 1040 185 920 930 310 190 955 965 N N 0 1 N 9 FIG. Between the third timeand a fourth time(T), the FDL decoder circuitrywrites the portion of chunk datato the portion of memory. In such example operations, the FDL decoder circuitryuses the start addressto identify an address in the portion of memoryto start writing the chunk data. In the example of, after receiving the portion of chunk data, the FDL decoder circuitryreceives the peripheral data. The FDL decoder circuitryprovides the peripheral datato the interface circuitryto begin updating the configuration of one or more of the bridge devices,. After providing the peripheral datato the interface circuitry, the FDL decoder circuitrycontinues by writing the portion of chunk datato the memory circuitry. After the fourth time(T), the portion of memorycontains the portions of chunk data,(CHNK_DATA[n:0]), the portion of memorycontains the original chunk data (ORG_CHNK_DATA[d:0]), and the portion of memorycontains the portions of chunk data,(CHNK_DATA[m:0]).

1020 1030 1030 1040 180 115 120 925 960 925 960 920 930 955 965 900 Advantageously, between the times,and the times,, the FDL decoder circuitrycan start configuring the bridge devices,for the firmware update using the peripheral data,. Advantageously, providing the peripheral data,between the portions of chunk data,,,reduces the total time of the firmware update of the configuration data.

11 FIG. 1 4 FIGS.and 1 5 FIGS.and 1 FIG. 9 FIG. 1100 1100 175 180 100 900 is a flowchart of embodiment method, according to an embodiment of the present disclosure. Methodmay be executed, instantiated, or performed using an example implementation of the FDL circuitryofand the FDL decoder circuitryofto update the firmware of the audio systemofusing the configuration dataof.

1100 610 615 620 625 630 635 1105 Methodbegins with the example operations of Blocks,,,,,. Control proceeds to Block.

540 1105 540 920 245 165 540 920 165 The chunk write circuitrybegins a chunk data write using the chunk address and chunk length. (Block). In example operations, the chunk write circuitrybegins writing the portion of chunk datato the chunk start addressin the memory circuitry. In such example operations, the chunk write circuitrycontinues writing the portion of chunk datato consecutive addresses of the memory circuitry.

550 1110 550 925 925 900 900 925 915 550 925 900 750 755 925 The interface manager circuitrydetermines if there is peripheral data to write. (Block). In example operations, the interface manager circuitrymonitors the BRA data stream (BRA_DATA) for the peripheral data. In some examples, the peripheral datais periodically positioned in the configuration data. For example, the configuration datais structured to have an instance of the peripheral dataevery two-hundred and fifty words of the chunk data. In such examples, the interface manager circuitrymonitors the BRA data stream (BRA_DATA) every two-hundred and fifty words for the peripheral data. In other examples, the configuration datacan include fixed data packets, such as the default data,, to identify the peripheral data.

550 1110 550 1115 550 170 115 120 925 170 945 940 935 170 925 115 120 915 165 925 180 900 9 10 10 FIGS.,A, andB If the interface manager circuitrydetermines there is peripheral data to write (e.g., Blockreturns a result of YES), the interface manager circuitryprovides the peripheral data to secondary devices. (Block). In example operations, the interface manager circuitryuses the interface circuitryto configure one or more of the bridge devices,using the peripheral data. In some examples, such as in, the interface circuitryuses I2C communication protocols to write the peripheral write datato the register addressof the peripheral device address. In such example operations, the interface circuitryuses the peripheral datato generate write commands for the bridge devices,without stopping the write of the chunk datato the memory circuitry. Advantageously, the peripheral dataallows the FDL decoder circuitryto sequence use of a second communication protocol during the firmware update of the configuration data.

550 1110 1115 540 1120 925 170 540 930 165 540 915 240 645 650 655 If the interface manager circuitrydetermines there is no peripheral data to write (e.g., Blockreturns a result of NO) or control proceeds from Block, the chunk write circuitryfinishes the chunk data write using the chunk length and address. (Block). In example operations, after providing the peripheral datato the interface circuitry, the chunk write circuitryproceeds by writing the portion of chunk datato the memory circuitry. In some examples, the chunk write circuitrydetermines the end of the chunk datausing the chunk data length. Control proceeds to the Blocks,,.

11 FIG. 1 4 FIGS.and 1 5 FIGS.and 1 FIG. 9 FIG. 175 180 100 900 Example methods are described with reference to the flowchart illustrated in. However, many other methods of implementing the FDL circuitryofand the FDL decoder circuitryofto update the audio systemofusing the configuration dataofmay also be used in this description. For example, the order of execution of the blocks may be changed, or some of the blocks described may be changed, eliminated, or combined. Similarly, additional operations may be included in the manufacturing process before, in between, or after the blocks shown in the illustrated examples.

12 FIG. 6 8 11 FIGS.,, and 1 4 5 FIGS.,, and 1200 175 180 1200 is a block diagram of an example programmable circuitry platformstructured to one or a combination of execute or instantiate one or more of the example machine-readable instructions or the example operations ofto implement the FDL circuitryand the FDL decoder circuitryof. The programmable circuitry platformcan be, for example, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cell phone, a smart phone, a tablet such as an iPad™), a personal digital assistant (PDA), an Internet appliance, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a gaming console, a personal video recorder, a set top box, a headset (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc.) or other wearable device, or any other type of computing or electronic device.

1200 1212 1212 1212 1212 1212 175 180 155 The programmable circuitry platformof the illustrated example includes programmable circuitry. The programmable circuitryof the illustrated example is hardware. For example, the programmable circuitrycan be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, or microcontrollers from any desired family or manufacturer. The programmable circuitrymay be implemented by one or more semiconductor based (e.g., silicon based) devices. In this example, the programmable circuitryimplements the FDL circuitryand the FDL decoder circuitryor, more generally, the controller.

1212 1213 1212 1214 1216 1214 1216 1218 1214 1216 1214 1216 1217 1217 1214 1216 The programmable circuitryof the illustrated example includes a local memory(e.g., a cache, registers, etc.). The programmable circuitryof the illustrated example is in communication with main memory,, which includes a volatile memoryand a non-volatile memory, by a bus. The volatile memorymay be implemented by one or more Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS® Dynamic Random Access Memory (RDRAM®), or any other type of RAM device. The non-volatile memorymay be implemented by one or a combination of flash memory or any other desired type of memory device. Access to the main memory,of the illustrated examples is controlled by a memory controller. In some examples, the memory controllermay be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired family or manufacturer, or any other type of circuitry to manage the flow of data going to and from the main memory,.

1200 1220 1220 The programmable circuitry platformof the illustrated example also includes interface circuitry. The interface circuitrymay be implemented by hardware in according to any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, a Bluetooth® interface, a near field communication (NFC) interface, a Peripheral Component Interconnect (PCI) interface, or a Peripheral Component Interconnect Express (PCIe) interface.

1222 1220 1222 1212 1222 In the illustrated example, one or more input devicesare connected to the interface circuitry. The input device(s)permit(s) a user (e.g., a human user, a machine user, etc.) to enter one of or a combination of data or commands into the programmable circuitry. The input device(s)can be implemented by, for example, one of or a combination of an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touchscreen, a trackpad, a trackball, an isopoint device, or a voice recognition system.

1224 1220 1224 1220 One or more output devicesare also connected to the interface circuitryof the illustrated example. The output device(s)can be implemented, for example, by one of or a combination of display devices (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-place switching (IPS) display, a touchscreen, etc.), a tactile output device, a printer, or speaker. The interface circuitryof the illustrated example, thus, includes one of or a combination of a graphics driver card, a graphics driver chip, or graphics processor circuitry such as a GPU.

1220 1226 The interface circuitryof the illustrated example also includes a communication device such as one of or a combination of a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, or a network interface to facilitate exchange of data with external machines (e.g., computing devices of any kind) by a network. The communication can be by, for example, an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a beyond-line-of-sight wireless system, a line-of-sight wireless system, a cellular telephone system, an optical connection, etc.

1200 1228 1228 The programmable circuitry platformof the illustrated example also includes one or more mass storage discs or devicesto store one or more of firmware, software, or data. Examples of such mass storage discs or devicesinclude one or more magnetic storage devices (e.g., floppy disk, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray disks, CDs, DVDs, etc.), RAID systems, or solid-state storage discs or devices such as flash memory devices and SSDs.

1232 1228 1214 1216 6 8 11 FIGS.,, and The machine-readable instructions, which may be implemented by the machine-readable instructions of, may be stored in one of or a combination of the mass storage device, in the volatile memory, in the non-volatile memory, or on at least one non-transitory computer readable storage medium such as a CD or DVD which may be removable.

13 FIG. 12 FIG. 12 FIG. 6 8 11 FIGS.,, and 4 5 FIGS.and 1 4 5 FIGS.,, and 6 8 11 FIGS.,, and 1212 1212 1300 1300 1300 1300 1300 1302 1300 1302 1300 1302 1302 1302 is a block diagram of an example implementation of the programmable circuitryof. In this example, the programmable circuitryofis implemented by a microprocessor. For example, the microprocessormay be a general-purpose microprocessor (e.g., general-purpose microprocessor circuitry). The microprocessorexecutes some or all of the machine-readable instructions of the flowcharts ofto effectively instantiate the circuitry ofas logic circuits to perform operations corresponding to those machine-readable instructions. In some such examples, the circuitry ofis instantiated by the hardware circuits of the microprocessorin combination with the machine-readable instructions. For example, the microprocessormay be implemented by multi-core hardware circuitry such as a CPU, a DSP, a GPU, an XPU, etc. Although it may include any number of example cores(e.g., 1 core), the microprocessorof this example is a multi-core semiconductor device including N cores. The coresof the microprocessormay operate independently or may cooperate to execute machine-readable instructions. For example, machine code corresponding to a firmware program, an embedded software program, or a software program may be executed by one of the coresor may be executed by multiple ones of the coresat the same or different times. In some examples, the machine code corresponding to the firmware program, the embedded software program, or the software program is split into threads and executed in parallel by two or more of the cores. The software program may correspond to a portion or all of the machine-readable instructions or operations represented by the flowcharts of.

1302 1304 1304 1302 1304 1304 1302 1306 1302 1306 1302 1320 1300 1310 1310 1320 1302 1310 1214 1216 12 FIG. The coresmay communicate by a first example bus. In some examples, the first busmay be implemented by a communication bus to effectuate communication associated with one(s) of the cores. For example, the first busmay be implemented by at least one of an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Also or alternatively, the first busmay be implemented by any other type of computing or electrical bus. The coresmay receive data, instructions, and signals from one or more external devices by example interface circuitry. The coresmay output data, instructions, and signals to the one or more external devices by the interface circuitry. Although the coresof this example include example local memory(e.g., Level 1 (L1) cache that may be split into an L1 data cache and an L1 instruction cache), the microprocessoralso includes example shared memorythat may be shared by the cores (e.g., Level 2 (L2 cache)) for high-speed access to data and instructions. Data and instructions may be transferred (e.g., shared) by one of or a combination of writing to or reading from the shared memory. The local memoryof each of the coresand the shared memorymay be part of a hierarchy of storage devices including multiple levels of cache memory and the main memory (e.g., the main memory,of). In some examples, higher levels of memory in the hierarchy exhibit lower access time and have smaller storage capacity than lower levels of memory. Changes in the various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherency policy.

1302 1302 1314 1316 1318 1320 1322 1302 1314 1302 1316 1302 1316 1316 1316 1316 Each coremay be referred to as a CPU, DSP, GPU, etc., or any other type of hardware circuitry. Each coreincludes control unit circuitry, arithmetic and logic (AL) circuitry (sometimes referred to as an ALU), a plurality of registers, the local memory, and a second example bus. Other structures may be present. For example, each coremay include vector unit circuitry, single instruction multiple data (SIMD) unit circuitry, load/store unit (LSU) circuitry, branch/jump unit circuitry, floating-point unit (FPU) circuitry, etc. The control unit circuitryincludes semiconductor-based circuits structured to control (e.g., coordinate) data movement within the corresponding core. The AL circuitryincludes semiconductor-based circuits structured to perform one or more mathematic or logic operations on the data within the corresponding core. The AL circuitryof some examples performs integer-based operations. In other examples, the AL circuitryalso performs floating-point operations. In yet other examples, the AL circuitrymay include first AL circuitry that performs integer-based operations and second AL circuitry that performs floating-point operations. In some examples, the AL circuitrymay be referred to as an Arithmetic Logic Unit (ALU).

1318 1316 1302 1318 1318 1318 1302 1322 13 FIG. The registersare semiconductor-based structures to store data and instructions such as results of one or more of the operations performed by the AL circuitryof the corresponding core. For example, the registersmay include vector register(s), SIMD register(s), general-purpose register(s), flag register(s), segment register(s), machine-specific register(s), instruction pointer register(s), control register(s), debug register(s), memory management register(s), machine check register(s), etc. The registersmay be arranged in a bank as shown in. Alternatively, the registersmay be organized in any other arrangement, format, or structure, such as by being distributed throughout the coreto shorten access time. The second busmay be implemented by at least one of an I2C bus, a SPI bus, a PCI bus, or a PCIe bus.

1302 1300 1300 Each coreor, more generally, the microprocessormay include additional or alternate structures to those shown and described above. For example, one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more converged/common mesh stops (CMSs), one or more shifters (e.g., barrel shifter(s)) or other circuitry may be present. The microprocessoris a semiconductor device fabricated to include many transistors interconnected to implement the structures described above in one or more integrated circuits (ICs) contained in one or more packages.

1300 1300 1300 1300 The microprocessormay include or cooperate with one or more accelerators (e.g., acceleration circuitry, hardware accelerators, etc.). In some examples, accelerators are implemented by logic circuitry to perform certain tasks more quickly and efficiently than can be done by a general-purpose processor. Examples of accelerators include ASICs and FPGAs such as those described herein. A GPU, DSP, or other programmable device can also be an accelerator. Accelerators may be on-board the microprocessor, in the same chip package as the microprocessor, or in one or more separate packages from the microprocessor.

14 FIG. 12 FIG. 13 FIG. 1212 1212 1400 1400 1400 1300 1400 is a block diagram of another example implementation of the programmable circuitryof. In this example, the programmable circuitryis implemented by FPGA circuitry. For example, the FPGA circuitrymay be implemented by an FPGA. The FPGA circuitrycan be used, for example, to perform operations that could otherwise be performed by the example microprocessorofexecuting corresponding machine-readable instructions. However, once configured, the FPGA circuitryinstantiates the operations and functions corresponding to the machine-readable instructions in hardware and, thus, can often execute the operations/functions faster than they could be performed by a general-purpose microprocessor executing the corresponding software.

1300 1400 1400 1400 11 1400 1400 13 FIG. 6 8 11 FIGS.,, and 14 FIG. 6 8 11 FIGS.,, and 6 8 FIGS., 6 8 11 FIGS.,, and 6 8 11 FIGS.,, and More specifically, in contrast to the microprocessorofdescribed above (which is a general purpose device that may be programmed to execute some or all of the machine-readable instructions represented by the flowchart(s) ofbut whose interconnections and logic circuitry are fixed once fabricated), the FPGA circuitryof the example ofincludes interconnections and logic circuitry that may be one of or a combination of configured, structured, programmed, and interconnected in different ways after fabrication to instantiate, for example, some or all of the operations/functions corresponding to the machine-readable instructions represented by the flowchart(s) of. In particular, the FPGA circuitrymay be thought of as an array of logic gates, interconnections, and switches. The switches can be programmed to change how the logic gates are interconnected by the interconnections, effectively forming one or more dedicated logic circuits (unless and until the FPGA circuitryis reprogrammed). The configured logic circuits enable the logic gates to cooperate in different ways to perform different operations on data received by input circuitry. Those operations may correspond to some or all of the instructions (e.g., the software and/or firmware) represented by the flowchart(s) of, and. As such, the FPGA circuitrymay be at least one of configured or structured to effectively instantiate some or all of the operations/functions corresponding to the machine-readable instructions of the flowchart(s) ofas dedicated logic circuits to perform the operations/functions corresponding to those software instructions in a dedicated manner analogous to an ASIC. Therefore, the FPGA circuitrymay perform the operations/functions corresponding to the some or all of the machine-readable instructions offaster than the general-purpose microprocessor can execute the same.

14 FIG. 14 FIG. 14 FIG. 14 FIG. 14 FIG. 1400 1400 1400 1400 1400 In the example of, the FPGA circuitryis at least one of configured or structured in response to being programmed (and/or reprogrammed one or more times) based on a binary file. In some examples, the binary file may be one of or both of compiled or generated based on instructions in a hardware description language (HDL) such as Lucid, Very High-Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) may write code or a program corresponding to one or more operations/functions in an HDL; the code/program may be translated into a low-level language as needed; and the code/program (e.g., the code/program in the low-level language) may be converted (e.g., by a compiler, a software application, etc.) into the binary file. In some examples, the FPGA circuitryofmay at least one of access or load the binary file to cause the FPGA circuitryofto be at least one of configured or structured to perform the one or more operations/functions. For example, the binary file may be implemented by one of or a combination of a bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), or machine-readable instructions accessible to the FPGA circuitryofto at least one of configure or structure the FPGA circuitryof, or portion(s) thereof.

1400 1400 1400 1400 14 FIG. 14 FIG. 14 FIG. 14 FIG. In some examples, the binary file is at least one of compiled, generated, transformed, or otherwise output from a uniform software platform utilized to program FPGAs. For example, the uniform software platform may translate first instructions (e.g., code or a program) that correspond to one or more operations/functions in a high-level language (e.g., C, C++, Python, etc.) into second instructions that correspond to the one or more operations/functions in an HDL. In some such examples, the binary file is at least one of compiled, generated, or otherwise output from the uniform software platform based on the second instructions. In some examples, the FPGA circuitryofmay at least one of access or load the binary file to cause the FPGA circuitryofto be at least one of configured or structured to perform the one or more operations/functions. For example, the binary file may be implemented by one of or a combination of a bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), or machine-readable instructions accessible to the FPGA circuitryofto at least one of configure or structure the FPGA circuitryof, or portion(s) thereof.

1400 1402 1404 1406 1404 1400 1404 1406 1406 1300 14 FIG. 13 FIG. The FPGA circuitryof, includes example input/output (I/O) circuitryto at least one of receive or output data to/from at least one of example configuration circuitryor external hardware. For example, the configuration circuitrymay be implemented by interface circuitry that may receive a binary file, which may be implemented by one or more of a bit stream, data, or machine-readable instructions, to configure the FPGA circuitry, or portion(s) thereof. In some such examples, the configuration circuitrymay receive the binary file from one of or a combination of a user, a machine (e.g., hardware circuitry (e.g., programmable or dedicated circuitry) that may implement an Artificial Intelligence/Machine Learning (AI/ML) model to generate the binary file, etc.), or any combination(s) thereof). In some examples, the external hardwaremay be implemented by external hardware circuitry. For example, the external hardwaremay be implemented by the microprocessorof.

1400 1408 1410 1412 1408 1410 1408 1408 1408 6 8 11 FIGS.,, and 14 FIG. The FPGA circuitryalso includes an array of example logic gate circuitry, a plurality of example configurable interconnections, and example storage circuitry. The logic gate circuitryand the configurable interconnectionsare configurable to instantiate one or more operations/functions that may correspond to at least some of the machine-readable instructions ofand/or other desired operations. The logic gate circuitryshown inis fabricated in blocks or groups. Each block includes semiconductor-based electrical structures that may be configured into logic circuits. In some examples, the electrical structures include logic gates (e.g., And gates, Or gates, Nor gates, etc.) that provide basic building blocks for logic circuits. Electrically controllable switches (e.g., transistors) are present within each of the logic gate circuitryto enable configuration of one of or a combination of the electrical structures or the logic gates to form circuits to perform desired operations/functions. The logic gate circuitrymay include other electrical structures such as look-up tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, etc.

1410 1408 The configurable interconnectionsof the illustrated example are conductive pathways, traces, vias, or the like that may include electrically controllable switches (e.g., transistors) whose state can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more of the logic gate circuitryto program desired logic circuits.

1412 1412 1412 1408 The storage circuitryof the illustrated example is structured to store result(s) of the one or more of the operations performed by corresponding logic gates. The storage circuitrymay be implemented by registers or the like. In the illustrated example, the storage circuitryis distributed amongst the logic gate circuitryto facilitate access and increase execution speed.

1400 1414 1414 1416 1416 1400 1418 1420 1422 1418 14 FIG. The example FPGA circuitryofalso includes example dedicated operations circuitry. In this example, the dedicated operations circuitryincludes special purpose circuitrythat may be invoked to implement commonly used functions to avoid the need to program those functions in the field. Examples of such special purpose circuitryinclude memory (e.g., DRAM) controller circuitry, PCIe controller circuitry, clock circuitry, transceiver circuitry, memory, and multiplier-accumulator circuitry. Other types of special purpose circuitry may be present. In some examples, the FPGA circuitrymay also include example general purpose programmable circuitrysuch as an example CPUor an example DSP. Other general purpose programmable circuitrymay also or alternatively be present such as a GPU, an XPU, etc., that can be programmed to perform other operations.

13 14 FIGS.and 12 FIG. 13 FIG. 12 FIG. 13 FIG. 14 FIG. 13 FIG. 6 8 11 FIGS.,, and 14 FIG. 6 8 11 FIGS.,, and 6 8 FIGS., 1212 1420 1212 1300 1400 1302 1400 11 Althoughillustrate two example implementations of the programmable circuitryof, many other approaches are contemplated. For example, FPGA circuitry may include an on-board CPU, such as one or more of the example CPUof. Therefore, the programmable circuitryofmay also be implemented by combining at least the example microprocessorofand the example FPGA circuitryof. In some such hybrid examples, one or more coresofmay execute a first portion of the machine-readable instructions represented by the flowchart(s) ofto perform first operation(s)/function(s), the FPGA circuitryofmay be at least one of configured or structured to perform second operation(s)/function(s) corresponding to a second portion of the machine-readable instructions represented by the flowcharts of, and/or an ASIC may be at least one of configured or structured to perform third operation(s)/function(s) corresponding to a third portion of the machine-readable instructions represented by the flowcharts of, and.

1 4 5 FIGS.,, and 13 FIG. 14 FIG. 1300 1400 Some or all of the circuitry ofmay, thus, be instantiated at the same or different times. For example, same and/or different portion(s) of the microprocessorofmay be programmed to execute portion(s) of machine-readable instructions at the same and/or different times. In some examples, same and/or different portion(s) of the FPGA circuitryofmay be at least one of configured or structured to perform operations/functions corresponding to portion(s) of machine-readable instructions at the same and/or different times.

1 4 5 FIGS.,, and 13 FIG. 14 FIG. 1 4 5 FIGS.,, and 13 FIG. 1300 1400 1300 In some examples, some or all of the circuitry ofmay be instantiated, for example, in one or more threads executing concurrently and/or in series. For example, the microprocessorofmay execute machine-readable instructions in one or more threads executing concurrently and/or in series. In some examples, the FPGA circuitryofmay be at least one of configured or structured to carry out operations/functions concurrently and/or in series. Moreover, in some examples, some or all of the circuitry ofmay be implemented within one or more virtual machines or containers executing on the microprocessorof.

1212 1300 1400 1212 1300 1420 1422 1400 12 FIG. 13 FIG. 14 FIG. 12 FIG. 13 FIG. 14 FIG. 14 FIG. 14 FIG. In some examples, the programmable circuitryofmay be in one or more packages. For example, at least one of the microprocessorofor the FPGA circuitryofmay be in one or more packages. In some examples, an XPU may be implemented by the programmable circuitryof, which may be in one or more packages. For example, the XPU may include a CPU (e.g., the microprocessorof, the CPUof, etc.) in one package, a DSP (e.g., the DSPof) in another package, a GPU in yet another package, and an FPGA (e.g., the FPGA circuitryof) in still yet another package.

175 180 175 180 155 175 180 155 175 180 1 FIG. 1 4 5 FIGS.,, and 1 4 5 FIGS.,, and 1 4 5 FIGS.,, and 1 4 5 FIGS.,, and While an example manner of implementing the FDL circuitryand the FDL decoder circuitryofis illustrated in, one or more of the elements, processes, or devices illustrated inmay be combined, divided, re-arranged, omitted, eliminated, or implemented in any other way. Further, the FDL circuitryand the FDL decoder circuitryor, more generally, the controller, may be implemented by hardware alone or by hardware in combination with software and firmware. Thus, for example, any of the FDL circuitryand the FDL decoder circuitryor, more generally, the controller, could be implemented by programmable circuitry in combination with one or more machine-readable instructions (e.g., firmware or software), processor circuitry, analog circuit(s), digital circuit(s), logic circuit(s), programmable processor(s), programmable microcontroller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), ASIC(s), programmable logic device(s) (PLD(s)), or field programmable logic device(s) (FPLD(s)) such as FPGAs. Further still, the example FDL circuitryand the FDL decoder circuitryofmay include one or more elements, processes, or devices in addition to, or instead of, those illustrated in, or may include more than one of any or all of the illustrated elements, processes and devices.

175 180 175 180 1212 1200 1 4 5 FIGS.,, and 1 4 FIGS., 6 8 11 FIGS.,, and 12 FIG. 13 14 FIG.or Flowchart(s) representative of example machine-readable instructions, which may be executed by programmable circuitry to at least one of implement or instantiate the FDL circuitryand the FDL decoder circuitryofor representative of example operations which may be performed by programmable circuitry to at least one of implement or instantiate the FDL circuitryand the FDL decoder circuitryof, and 5, are shown in. The machine-readable instructions may be one or more executable programs or portion(s) of one or more executable programs for execution by programmable circuitry such as the programmable circuitryshown in the example processor platformdescribed below in connection withand may be one or more function(s) or portion(s) of functions to be performed by the example programmable circuitry (e.g., an FPGA) described below in connection with. In some examples, the machine-readable instructions cause an operation, a task, etc., to be carried out or performed in an automated manner in the real-world. As used herein, “automated” means without human involvement.

6 8 11 FIGS.,, and 175 180 The program may be embodied in instructions (e.g., software and/or firmware) stored on one or more non-transitory computer readable and/or machine-readable storage medium such as one of or a combination of cache memory, a magnetic-storage device or disk (e.g., a floppy disk, a Hard Disk Drive (HDD), etc.), an optical-storage device or disk (e.g., a Blu-ray disk, a Compact Disk (CD), a Digital Versatile Disk (DVD), etc.), a Redundant Array of Independent Disks (RAID), a register, ROM, a solid-state drive (SSD), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., Random Access Memory (RAM) of any type, etc.), or any other storage device or storage disk. The instructions of the non-transitory computer readable and/or machine-readable medium may program or be executed by programmable circuitry located in one or more hardware devices, but the entire program or parts thereof could alternatively be executed or instantiated by one or more hardware devices other than the programmable circuitry or embodied in dedicated hardware. The machine-readable instructions may be distributed across multiple hardware devices or executed by two or more hardware devices (e.g., a server and a client hardware device). For example, the client hardware device may be implemented by an endpoint client hardware device (e.g., a hardware device associated with a human and/or machine user) or an intermediate client hardware device gateway (e.g., a radio access network (RAN)) that may facilitate communication between a server and an endpoint client hardware device. Similarly, the non-transitory computer readable storage medium may include one or more mediums. Further, although the example program is described with reference to the flowchart(s) illustrated in, many other methods of implementing the example FDL circuitryand the FDL decoder circuitrymay alternatively be used. For example, the order of execution of the blocks of the flowchart(s) may be changed, or some of the blocks described may be changed, eliminated, or combined. Also or alternatively, any or all of the blocks of the flow chart may be implemented by one or more hardware circuits (e.g., processor circuitry, discrete, integrated analog and/or digital circuitry, an FPGA, an ASIC, a comparator, an operational-amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware. The programmable circuitry may be distributed in different network locations or local to one or more hardware devices (e.g., a single-core processor (e.g., a single core CPU), a multi-core processor (e.g., a multi-core CPU, an XPU, etc.)). As used herein, programmable circuitry includes any type(s) of circuitry that may be programmed to perform a desired function such as, for example, one of or a combination of a CPU or an FPGA. The programmable circuitry may include one or more CPUs and/or one or more FPGAs located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate housings), one or more CPUs or FPGAs in a single machine, one or multiple CPUs or FPGAs distributed across multiple servers of a server rack, multiple processors distributed across one or more server racks. Also or alternatively, programmable circuitry may include a programmable logic device (PLD), a generic array logic (GAL) device, a programmable array logic (PAL) device, a complex programmable logic device (CPLD), a simple programmable logic device (SPLD), a microcontroller (MCU), a programmable system on chip (PSoC), etc., or any combination(s) thereof in any of the contexts described above.

The machine-readable instructions described herein may be stored in one or more of a compressed format, an encrypted format, a fragmented format, a compiled format, an executable format, a packaged format, etc. Machine readable instructions as described herein may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.), etc.) or a data structure (e.g., as portion(s) of instructions, code, representations of code, etc.) that may be utilized to create, manufacture, or produce machine executable instructions. For example, the machine-readable instructions may be fragmented and stored on one or more storage devices, disks or computing devices (e.g., servers) located at the same or different locations of a network or collection of networks (e.g., in the cloud, in edge devices, etc.). The machine-readable instructions may require one or more of installation, modification, adaptation, updating, combining, supplementing, configuring, decryption, decompression, unpacking, distribution, reassignment, compilation, etc., in order to make them directly readable, interpretable, or executable by a computing device or other machine. For example, the machine-readable instructions may be stored in multiple parts, which are individually compressed, encrypted, or stored on separate computing devices, wherein the parts when decrypted, decompressed, or combined form a set of one or more computer-executable or machine executable instructions that implement one or more functions or operations that may together form a program such as that described herein.

In another example, the machine-readable instructions may be stored in a state in which they may be read by programmable circuitry, but require addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., in order to execute the machine-readable instructions on a particular computing device or other device. In another example, the machine-readable instructions may need to be configured (e.g., settings stored, data input, network addresses recorded, etc.) before the machine-readable instructions or the corresponding program(s) can be executed in whole or in part. Thus, machine-readable, computer readable or machine-readable media, as used herein, may include one or a combination of instructions and program(s) regardless of the particular format or state of the machine-readable instructions or program(s).

The machine-readable instructions described herein can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions may be represented using any of the following languages: C, C++, Java, C-Sharp, Perl, Python, JavaScript, HyperText Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

6 8 11 FIGS.,, and As mentioned above, the example operations ofmay be implemented using executable instructions (e.g., computer readable and/or machine-readable instructions) stored on one or more non-transitory computer readable or machine-readable media. As used herein, the terms non-transitory computer readable medium, non-transitory computer readable storage medium, non-transitory machine-readable medium, and non-transitory machine-readable storage medium are expressly defined to include any type of computer readable storage device or storage disk and to exclude propagating signals and to exclude transmission media. Examples of such non-transitory computer readable medium, non-transitory computer readable storage medium, non-transitory machine-readable medium, or non-transitory machine-readable storage medium include one or more optical storage devices, magnetic storage devices, an HDD, a flash memory, a read-only memory (ROM), a CD, a DVD, a cache, a RAM of any type, a register, or any other storage device or storage disk in which information is stored for any duration (e.g., for extended time periods, permanently, for brief instances, for temporarily buffering, for caching of the information). As used herein, the terms “non-transitory computer readable storage device” and “non-transitory machine-readable storage device” are defined to include any physical (mechanical, magnetic, electromechanical, or electrical) hardware to retain information for a time period, but to exclude propagating signals and to exclude transmission media. Examples of non-transitory computer readable storage devices or non-transitory machine-readable storage devices include one or a combination of random-access memory of any type, read only memory of any type, solid state memory, flash memory, optical discs, magnetic disks, disk drives, or redundant array of independent disks (RAID) systems. As used herein, the term “device” refers to physical structure such as one of or a combination of mechanical, electromechanical, or electrical equipment, hardware, or circuitry that may or may not be configured by computer readable instructions, machine-readable instructions, etc., or manufactured to execute computer-readable instructions, machine-readable instructions, etc.

Example embodiments of the present disclosure are summarized here. Other embodiments can also be understood from the entirety of the specification and the claims filed herein.

Example 1. A device including: memory circuitry having a first memory portion and a second memory portion, the first memory portion corresponding to a first range of memory addresses, the second memory portion corresponding to a second range of memory addresses, where the first range of memory addresses are non-consecutive to the second range of memory addresses; and a controller coupled to the memory circuitry, the controller configured to: request first data; after requesting the first data, receive the first data in a packet having a first data set and a second data set, the first data set including a first chunk start address corresponding to an address of the first range of memory addresses, the second data set including a second chunk start address corresponding to an address of the second range of memory address; write data of the first data set to the first memory portion using the first chunk start address; and write data of the second data set to the second memory portion using the second chunk start address.

Example 2. The device of example 1, where the packet includes a header that includes a payload length field, and a payload including the first and second data sets.

Example 3. The device of one of examples 1 or 2, where the memory circuitry further includes a third memory portion corresponding to a third range of memory addresses, the first and third ranges of memory addresses being consecutive addresses, and the second and third ranges of memory addresses being consecutive addresses.

Example 4. The device of one of examples 1 to 3, where to request the first data, the controller is configured to: generate a bulk register access (BRA) call command; and provide the BRA call command to a host device.

Example 5. The device of one of examples 1 to 4, further including a host device coupled to the controller, the host device configured to, after receiving the BRA call, provide the first data including the first data set and the second data set using SoundWire protocols.

Example 6. The device of one of examples 1 to 5, where the data of the first data set includes chunk data, where the first data set further includes a chunk header, the chunk header including the first chunk start address, where the first chunk start address corresponds to the start address in the first range of addresses of the first memory portion.

Example 7. The device of one of examples 1 to 6, where the chunk header further includes a chunk start address, the chunk start address corresponds to the start address in the first range of addresses of the first memory portion, and the controller is further configured to write the chunk data of the first data set beginning at the chunk start address.

Example 8. The device of one of examples 1 to 7, where the data of the first data set includes chunk data, where the first data set further includes cyclic redundancy check (CRC) data, and the controller is further configured to verify the write of the chunk data to the first memory portion using the CRC data.

Example 9. The device of one of examples 1 to 8, where the CRC data includes a CRC value and default data, and the controller further configured to: calculate a real-time CRC value using the write of the first data set; compare the real-time CRC value to the CRC value; and after determining the real-time CRC value is equal to the CRC value, compare subsequent data of the first data set to the default data; and after determining the default data matches reference data, determine that the write of the first data set is successful.

Example 10. The device of one of examples 1 to 9, where the first data set further includes a first portion, peripheral data, and a second portion, the device further including: a bridge device coupled to the controller; and where the controller is further configured to: after writing the first portion of the first data set to the first memory portion, write the peripheral data to the bridge device; and write the second portion of the data of the first data set to the first memory portion.

Example 11. The device of one of examples 1 to 10, where the controller is configured to write the second portion of the data of the first data set to the first memory portion after writing the peripheral data to the bridge device.

Example 12. The device of one of examples 1 to 11, where the controller is configured to write at least a portion of the second portion of the data of the first data set to the first memory portion while writing the peripheral data to the bridge device.

Example 13. The device of one of examples 1 to 12, where the controller writes the peripheral data to the bridge device using an inter-integrated circuit (I2C) protocol.

Example 14. The device of one of examples 1 to 13, further including a speaker or microphone coupled to the bridge device.

Example 15. A method including: requesting, by a first device, first data using a first protocol; after requesting the first data, receiving, by the first device, a packet including the first data using the first protocol, the first data having a first data set and a second data set, the first data set including peripheral data, the second data set including a chunk start address corresponding to an address of a first portion of memory; writing, by the first device, a first portion of the first data set to a second portion of memory; after writing the first portion of the first data set, providing, by the first device, the peripheral data to a second device using a second protocol; after writing the first portion of the first data set, writing, by the first device, a second portion of the first data set to the second portion of memory; and after writing the second portion of the first data set, writing data of the second data set to the first portion of memory using the chunk start address of the second data set.

Example 16. The method of example 15, where providing the peripheral data to the second device occurs while receiving, by the first device, the packet.

Example 17. The method of one of examples 15 or 16, where providing the peripheral data to the second device occurs while receiving, by the first device, at least a portion of the second data set.

Example 18. The method of one of examples 15 to 17, where the first data includes first configuration data for the first device, the method further including, after receiving the first data, receiving audio data via the first protocol.

Example 19. The method of one of examples 15 to 18, where the first data includes second configuration data for the second device.

Example 20. The method of one of examples 15 to 19, further including configuring the second device, and a third device, using the second configuration data.

Example 21. The method of one of examples 15 to 20, where the requesting for first data includes: generating a bulk register addressing (BRA) call command; and providing the BRA call command to a host device having the first data.

Example 22. The method of one of examples 15 to 21, where the first protocol is SoundWire and the second protocol is inter-integrated circuit (I2C).

Example 23. The method of one of examples 15 to 22, where the peripheral data includes peripheral device commands and the second device is a bridge device supporting at least one of a microphone or speaker.

Example 24. The method of one of examples 15 to 23, where the first data set further includes cyclic redundancy check (CRC) data, the method further including, verifying the write of the first and second portions of the first data set using the CRC data.

Example 25. The method of one of examples 15 to 24, where the CRC data includes a CRC value and default data, and the method further including: calculating a real-time CRC value using the write of the first data set; comparing the real-time CRC value to the CRC value; and after determining the real-time CRC value is equal to the CRC value, comparing subsequent data of the first data set to the default data; and after determining the default data matches reference data, determining the write of the first data set is successful.

Example 26. A device including: memory circuitry having a first memory portion, a second memory portion, and a third memory portion, the first memory portion corresponding to a first range of memory addresses, the second memory portion corresponding to a second range of memory addresses, the third memory portion corresponding to a third range of memory addresses, where the first and second ranges of memory addresses are consecutive addresses, and where the second and third ranges of memory addresses are consecutive addresses; and a controller coupled to the memory circuitry, the controller configured to: request configuration data; after requesting the configuration data, receive the configuration data having a first data set and a second data set, the first data set including a first memory address in the first range of memory addresses, the second data set including a second memory address of in the third range of memory addresses; write data of the first data set to the first memory portion using the first memory address; and write data of the second data set to the third memory portion using the second memory address.

Example 27. The device of example 26, where the configuration data includes configuration data for configuring the device.

Example 28. The device of one of examples 26 or 27, where the requesting for update data includes: generating a bulk register addressing (BRA) call command; and providing the BRA call command to a host device having the first data.

Example 29. The device of one of examples 26 to 28, where the first data set includes chunk data, the first data set further includes cyclic redundancy check (CRC) data, and the controller is further configured to verify the write of the chunk data to the first memory portion using the CRC data.

Example 30. The device of one of examples 26 to 29, where the CRC data includes a CRC value and default data, and the controller further configured to: calculate a real-time CRC value using the write of the first data set; compare the real-time CRC value to the CRC value; and after determining the real-time CRC value is equal to the CRC value, compare subsequent data of the first data set to the default data; and after determining the default data matches reference data, determine the write of the first data set is successful.

Example 31. The device of one of examples 26 to 30, where the first data set further includes a first portion, peripheral data, and a second portion, and the device further including: a bridge device coupled to the controller; and where the controller is further configured to: after writing the first portion of the first data set to the first memory portion, write the peripheral data to the bridge device; and write the second portion of the first data set to the first memory portion.

Example 32. An electronic device including: a primary device; a secondary device; and an audio device coupled to the primary device and the secondary device, the audio device configured to: receive an update using a first communication protocol, the update having a first data set and a second data set, the update corresponding to operations of the secondary device; write data of the first data set to a first portion of memory, the first portion of memory corresponding to first operations of the secondary device; and write data of the second data set to a second portion of memory, the second portion of memory corresponding to second operations of the secondary device, the first and second portions of memory have non-consecutive memory addresses.

As used herein, “approximately” and “about” modify their subjects/values to recognize the potential presence of variations that occur in real world applications. For example, “approximately” and “about” may modify dimensions that may not be exact due to at least one of manufacturing tolerances or other real-world imperfections. For example, “approximately” and “about” may indicate such dimensions may be within a tolerance range of +/−10% unless otherwise specified herein.

As used herein, the phrase “in communication,” including variations thereof, encompasses one of or a combination of direct communication or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication or constant communication, but rather also includes selective communication at least one of periodic intervals, scheduled intervals, aperiodic intervals, or one-time events.

As used herein, “programmable circuitry” may include at least one of (i) one or more special purpose electrical circuits (e.g., an application specific circuit (ASIC)) structured to perform specific operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), or (ii) one or more general purpose semiconductor-based electrical circuits programmable with instructions to perform one or more specific functions(s) or operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include programmable microprocessors such as Central Processor Units (CPUs) that may execute first instructions to perform one or more operations or functions, Field Programmable Gate Arrays (FPGAs) that may be programmed with second instructions to at least one of configure or structure the FPGAs to instantiate one or more operations or functions corresponding to the first instructions, Graphics Processor Units (GPUs) that may execute first instructions to perform one or more operations or functions, Digital Signal Processors (DSPs) that may execute first instructions to perform one or more operations or functions, XPUs, Network Processing Units (NPUs) one or more microcontrollers that may execute first instructions to perform one or more operations or functions or integrated circuits such as Application Specific Integrated Circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system including multiple types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and any combination(s) thereof), and orchestration technology (e.g., application programming interface(s) (API(s)) that may assign computing task(s) to whichever one(s) of the multiple types of programmable circuitry is/are suited and available to perform the computing task(s).

Circuits described herein are reconfigurable to include the replaced components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in at least one of series or parallel to provide an amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor. While certain elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit and some features illustrated as being internal to the integrated circuit may be incorporated outside of the integrated. As used herein, the term “integrated circuit” means one or more circuits that are at least one of: (i) incorporated in/over a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; or (iv) incorporated in/on the same printed circuit board.

Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.