Cable Failure Protection and Battery Kickstart in an Electronic Device

This application claims the benefit of U.S. provisional patent application Ser. No. 63/708,444, filed on Oct. 17, 2024, and U.S. provisional patent application Ser. No. 63/742,042, filed on Jan. 6, 2025, the disclosures of which are hereby incorporated herein by reference in their entireties.

The present disclosure is related to universal serial bus type-C (USB-C) cable failure protection and depleted battery kickstart in an electronic device.

Today's electronic devices (e.g. smartphones and wireless headphones) are typically powered by an embedded battery and/or low dropout (LDO) regulator. Often times, these electronic devices are charged periodically via a universal serial bus type-C (USB-C) cable connecting the electronic devices to an external power supply (e.g., wall charger or portable power bank).

USB-C is an industry-standard connector for transmitting both data and power on a single cable. The USB-C connector was developed by the USB Implementers Forum (USB-IF), a group of companies that has developed, certified, and shepherded the USB standard over the years.

1 2 A standard USB-C receptacle and plug include many pins. Among them, a pair of configuration channel (CC) pins (denoted as CC, CC), multiple bus voltage (VBUS) pins, and multiple ground (GND) pins are particularly relevant for power charging purposes. The pair of CC pins is used for detecting an attachment of the USB-C cable and an orientation of the USB-C cable once attached. The VBUS pins are used for providing a charging voltage/current from the external power supply to the electronic device once the USB-C cable is properly attached between them.

1 FIG. 10 12 14 12 14 14 12 1 2 14 1 2 12 14 12 1 2 14 12 10 14 12 14 is a schematic diagram providing an exemplary illustration as to how a valid connection of a USB-C cablebetween a USB-C source(e.g., external power supply) and a USB-C sink(e.g., electronic device) can be detected. According to release 2.0 of the USB-C cable and connector specification, the general concept for setting up a valid connection between the USB-C sourceand the USB-C sinkis based on being able to detect terminations residing in the USB-C sink. Initially, the USB-C sourceexposes independent Rp terminations on the CC, CCpins, whereas the USB-C sinkexposes independent Rd terminations on the CC, CCpins. To detect the valid connection between the USB-C sourceand the USB-C sink, the USB-C sourcemonitors the CC, CCpins for a voltage lower than an unterminated voltage, which indicates that the USB-C sinkis attached to the USB-C sourcevia the USB-C cable. Upon detecting the attachment of the USB-C sink, the USB-C sourceasserts a bus voltage on the VBUS pins (not shown). Accordingly, the USB-C sinkcan charge the embedded battery and/or LDO regulator based on the bus voltage.

Embodiments of the disclosure relate to cable failure protection and battery kickstart in an electronic device. When the electronic device is attached to an external power supply via a universal serial bus type-C (USB-C) cable, it is important to protect the electronic device from being damaged by a cable failure (e.g., overcurrent, overtemperature, and/or faulty cable). Additionally, when a battery in the electronic device is fully depleted, it is necessary to kickstart recharging of the depleted battery upon attaching to the USB-C cable. In this regard, a power management integrated circuit (PMIC) is provided in the electronic device and configured in accordance with the USB-C standard to protect the electronic device from the cable failure and kickstart recharging of the depleted battery. By integrating cable failure protection and battery kickstart functionalities into the PMIC, as opposed to using discrete solutions, it is possible to reduce cost and footprint of the PMIC, thus making the PMIC suitable for small formfactor electronic devices.

In one aspect, a USB-C charging system is provided. The USB-C charging system includes a USB-C connector. The USB-C connector includes a pair of configuration channel (CC) pins. The pair of CC pins is configured to indicate whether the USB-C connector is attached to an external power supply via a USB-C cable. The USB-C connector also includes a bus voltage (VBUS) pin. The VBUS pin is configured to receive a bus voltage from the external power supply when the pair of CC pins indicate that the USB-C connector is attached to the external power supply. The USB-C charging system also includes a PMIC. The PMIC is coupled to the USB-C connector. The PMIC includes a battery charging circuit. The battery charging circuit is coupled to the VBUS pin. The battery charging circuit is configured to charge an internal always-on voltage regulator based on the bus voltage to provide an always-on voltage (VAO). The PMIC also includes a control circuit. The control circuit is coupled to the pair of CC pins. The control circuit is configured to emulate a detachment condition to the external power supply via the pair of CC pins in response to detecting a failure condition of the USB-C cable to thereby cancel the bus voltage on the VBUS pin. The control circuit is also configured to emulate an attachment condition to the external power supply via the pair of CC pins when the internal always-on voltage regulator is depleted to thereby kickstart the bus voltage on the VBUS pin to charge the internal always-on voltage regulator.

In another aspect, an electronic device is provided. The electronic device includes a USB-C charging system. The USB-C charging system includes a USB-C connector. The USB-C connector includes a pair of CC pins. The pair of CC pins is configured to indicate whether the USB-C connector is attached to an external power supply via a USB-C cable. The USB-C connector also includes a VBUS pin. The VBUS pin is configured to receive a bus voltage from the external power supply when the pair of CC pins indicate that the USB-C connector is attached to the external power supply. The USB-C charging system also includes a PMIC. The PMIC is coupled to the USB-C connector. The PMIC includes a battery charging circuit. The battery charging circuit is coupled to the VBUS pin. The battery charging circuit is configured to charge an internal always-on voltage regulator based on the bus voltage to provide a VAO. The PMIC also includes a control circuit. The control circuit is coupled to the pair of CC pins. The control circuit is configured to emulate a detachment condition to the external power supply via the pair of CC pins in response to detecting a failure condition of the USB-C cable to thereby cancel the bus voltage on the VBUS pin. The control circuit is also configured to emulate an attachment condition to the external power supply via the pair of CC pins when the internal always-on voltage regulator is depleted to thereby kickstart the bus voltage on the VBUS pin to charge the internal always-on voltage regulator.

In another aspect, a method for enabling cable failure protection and battery kickstart in a USB-C charging system is provided. The method includes indicating, via a pair of CC pins in a USB-C connector, whether the USB-C connector is attached to an external power supply via a USB-C cable. The method also includes receiving, via a VBUS pin in the USB-C connector, a bus voltage from the external power supply when the pair of CC pins indicate that the USB-C connector is attached to the external power supply. The method also includes charging an internal always-on voltage regulator based on the bus voltage to provide a VAO. The method also includes emulating a detachment condition to the external power supply via the pair of CC pins in response to detecting a failure condition of the USB-C cable to thereby cancel the bus voltage on the VBUS pin. The method also includes emulating an attachment condition to the external power supply via the pair of CC pins when the internal always-on voltage regulator is depleted to thereby kickstart the bus voltage on the VBUS pin to charge the internal always-on voltage regulator.

Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

1 FIG. is a schematic diagram providing an exemplary illustration as to how a valid Universal Serial Bus Type-C (USB-C) cable connection between a USB-C source and a USB-C sink can be detected;

2 FIG. is a schematic diagram of an exemplary USB-C charging system wherein a protection circuit and a control circuit can be integrated into a power management integrated circuit (PMIC) to enable cable failure protection and battery kickstart when the PMIC is attached to an external power supply via a USB-C cable;

3 FIG. 2 FIG. is a schematic diagram providing an exemplary detailed illustration of the PMIC in the USB-C charging system ofconfigured according to an embodiment of the present disclosure;

4 FIG. 3 FIG. is a graphic diagram providing an exemplary illustration as to how the protection circuit and the control circuit in the PMIC ofcan enable a battery kickstart in the PMIC;

5 FIG. 3 FIG. is a graphic diagram providing an exemplary illustration as to how the protection circuit and the control circuit in the PMIC ofcan protect the PMIC from a cable failure;

6 FIG. 2 3 FIGS.and is a schematic diagram of an exemplary communication device wherein the USB-C charging systems ofcan be provided; and

7 FIG. 2 3 FIGS.and is a flowchart of an exemplary process for providing battery kickstart and cable failure protection in the USB-C charging systems of.

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Embodiments are described herein with reference to cable failure protection and battery kickstart in an electronic device. When the electronic device is attached to an external power supply via a universal serial bus type-C (USB-C) cable, it is important to protect the electronic device from being damaged by a cable failure (e.g., overcurrent, overtemperature, and/or faulty cable). Additionally, when a battery in the electronic device is fully depleted, it is necessary to kickstart recharging of the depleted battery upon attaching to the USB-C cable. In this regard, a power management integrated circuit (PMIC) is provided in the electronic device and configured in accordance with the USB-C standard to protect the electronic device from the cable failure and kickstart recharging of the depleted battery. By integrating cable failure protection and battery kickstart functionalities into the PMIC, as opposed to using discrete solutions, it is possible to reduce cost and footprint of the PMIC, thus making the PMIC suitable for small formfactor electronic devices.

2 FIG. 16 18 20 22 22 24 26 22 24 28 28 28 1 2 28 is a schematic diagram of an exemplary USB-C charging systemwherein a protection circuitand a control circuitcan be integrated into a PMICto enable cable failure protection and battery kickstart when the PMICis attached to an external power supplyvia a USB-C cable. The PMICis attached to the external power supply(e.g., wall charger, portable power bank, etc.) via a USB-C connector. The USB-C connectorincludes all the physical pins as defined in release 2.0 of the USB-C cable and connector specification (hereinafter “USB-C specification”). Among all the physical pins in the USB-C connector, only a pair of configuration channel (CC) pins (denoted as CC, CC) and a bus voltage pin VBUS are illustrated herein. All other pins in the USB-C connectorare omitted for the sake of simplicity.

22 1 2 28 24 28 24 22 24 22 30 32 22 34 34 22 22 24 1 2 22 CC1 CC2 CC1 CC2 BUS CHG BUS BAT BUS CC1 CC2 BUS According to the USB-C specification, the PMICwill maintain unterminated voltages V, Von the pair of CC pins CC, CC, respectively, before the USB-C connectoris attached to the external power supply. When the USB-C connectoris attached to the external power supply, the PMICwill pull down at least one of the unterminated voltages V, Vsuch that the external power supplycan detect the attachment of the PMICand assert a bus voltage Von the bus voltage pin VBUS. Accordingly, a battery charging circuitcan generate a charging current Ibased on the bus voltage Vto thereby charge a batteryto a battery voltage V. The PMICmay further include an internal always-on voltage regulator, which can be a low dropout (LDO) regulator. The internal always-on voltage regulatorcan generate an always-on voltage (VAO) based on the bus voltage Vto thereby power normal operation of the PMIC. When the PMICis detached from the external power supply, the voltages on the pair of CC pins CC, CCwill return to the unterminated voltages V, V. Accordingly, the external power supply can detect the detachment of the PMICand cancel the bus voltage V.

22 24 22 24 32 22 1 2 24 30 32 CC1 CC2 BUS CC1 CC2 BUS As described in detail below, the PMICcan be configured to emulate the detachment condition by raising the voltages V, Vin response to detecting a cable failure condition (e.g., overcurrent, overtemperature, faulty cable, etc.) to thereby cause the external power supplyto cancel the bus voltage Vwithout having to physically detach the PMICfrom the external power supply. In the event that the batteryis fully depleted, the PMICcan operate based on respective voltages on the pair of CC pins CC, CCto pull down the voltage V, Vto thereby emulate the attachment condition. As a result, the external power supplywill assert the bus voltage Von the bus voltage pin VBUS to allow the battery charging circuitto recharge the fully depleted batteryto provide the always-on voltage VAO.

36 28 28 28 28 NTC NTC NTC NTC In an embodiment, a negative temperature coefficient (NTC) thermistor(e.g., 10 KΩ, 3380K) is provided in proximity to the USB-C connectorto thereby generate an NTC voltage V. Herein, the NTC voltage Vis inversely related to the temperature of the USB-C connector. When the temperature of the USB-C connectorincreases, the NTC voltage Vwill decrease. In contrast, when the temperature of the USB-C connectordecreases, the NTC voltage Vwill increase.

18 30 18 28 26 18 28 26 18 20 20 1 2 24 22 NTC CC1 CC2 BUS The protection circuitcan be activated by the battery charging circuitbased on an activation signal VAO_OK. Once activated, the protection circuitis configured to determine whether the USB-C connectorand/or the USB-C cableis faulty based on the NTC voltage V. Should the protection circuitdetermine that the USB-C connectorand/or the USB-C cableis faulty, the protection circuitwill provide a failure correction signal CC_PLDWN to the control circuit. Accordingly, the control circuitwill emulate the detachment condition by pulling up one or more of the voltages V, Von one or more of the pair of CC pins CC, CC. In response, the external power supplywill cancel the bus voltage Vto thereby protect the PMIC.

20 32 20 20 1 2 20 24 30 32 CC1 CC2 CC1 CC2 BUS Notably, the control circuitis also powered by the always-on voltage VAO under normal operating conditions. However, when the batteryis fully depleted, the control circuitmay no longer be able to operate based on the always-on voltage VAO. In this regard, the control circuitmay instead operate based on one or more of the voltages V, Von one or more of the pair of CC pins CC, CC. Specifically, the control circuitmay pull down one or more of the voltages V, Vto thereby emulate the attachment condition. As a result, the external power supplywill assert the bus voltage Von the bus voltage pin VBUS to allow the battery charging circuitto recharge the fully depleted battery.

3 FIG. 2 FIG. 2 3 FIGS.and 22 is a schematic diagram providing an exemplary detailed illustration of the PMICinconfigured according to an embodiment of the present disclosure. Common elements betweenare shown therein with common element numbers and will not be re-described herein.

30 38 24 38 32 34 32 34 BUS CHG BUS BUS BUS Herein, the battery charging circuitincludes a charging circuitthat is coupled to the bus voltage pin VBUS. When the external power supplyasserts the bus voltage Von the bus voltage pin VBUS, the charging circuitgenerates the charging current Ibased on the bus voltage Vto thereby charge the battery. The internal always-on voltage regulatoris also charged by the bus voltage Vto thereby provide the always-on voltage VAO. In this regard, when the bus voltage Vis present on the bus voltage pin VBUS, both the batteryand the internal always-on voltage regulatorwill be charged.

18 36 40 22 18 42 42 44 44 The protection circuitis coupled to the NTC thermistorvia an NTC pinin the PMIC. The protection circuitincludes an internal current sourcethat is powered by the internal always-on voltage VAO. The internal current sourceis coupled to a fault detection circuitvia a switch SW. In this regard, the fault detection circuitcan be activated in presence of the internal always-on voltage VAO by closing the switch SW or deactivated in absence of the internal always-on voltage VAO by opening the switch SW.

44 46 46 40 46 48 48 20 48 44 NTC NTC NTC NTC The fault detection circuitincludes a fault detection comparator. The fault detection comparatoris coupled to the NTC pinto receive the NTC voltage Vand compare the NTC voltage Vagainst a detection threshold TMP_REF. When the NTC voltage Vis below the detection threshold TMP_REF (V<TMP_REF), the fault detection comparatorwill generate a fault indication USB_FAULT and provide the fault indication USB_FAULT to a fault detection logic AND gate. The fault detection logic AND gatewill then provide the failure correction signal CC_PLDWN to the control circuit. Notably, the fault detection logic AND gatewill only generate the failure correction signal CC_PLDWN when the fault detection circuitis activated in the presence of the always-on voltage VAO.

18 50 52 1 2 50 52 28 24 54 CC1 CC2 CC1 CC2 The protection circuitalso includes a pair of CC comparators,, each coupled to a respective one of the pair of CC pins CC, CC. Each of the CC comparators,compares a respective one of the voltages V, Vagainst a detection threshold DET_TH to determine whether the USB-C connectorhas been attached to the external power supply. A logic OR gateis configured to generate a CC detection indication CC_DET when any of the voltages V, Vis above the detection threshold DET_TH.

18 56 44 34 44 18 32 The protection circuitfurther includes a protection control comparatorthat generates a protection enable signal TMP_PRO when the CC detection indication CC_DET and the activation signal VAO_OK, which indicates the presence of the always-on voltage VAO, are both present. The protection enable signal TMP_PRO will close the switch SW to thereby activate the fault detection circuit. In an embodiment, the internal always-on voltage regulatorwill only assert the activation signal VAO_OK when the always-on voltage VAO is above a certain voltage level. As such, the fault detection circuit, and therefore the protection circuit, will not be enabled when the batteryis fully depleted.

20 1 2 20 58 60 62 64 58 60 62 64 A B A B The control circuitincludes a pair of resistors R, R(e.g., 5.1 KΩ) that are coupled to the pair of CC pins CC, CC, respectively. The control circuitalso includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistorand the second transistorare coupled in parallel between the resistor Rand a ground (GND), whereas the third transistorand the fourth transistorare coupled in parallel between the resistor Rand the GND.

20 1 2 3 4 1 60 1 2 64 1 3 58 1 4 62 1 The control circuitfurther includes a first inverter U, a second inverter U, a third inverter U, and a fourth inverter U. The first inverter Uis coupled between the second transistorand a resistor R, the second inverter Uis coupled between the fourth transistorand the resistor R, the third inverter Uis coupled between the first transistorand the resistor R, and the fourth inverter Uis coupled between the third transistorand the resistor R.

1 1 2 60 64 32 22 60 1 64 2 1 2 24 32 A CC1 B CC2 CC1 CC2 BUS In an embodiment, the resistor Ris coupled to the GND to ensure that a default state of the failure correction signal CC_PLDWN is kept low such that the first inverter Uand the second inverter Ucan turn on the second transistorand the fourth transistor, respectively, when the batteryis fully depleted and the rest of the PMICis powered off. Specifically, when the second transistoris turned on by the first inverter U, the resistor Rwill be coupled to the GND to thereby reduce the voltage V. Likewise, when the fourth transistoris turned on by the second inverter U, the resistor Rwill be coupled to the GND to thereby reduce the voltage V. As described earlier, by pulling down the voltages V, Von the pair of CC pins CC, CC, it is possible to emulate the attachment condition to thereby cause the external power supplyto assert the bus voltage Vto recharge the battery.

4 FIG. 3 FIG. 3 4 FIGS.and 18 20 22 is a graphic diagram providing an exemplary illustration as to how the protection circuitand the control circuitin the PMICofcan enable the battery kickstart operation. Common elements betweenare shown therein with common element numbers and will not be re-described herein.

1 1 CC1 CC2 2 2 1 CC1 CC2 3 3 2 BUS 4 4 3 5 5 4 22 24 32 22 24 26 28 1 2 20 24 34 56 18 18 Prior to time T, the PMICis not yet attached to the external power supplybut the batteryis fully depleted. At time T, the PMICis attached to the external power supplyvia the USB-C cableand the USB-C connector. As such, the voltages V, Von the pair of CC pins CC, CCare both held high at the unterminated level. At time T(T>T), the control circuitpulls down the voltages V, Vto emulate the attachment condition. Accordingly, at time T(T≥T), the external power supplyasserts the bus voltage Von the voltage supply pin VBUS. Subsequently, at time T(T>T), the internal always-on voltage regulatoris sufficiently charged to the always-on voltage VAO and generates the activation signal VAO_OK. The protection control comparatorthen generates the protection enable signal TMP_PRO at time T(T>T) to activate the protection circuit. The failure correction signal CC_PLDWN is kept low until the protection circuitdetects the cable failure.

3 FIG. 3 4 3 4 32 34 3 4 18 44 3 4 58 62 A B CC1 CC2 With reference back to, the third inverter Uand the fourth inverter Uare each powered by the always-on voltage VAO. In this regard, the third inverter Uand the fourth inverter Uwill not be operational when the batteryis fully depleted. When the internal always-on voltage regulatoris sufficiently charged to provide the always-on voltage VAO, the third inverter Uand the fourth inverter Uwill be operational along with the protection circuit. As such, when the fault detection circuitasserts the failure correction signal CC_PLDWN, the third inverter Uand the fourth inverter Uwill open the first transistorand the third transistor. Accordingly, the resistors R, Rwill become floating to thereby pull up the voltages V, Vto thereby emulate the detachment condition.

5 FIG. 3 FIG. 3 5 FIGS.and 18 20 22 is a graphic diagram providing an exemplary illustration as to how the protection circuitand the control circuitin the PMICofcan protect the PMIC from the cable failure. Common elements betweenare shown therein with common element numbers and will not be re-described herein.

1 NTC 2 2 1 NTC 3 3 2 CC1 CC2 BUS 4 4 3 NTC CC1 CC2 BUS 18 46 48 3 4 58 62 1 2 24 3 4 58 62 1 2 24 At time T, the protection circuitis activated to monitor the NTC voltage V. At time T(T≥T), the NTC voltage Vfalls below the detection threshold TMP_REF. Accordingly, at time T(T≥T), the fault detection comparatorwill generate the fault indication USB_FAULT to thereby cause the fault detection logic AND gateto assert the failure correction signal CC_PLDWN. Accordingly, the third inverter Uand the fourth inverter Uwill open the first transistorand the third transistor, respectively, to raise the voltages V, Von the pair of CC pins CC, CCto thereby cause the external power supplyto cancel the bus voltage Von the bus voltage pin VBUS. At time T(T>T), the NTC voltage Vrises above the detection threshold TMP_REF. Accordingly, the fault indication USB_FAULT becomes low causing the failure correction signal CC_PLDWN to be de-asserted. The third inverter Uand the fourth inverter U, in turn, will close the first transistorand the third transistor, respectively, to pull down the voltages V, Von the pair of CC pins CC, CCto thereby cause the external power supplyto re-assert the bus voltage Von the bus voltage pin VBUS.

16 100 16 2 3 FIGS.and 6 FIG. 2 3 FIGS.and The USB-C charging systemofcan be provided in a communication device to support the embodiments described above. In this regard,is a schematic diagram of an exemplary communication devicewherein the USB-C charging systemofcan be provided.

100 100 102 104 106 108 110 112 114 102 102 108 112 110 Herein, the communication devicecan be any type of communication devices, such as mobile terminals, smart watches, tablets, computers, navigation devices, access points, base stations (e.g., eNB, gNB, etc.), and like wireless communication devices that support wireless communications, such as cellular, wireless local area network (WLAN), Ultra-wideband (UWB), Bluetooth, and near-field communications. The communication devicewill generally include a control system, a baseband processor, transmit circuitry, receive circuitry, antenna switching circuitry, multiple antennas, and user interface circuitry. In a non-limiting example, the control systemcan be a field-programmable gate array (FPGA), as an example. In this regard, the control systemcan include at least a microprocessor, an embedded memory circuit, and a communication bus interface. The receive circuitryreceives radio frequency signals via the antennasand through the antenna switching circuitryfrom one or more base stations. A low-noise amplifier and a filter cooperate to amplify and remove broadband interference from the received signal for processing. Downconversion and digitization circuitry (not shown) will then downconvert the filtered, received signal to an intermediate or baseband frequency signal, which is then digitized into one or more digital streams using analog-to-digital converters (ADCs).

104 104 The baseband processorprocesses the digitized received signal to extract the information or data bits conveyed in the received signal. This processing typically comprises demodulation, decoding, and error correction operations, as will be discussed in greater detail below. The baseband processoris generally implemented in one or more digital signal processors (DSPs) and application-specific integrated circuits (ASICs).

104 102 106 112 110 112 106 108 For transmission, the baseband processorreceives digitized data, which may represent voice, data, or control information, from the control system, which it encodes for transmission. The encoded data is output to the transmit circuitry, where a digital-to-analog converter (DAC) converts the digitally encoded data into an analog signal and a modulator modulates the analog signal onto a carrier signal that is at a desired transmit frequency or frequencies. A power amplifier will amplify the modulated carrier signal to a level appropriate for transmission and deliver the modulated carrier signal to the antennasthrough the antenna switching circuitry. The multiple antennasand the replicated transmitand receive circuitrymay provide spatial diversity. Modulation and processing details will be understood by those skilled in the art.

16 200 16 2 3 FIGS.and 7 FIG. 2 3 FIGS.and In an embodiment, the USB-C charging systemofcan be operated in accordance with a process. In this regard,is a flowchart of an exemplary processfor enabling cable failure protection and battery kickstart in the USB-C charging systemof.

200 1 2 28 28 24 26 202 200 28 24 1 2 28 24 204 200 34 206 200 24 1 2 26 208 200 24 1 2 34 34 210 BUS BUS BUS BUS Herein, the processincludes indicating, via the pair of CC pins CC, CCin the USB-C connector, whether the USB-C connectoris attached to the external power supplyvia the USB-C cable(step). The processalso includes receiving, via the VBUS pin in the USB-C connector, the bus voltage Vfrom the external power supplywhen the pair of CC pins CC, CCindicate that the USB-C connectoris attached to the external power supply(step). The processalso includes charging the internal always-on voltage regulatorbased on the bus voltage Vto provide the always-on voltage VAO (step). The processalso includes emulating the detachment condition to the external power supplyvia the pair of CC pins CC, CCin response to detecting the failure condition of the USB-C cableto thereby cancel the bus voltage Von the VBUS pin (step). The processalso includes emulating the attachment condition to the external power supplyvia the pair of CC pins CC, CCwhen the internal always-on voltage regulatoris depleted to thereby kickstart the bus voltage Von the VBUS pin to charge the internal always-on voltage regulator(step).

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.