Method of Manufacturing Semiconductor Device Including Two-Dimensional Materials

This application claims priority to Korean Patent Application No. 10-2024-0145121, filed on Oct. 22, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

The present disclosure relates to a method of manufacturing a semiconductor device including two-dimensional materials.

Two-dimensional materials include atoms that form a specific crystal structure. Research and development have been conducted on various two-dimensional materials having semiconductor or insulator properties. These two-dimensional materials have attracted attention as next-generation materials that may overcome limitations of related devices.

To grow two-dimensional materials with high quality and uniform thickness on a wafer scale, a metal organic precursor may be introduced. However, when patterning two-dimensional materials on a wafer, there are process issues such as a decrease in the quality of the thin film and the need for complex processes in multiple operations.

One or more example embodiments provide a method of manufacturing a semiconductor device including supplying an etchant to a chamber using surface wave plasma to remove a residue from a two-dimensional material layer.

According to an aspect of an example embodiment, a method of manufacturing a semiconductor device includes: providing a two-dimensional material layer on a substrate; and supplying an etchant to the two-dimensional material layer to remove a residue from the two-dimensional material layer. The supplying the etchant to the two-dimensional material layer includes: supplying a first process gas to a chamber in which the substrate is provided; supplying microwaves to the chamber to form a first plasma in the chamber; and supplying a second process gas, including a different material from the first process gas, to the chamber to form a second plasma including the etchant.

According to another aspect of an example embodiment, a method of manufacturing a semiconductor device includes: providing a two-dimensional material layer on a substrate; forming a mask layer on the two-dimensional material layer, wherein the mask layer exposes a first region and a second region of the two-dimensional material layer; forming a first source/drain electrode on the first region and a second source/drain electrode on the second region; removing the mask layer to expose a third region of the two-dimensional material layer between the first region and the second region; and removing a residue on the third region of the two-dimensional material layer. The removing the residue includes: supplying a first process gas to a chamber in which the substrate is provided; supplying microwaves to the chamber to form a first plasma in the chamber; and supplying a second process gas, including a different material from the first process gas, to the chamber to form a second plasma.

According to another aspect of an example embodiment, a method of manufacturing a semiconductor device includes: providing a two-dimensional material layer on a substrate; and supplying an etchant to the two-dimensional material layer to remove a residue from the two-dimensional material layer. The supplying the etchant to the two-dimensional material layer includes: supplying a first process gas to a chamber in which the substrate is provided; supplying microwaves to the chamber to form a first plasma in the chamber; and supplying a second process gas, including a different material from the first process gas, to the chamber to form a second plasma. The second process gas includes hydrogen. The second plasma includes the etchant. The etchant includes hydrogen radicals. The residue is removed from a surface of the two-dimensional material layer by the hydrogen radicals.

According to one or more example embodiments, because residues are removed using surface wave plasma, damage to the two-dimensional material layer may be prevented or reduced. Additionally, because plasma is formed in a chamber, the process time may be shortened.

Advantages and effects are not limited to the foregoing, and may be more easily understood in view of the following description of example embodiments.

Hereinafter, example embodiments of the present disclosure will be described with reference to the accompanying drawings. Embodiments described herein are example embodiments, and thus, the present disclosure is not limited thereto, and may be realized in various other forms. Each example embodiment provided in the following description is not excluded from being associated with one or more features of another example or another example embodiment also provided herein or not provided herein but consistent with the present disclosure. It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer, or intervening elements or layers may be present. By contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. It will be also understood that, even if a certain operation of manufacturing an apparatus or structure is described later than another operation, the operation may be performed later than the other operation unless the other operation is described as being performed after the operation. The same reference numerals are used to denote the same elements in the drawings, and repeated descriptions thereof will be omitted.

1 FIG. is a flowchart illustrating a method of manufacturing a semiconductor device according to an example embodiment.

1 FIG. 100 110 120 130 Referring to, a method of manufacturing semiconductor device according to an example embodiment may include forming a two-dimensional material layer on a substrate (S), forming source/drain electrodes on first and second regions of the two-dimensional material layer (S), removing a residue on the two-dimensional material layer by supplying an etchant to the two-dimensional material layer (S), and forming a gate dielectric layer and a gate electrode on a third region of the two-dimensional material layer (S).

2 2 FIGS.A toF are vertical cross-sectional views illustrating a method of manufacturing a semiconductor device according to an example embodiment.

1 2 FIGS.andA 120 130 110 110 110 110 Referring to, a back gate electrodeand a back gate dielectric layermay be formed on a substrate. The substratemay be a semiconductor substrate, an insulating substrate, or a semiconductor substrate having an insulating layer formed on a surface, but is not limited thereto. The substratemay include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. For example, the substratemay be a silicon substrate in which silicon oxide is formed on silicon.

120 110 130 110 120 120 110 120 130 The back gate electrodemay be disposed on the substrate, and the back gate dielectric layermay cover the substrateand the back gate electrode. The back gate electrodemay be disposed on an insulating layer of the substrate. According to an example embodiment, the back gate electrodeand the back gate dielectric layermay be omitted.

120 The back gate electrodemay include a conductive material, and the conductive material may include at least one of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, tungsten nitride, etc.), a conductive metal oxide (e.g., indium tin oxide (ITO), indium zinc oxide (IZO), etc.), a metal (e.g., tungsten, titanium, tantalum, cobalt, aluminum, ruthenium, etc.), and a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

130 130 2 3 2 3 2 2 3 2 x y 2 x y 2 3 x y x y x y 2 3 The back gate dielectric layermay include at least one of a silicon oxide, a silicon nitride, a low-κ material, and a high-κ material. The high-κ material may refer to a dielectric material having a dielectric constant higher than that of silicon oxide, and the low-κ material may refer to a dielectric material having a dielectric constant lower than that of silicon oxide. The high-κ material may be, for example, a metal oxide or a metal oxynitride. The high-κ material may be, for example, any one of aluminum oxide (AlO), tantalum oxide (TaO), titanium oxide (TiO), yttrium oxide (YO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), hafnium oxide (HfO), hafnium silicon oxide (HfSiO), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), lanthanum hafnium oxide (LaHfO), hafnium aluminum oxide (HfAlO), and praseodymium oxide (PrO). The back gate dielectric layermay be formed as a single layer or multiple layers of the aforementioned materials.

140 110 100 140 130 120 130 140 110 140 140 140 6 2 5 2 2 A two-dimensional material layermay be formed on a substrate(S). For example, the two-dimensional material layermay be formed on the back gate dielectric layer. For example, the back gate electrodeand the back gate dielectric layermay be omitted, and the two-dimensional material layermay be formed on the substrate. The two-dimensional material layermay include a two-dimensional material. The two-dimensional material layermay be formed by a deposition process such as a chemical vapor deposition (CVD) method. For example, the two-dimensional material layermay be formed by a CVD method using an organic ligand, such as Mo(CO)and (CH)S, as a precursor.

The two-dimensional material refers to a semiconductor material having a two-dimensional crystal structure. The two-dimensional material may have a layered structure of a monolayer or a multilayer. Each layer included in the two-dimensional material may have a thickness on an atomic level. For example, thickness of each layer included in the two-dimensional material may correspond to a thickness of a single atom. The two-dimensional material may include, for example, a transition metal dichalcogenide (TMD).

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 2 The TMD may include, for example, one transition metal among Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, and Re, and one chalcogen element among S, Se, and Te. The TMD may be expressed, for example, as MX, where M represents a transition metal and X represents a chalcogen element. For example, M may be Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, or the like, and X may be S, Se, Te, or the like. Accordingly, for example, the TMD may include MoS, MoSe, MoTe, WS, WSe, WTe, ZrS, ZrSe, HfS, HfSe, NbSe, and ReSe. Alternatively, the TMD may not be expressed as MX. In this case, for example, the TMD may include CuS, a compound of Cu, a transition metal, and S, a chalcogen element. On the other hand, the TMD may be a chalcogenide material including a non-transition metal. The non-transition metal may include, for example, Ga, In, Sn, Ge, Pb, etc. In this case, the TMD may include a compound of a non-transition metal such as Ga, In, Sn, Ge and Pb, and a chalcogen element such as S, Se and Te. For example, the TMD may include SnSe, GaS, GaSe, GaTe, GeSe, InSe, and InSnS.

As described above, the TMD may include one metal element among Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Cu, Ga, In, Sn, Ge and Pb, and one chalcogen element among S, Se and Te. However, the materials described above are only examples, and other materials may be used as TMD materials.

140 The two-dimensional material layermay further include a predetermined dopant to control the mobility of the two-dimensional semiconductor material. Specifically, the two-dimensional semiconductor material may be doped with a P-type dopant or an N-type dopant. The P-type dopant or the N-type dopant may be doped by ion implantation or chemical doping.

2 4 4 2 6 2 4 3 2 4 3 4 3 4 3 2 6 2 2 A source of the P-type dopant may include, for example, ionic liquids such as NOBF, NOBFand NOSbF, acidic compounds such as HCl, HPO, CHCOOH, HSOand HNO, organic compounds such as dichlorodicyanoquinone (DDQ), oxone, dimyristoylphosphatidylinositol (DMPI), and trifluoromethanesulfoneimide. Alternatively, a source of the P-type dopant may include HPtCl, AuCl, HAuCl, silver trifluoromethanesulfonate (AgOTf), AgNO, HPdCl, Pd(OAc), and Cu(CN).

A source of the N-type dopant may include, for example, a reduction product of a substituted or unsubstituted nicotinamide; a reduction product of a compound which is chemically bound to a substituted or unsubstituted nicotinamide; and a compound including at least two pyridinium moieties in which a nitrogen atom of at least one of the pyridinium moieties is reduced. For example, the source of the N-type dopant may include nicotinamide mononucleotide-H (NMNH), nicotinamide adenine dinucleotide-H (NADH), nicotinamide adenine dinucleotide phosphate-H (NADPH), or a viologen. Alternatively, the source of the N-type dopant may include a polymer such as polyethylenimine (PEI). Alternatively, the N-type dopant may include an alkali metal such as K or Li. The P-type dopant and N-type dopant materials described above are provided as examples, and various other materials may be used as dopants.

2 FIG.B 140 130 140 140 140 140 140 140 140 140 140 140 a b a b c c Referring to, the method may include forming a mask layer M on a two-dimensional material layer. The mask layer M may be formed to cover the back gate dielectric layerand the two-dimensional material layer, and may be patterned to expose a portion of the two-dimensional material layer. The patterning process may include removing a portion of the mask layer M by a wet etching process. The portions of the two-dimensional material layerexposed by the mask layer M may be referred to as a first regionand a second region, respectively. A portion of the two-dimensional material layerbetween the first regionand the second regionmay be referred to as a third region. The third regionmay be covered with a mask layer M.

x y z In an example embodiment, the mask layer M may include a CHO-based hydrocarbon material (wherein X, Y and Z are arbitrary integers). For example, the mask layer M may be a photoresist, and may include materials such as 2-heptanone, dihydro-2-furanone, and 1-Methoxy-2-propanol acetate.

1 2 FIGS.andC 150 140 140 140 110 150 150 140 140 140 130 140 a b a b Referring to, source/drain electrodesmay be formed on the first and second regionsandof the two-dimensional material layer(S). The source/drain electrodesmay be formed by depositing a conductive material. The source/drain electrodesmay cover side surfaces and upper surfaces of the first and second regionsandof the two-dimensional material layer, as well as a portion of the back gate dielectric layerbetween the mask M and the two-dimensional material layer. A conductive material may also be deposited on an upper surface of the mask layer M.

150 The source/drain electrodemay include a conductive material, and the conductive material may include at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal oxide, a metal, or a metal-semiconductor compound.

2 FIG.D 140 140 c Referring to, the conductive material on the upper surface of the mask layer M may be removed, and the mask layer M may be removed. For example, the mask layer M may be removed by a stripping process, and the third regionof the two-dimensional material layermay be exposed.

145 140 145 140 140 145 140 140 140 140 c In an example embodiment, a residuemay remain on the two-dimensional material layer. For example, the residuemay remain on the third regionof the two-dimensional material layerafter the mask layer M is removed. The residuemay be derived from the mask layer M and/or the two-dimensional material layer. For example, in a process of removing the mask layer M, a portion of the mask layer M may not be completely removed and may remain on the two-dimensional material layer. As another example, a precursor used when depositing the two-dimensional material layermay remain on the two-dimensional material layer.

1 FIG. 2 FIG.E 3 5 FIGS.to 145 140 140 120 140 Referring toand, the residueon the two-dimensional material layermay be removed by supplying an etchant on the two-dimensional material layer(S). A method of supplying an etchant on the two-dimensional material layerwill be described in detail below with reference to.

1 FIG. 2 FIG.F 2 FIG.F 160 170 140 140 130 100 100 160 150 150 c Referring toand, a gate dielectric layerand a gate electrodemay be formed on the third regionof the two-dimensional material layer(S), and a semiconductor devicemay be manufactured. A structure of the semiconductor deviceillustrated inis provided as an example and example embodiments are not limited thereto. According to an example embodiment, an upper surface of the gate dielectric layermay cover upper surfaces of the source/drain electrodesor may be disposed on a level higher than the upper surfaces of the source/drain electrodes.

160 170 The gate dielectric layermay include at least one of silicon oxide, silicon nitride, a low-κ material, and a high-κ material. The gate electrodemay include a conductive material, and the conductive material may include at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal oxide, a metal, and a metal-semiconductor compound.

100 140 140 140 140 100 110 a b c The semiconductor devicemay include, for example, a field effect transistor (FET). The first and second regionsandof the two-dimensional material layermay function as a source/drain of the transistor, and the third regionmay function as a channel. The semiconductor devicemay further include a peripheral circuit disposed on the substrateand configured to select and control an impurity region due to doping, an electronic device such as a transistor, or memory cells for storing data.

100 140 100 170 140 c In an example embodiment, the semiconductor devicemay include a Fin Field Effect Transistor (FinFET) in which the third regionhas a fin shape. In an example embodiment, the semiconductor devicemay include a Multi-Bridge Channel (MBC) FET in which the gate electrodesurrounds the two-dimensional material layerin a Gate all around (GAA) structure.

3 FIG. is a flow chart illustrating a method of removing residue according to an example embodiment.

3 FIG. 120 145 140 140 121 122 123 Referring to, a method (S) of removing the residueon the two-dimensional material layerby supplying the etchant on the two-dimensional material layermay include supplying a first process gas to a chamber (S), supplying microwaves to the chamber to form a first plasma (S), and supplying a second process gas into the chamber to form a second plasma (S).

4 FIG.A 4 FIG.A 120 145 is a cross-sectional view of a plasma processing device according to an example embodiment.illustrates a plasma processing device including a chamber in which the method (S) for removing the residueis performed.

4 FIG.A 1 10 20 10 10 10 10 Referring to, a plasma processing devicemay include a chamberand a microwave generating deviceconnected to the chamberand supplying microwaves to the chamber. The chambermay include side walls that define an internal space of the chamber.

10 10 15 15 10 15 15 1 110 2 2 FIGS.A toF The chambermay include a metal material such as aluminum (Al). In an example embodiment, the chambermay include a wafer transfer port, and the wafer transfer portmay be disposed on (and may extend through) a side wall of the chamberso that a semiconductor wafer W may be loaded or unloaded through the wafer transfer port. The wafer transfer portmay be coupled to a transfer chamber of another semiconductor wafer processing device and/or other chambers of the plasma processing device. The semiconductor wafer W may include a substratedescribed with reference to.

10 17 17 17 10 10 The chambermay include an exhaust pipeconnected to a wall of a lower portion thereof. The exhaust pipemay be connected to a vacuum pump. The exhaust pipemay exhaust process gases, process byproducts, and the like, in the chamber, and may be used to control the pressure in the chamber.

10 32 34 32 34 32 32 34 10 The chambermay include an electrostatic chuckto support a semiconductor wafer W and a lower supportersupporting the electrostatic chuck. The lower supportermay vertically raise or lower the electrostatic chuck. The electrostatic chuckand the lower supportermay be disposed in a lower portion of the chamber.

32 10 32 2 3 The electrostatic chuckmay be a susceptor including a heating member (e.g., a heater or heating device), and the heating member may be disposed in the susceptor. The heating member may be provided with power from the outside of the chamberor the outside of the susceptor to heat the susceptor. The susceptor may include a ceramic material, such as aluminum nitride (AlN), aluminum oxide (AlO), or the like. In an example embodiment, the electrostatic chuckmay include an electrode inside, and the electrode may be connected to a high-frequency power source. The electrode may apply a bias voltage to the semiconductor wafer W.

10 36 32 The chambermay include a guide ringextending along an outer periphery of the electrostatic chuckto guide the semiconductor wafer W.

10 40 50 10 40 50 32 40 50 10 40 42 10 40 10 2 2 2 3 The chambermay further include an upper gas ringand a lower gas ringdisposed in an upper portion of the chamber. The upper gas ringand the lower gas ringmay be disposed on the semiconductor wafer W and the electrostatic chuck. The upper gas ringand the lower gas ringmay extend in a circumferential direction along the side wall of the chamber. The upper gas ringmay be connected to an upper gas supply device, and may supply a process gas into the chamber. For example, the upper gas ringmay supply at least one of Ar, H, CO, O, NH, and He into the chamber.

50 40 50 52 10 50 10 2 4 2 The lower gas ringmay be disposed below the upper gas ring. The lower gas ringmay be connected to a lower gas supply deviceand may supply a process gas into the chamber. For example, the lower gas ringmay supply at least one of DCS, N, CH, H, HCl, He, or Ar into the chamber.

10 60 62 40 The chambermay further include a dielectric plateand a planar antennadisposed on the upper gas ring.

60 60 40 60 10 60 40 60 10 The dielectric platemay be formed of a dielectric. The dielectric platemay be disposed on the upper gas ring, and a lower surface of the dielectric platemay be exposed to an internal space of the chamber. Microwaves transmitted through the dielectric platemay be supplied to the process gas supplied to the chamber by the upper gas ring, and may generate surface wave plasma in a portion directly below the dielectric platein the chamber.

62 60 62 22 60 62 64 The planar antennamay be disposed on the dielectric plate. The planar antennamay be connected to a waveguide, and may radiate microwaves to the dielectric plate. The planar antennamay include portions defining a plurality of slotsfor uniformly radiating microwaves.

1 70 10 70 10 The plasma processing devicemay further include an analyzeron the side wall of the chamber. The analyzermay be an Optical Emission Spectroscopy (OES) device. The OES device may receive light from outside the chamberto analyze the uniformity of plasma in the chamber, plasma stability, and substances within the plasma.

4 FIG.B is a cross-sectional view of a plasma processing device according to an example embodiment.

4 FIG.B 1 55 10 55 50 55 10 Referring to, the plasma processing devicemay further include an electrode ringdisposed in the chamber. The electrode ringmay be disposed between the lower gas ringand the semiconductor wafer W. For example, the electrode ringmay extend in a horizontal direction along the side wall of the chamber.

55 10 55 55 2 2 The electrode ringmay be connected to a power source outside the chamber, and voltage may be applied to the electrode ring. In an example embodiment, the electrode ringmay apply an electric field to the second plasma Pdescribed below, and may improve plasma uniformity. Accordingly, the second plasma Pmay be uniformly provided on the semiconductor wafer W.

5 FIG. 3 5 FIGS.to is a conceptual diagram illustrating a method of removing a residue according to an example embodiment. Hereinafter, the method of removing a residue will be explained with reference to.

3 5 FIGS.to 1 10 121 1 40 42 1 40 1 1 2 2 2 3 Referring to, a first process gas Gmay be supplied to the chamber(S). The first process gas Gmay be supplied by the upper gas ring. For example, the upper gas supply devicemay supply the first process gas Gto the upper gas ring. The first process gas Gmay include at least one of Ar, H, CO, O, NH, or He. For example, the first process gas Gmay include Ar and He.

10 1 122 20 62 10 22 62 60 60 1 1 60 1 Then, microwaves may be supplied to the chamberto form a first plasma P(S). For example, the microwaves generated from the microwave generating devicemay be transmitted to the planar antennadisposed in the upper portion of the chamberthrough the waveguide. The planar antennamay evenly radiate the microwaves to the dielectric plate. The microwaves may be transmitted to the dielectric plateto ionize the first process gas G, and the first plasma Pmay be formed below the dielectric plate. The first plasma Pmay include, for example, Ar ions, He ions, and electrons (illustrated as Pa).

1 2 10 2 123 2 50 52 2 50 2 1 140 1 2 1 2 2 2 2 2 4 2 2 After the first plasma Pis formed, a second process gas Gmay be supplied to the chamberto form a second plasma P(S). The second process gas Gmay be supplied by the lower gas ring. For example, the lower gas supply devicemay supply the second process gas Gto the lower gas ring. The second process gas Gmay be injected below the first plasma P(i.e., between the two-dimensional material layerand the first plasma P). The second process gas Gmay include a different material (illustrated as Pb) from the first process gas G. The second process gas Gmay include at least one of Dichlorosilane (DCS), N, CH, H, HCl, He, or Ar. For example, the second process gas Gmay include hydrogen (H), helium (He), and argon (Ar). The second process gas Gmay include an inert gas such as Ar or He, and a flow rate ratio of the inert gas and the hydrogen gas of the second process gas Gmay be 1:n (n is 1 to 10).

2 1 2 2 145 140 145 121 122 123 55 2 4 FIG.B The second process gas Gmay react with electrons formed from the first plasma P, and the second plasma Pmay be formed. The second plasma Pmay include an etchant, and the etchant may include, for example, hydrogen radicals. The hydrogen radicals may remove the residuefrom the surface of the two-dimensional material layer. The hydrogen radicals may remove carbon-containing residuesby physical and/or chemical methods. Operations S, Sand Smay be performed in a range of about 5 seconds to about 60 seconds, respectively. As described with reference to, the electrode ringmay apply an electric field to the second plasma P. Accordingly, the hydrogen radicals may be uniformly supplied across the entire semiconductor wafer W by the electric field.

Among plasma generation methods, there are provided a capacitively coupled plasma (CCP) method and an inductively coupled plasma (ICP) method depending on an RF power application method. The capacitively coupled method and the inductively coupled method may form high-density plasma in the chamber and apply excessive ion bombardment to an inner wall of the chamber or the substrate. Additionally, in the plasma formed by the inductively coupled method, it may be difficult to form and maintain a uniform plasma. Additionally, a remote plasma source (RPS) method for forming plasma outside the chamber in which processes such as deposition and etching are performed and supplying the plasma or components of the plasma into the chamber may find it difficult to uniformly supply radicals onto the substrate.

1 2 10 1 2 1 2 110 140 110 1 2 2 140 140 120 145 140 140 According to example embodiments, the first plasma Pand the second plasma Pmay be formed in the chamber, and because the first plasma Pand the second plasma Pare surface wave plasmas, the first plasma Pand the second plasma Pmay reduce damage to the substrateor the two-dimensional material layeron the substrate. For example, the first plasma Pmay be a high-density plasma with a high electron temperature, and the second plasma Pmay be a low-density plasma. Accordingly, hydrogen radicals included in the second plasma Pmay reduce damage to the two-dimensional material layer. For example, a volume change of the two-dimensional material layerdue to a removal process (S) of the residuemay be about 5.4%. Accordingly, it may be possible to prevent the deterioration of the electrical characteristics of the thin film, such as an increase in the contact resistance of the two-dimensional material layerdue to damage to the two-dimensional material layerand a voltage drop due to the contact resistance.

145 1 2 10 140 Additionally, as compared to the RPS method, the method of removing the residueaccording to example embodiments may form plasmas Pand Pin the chamber, so that the hydrogen radicals may be effectively transmitted onto the two-dimensional material layerand the process time may be shortened.

145 140 145 140 2 In the case of performing high-temperature treatment to remove the residuesuch as carbon impurities, there may be a concern that sulfur vacancy defects may occur in the two-dimensional material layersuch as MoS. However, because the method of removing the residueis performed at a relatively low temperature, it may be possible to prevent the sulfur vacancy defects and the deterioration of thin film properties of the two-dimensional material layer. For example, the process may be performed in a range of about 100 degrees Celsius to about 250 degrees Celsius.

2 10 10 10 110 140 145 140 2 10 3 A flow rate of the second process gas Gsupplied to the chambermay be in the range of about 10 standard cubic centimeters per minute (SCCM) to about 500 SCCM. In an example embodiment, the pressure in the chambermay be in the range of about 10 mTorr to about 500 mTorr. In an example embodiment, the pressure in the chambermay be in the range of about 50 mTorr to about 100 mTorr. According to example embodiments, on the substrate, for example, on the two-dimensional material layer, an electron temperature may be greater than 0 and less than about 2 eV. Accordingly, the residuemay be removed without damaging the two-dimensional material layer. The ion density of the second plasma Pmay be greater than 0 and less than about 10×10/cm.

6 FIG. is a cross-sectional view of a plasma processing device according to an example embodiment.

6 FIG. 1 80 80 110 110 120 145 70 80 Referring to, the plasma processing devicemay further include a sensor. The sensormay include a probe connected to the substrateand may measure ion density and electron temperature on the substrate. Hereinafter, results of measuring plasma and electron temperature in the removal process (S) of the residueusing the analyzerand the sensorwill be described.

7 FIG.A 7 FIG.B 70 10 70 140 120 145 10 145 140 andillustrate results of OES analysis. As described above, the OES analyzermeasures substances in the chamber, such as plasma. For example, the OES analyzermeasures substances removed from a surface of the two-dimensional material layerby the removal process (S) of the residueand scattered into the chamber, rather than the residueattached to the surface of the two-dimensional material layer.

7 FIG.A 7 FIG.A 3 5 FIGS.to 7 FIG.A 7 FIG.B 1 2 145 2 2 illustrates the results of detecting a substance in plasma in Comparative Example 1 and example embodiments. Referring to, in Comparative Example 1, plasma was formed on a silicon wafer on which deposition and etching processes were not performed, and analysis was performed on the plasma. In example embodiments, analysis was performed on the first and second plasmas Pand Pdescribed in. As illustrated in, a high peak was observed at a wavelength corresponding to carbon (C). Accordingly, as illustrated in, the wavelength corresponding to carbon (C) was measured over time to measure carbon impurities included in the residue.

7 FIG.B 7 FIG.B 1 1 145 140 1 2 2 3 140 145 2 Referring to, the first plasma Pwas formed at t. It was observed that the residueon the two-dimensional material layerwas partially removed by ions, electrons, and radicals included in the first plasma P. Then, the second plasma Pwas formed from tto t, and an etchant such as hydrogen radicals was supplied onto the two-dimensional material layer. As illustrated in, a larger amount of carbon (C) was observed in example embodiments than in Comparative Example 1, so that it may be seen that a relatively large amount of residuewas removed in example embodiments.

8 FIG.A 8 FIG.B illustrates a wafer map according to pressure change.illustrates a wafer map according to a flow rate change. The wafer map illustrates the distribution of ion density on the semiconductor wafer W. ‘Radial’ shows a distribution pattern in a radial direction of ion density, ‘planar’ shows an asymmetrical distribution pattern of ion density, and ‘residual’ shows a remaining distribution pattern excluding ‘radial’ and ‘planar.’ ‘Original’ shows a distribution pattern reflecting all of ‘radial,’ ‘planar’ and ‘residual.’ An electron temperature in all regions on the wafer is less than 2 eV.

8 8 FIGS.A andB 10 10 10 Referring to, it was observed that as the pressure in the chamberincreased and the flow rate in the chamberincreased, the electron temperature decreased and the radial dispersion decreased. Here, the flow rate may refer to the sum of flow rates of process gases provided in the chamber.

TABLE 1 Average ion density Average electron Pressure (mTorr) 10 3 (10/cm) temperature (eV) 15 38.6 10.42 20 35.4 9.12 30 29.8 6.99

10 10 10 3 10 3 10 3 10 3 10 3 10 3 10 3 10 3 10 3 Table 1 shows the ion density and electron temperature according to the pressure in the chamber. Referring to Table 1, as the pressure inside the chamberincreased, the ion density and electron temperature decreased. Specifically, when the pressure was 15 mTorr, the ion density (the number of ions per unit volume) was 36.9×10/cmto 40.55×10/cm, and an average was 38.6×10cm. The electron temperature was 9.89 eV to 11.31 eV, and an average was 10.42 eV. When the pressure was 20 mTorr, the ion density was 33.4×10/cmto 37.7×10/cm, and an average was 35.4×10/cm. The electron temperature was 8.19 eV to 10.03 eV, and an average was 9.12 eV. When the pressure is 30 mTorr, the ion density was 25.7×10/cmto 33.86×10/cm, and an average was 29.8×10/cm. The electron temperature was 5.57 eV to 8.49 eV, and an average was 6.99 eV.

TABLE 2 Ion density Electron Flow rate (SCCM) 10 3 (10/cm) temperature (eV) 15 36.6 9.5 20 34.8 8.81 30 34.3 8.7

10 10 10 3 10 3 10 3 10 3 10 3 10 3 10 3 10 3 10 3 Table 2 shows the ion density and electron temperature according to the flow rate inside the chamber. Referring to Table 2, as the flow rate of the process gas in the chamberincreased, the ion density and electron temperature decreased. Specifically, when the flow rate was 0 SCMM, the ion density was 35.1×10/cmto 39.2×10/cm, and an average was 36.6×10/cm. The electron temperature was 8.81 eV to 10.5 eV, and an average was 9.50 eV. When the flow rate was 20 SCCM, the ion density was 32.6×10/cmto 38.9×10/cm, and an average was 34.8×10/cm. The electron temperature was 7.92 eV to 10.44 eV, and an average was 8.81 eV. When the flow rate was 200 SCCM, the ion density was 32.7×10/cmto 37.0×10/cm, and an average was 34.3×10/cm. The electron temperature was 8.02 eV to 9.73 eV, and the average was 8.70 eV.

9 9 FIGS.A toC 9 9 FIGS.A andB 9 FIG.C illustrate results of measuring the electron temperature and the results of measuring the ion density.illustrate a change in the electron temperature according to the pressure depending on the output of the microwaves.illustrates the ion density according to the pressure depending on the output of the microwaves.

9 9 FIGS.A andB 10 145 140 Referring to, the electron temperature decreases as the pressure inside the chamberincreases. For example, as the pressure increases, the electron temperature decreases below 2 eV. At an electron temperature of about 2 eV or less, the residuemay be effectively removed without damaging the two-dimensional material layer. Additionally, it was observed that the electron temperature decreased as the output of the microwave increased.

9 FIG.C 10 145 140 10 3 Referring to, the ion density decreases as the pressure in the chamberincreases. For example, as the pressure increases, the ion density becomes lower than 10 eV. At an ion density of about 10×10/cmor less, the residuemay be effectively removed without damaging the two-dimensional material layer. Additionally, it was observed that the ion density decreased as the output of the microwaves increased.

10 10 FIGS.A andB 10 FIG.A 10 FIG.B 10 10 FIGS.A andB 10 10 FIGS.A andB illustrate a surface of a two-dimensional material according to a comparative example and example embodiments.illustrates a two-dimensional material layer according to a comparative example, andillustrates a two-dimensional material layer according to an example embodiment. Upper portions ofillustrate a surface of the two-dimensional material layer captured with a scanning electron microscope (SEM). Lower portions ofillustrate a surface of the two-dimensional material layer captured with a phase shifting interferometer.

10 FIG.A 10 FIG.B 120 120 Referring to, when the removal process (S) of the residue was not performed in Comparative Example 2, it was observed that the two-dimensional material layer was covered with the residue. Referring to, the residue was removed by the removal process (S) of the residue, and one or two two-dimensional material layers were observed.

11 11 FIGS.A andB 11 FIG.A 11 FIG.B 2g 2 1g 2 illustrate Raman spectra of the two-dimensional material layers according to example embodiments and a comparative example. Specifically,illustrates results of Raman spectrum analysis of the two-dimensional material layer in example embodiments, andillustrates results of Raman spectrum analysis of the two-dimensional material layer in the comparative example. Erepresents a peak of MoSin an in-plane mode, and Arepresents a peak of MoSin an out-of-plane mode. An Si peak represents silicon included in the substrate.

11 FIG.A 2 2 2 120 120 120 120 Referring to, according to example embodiments, it was observed that the peak of MoSbarely changed before and after performing the removal process (S) of the residue. In example embodiments, the removal process (S) of the residue was performed in a range in which the electron temperature on the surface of the two-dimensional material layer was less than 2 eV. A volume change of the two-dimensional material layer, MoS, due to the removal process (S) of the residue, was within about 5.4%. That is, damage to MoSmay be prevented during the removal process (S) of the residue.

11 FIG.B 11 FIG.A 2 2 120 120 Referring to, it was observed that a peak change of MoSwas relatively large before and after performing the removal process (S) of the residue in Comparative Example 3. In Comparative Example 3, the electron temperature on the surface of the two-dimensional material layer was performed in a range in which the removal process (S) of the residue was greater than 2 eV. In contrast to, it was observed that significant damage to MoSoccurred in Comparative Example 3.

While aspects of example embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.