Semiconductor Device and Insulating Switch

The present invention claims priority under 35 U.S.C. § 119 to Japanese Patent Application No. 2024-186555, filed on Oct. 23, 2024, the entire contents of which are incorporated herein by reference.

The present disclosure relates to a semiconductor device and an insulating switch.

In the related art, there is known a bidirectional switch in which a source of a first MOSFET and a source of a second MOSFET are connected to each other. The bidirectional switch includes a first drain terminal connected to a drain electrode of the first MOSFET, a first gate terminal connected to a gate electrode of the first MOSFET, a second drain terminal connected to a drain electrode of the second MOSFET, a second gate terminal connected to a gate electrode of the second MOSFET, and a common source terminal to which a source electrode of the first MOSFET and a source electrode of the second MOSFET are connected.

Hereinafter, several embodiments of a semiconductor device of the present disclosure will be described with reference to the accompanying drawings. For the sake of simplicity and clarity of description, components shown in the drawings are not necessarily drawn on a constant scale. In addition, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings are merely illustrative of embodiments of the present disclosure and should not be considered as limiting the present disclosure.

The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. The detailed description is merely explanatory in nature and is not intended to limit the embodiments of the present disclosure or application and uses of such embodiments.

The terms “first,” “second,” “third,” and the like used in the present disclosure are merely used to label and are not necessarily intended to assign any order to their objects. The term “at least one” used in the present disclosure means “one or more” of the desired options. As an example, the term “at least one” used in the present disclosure means “only one option” or “both of two options” if the number of options is two. As another example, the term “at least one” used in the present disclosure means “only one option” or “any combination of two or more options” if the number of options is three or more.

800 10 800 1 FIG. 1 FIG. A schematic configuration of an insulating switchincluding a semiconductor deviceaccording to a first embodiment will be described with reference to.shows the schematic configuration of the insulating switch.

800 800 2 810 800 821 822 10 821 1 10 1 822 1 810 10 1 FIG. The insulating switchshown inmay be mounted on a device such as a sequencer. The insulating switchmay be used as a switch for switching on and off a circuit that supplies a driving voltage VDto a load. In one example, the insulating switchincludes a power supply circuitand a signal generation circuit, which are electrically connected to a semiconductor device. The power supply circuitis configured to supply an operating voltage VDto the semiconductor device. The operating voltage VDis, for example, a direct current voltage. The signal generation circuitis configured to output a control signal Sfor controlling the loadto the semiconductor device.

800 821 822 800 821 822 800 800 1 FIG. The configuration of the insulating switchis not limited to the example shown inand may be changed arbitrarily. In one example, at least one of the power supply circuitor the signal generation circuitmay be provided outside the insulating switch. In this case, between the power supply circuitand the signal generation circuit, a circuit provided outside the insulating switchis electrically connected to the insulating switch.

10 1 810 810 10 11 16 The semiconductor deviceis configured to switch, in response to the control signal S, between a state (on state) in which a current flows through the loadand a state (off state) in which no current flows through the load. The semiconductor deviceincludes first to sixth terminalsto.

11 12 810 810 11 12 810 811 812 810 1 FIG. The first terminaland the second terminalare terminals configured to be electrically connectable to the load. That is, the loadis connected to the first terminalor the second terminalaccording to a usage mode of the load. In, a first loadand a second loadare shown as the load.

10 50 11 12 811 800 811 11 831 2 811 12 832 2 832 2 831 832 811 832 2 2 50 11 12 The semiconductor deviceincludes a switch circuitconnected between the first terminaland the second terminal. The first loadindicates a load connected to the insulating switchto be driven in a sink mode as an example of a usage form. The first loadis electrically connected between the first terminaland a high potential terminalthat supplies the driving voltage VDto the first load. The second terminalis connected to a low potential terminalthat has a lower potential than the driving voltage VD. The low potential terminalmay be a reference terminal that serves as a reference potential for the driving voltage VD. The high potential terminaland the low potential terminalmay be terminals or cables of a power source that supplies electric power for operating the first load. The low potential terminalmay be, for example, a ground terminal. The driving voltage VDis, for example, 36 V. A reference voltage is, for example, 0 V. Each of the driving voltage VDand the reference voltage may be changed as appropriate. When the switch circuitis in an on state, a current flows from the first terminalto the second terminal.

812 800 812 11 832 12 831 2 50 12 11 The second loadindicates a load connected to the insulating switchto be driven in a source mode, as an example of another usage form. The second loadis connected between the first terminaland the low potential terminal. The second terminalis connected to the high potential terminalthat supplies the driving voltage VD. When the switch circuitis in an on state, a current flows from the second terminalto the first terminal.

13 14 15 821 16 822 The third terminalis, for example, in an electrically floating state. The fourth terminaland the fifth terminalare terminals configured to be electrically connectable to the power supply circuit. The sixth terminalis a terminal configured to be electrically connectable to the signal generation circuit.

10 20 30 40 50 20 14 16 20 821 822 20 30 20 50 20 30 The semiconductor deviceincludes a drive circuit, an insulating circuit, a control circuit, and the above-mentioned switch circuit. The drive circuitis electrically connected to the fourth to sixth terminalsto. That is, the drive circuitis electrically connectable to the power supply circuitand the signal generation circuit. The drive circuitis electrically connected to the insulating circuit. The drive circuitis configured to generate a pulse signal SP for controlling the switch circuit. The drive circuitis configured to output the pulse signal SP to the insulating circuit.

20 21 22 21 821 822 22 821 21 The drive circuitmay include, for example, a pulse signal generation circuitand an oscillation circuit. The pulse signal generation circuitis electrically connected to both the power supply circuitand the signal generation circuit. The oscillation circuitis electrically connected to both the power supply circuitand the pulse signal generation circuit.

22 22 22 21 1 30 800 The oscillation circuitis configured to output a clock signal CLK. The clock signal CLK may be, for example, a square wave. The clock signal CLK has a predetermined frequency and a predetermined duty. The oscillation circuitmay be configured to change the frequency of the clock signal CLK. The oscillation circuitmay also be configured to output and stop the clock signal CLK by, for example, an enable signal. The pulse signal generation circuitis configured to generate the pulse signal SP based on the clock signal CLK and the control signal S, and to output the pulse signal SP to the insulating circuit. The clock signal CLK may be supplied from outside of the insulating switch.

30 20 40 30 31 31 32 33 32 21 20 20 32 33 40 31 33 21 32 32 33 The insulating circuitis electrically connected to the drive circuitand the control circuit. The insulating circuitincludes a transformer. The transformerincludes a first coiland a second coil. The first coilis electrically connected to the pulse signal generation circuitof the drive circuit. Therefore, it can be said that the drive circuitis configured to output a pulse signal to the first coil. The second coilis electrically connected to the control circuit. The transformeris configured to cause an induced current to flow through the second coilby the pulse signal SP supplied from the pulse signal generation circuitto the first coil. Here, the first coilis an example of a “first insulating element,” and the second coilis an example of a “second insulating element.”

40 50 40 50 40 41 42 The control circuitis electrically connected to the switch circuit. The control circuitis configured to control driving the switch circuit. The control circuitincludes a rectifier circuitand a gate voltage control circuit.

41 33 31 41 The rectifier circuitis configured to rectify the induced current flowing through the second coilof the transformer. The rectifier circuitmay include, for example, a plurality of diodes that rectify the induced current. Each of the plurality of diodes may be formed by, for example, a diode-connected transistor.

42 50 42 2 50 41 2 50 42 The gate voltage control circuitis electrically connected to the switch circuit. The gate voltage control circuitis configured to generate a drive signal Sfor controlling the switch circuitbased on a current from the rectifier circuit, and to output the drive signal Sto the switch circuit. In one example, the gate voltage control circuitmay include circuit elements such as a transistor, a capacitor, and a resistor.

50 11 13 50 50 51 52 51 52 51 52 The switch circuitis electrically connected to each of the first to third terminalsto. The switch circuitmay be formed by a bidirectional switch. In one example, the switch circuithas a configuration in which a first transistorand a second transistorare connected in series. The transistorsandare high electron mobility transistors (HEMTs) including nitride semiconductors. In one example, each of the first transistorand the second transistoris formed by a normally-off GaN HEMT.

51 52 51 52 42 51 52 51 52 42 42 51 52 51 52 51 11 52 12 51 52 11 12 Each of the first transistorand the second transistorincludes a source, a drain, and a gate. The gates of the transistorsandare electrically connected to the gate voltage control circuit. The sources of the transistorsandare electrically connected to each other. The sources of the transistorsandare electrically connected to the gate voltage control circuit. That is, the gate voltage control circuitis electrically connected to each of the gates of the transistorsandand each of the sources of the transistorsand. The drain of the first transistoris electrically connected to the first terminal. The drain of the second transistoris electrically connected to the second terminal. Therefore, the first transistorand the second transistorare connected in series between the first terminaland the second terminal.

51 52 51 52 51 52 51 52 51 52 The first transistorand the second transistor, which are formed by GaN HEMTs, include a substrate. The substrate of the first transistorand the second transistormay be, for example, a silicon (Si) substrate. The substrate of the first transistorand the second transistormay be an integrated single substrate. The substrate may be applied with a source potential of the first transistorand the second transistor. In one example, the substrate is electrically connected to the sources of the first transistorand the second transistor.

800 21 1 822 22 32 30 33 30 41 33 42 2 41 41 33 42 2 51 52 50 41 2 2 51 52 50 2 51 52 51 52 50 50 810 811 832 50 810 811 In the insulating switchhaving the above-mentioned configuration, the pulse signal SP, which is generated by the pulse signal generation circuitbased on the control signal Sfrom the signal generation circuitand the clock signal CLK from the oscillation circuit, is supplied to the first coilof the insulating circuit. Thus, an induced current corresponding to the pulse signal SP is generated in the second coilof the insulating circuit. The rectifier circuitrectifies the induced current flowing through the second coilto generate a DC voltage. The gate voltage control circuitgenerates the drive signal Sby the DC voltage of the rectifier circuit. In one example, the rectifier circuitrectifies the induced current from the second coilto generate a desired DC voltage. The DC voltage is, for example, 6 V or more and 7 V or less. The gate voltage control circuitgenerates the drive signal S, which has a voltage corresponding to the control of the first transistorand the second transistorof the switch circuit, using the DC voltage from the rectifier circuit. The voltage of the drive signal Smay be 5 V or more and 5.5 V or less, for example, 5.25 V. The drive signal Sis supplied to the gates of the first transistorand the second transistorof the switch circuit. Therefore, when the drive signal Sbecomes higher than a threshold voltage of the first transistorand the second transistor, the first transistorand the second transistorare turned on. As a result, the switch circuitis electrically conducted. By the electrically conducted switch circuit, a current flows from the load(load) to the low potential terminalvia the switch circuit, and the load(load) is driven.

33 41 42 42 41 2 51 52 When the DC voltage obtained by rectifying the induced current from the second coilby the rectifier circuitis less than a gate threshold value, the gate voltage control circuitmay include a step-up circuit that steps the DC voltage up. In other words, the gate voltage control circuitmay be configured to step up the DC voltage from the rectifier circuitto generate the drive signal Sof a voltage required to turn the first transistorand the second transistoron.

10 10 10 120 10 2 FIG. 3 FIG. 2 FIG. 3 FIG. 2 FIG. An overall configuration of the semiconductor deviceof the first embodiment will be described with reference toand.shows a schematic internal plan-view structure of the semiconductor device.shows a schematic cross-sectional structure of the semiconductor devicetaken along an XZ plane. In, a sealing resin, which will be described later, is indicated by a two-dot chain line for the convenience of explaining the internal structure of the semiconductor device.

10 In the present disclosure, components may be described based on mutually orthogonal X, Y, and Z axes indicated in the drawings. Here, a direction along the X axis is referred to as an “X direction,” a direction along the Y axis is referred to as a “Y direction,” and a direction along the Z axis is referred to as a “Z direction.” In addition, the term “plan view” used in the present disclosure refers to viewing the semiconductor devicein the Z direction.

2 FIG. 3 FIG. 10 10 60 70 80 90 As shown inand, the semiconductor deviceis a semiconductor device in which a plurality of semiconductor chips are packaged together. In the first embodiment, the semiconductor deviceincludes, as the semiconductor chips, a drive circuit chip, an insulating chip, a control circuit chip, and a switch circuit chip.

10 10 A package format of the semiconductor deviceis a small outline (SO) type, and is, for example, a small outline package (SOP). The package format of the semiconductor devicemay be changed arbitrarily. The package format is not limited to the SOP, and may be a quad for non-lead package (QFN), a dual flat package (DFP), a dual inline package (DIP), a quad flat package (QFP), a single inline package (SIP), a small outline J-leaded package (SOJ), or various package structures similar to these packages.

10 100 110 120 60 110 70 110 80 100 90 100 In the first embodiment, the semiconductor deviceincludes a first support, a second support, and the sealing resin. The drive circuit chipis mounted on the second support. In one example, the insulating chipis mounted on the second support. The control circuit chipis mounted on the first support. The switch circuit chipis mounted on the first support.

120 120 120 121 122 121 121 122 120 123 126 121 122 123 124 120 125 126 120 3 FIG. 2 FIG. The sealing resinis formed of a resin material having electrical insulating properties. The resin material may be, for example, a resin containing an epoxy resin. The resin material may be colored black or the like. The sealing resinmay be in the form of a flat plate with a thickness direction thereof being the Z direction. As shown in, the sealing resinincludes a sealing upper surfaceand a sealing lower surfaceopposite the sealing upper surface. The sealing upper surfaceand the sealing lower surfaceare provided at positions spaced apart from each other in the Z direction. The sealing resinincludes four sealing side surfacesto(see) that connect the sealing upper surfaceand the sealing lower surface. The sealing side surfacesandconstitute both end surfaces of the sealing resinin the X direction. The sealing side surfacesandconstitute both end surfaces of the sealing resinin the Y direction.

100 110 100 110 100 110 120 100 110 100 124 110 Each of the first supportand the second supporthas electrical conductivity. The supportsandare formed of a material including Cu (copper), Fe (iron), Al (aluminum), and the like. The first supportand the second supportare provided over both an inside and an outside of the sealing resin. The first supportand the second supportare disposed to be spaced apart from each other in the X direction. The first supportis disposed closer to the sealing side surfacethan the second support.

2 FIG. 1 FIG. 1 FIG. 1 FIG. 100 101 120 102 104 120 102 11 103 12 104 13 As shown in, the first supportincludes a first die paddisposed inside the sealing resin, and a plurality of first to third terminalstodisposed across the inside and outside of the sealing resin. The first terminalconstitutes the first terminalshown in, the second terminalconstitutes the second terminalshown in, and the third terminalconstitutes the third terminalshown in.

80 90 101 101 120 101 101 Both the control circuit chipand the switch circuit chipare mounted on the first die pad. In one example, the first die padis not exposed from the sealing resin. The first die padhas a flat plate shape with a thickness direction thereof being the Z direction. In one example, the first die padhas a rectangular shape in a plan view with long sides thereof extending in the X direction and short sides thereof extending in the Y direction.

102 104 110 101 102 104 104 102 103 101 104 102 103 102 104 124 120 102 103 101 104 101 The first to third terminalstoare disposed on an opposite side of the second supportin the X direction with respect to the first die pad. The first to third terminalstoare disposed to be spaced apart from one another in the Y direction. The third terminalis disposed on a side where the first terminaland the second terminalare disposed with respect to the first die pad. The third terminalis disposed between the first terminaland the second terminalin the Y direction. Portions of the first to third terminalstoprotrude from the sealing side surfacetoward the outside of the sealing resin. Each of the first terminaland the second terminalis disposed to be spaced apart from the first die pad. The third terminalis integrated with the first die pad.

110 111 120 112 114 120 112 14 113 15 114 16 1 FIG. 1 FIG. 1 FIG. The second supportincludes a second die paddisposed inside the sealing resin, and a plurality of fourth to sixth terminalstodisposed across the inside and outside of the sealing resin. The fourth terminalconstitutes the fourth terminalshown in, the fifth terminalconstitutes the fifth terminalshown in, and the sixth terminalconstitutes the sixth terminalshown in.

111 101 60 70 111 111 120 111 111 The second die padis disposed to be spaced apart from the first die padin the X direction. Both the drive circuit chipand the insulating chipare mounted on the second die pad. In one example, the second die padis not exposed from the sealing resin. The second die padhas a flat plate shape with a thickness direction thereof being the Z direction. In one example, the second die padhas a rectangular shape in a plan view with long sides thereof extending in the X direction and short sides thereof extending in the Y direction.

112 114 100 111 112 114 112 114 123 120 112 114 111 113 111 113 126 112 114 114 112 113 The fourth to sixth terminalstoare disposed on an opposite side of the first supportin the X direction with respect to the second die pad. The fourth to sixth terminalstoare disposed to be spaced apart from one another in the Y direction. Portions of the fourth to sixth terminalstoprotrude from the sealing side surfacetoward the outside of the sealing resin. Each of the fourth terminaland the sixth terminalis disposed to be spaced apart from the second die pad. The fifth terminalis integrated with the second die pad. The fifth terminalis disposed closer to the sealing side surfacethan the fourth terminaland the sixth terminal. The sixth terminalis disposed between the fourth terminaland the fifth terminalin the Y direction.

2 FIG. 3 FIG. 60 70 80 90 70 80 60 90 70 60 80 As shown inand, the drive circuit chip, the insulating chip, the control circuit chip, and the switch circuit chipare disposed to be spaced apart from one another in the X direction. Both the insulating chipand the control circuit chipare disposed between the drive circuit chipand the switch circuit chipin the X direction. The insulating chipis disposed between the drive circuit chipand the control circuit chipin the X direction.

60 20 60 21 22 60 60 60 111 1 FIG. 1 FIG. The drive circuit chipincludes the drive circuitshown in. More specifically, the drive circuit chipincludes the pulse signal generation circuitand the oscillation circuitshown in. The drive circuit chiphas a flat plate shape with a thickness direction thereof being the Z direction. The drive circuit chiphas a rectangular shape having short and long sides in a plan view. The drive circuit chipis mounted on the second die padwith the long sides thereof extending along the Y direction and the short sides thereof extending along the X direction, for example.

3 FIG. 60 111 4 60 60 60 60 60 4 4 As shown in, the drive circuit chipis bonded to the second die padby a fourth conductive bonding material SD. The drive circuit chiphas a fourth chip front surfaceS and a fourth chip rear surfaceR opposite the fourth chip front surfaceS. The fourth chip rear surfaceR is in contact with the fourth conductive bonding material SD. As the fourth conductive bonding material SD, for example, at least one of solder paste, silver (Ag) paste, Cu paste, or gold (Au) paste may be used.

60 61 62 61 61 60 62 60 The drive circuit chipincludes a fourth semiconductor substrateand a fourth insulatorprovided over the fourth semiconductor substrate. The fourth semiconductor substrateincludes the fourth chip rear surfaceR. The fourth insulatorincludes the fourth chip front surfaceS.

61 61 61 61 61 61 61 20 21 22 61 62 61 61 62 61 The fourth semiconductor substratehas a flat plate shape with a thickness direction thereof being the Z direction. The fourth semiconductor substrateis formed of, for example, a material containing Si. In one example, a Si substrate may be used for the fourth semiconductor substrate. Instead of the Si substrate, a silicon carbide (SiC) substrate or a gallium nitride (GaN) substrate may be used for the fourth semiconductor substrate. A fourth semiconductor layerA epitaxially grown from the fourth semiconductor substrateis provided over the fourth semiconductor substrate. The drive circuit(the pulse signal generation circuitand the oscillation circuit) is provided in the fourth semiconductor layerA. The fourth insulatoris provided over the fourth semiconductor layerA. In other words, the fourth semiconductor layerA is provided between the fourth insulatorand the fourth semiconductor substrate.

62 61 62 2 The fourth insulatoris provided over an entirety of the fourth semiconductor layerA in a plan view, for example. The fourth insulatormay include an insulating layer containing at least one of silicon oxide (SiO) or silicon nitride (SiN), and a protective layer provided over the insulating layer. The protective layer may be formed of, for example, polyimide (PI).

2 FIG. 3 FIG. 60 63 63 63 63 62 63 63 62 63 63 62 63 63 63 63 63 63 22 63 63 21 63 63 60 112 114 63 63 60 70 As shown in, the drive circuit chipincludes first to fifth padsA toE. The first to fifth padsA toE are provided in the fourth insulator(see). The first to fifth padsA toE are exposed from the fourth insulatorin a plan view. More specifically, the first to fifth padsA toE are provided over the insulating layer of the fourth insulator. The protective layer is provided to partially cover the first to fifth padsA toE. Therefore, the first to fifth padsA toE include portions exposed from the protective layer in a plan view. The first padA and the second padB are electrically connected to the oscillation circuit. The third to fifth padsC toE are electrically connected to the pulse signal generation circuit. The first to third padsA toC are provided in the fourth chip front surfaceS and disposed closer to the fourth to sixth terminalstoin a plan view. The fourth padD and the fifth padE are provided in the fourth chip front surfaceS and disposed closer to the insulating chipin a plan view.

70 31 70 70 70 111 1 FIG. The insulating chipincludes the transformershown in. The insulating chiphas a flat plate shape with a thickness direction thereof being the Z direction. The insulating chiphas a rectangular shape having short and long sides in a plan view. The insulating chipis mounted on the second die padwith the long sides thereof extending along the Y direction and the short sides thereof extending along the X direction, for example.

3 FIG. 70 111 3 70 70 70 70 70 3 3 As shown in, the insulating chipis bonded to the second die padby a third conductive bonding material SD. The insulating chipincludes a third chip front surfaceS and a third chip rear surfaceR opposite the third chip front surfaceS. The third chip rear surfaceR is in contact with the third conductive bonding material SD. The third conductive bonding material SDmay be at least one of solder paste, Ag paste, Cu paste, or Au paste.

70 71 72 71 73 73 71 70 72 70 2 FIG. The insulating chipincludes a third semiconductor substrate, a third insulatorprovided over the third semiconductor substrate, and first to fourth padsA toD (see). The third semiconductor substrateincludes the third chip rear surfaceR. The third insulatorincludes the third chip front surfaceS.

71 71 71 71 The third semiconductor substratehas a flat plate shape with a thickness direction thereof being the Z direction. The third semiconductor substrateis formed of a material containing Si, for example. In one example, a Si substrate may be used for the third semiconductor substrate. Instead of the Si substrate, a SiC substrate may be used for the third semiconductor substrate.

2 FIG. 3 FIG. 73 73 72 73 73 72 73 73 32 31 73 73 70 60 73 73 33 31 73 73 70 As shown in, the first to fourth padsA toD are provided in the third insulator(see). The first to fourth padsA toD are exposed from the third insulatorin a plan view. The first padA and the second padB are electrically connected to the first coilof the transformer. The first padA and the second padB are provided in the third chip front surfaceS and disposed closer to the drive circuit chip. The third padC and the fourth padD are electrically connected to the second coilof the transformer. The third padC and the fourth padD are disposed at a center of the third chip front surfaceS in the X direction.

80 40 40 90 80 80 80 101 1 FIG. The control circuit chipincludes the control circuitshown in. The control circuitis configured to control driving the switch circuit chip. The control circuit chiphas a flat plate shape with a thickness direction thereof being the Z direction. The control circuit chiphas a rectangular shape having short and long sides in a plan view. The control circuit chipis mounted on the first die pad, for example, with the long sides thereof extending in the Y direction and the short sides thereof extending in the X direction.

3 FIG. 80 101 2 80 80 80 80 80 2 2 As shown in, the control circuit chipis bonded to the first die padby a second conductive bonding material SD. The control circuit chiphas a second chip front surfaceS and a second chip rear surfaceR opposite the second chip front surfaceS. The second chip rear surfaceR is in contact with the second conductive bonding material SD. The second conductive bonding material SDmay be at least one of solder paste, Ag paste, Cu paste, or Au paste.

80 81 82 81 81 80 82 80 81 101 2 The control circuit chipincludes a second semiconductor substrateand a second insulatorprovided over the second semiconductor substrate. The second semiconductor substrateincludes the second chip rear surfaceR. The second insulatorincludes the second chip front surfaceS. The second semiconductor substrateis electrically connected to the first die padby the second conductive bonding material SD.

81 81 81 81 81 81 81 40 41 42 81 82 81 81 82 81 The second semiconductor substratehas a flat plate shape with a thickness direction thereof being the Z direction. The second semiconductor substrateis formed of a material containing Si, for example. In one example, a Si substrate may be used for the second semiconductor substrate. Instead of the Si substrate, a SiC substrate may be used for the second semiconductor substrate. A second semiconductor layerA epitaxially grown from the second semiconductor substrateis provided over the second semiconductor substrate. The control circuit(the rectifier circuitand the gate voltage control circuit) is provided in the second semiconductor layerA. The second insulatoris provided over the second semiconductor layerA. In other words, the second semiconductor layerA is provided between the second insulatorand the second semiconductor substrate.

82 81 82 2 The second insulatoris provided over an entirety of the second semiconductor layerA in a plan view, for example. The second insulatormay include an insulating layer containing at least one of SiOor SiN, and a protective layer provided over the insulating layer. The protective layer may be formed of, for example, PI.

2 FIG. 3 FIG. 80 83 83 83 83 82 83 83 82 73 73 41 40 83 83 80 70 83 83 42 40 83 83 80 90 As shown in, the control circuit chipincludes first to fourth padsA toD. The first to fourth padsA toD are provided in the second insulator(see). The first to fourth padsA toD are exposed from the second insulatorin a plan view. The first padA and the second padB are electrically connected to the rectifier circuitof the control circuit. The first padA and the second padB are provided in the second chip front surfaceS and disposed closer to the insulating chip. The third padC and the fourth padD are electrically connected to the gate voltage control circuitof the control circuit. The third padC and the fourth padD are provided in the second chip front surfaceS and disposed closer to the switch circuit chip.

90 50 90 90 90 101 1 FIG. The switch circuit chipincludes the switch circuitshown in. The switch circuit chiphas a flat plate shape with a thickness direction thereof being the Z direction. The switch circuit chiphas a rectangular shape having short and long sides in a plan view. The switch circuit chipis mounted on the first die padwith the long sides thereof extending along the Y direction and the short sides thereof extending along the X direction, for example.

3 FIG. 90 101 1 90 90 90 90 90 1 1 As shown in, the switch circuit chipis bonded to the first die padby a first conductive bonding material SD. The switch circuit chiphas a first chip front surfaceS and a first chip rear surfaceR opposite the first chip front surfaceS. The first chip rear surfaceR is in contact with the first conductive bonding material SD. The first conductive bonding material SDmay be at least one of solder paste, Ag paste, Cu paste, or Au paste.

90 91 51 52 98 91 93 93 91 90 98 90 91 101 1 The switch circuit chipincludes a first semiconductor substratecorresponding to the substrates of the first transistorand the second transistordescribed above, a first insulatorprovided over the first semiconductor substrate, and first to fourth padsA toD. The first semiconductor substrateincludes the first chip rear surfaceR. The first insulatorincludes the first chip front surfaceS. The first semiconductor substrateis electrically connected to the first die padby the first conductive bonding material SD.

91 81 1 101 2 Therefore, the first semiconductor substrateis electrically connected to the second semiconductor substratevia the first conductive bonding material SD, the first die pad, and the second conductive bonding material SD.

91 91 91 91 The first semiconductor substratehas a flat plate shape with a thickness direction thereof being the Z direction. The first semiconductor substrateis formed of a material containing Si, for example. In one example, a Si substrate may be used for the first semiconductor substrate. Instead of the Si substrate, a SiC substrate may be used for the first semiconductor substrate.

93 93 98 93 93 98 93 51 52 93 51 52 51 52 93 93 90 80 93 51 93 52 93 93 90 102 104 90 1 FIG. The first to fourth padsA toD are provided in the first insulator. The first to fourth padsA toD are exposed from the first insulatorin a plan view. The first padA is electrically connected to the gates of the first transistorand the second transistorshown in. The second padB is electrically connected to a node ND between the source of the first transistorand the source of the second transistor, and to the substrates of the first transistorand the second transistor. The first padA and the second padB are provided in the first chip front surfaceS and disposed closer to the control circuit chip. The third padC is electrically connected to the drain of the first transistor. The fourth padD is electrically connected to the drain of the second transistor. The third padC and the fourth padD are provided in the first chip front surfaceS and disposed closer to the first to third terminalsto. An internal configuration of the switch circuit chipwill be described later.

60 70 80 90 10 1 11 1 11 1 11 120 2 FIG. 2 FIG. Next, an electrical connection configuration among the drive circuit chip, the insulating chip, the control circuit chip, and the switch circuit chipwill be described with reference to. As shown in, the semiconductor deviceincludes first to eleventh wires Wto Was the electrical connection configuration. The first to eleventh wires Wto Ware, for example, bonding wires, and are formed of a material including Au, Al, Cu, Ag, and the like. The first to eleventh wires Wto Ware sealed by the sealing resin.

1 3 63 63 60 112 114 1 63 112 2 63 113 3 63 114 63 112 63 113 22 21 112 113 63 114 21 114 1 FIG. The first to third wires Wto Wconnect the first to third padsA toC of the drive circuit chipto the fourth to sixth terminalsto, respectively. The first wire Wconnects the first padA and the fourth terminalto each other, the second wire Wconnects the second padB and the fifth terminalto each other, and the third wire Wconnects the third padC and the sixth terminalto each other. Thus, the first padA is electrically connected to the fourth terminal, and the second padB is electrically connected to the fifth terminal. That is, both the oscillation circuitand the pulse signal generation circuit(see) are electrically connected to the fourth terminaland the fifth terminal. In addition, the third padC is electrically connected to the sixth terminal. That is, the pulse signal generation circuitis electrically connected to the sixth terminal.

4 5 60 70 4 5 63 63 60 73 73 70 4 63 73 5 63 73 63 73 63 73 21 32 31 1 FIG. The fourth wire Wand the fifth wire Welectrically connect the drive circuit chipand the insulating chip. More specifically, the fourth wire Wand the fifth wire Wconnect the fourth padD and the fifth padE of the drive circuit chipto the first padA and the second padB of the insulating chip, respectively. The fourth wire Wconnects the fourth padD and the first padA to each other, and the fifth wire Wconnects the fifth padE and the second padB to each other. Thus, the fourth padD and the first padA are electrically connected to each other, and the fifth padE and the second padB are electrically connected to each other. That is, the pulse signal generation circuitand the first coilof the transformer(see) are electrically connected to each other.

6 7 70 80 6 7 73 73 70 83 83 80 6 73 83 7 73 83 73 83 73 83 33 31 41 1 FIG. The sixth wire Wand the seventh wire Welectrically connect the insulating chipand the control circuit chip. More specifically, the sixth wire Wand the seventh wire Wconnect the third padC and the fourth padD of the insulating chipto the first padA and the second padB of the control circuit chip, respectively. The sixth wire Wconnects the third padC and the first padA to each other, and the seventh wire Wconnects the fourth padD and the second padB to each other. Thus, the third padC and the first padA are electrically connected to each other, and the fourth padD and the second padB are electrically connected to each other. That is, the second coilof the transformerand the rectifier circuit(see) are electrically connected to each other.

8 9 83 83 80 93 93 90 8 83 93 9 83 93 83 93 83 93 42 51 52 42 51 52 1 FIG. The eighth wire Wand the ninth wire Wconnect the third padC and the fourth padD of the control circuit chipto the first padA and the second padB of the switch circuit chip, respectively. The eighth wire Wconnects the third padC and the first padA to each other, and the ninth wire Wconnects the fourth padD and the second padB to each other. Thus, the third padC and the first padA are electrically connected to each other, and the fourth padD and the second padB are electrically connected to each other. That is, the gate voltage control circuitshown inis electrically connected to the gates of the first transistorand the second transistor. In addition, the gate voltage control circuitis electrically connected to the source of the first transistorand the source of the second transistor.

10 11 93 93 90 102 103 10 93 102 11 93 103 51 102 52 103 The tenth wire Wand the eleventh wire Wconnect the third padC and the fourth padD of the switch circuit chipto the first terminaland the second terminal, respectively. The tenth wire Wconnects the third padC and the first terminalto each other, and the eleventh wire Wconnects the fourth padD and the second terminalto each other. Thus, the drain of the first transistoris electrically connected to the first terminal, and the drain of the second transistoris electrically connected to the second terminal.

93 90 93 93 93 83 80 83 10 11 8 9 6 7 4 5 112 113 114 1 3 Here, the first padA of the switch circuit chipcorresponds to a “first input pad,” the second padB corresponds to a “second input pad,” the third padC corresponds to a “first power supply pad,” and the fourth padD corresponds to a “second power supply pad.” The third padC of the control circuit chipcorresponds to a “first output pad,” and the fourth padD corresponds to a “second output pad.” The tenth wire Wcorresponds to a “first power supply connector,” and the eleventh wire Wcorresponds to a “second power supply connector.” The eighth wire Wcorresponds to a “first connector,” and the ninth wire Wcorresponds to a “second connector.” The sixth wire Wand the seventh wire Wcorrespond to a “relay connector.” The fourth wire Wand the fifth wire Wcorrespond to an “intermediate connector.” The fourth terminalcorresponds to a “power supply terminal,” the fifth terminalcorresponds to a “ground terminal,” and the sixth terminalcorresponds to a “signal terminal.” The first wire Wcorresponds to a “power supply connector,” and the third wire Wcorresponds to a “signal connector.”

70 70 73 73 70 73 73 4 7 72 71 71 72 4 FIG. 5 FIG. 4 FIG. 2 FIG. 5 FIG. 2 FIG. 4 FIG. 5 FIG. The internal structure of the insulating chipwill be described with reference toand.shows a schematic cross-sectional structure of the insulating chiptaken along the XZ plane passing through the first padA and the third padC in, andshows a schematic cross-sectional structure of the insulating chiptaken along the XZ plane passing through the second padB and the fourth padD in. For the sake of convenience, the fourth to seventh wires Wto Ware omitted inand. Further, in order to ease understanding of the drawings, a thickness of the third insulatoris shown to be larger than a thickness of the third semiconductor substrate. Actually, the thickness of the third semiconductor substrateis larger than the thickness of the third insulator.

4 FIG. 5 FIG. 72 71 70 72 72 72 72 71 As shown inand, the third insulatorprovided over the third semiconductor substratein the insulating chiphas an upper surfaceS and a lower surfaceR opposite the upper surfaceS. The lower surfaceR is in contact with the third semiconductor substrate.

72 72 71 72 72 72 72 72 72 72 72 72 72 71 72 72 2 The third insulatorincludes a plurality of insulating filmsA stacked in the Z direction from the third semiconductor substrate. The insulating filmsA include a first insulating filmAA and a second insulating filmAB provided over the first insulating filmAA. The first insulating filmAA may be formed of a material including SiN, SiC, nitrogen-added silicon carbide (SiCN), or the like. The second insulating filmAB is, for example, an interlayer insulating film. The second insulating filmAB may be formed of a material including SiO. A thickness of the second insulating filmAB may be larger than a thickness of the first insulating filmAA. Both a lowermost insulating filmAC in contact with the third semiconductor substrateand an uppermost insulating filmAD may be formed by the second insulating filmAB.

4 FIG. 32 33 31 72 72 32 33 32 72 72 33 32 71 33 72 32 33 32 33 32 33 32 33 As shown in, the first coiland the second coilof the transformerare provided in the plurality of insulating filmsA of the third insulator. The first coiland the second coilare disposed to face each other while being spaced apart from each other in the Z direction. The first coilis disposed closer to the lower surfaceR of the third insulatorthan the second coil. It can also be said that the first coilis disposed closer to the third semiconductor substratethan the second coil. The plurality of insulating filmsA are interposed between the first coiland the second coilin the Z direction. Both the first coiland the second coilmay be formed of a material containing one or more substances appropriately selected from titanium (Ti), titanium nitride (TiN), Au, Ag, Cu, Al, and tungsten (W). In one example, both the first coiland the second coilare formed of a material containing Cu. Both the first coiland the second coilmay have, for example, a circular spiral shape in a plan view.

32 32 32 32 32 5 FIG. The first coilincludes a first inner endA that constitutes an inner end in a winding direction of the circular spiral first coil, and a first outer endB (see) that constitutes an outer end in the winding direction of the first coil.

4 FIG. 5 FIG. 70 74 75 74 75 As shown inand, the insulating chipincludes a first inner wiringand a first outer wiring. Each of the first inner wiringand the first outer wiringmay be formed of a material including one or more substances appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

4 FIG. 74 32 32 73 32 73 74 72 As shown in, the first inner wiringconnects the first inner endA of the first coiland the first padA to each other. Thus, the first coiland the first padA are electrically connected to each other. The first inner wiringmay include a first inner wiring portion extending in the Z direction to penetrate the plurality of insulating filmsA, and a second inner wiring portion extending in the X direction.

5 FIG. 75 32 32 73 32 73 75 72 75 71 As shown in, the first outer wiringconnects the first outer endB of the first coiland the second padB to each other. Thus, the first coiland the second padB are electrically connected to each other. The first outer wiringmay include a first outer wiring portion extending in the Z direction to penetrate the plurality of insulating filmsA, and a second outer wiring portion extending in the X direction. The first outer wiringmay be electrically connected to, for example, the third semiconductor substrate.

33 33 33 33 33 4 FIG. The second coilincludes a second inner endA (see) that constitutes an inner end of the circular spiral second coilin a winding direction, and a second outer endB that constitutes an outer end of the second coilin the winding direction.

4 FIG. 5 FIG. 70 76 77 76 77 As shown inand, the insulating chipincludes a second inner wiringand a second outer wiring. Each of the second inner wiringand the second outer wiringmay be formed of a material including one or more substances appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

4 FIG. 76 33 33 73 33 73 76 73 33 76 72 As shown in, the second inner wiringconnects the second inner endA of the second coiland the third padC to each other. Thus, the second coiland the third padC are electrically connected to each other. The second inner wiringis disposed at a position overlapping with both the third padC and the second inner endA in a plan view. The second inner wiringmay be a via that penetrates the uppermost insulating filmAD in the Z direction.

5 FIG. 77 33 33 73 33 73 77 73 33 77 72 As shown in, the second outer wiringconnects the second outer endB of the second coiland the fourth padD to each other. Thus, the second coiland the fourth padD are electrically connected to each other. The second outer wiringis disposed at a position overlapping with both the fourth padD and the second outer endB in a plan view. The second outer wiringmay be a via that penetrates the uppermost insulating filmAD in the Z direction.

4 FIG. 5 FIG. 70 78 78 72 78 33 78 33 78 33 78 78 33 78 As shown inand, the insulating chipincludes a dummy coil. The dummy coilis provided in the third insulator. The dummy coilis provided at the same position as the second coilin the Z direction. The dummy coilis provided to surround the second coilin a plan view. The dummy coilis provided around the second coil. The dummy coilmay be formed of a material including one or more substances appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W. The dummy coilcan suppress electric field concentration on the second coil. The dummy coilmay be omitted.

70 72 72 72 72 72 72 72 72 2 The insulating chipincludes a passivation filmB and a protective filmC as a third insulator. The passivation filmB is provided over the uppermost insulating filmAD. The passivation filmB is a film that protects the insulating filmA. The passivation filmB is formed of a material including, for example, SiO, SiN, SiCN, and the like.

73 73 72 72 73 73 72 73 73 The first to fourth padsA toD are provided over the uppermost insulating filmAD. The passivation filmB covers each of the first to fourth padsA toD. Further, the passivation filmB includes openings that partially expose the first to fourth padsA toD in the Z direction.

72 72 72 72 72 73 73 72 The protective filmC is provided over the passivation filmB. The protective filmC is formed of a material containing PI, for example. The protective filmC includes openings that communicate with the openings of the passivation filmB. As a result, the first to fourth padsA toD are partially exposed in the Z direction from the protective filmC.

80 80 83 83 6 FIG. 6 FIG. 2 FIG. An internal configuration of the control circuit chipwill be described with reference to.shows a schematic cross-sectional structure of the control circuit chiptaken along the XZ plane passing through the second padB and the fourth padD in.

6 FIG. 2 FIG. 80 81 81 41 42 81 83 83 81 82 81 As shown in, the control circuit chipincludes the second semiconductor layerA epitaxially grown from the second semiconductor substrateas described above. Both the rectifier circuitand the gate voltage control circuitare provided, for example, in the second semiconductor layerA. The first to fourth padsA toD (see) are provided over the second semiconductor layerA. The second insulatoris provided over the second semiconductor layerA.

80 84 85 86 84 86 81 84 86 The control circuit chipincludes a plurality of first connection wirings, a plurality of second connection wirings, and a plurality of third connection wirings. The first to third connection wiringstoare provided in the second semiconductor layerA. Each of the first to third connection wiringstomay be formed of a material containing one or more substances appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

84 41 83 83 85 41 42 86 42 83 83 86 86 42 83 86 42 83 86 81 42 83 86 83 86 42 2 83 83 86 42 42 83 81 86 86 42 83 81 2 FIG. The first connection wiringsconnect the rectifier circuitto the first padA and the second padB. The second connection wiringsconnect the rectifier circuitto the gate voltage control circuit. The third connection wiringsconnect the gate voltage control circuitto the third padC and the fourth padD. As shown in, the third connection wiringsinclude a wiringA that connects the gate voltage control circuitand the third padC to each other, and a wiringB that connects the gate voltage control circuitto the fourth padD to each other. The wiringB is electrically connected to the second semiconductor substrate. It can be said that the gate voltage control circuitis configured such that the third padC connected by the wiringA has a desired potential difference with respect to the fourth padD connected by the wiringB. Further, it can be said that the gate voltage control circuitis configured to generate the drive signal Shaving the potential difference between the third padC and the fourth padD as a drive voltage. The wiringB may include a wiring connected to a circuit element constituting the gate voltage control circuit, and a region constituting the circuit element, for example, a source region of an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET). Thus, each of the gate voltage control circuitand the fourth padD is electrically connected to the second semiconductor substrate. On the other hand, among the plurality of third connection wirings, the third connection wiringthat connects the gate voltage control circuitand the third padC to each other is not connected to the second semiconductor substrate.

90 90 51 52 90 8 8 7 FIG. 8 FIG. 7 FIG. 8 FIG. 7 FIG. An internal configuration of the switch circuit chipwill be described with reference toand.shows a partially enlarged schematic plan-view structure of a region in the switch circuit chip, in which the first transistorand the second transistorare provided.shows a schematic cross-sectional structure of the switch circuit chiptaken along line F-Fin.

8 FIG. 90 92 91 94 92 92 91 94 92 2 92 1 91 2 92 3 94 3 94 1 91 As shown in, the switch circuit chipincludes an insulating layerprovided over the first semiconductor substrateand a nitride semiconductor layerprovided over the insulating layer. The insulating layeris a layer that insulates the first semiconductor substratefrom the nitride semiconductor layer. The insulating layeris formed of, for example, aluminum nitride (AlN). In one example, a thickness Tof the insulating layermay be smaller than a thickness Tof the first semiconductor substrate. In one example, the thickness Tof the insulating layermay be smaller than a thickness Tof the nitride semiconductor layer. In one example, the thickness Tof the nitride semiconductor layermay be smaller than the thickness Tof the first semiconductor substrate.

94 94 92 94 94 94 94 The nitride semiconductor layerincludes a buffer layerA provided over the insulating layer, an electron transit layerB provided over the buffer layerA, and an electron supply layerC provided over the electron transit layerB.

94 91 94 94 94 94 94 94 The buffer layerA may be formed of any material capable of suppressing occurrence of warpage and cracks of a wafer due to mismatching in thermal expansion coefficients between the first semiconductor substrateand the electron transit layerB. The buffer layerA may include one or more nitride semiconductor layers. The buffer layerA may be formed of a material including aluminum gallium nitride (AlGaN). The buffer layerA may include, for example, an AlGaN layer and at least one of graded AlGaN layers having different Al compositions. For example, the buffer layerA may be formed by a single AlGaN layer, a layer having an AlGaN/GaN superlattice structure, a layer having an AlN/AlGaN superlattice structure, or a layer having an AlN/GaN superlattice structure. The buffer layerA may include a plurality of AlGaN layers having different compositions.

94 94 94 In order to suppress a leakage current in the buffer layerA, impurities may be introduced into a portion of the buffer layerA to make the buffer layerA semi-insulating. In this case, the impurities are, for example, carbon (C) or Fe.

94 94 94 94 94 94 94 94 94 94 94 94 94 94 The electron transit layerB may be, for example, a GaN layer. The electron transit layerB may include one or more nitride semiconductor layers. In order to suppress a leakage current in the electron transit layerB, the electron transit layerB may include a doped layerBA, which is made semi-insulating, except for a surface layer region, by introducing acceptor-type impurities into a portion of the electron transit layerB. It can be said that the doped layerBA is formed by a material including GaN doped with acceptor-type impurities. In this case, the acceptor-type impurities are, for example, C. The doped layerBA is provided over the buffer layerA. In one example, the doped layerBA is provided in the electron transit layerB and disposed closer to the buffer layerA in the Z direction. In one example, the doped layerBA is in contact with the buffer layerA.

94 94 94 94 94 94 94 94 x 1-x The electron supply layerC is formed by a nitride semiconductor having a larger band gap than the electron transit layerB. The electron supply layerC may be, for example, an AlGaN layer. Since the band gap increases as an Al composition increases, the electron supply layerC, which is an AlGaN layer, has a larger band gap than the electron transit layerB, which is a GaN layer. In one example, the electron supply layerC is formed of AlGaN with an Al composition ratio x. In this case, the Al composition ratio x is 0.1<x<0.4, and more specifically 0.1<x<0.3. A thickness of the electron supply layerC may be smaller than a thickness of the electron transit layerB.

94 94 94 94 94 94 94 94 94 94 95 94 94 94 The electron transit layerB and the electron supply layerC have different lattice constants in a bulk region. Therefore, the nitride semiconductor (e.g., GaN) constituting the electron transit layerB and the nitride semiconductor (e.g., AlGaN) constituting the electron supply layerC form a lattice mismatch type heterojunction. Due to spontaneous polarization of the electron transit layerB and the electron supply layerC and piezoelectric polarization caused by a compressive stress applied to the heterojunction of the electron transit layerB, an energy level of a conduction band of the electron transit layerB in a vicinity of an heterojunction interface between the electron transit layerB and the electron supply layerC becomes lower than the Fermi level. Thus, a two-dimensional electron gas (2DEG)spreads in the electron transit layerB in the vicinity of the heterojunction interface between the electron transit layerB and the electron supply layerC (e.g., at a distance of about several nm from the interface).

90 96 94 97 96 97 94 96 97 94 The switch circuit chipincludes a gate layerprovided over a portion of the electron supply layerC, and a gate electrodeG provided over the gate layer. Therefore, it can be said that the gate electrodeG is provided over the electron supply layerC. It can also be said that the gate layeris interposed between the gate electrodeG and the electron supply layerC.

96 96 94 96 The gate layeris formed by a nitride semiconductor. In one example, the gate layeris formed by a nitride semiconductor having a band gap smaller than that of the electron supply layerC and containing acceptor-type impurities. In one example, the gate layeris GaN doped with acceptor-type impurities (a p-type GaN layer). The acceptor-type impurities may be at least one of magnesium (Mg), zinc (Zn), or C.

97 97 97 97 96 The gate electrodeG includes one or more metal layers. In one example, the gate electrodeG may be a TiN layer. In another example, the gate electrodeG may be formed by a first metal layer formed of Ti, and a second metal layer provided over the first metal layer and formed of TiN. The gate electrodeG may be formed by a material having a property of forming a Schottky junction with the gate layer, for example. One example of such a material is TiN.

98 94 98 98 98 94 96 97 98 98 98 98 98 94 98 98 98 2 2 3 The first insulatoris provided over the electron supply layerC. The first insulatorincludes a passivation filmA. The passivation filmA covers the electron supply layerC, the gate layer, and the gate electrodeG. The passivation filmA may be formed of, for example, one or any combination of SiO, SiN, silicon oxynitride (SiON), alumina (AlO), AlN, and aluminum oxynitride (AlON). The passivation filmA includes a source openingAA, a first drain openingAB, and a second drain openingAC, each of which exposes a portion of an upper surface of the electron supply layerC. The source openingAA is disposed between the first drain openingAB and the second drain openingAC in the Y direction.

90 97 98 97 98 97 98 97 94 98 95 94 97 94 98 97 94 98 95 94 97 97 97 94 The switch circuit chipincludes a source electrodeS provided in the source openingAA, a first drain electrodeDA provided in the first drain openingAB, and a second drain electrodeDB provided in the second drain openingAC. The source electrodeS includes a source contact that is in contact with the electron supply layerC via the source openingAA. The source contact is in ohmic contact with the 2DEGdirectly below the electron supply layerC. The first drain electrodeDA includes a first drain contact that is in contact with the electron supply layerC via the first drain openingAB. The second drain electrodeDB includes a second drain contact that is in contact with the electron supply layerC via the second drain openingAC. Both the first drain contact and the second drain contact are in ohmic contact with the 2DEGdirectly below the electron supply layerC. Therefore, it can be said that the source electrodeS, the first drain electrodeDA, and the second drain electrodeDB are provided over the electron supply layerC.

97 97 97 97 97 97 97 97 97 94 The source electrodeS, the first drain electrodeDA, and the second drain electrodeDB include one or more metal layers. In one example, the source electrodeS, the first drain electrodeDA, and the second drain electrodeDB may be formed of one or any combination of Ti, TiN, Al, aluminum silicon copper (AlSiCu), and aluminum copper (AlCu). In one example, the source electrodeS, the first drain electrodeDA, and the second drain electrodeDB are formed by a first metal layer in contact with the electron supply layerC, a second metal layer stacked on the first metal layer, a third metal layer stacked on the second metal layer, and a fourth metal layer stacked on the third metal layer. The first metal layer is, for example, a Ti layer, the second metal layer is, for example, an Al layer, the third metal layer is, for example, a Ti layer, and the fourth metal layer is, for example, a TiN layer.

96 97 95 96 2 97 95 94 96 In a structure in which the gate layeris formed by a nitride semiconductor containing acceptor-type impurities, at a zero bias in which no voltage is applied to the gate electrodeG, the 2DEGin a region directly below the gate layeris depleted, so that a conductive path (channel) is blocked. Thus, a normally-off type HEMT having a gate threshold voltage of a positive value is implemented. When the drive signal Sof an appropriate voltage (on voltage) is applied to the gate electrodeG, a channel is formed by the 2DEGin a region of the electron transit layerB directly below the gate layer, so that the source and the drain are electrically connected.

98 98 98 97 97 97 98 2 The first insulatorincludes a first interlayer insulating filmB. The first interlayer insulating filmB is provided to cover the source electrodeS, the first drain electrodeDA, and the second drain electrodeDB. The first interlayer insulating filmB may be formed of, for example, SiO.

90 99 99 99 99 98 99 99 99 99 99 99 99 99 The switch circuit chipincludes a source wiringS, a first drain wiringDA, a second drain wiringDB, and a gate wiringG provided over the first interlayer insulating filmB. The source wiringS, the first drain wiringDA, the second drain wiringDB, and the gate wiringG include one or a plurality of metal layers. The source wiringS, the first drain wiringDA, the second drain wiringDB, and the gate wiringG may be formed of one or any combination of Ti, TiN, Al, AlSiCu, and AlCu.

99 97 99 99 97 99 97 99 99 97 99 97 99 99 97 99 97 99 99 97 99 99 99 99 98 99 99 99 99 The source wiringS is connected to the source electrodeS by a source viaSP. Thus, the source wiringS is electrically connected to the source electrodeS. The first drain wiringDA is connected to the first drain electrodeDA by a first drain viaDP. Thus, the first drain wiringDA is electrically connected to the first drain electrodeDA. The second drain wiringDB is connected to the second drain electrodeDB by a second drain viaDQ. Thus, the second drain wiringDB is electrically connected to the second drain electrodeDB. The gate wiringG is connected to the gate electrodeG by a gate viaGP. Thus, the gate wiringG is electrically connected to the gate electrodeG. Each of the source viaSP, the first drain viaDP, the second drain viaDQ, and the gate viaGP is provided in the first interlayer insulating filmB. Each of the source viaSP, the first drain viaDP, the second drain viaDQ, and the gate viaGP may be formed of a material including one or more substances appropriately selected from Ti, TiN, Au, Ag, Cu, Al, and W.

98 98 98 99 99 99 99 98 2 The first insulatorincludes a second interlayer insulating filmC. The second interlayer insulating filmC is provided to cover the source wiringS, the first drain wiringDA, the second drain wiringDB, and the gate wiringG. The second interlayer insulating filmC may be formed of, for example, SiO.

93 93 98 93 99 93 97 99 99 93 99 99 93 97 99 99 99 93 99 93 97 99 99 93 99 93 97 99 99 2 FIG. The first to fourth padsA toD (see) are provided over the second interlayer insulating filmC. The first padA is connected to the gate wiringG by a gate connection wiring (not shown). Therefore, the first padA is electrically connected to the gate electrodeG via the gate connection wiring, the gate wiringG, and the gate viaGP. The second padB is connected to the source wiringS by a source connection wiringSQ. Therefore, the second padB is electrically connected to the source electrodeS via the source connection wiringSQ, the source wiringS, and the source viaSP. The third padC is connected to the first drain wiringDA by a first drain connection wiring (not shown). Therefore, the third padC is electrically connected to the first drain electrodeDA via the first drain connection wiring, the first drain wiringDA, and the first drain viaDP. The fourth padD is connected to the second drain wiringDB by a second drain connection wiring (not shown). Therefore, the fourth padD is electrically connected to the second drain electrodeDB via the second drain connection wiring, the second drain wiringDB, and the second drain viaDQ.

98 98 98 93 93 98 90 98 The first insulatorincludes a protective filmD. The protective filmD is provided to cover the first to fourth padsA toD. The protective filmD constitutes the first chip front surfaceS. The protective filmD is formed of a material including PI, for example.

98 93 93 93 93 98 51 52 92 90 The protective filmD includes openings corresponding to the first to fourth padsA toD, respectively. Thus, the first to fourth padsA toD are partially exposed from the protective filmD in the Z direction. As described above, the first transistorand the second transistorare provided between the insulating layerand the first chip front surfaceS in the Z direction.

7 FIG. 7 FIG. 90 97 97 97 97 As shown in, the switch circuit chipincludes an HEMT structure. For clarity of illustration,shows a schematic plan-view structure of the source electrodeS, the gate electrodeG, the drain electrodesDA andDB, and surroundings thereof.

90 7 FIG. The switch circuit chipincludes a plurality of transistor elements having HEMT structures. Althoughshows, for example, a plurality of transistor elements arranged in the Y direction, actually, the transistor elements are arranged in both the X direction and the Y direction.

97 97 97 97 97 97 The first drain electrodeDA is provided in each transistor element. The second drain electrodeDB is provided in each transistor element. The first drain electrodeDA and the second drain electrodeDB are disposed to be spaced apart from each other in the Y direction. Each of the drain electrodesDA andDB has a strip shape extending along the X direction in a plan view.

97 97 97 97 97 97 97 97 97 97 The source electrodeS is provided as a common electrode for the transistor element provided with the first drain electrodeDA and for the transistor element provided with the second drain electrodeDB. The source electrodeS is disposed between the first drain electrodeDA and the second drain electrodeDB in the Y direction. It can also be said that the first drain electrodeDA and the second drain electrodeDB are disposed on both sides of the source electrodeS in a spaced-apart relationship. The source electrodeS has a strip shape extending along the X direction in a plan view.

96 97 96 97 97 97 97 96 97 96 97 97 97 97 97 The gate layerand the gate electrodeG are provided in common to the plurality of transistor elements. The gate layerand the gate electrodeG are provided in an annular shape to surround the first drain electrodeDA, the second drain electrodeDB, and the source electrodeS individually in a plan view. It can also be said that the gate layerand the gate electrodeG are provided in a lattice shape in a plan view. Therefore, it can also be said that the gate layerand the gate electrodeG are disposed between the source electrodeS and the first drain electrodeDA, and between the source electrodeS and the second drain electrodeDB in a plan view.

99 99 99 99 99 99 99 99 Although not shown, each of the source wiringS, the first drain wiringDA, the second drain wiringDB, and the gate wiringG may extend in the X direction. The source wiringS, the first drain wiringDA, the second drain wiringDB, and the gate wiringG are disposed to be spaced apart from one another in the Y direction.

99 99 99 99 99 99 99 Each of the first drain wiringDA, the second drain wiringDB, and the gate wiringG may extend in the Y direction. In this case, the source wiringS, the first drain wiringDA, the second drain wiringDB, and the gate wiringG are disposed to be spaced apart from each other in the X direction.

10 80 90 82 98 7 11 9 FIG. 9 FIG. 3 FIG. 9 FIG. An operation of the semiconductor deviceaccording to the first embodiment will be described with reference to.shows a schematic cross-sectional structure of the control circuit chip, the switch circuit chip, and surroundings thereof shown in. For the sake of convenience, the second insulator, the protective filmD, the seventh wire W, and the eleventh wire Ware omitted in.

9 FIG. 9 FIG. 51 52 93 90 93 83 80 9 83 81 80 86 86 81 101 2 91 90 101 1 51 52 101 80 51 52 91 101 91 81 91 91 90 As shown in, the source of the first transistorand the source of the second transistorare electrically connected to the second padB of the switch circuit chip. The second padB is electrically connected to the fourth padD of the control circuit chipby the ninth wire W. The fourth padD is electrically connected to the second semiconductor substrateof the control circuit chipby the wiringB of the third connection wiring. The second semiconductor substrateis electrically connected to the first die padby the second conductive bonding material SD. The first semiconductor substrateof the switch circuit chipis electrically connected to the first die padby the first conductive bonding material SD. Thus, as indicated by a dot line arrow in, the source of the first transistorand the source of the second transistorare electrically connected to the first die padvia the control circuit chip. Further, the source of the first transistorand the source of the second transistorare electrically connected to the first semiconductor substratevia the first die pad. Therefore, since a potential of the first semiconductor substratebecomes equal to a potential of the second semiconductor substrate, the potential of the first semiconductor substrateis stabilized to a source potential. Furthermore, since the potential of the first semiconductor substratecoincides with the source potential, electrical characteristics of the switch circuit chipis stabilized.

51 52 101 93 In addition, a pad, which is electrically connected to the source of the first transistorand the source of the second transistorand electrically connected to the first die padby, for example, a wire, does not need to be provided separately from the second padB. Therefore, the wire described above can also be omitted.

10 The semiconductor deviceaccording to the first embodiment provides the following effects.

10 101 90 101 80 101 40 90 1 101 90 2 101 80 102 103 101 120 1 2 90 80 102 103 90 90 90 90 91 90 101 1 92 91 51 52 92 90 90 51 52 51 52 101 80 (1-1) The semiconductor deviceincludes: the first die pad; the switch circuit chipmounted on the first die pad; the control circuit chipmounted on the first die padand including the control circuitconfigured to control driving the switch circuit chip; the first conductive bonding material SDconfigured to bond the first die padand the switch circuit chip; the second conductive bonding material SDconfigured to bond the first die padand the control circuit chip; the first terminaland the second terminal, which are disposed to be spaced apart from the first die pad; and the sealing resinconfigured to at least seal the first conductive bonding material SD, the second conductive bonding material SD, the switch circuit chip, and the control circuit chip, and configured to at least partially expose both the first terminaland the second terminal. The switch circuit chipincludes the first chip front surfaceS, the first chip rear surfaceR opposite the first chip front surfaceS, the first semiconductor substrateconstituting the first chip rear surfaceR and bonded to the first die padby the first conductive bonding material SD, the insulating layerprovided over the first semiconductor substrate, and the first transistorand the second transistorthat are provided between the insulating layerand the first chip front surfaceS in the thickness direction of the switch circuit chip(Z direction) and have sources connected to each other. Both the first transistorand the second transistorare high electron mobility transistors including a nitride semiconductor. The source of the first transistorand the source of the second transistorare electrically connected to the first die padvia the control circuit chip.

51 52 91 80 2 101 1 51 52 91 91 90 With this configuration, the source of the first transistorand the source of the second transistorare electrically connected to the first semiconductor substratevia the control circuit chip, the second conductive bonding material SD, the first die pad, and the first conductive bonding material SD. Therefore, a source potential of each of the transistorsandand a potential of the first semiconductor substratebecome equal to each other, which stabilizes the potential of the first semiconductor substrate. Accordingly, it is possible to stabilize electrical characteristics of the switch circuit chip.

80 80 80 80 81 80 101 2 83 80 83 81 80 90 93 90 51 52 93 90 51 52 10 8 83 93 9 83 93 (1-2) The control circuit chipincludes the second chip front surfaceS, the second chip rear surfaceR opposite the second chip front surfaceS, the second semiconductor substrateconstituting the second chip rear surfaceR and bonded to the first die padby the second conductive bonding material SD, the third padC exposed from the second chip front surfaceS, and the fourth padD electrically connected to the second semiconductor substrateand exposed from the second chip front surfaceS. The switch circuit chipincludes the first padA exposed from the first chip front surfaceS and electrically connected to both the gate of the first transistorand the gate of the second transistor, and the second padB exposed from the first chip front surfaceS and electrically connected to the source of the first transistorand the source of the second transistor. The semiconductor devicefurther includes the eighth wire Wconnecting the third padC and the first padA, and the ninth wire Wconnecting the fourth padD and the second padB.

81 80 51 52 83 80 93 90 9 51 52 81 80 90 With this configuration, the second semiconductor substrateof the control circuit chipis electrically connected to the source of the first transistorand the source of the second transistorvia the fourth padD of the control circuit chip, the second padB of the switch circuit chip, and the ninth wire W. Therefore, the source potential of each of the transistorsandbecomes equal to the potential of the second semiconductor substrate. Accordingly, it is possible to stabilize the electrical characteristics of the control circuit chipand the switch circuit chip.

83 101 93 101 10 51 52 91 81 In addition, by connecting the third padC and the first die padby the wire, and connecting the second padB and the first die padby the wire, a configuration of the semiconductor devicecan be simplified compared to a configuration in which the sources of the respective transistorsand, the first semiconductor substrate, and the second semiconductor substrateare electrically connected.

10 104 101 104 120 (1-3) The semiconductor devicefurther includes the third terminalintegrated with the first die pad. A portion of the third terminalis exposed from the sealing resin.

104 101 101 10 With this configuration, the third terminalserves as a hanging lead for the first die pad. Thus, the first die padcan be stably supported when manufacturing the semiconductor device.

2 92 1 91 (1-4) The thickness Tof the insulating layeris smaller than the thickness Tof the first semiconductor substrate.

90 2 92 1 91 With this configuration, the switch circuit chipcan be made thinner compared to a case in which the thickness Tof the insulating layeris equal to or larger than the thickness Tof the first semiconductor substrate.

92 (1-5) The insulating layeris formed of a material including AlN.

92 51 52 91 90 With this configuration, since heat dissipation performance of the insulating layeris improved, it becomes easier to transfer heat from the first transistorand the second transistorto the first semiconductor substrate. Accordingly, it is possible to improve heat dissipation performance of the switch circuit chip.

10 111 101 70 111 7 8 70 80 120 70 7 8 (1-6) The semiconductor devicefurther includes the second die paddisposed to be spaced apart from the first die padin the X direction, the insulating chipmounted on the second die pad, and the seventh wire Wand the eighth wire Wconfigured to electrically connect the insulating chipand the control circuit chip. The sealing resinseals the insulating chip, the seventh wire W, and the eighth wire W.

70 10 80 90 10 70 80 70 10 With this configuration, by embedding the insulating chipin the semiconductor device, the control circuit chipand the switch circuit chipcan be protected when static electricity or the like is applied to the semiconductor device. In addition, a length of a path electrically connecting the insulating chipand the control circuit chipcan be shortened compared to a case in which the insulating chipis provided outside the semiconductor device. Accordingly, it is possible to reduce an inductance caused by a distance of the path described above.

10 60 111 4 5 70 60 120 60 4 5 (1-7) The semiconductor devicefurther includes the drive circuit chipmounted on the second die pad, and the fourth wire Wand the fifth wire Wthat connect the insulating chipand the drive circuit chip. The sealing resinseals the drive circuit chip, the fourth wire W, and the fifth wire W.

60 70 60 10 With this configuration, a length of a path electrically connecting the drive circuit chipand the insulating chipcan be made shorter compared to a case in which the drive circuit chipis provided outside the semiconductor device. Accordingly, it is possible to reduce an inductance caused by a length of the path described above.

10 112 114 111 113 111 112 114 113 101 111 114 101 112 113 (1-8) The semiconductor devicefurther includes the fourth terminaland the sixth terminalthat are disposed to be spaced apart from the second die pad, and the fifth terminalintegrated with the second die pad. The fourth terminal, the sixth terminal, and the fifth terminalare disposed on the opposite side of the first die padwith respect to the second die pad. The sixth terminalis disposed on the side of the first die padwhere the fourth terminaland the fifth terminalare disposed.

104 112 114 10 With this configuration, it is possible to ensure a long creepage distance between the third terminaland the fourth to sixth terminalsto. Accordingly, it is possible to suppress a decrease in a dielectric strength of the semiconductor device.

10 10 10 70 80 10 FIG. 11 FIG. A semiconductor deviceaccording to a second embodiment will be described with reference toand. The semiconductor deviceaccording to the second embodiment differs from the semiconductor deviceaccording to the first embodiment mainly in omitting the insulating chipand in a configuration of the control circuit chip. In the following, components common with the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted.

10 FIG. 10 FIG. 10 10 60 80 90 60 90 shows a schematic plan-view structure of the semiconductor deviceaccording to the second embodiment. As shown in, the semiconductor deviceaccording to the second embodiment includes the drive circuit chip, the control circuit chip, and the switch circuit chipas semiconductor chips. Configurations of the drive circuit chipand the switch circuit chipare the same as those of the first embodiment.

60 111 70 111 111 The drive circuit chipis mounted on the second die pad. On the other hand, in the second embodiment, the insulating chipis not mounted. Therefore, the dimension in the X direction of the second die padmay be smaller than the dimension in the X direction of the second die padin the first embodiment.

10 12 13 4 7 12 13 60 80 12 63 60 83 80 13 63 60 83 80 The semiconductor deviceincludes a twelfth wire Wand a thirteenth wire Winstead of the fourth to seventh wires Wto Wof the first embodiment. The twelfth wire Wand the thirteenth wire Wconnect the drive circuit chipand the control circuit chip. The twelfth wire Wconnects the fourth padD of the drive circuit chipand the first padA of the control circuit chipto each other. The thirteenth wire Wconnects the fifth padE of the drive circuit chipand the second padB of the control circuit chipto each other.

12 13 120 12 13 12 13 3 FIG. The twelfth wire Wand the thirteenth wire Ware sealed with the sealing resin(see). The twelfth wire Wand the thirteenth wire Ware, for example, bonding wires, and are formed of a material including Au, Al, Cu, Ag, and the like. Here, the twelfth wire Wand the thirteenth wire Ware an example of a “chip connector.”

80 80 101 80 101 101 111 In the second embodiment, an X-direction dimension of the control circuit chipis larger than that of the control circuit chipof the first embodiment. Accordingly, an X-direction dimension of the first die padon which the control circuit chipis mounted is larger than that of the first die padof the first embodiment. The X-direction dimension of the first die padis also larger than an X-direction dimension of the second die pad.

11 FIG. 10 FIG. 11 FIG. 80 9 13 schematically shows a cross-sectional structure of the control circuit chipshown in. For the sake of convenience, the ninth wire Wand the thirteenth wire Ware omitted in.

11 FIG. 80 31 41 42 82 80 82 82 82 82 2 As shown in, the control circuit chipincludes the transformer, the rectifier circuit, and the gate voltage control circuit. The second insulatorof the control circuit chipmay include an insulating layerA containing at least one of SiOor SiN, and a protective layerB provided over the insulating layerA. The protective layerB may be formed of, for example, PI.

41 42 81 81 31 82 32 33 31 33 81 32 32 32 83 74 32 32 83 75 33 33 41 76 33 33 41 77 4 FIG. 2 FIG. 4 FIG. 5 FIG. 4 FIG. 4 FIG. 5 FIG. Both the rectifier circuitand the gate voltage control circuitare provided in the second semiconductor layerA provided over the second semiconductor substrate. The transformeris provided in the insulating layerA. The first coiland the second coilof the transformerare disposed to face each other in the Z direction. The second coilis disposed closer to the second semiconductor substratethan the first coil. The first inner endA (see) of the first coilis connected to the first padA (see) by the first inner wiring(see). The first outer endB (see) of the first coilis connected to the second padB by the first outer wiring. The second inner endA (see) of the second coilis connected to the rectifier circuitby the second inner wiring(see). The second outer endB (see) of the second coilis connected to the rectifier circuitby the second outer wiring.

86 86 86 83 83 42 82 86 83 81 86 83 81 10 FIG. The wiringA (see) and wiringB of the third connection wiringthat connect each of the third padC and the fourth padD to the gate voltage control circuitextend to penetrate the insulating layerA in the Z direction. The wiringB connected to the fourth padD is electrically connected to the second semiconductor substrate, as in the first embodiment. Further, the wiringA connected to the third padC is not electrically connected to the second semiconductor substrate, as in the first embodiment.

10 The semiconductor deviceaccording to the second embodiment provides the following effects.

10 111 101 60 111 12 13 80 60 60 20 80 80 41 32 20 33 32 41 42 41 120 60 12 13 (2-1) The semiconductor deviceincludes the second die paddisposed to be spaced apart from the first die pad, the drive circuit chipmounted on the second die pad, and the twelfth wire Wand the thirteenth wire Wthat connect the control circuit chipand the drive circuit chip. The drive circuit chipincludes the drive circuitconfigured to output a signal to the control circuit chip. The control circuit chipincludes the rectifier circuit, the first coilelectrically connected to the drive circuit, the second coildisposed to face the first coiland electrically connected to the rectifier circuit, and the gate voltage control circuitelectrically connected to the rectifier circuit. The sealing resinseals the drive circuit chip, the twelfth wire W, and the thirteenth wire W.

10 10 With this configuration, the number of semiconductor chips in the semiconductor devicecan be reduced. In addition, the number of connectors (wires) connecting the semiconductor chips to one another can be reduced. Accordingly, it is possible to simplify the configuration of the semiconductor device. Further, it is possible to reduce the inductance caused by the connectors (wires).

10 10 10 50 12 FIG. 13 FIG. A semiconductor deviceaccording to a third embodiment will be described with reference toand. The semiconductor deviceaccording to the third embodiment differs from the semiconductor deviceaccording to the first embodiment mainly in that the former includes a plurality of switch circuits. In the following, components common with the first embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted.

800 10 800 12 FIG. 12 FIG. A circuit configuration of the insulating switchincluding the semiconductor deviceof the third embodiment will be described with reference to.shows a schematic circuit configuration of the insulating switch.

12 FIG. 50 10 50 50 40 50 50 10 11 13 50 11 13 50 14 15 16 50 16 50 As shown in, the plurality of switch circuitsof the semiconductor deviceincludes a first switch circuitA and a second switch circuitB. The control circuitis configured to individually control driving the first switch circuitA and the second switch circuitB. The semiconductor deviceincludes first to third terminalsA toA corresponding to the first switch circuitA, first to third terminalsB toB corresponding to the second switch circuitB, the fourth terminal, the fifth terminal, a sixth terminalA corresponding to the first switch circuitA, and a sixth terminalB corresponding to the second switch circuitB.

20 21 21 22 22 21 21 821 21 21 22 14 15 822 21 21 822 21 16 822 21 16 The drive circuitincludes a first pulse signal generation circuitA, a second pulse signal generation circuitB, and the oscillation circuit. The oscillation circuitis electrically connected to each of the first pulse signal generation circuitA and the second pulse signal generation circuitB. The power supply circuitis electrically connected to the first pulse signal generation circuitA, the second pulse signal generation circuitB, and the oscillation circuitvia the fourth terminaland the fifth terminal. The signal generation circuitis electrically connected to the first pulse signal generation circuitA and the second pulse signal generation circuitB individually. More specifically, the signal generation circuitis electrically connected to the first pulse signal generation circuitA via the sixth terminalA. The signal generation circuitis electrically connected to the second pulse signal generation circuitB via the sixth terminalB.

21 50 1 822 22 21 50 1 822 22 The first pulse signal generation circuitA is configured to generate a first pulse signal for controlling driving the first switch circuitA, based on a control signal SA of the signal generation circuitand the clock signal CLK of the oscillation circuit. The second pulse signal generation circuitB is configured to generate a second pulse signal for controlling driving the second switch circuitB, based on a control signal SB of the signal generation circuitand the clock signal CLK of the oscillation circuit.

30 31 31 31 31 31 32 31 21 32 31 21 1 FIG. The insulating circuitincludes a first transformerA and a second transformerB. Configurations of the transformersA andB are the same as, for example, the transformerof the first embodiment (see). A first coilof the first transformerA is electrically connected to the first pulse signal generation circuitA. A first coilof the second transformerB is electrically connected to the second pulse signal generation circuitB.

40 40 50 40 50 The control circuitincludes a first control circuitA electrically connected to the first switch circuitA and a second control circuitB electrically connected to the second switch circuitB.

40 41 42 41 33 31 41 33 31 42 41 42 51 52 90 The first control circuitA includes a first rectifier circuitA and a first gate voltage control circuitA. The first rectifier circuitA is electrically connected to a second coilof the first transformerA. The first rectifier circuitA is configured to rectify an induced current generated in the second coilof the first transformerA. The first gate voltage control circuitA is electrically connected to the first rectifier circuitA. The first gate voltage control circuitA is configured to supply a gate voltage to each of a first transistorand a second transistorof a first switch circuit chipA.

40 41 42 41 33 31 41 33 31 42 41 42 51 52 90 The second control circuitB includes a second rectifier circuitB and a second gate voltage control circuitB. The second rectifier circuitB is configured to rectify an induced current generated in a second coilof the second transformerB. The second rectifier circuitB is electrically connected to the second coilof the second transformerB. The second gate voltage control circuitB is electrically connected to the second rectifier circuitB. The second gate voltage control circuitB is configured to supply a gate voltage to each of a first transistorand a second transistorof a second switch circuit chipB.

50 50 51 52 51 52 50 50 42 51 52 50 51 52 42 51 52 50 51 52 Both the first switch circuitA and the second switch circuitB include the first transistorand the second transistor. An electrical connection configuration between the first transistorand the second transistorin each of the switch circuitsA andB is the same as that in the first embodiment. The first gate voltage control circuitA is electrically connected to each of the gates of the transistorsandof the first switch circuitA and a node ND between sources of the transistorsand. The second gate voltage control circuitB is electrically connected to each of the gates of the transistorsandof the second switch circuitB and a node ND between the sources of the transistorsand.

51 50 11 52 12 51 52 50 13 51 50 11 52 12 51 50 13 A drain of the first transistorof the first switch circuitA is electrically connected to the first terminalA, and a drain of the second transistoris electrically connected to the second terminalA. The node ND between the sources of the transistorsandof the first switch circuitA is electrically connected to the third terminalA. A drain of the first transistorof the second switch circuitB is electrically connected to the first terminalB, and a drain of the second transistoris electrically connected to the second terminalB. The node ND between the sources of the transistorsof the second switch circuitB is electrically connected to the third terminalB.

12 FIG. 1 FIG. 811 831 11 12 832 811 831 11 12 832 812 11 11 In the example shown in, a first loadA is electrically connected between the high potential terminaland the first terminalA. The second terminalA is electrically connected to the low potential terminal. A first loadB is electrically connected between the high potential terminaland the first terminalB. The second terminalB is electrically connected to the low potential terminal. The second loadshown inmay be connected to the first terminalsA andB.

10 10 13 FIG. 13 FIG. 12 FIG. 12 FIG. A configuration of the semiconductor deviceaccording to the third embodiment will be described with reference to.schematically shows a plan-view structure of the semiconductor deviceshown in. In the following description, reference is made tofor circuits included in each chip.

13 FIG. 10 80 90 80 80 40 80 40 90 90 50 90 50 As shown in, the semiconductor deviceincludes a plurality of control circuit chipsand a plurality of switch circuit chips. The plurality of control circuit chipsincludes a first control circuit chipA including the first control circuitA, and a second control circuit chipB including the second control circuitB. The plurality of switch circuit chipsincludes a first switch circuit chipA including the first switch circuitA, and a second switch circuit chipB including the second switch circuitB.

100 102 103 90 102 103 90 104 104 102 102 103 103 104 104 110 101 104 104 101 104 102 103 104 102 103 The first supportincludes a first terminalA and a second terminalA that correspond to the first switch circuit chipA, a first terminalB and a second terminalB that correspond to the second switch circuit chipB, and third terminalsA andB. The first terminalsA andB, the second terminalsA andB, and the third terminalsA andB are disposed on an opposite side of the second supportin the X direction with respect to the first die pad. The third terminalsA andB are integrated with the first die pad. The third terminalA is disposed between the first terminalA and the second terminalA in the Y direction. The third terminalB is disposed between the first terminalB and the second terminalB in the Y direction.

110 112 113 114 90 114 90 112 113 114 114 100 111 113 111 The second supportincludes a fourth terminal, a fifth terminal, a sixth terminalA corresponding to the first switch circuit chipA, and a sixth terminalB corresponding to the second switch circuit chipB. The fourth terminal, the fifth terminal, and the sixth terminalsA andB are disposed on an opposite side of the first supportin the X direction with respect to the second die pad. The fifth terminalis integrated with the second die pad.

60 63 63 63 114 63 114 10 3 114 63 3 114 63 63 63 63 63 63 60 125 120 63 63 63 60 126 120 The drive circuit chipincludes a first padA, a second padB, a third padCA corresponding to the sixth terminalA, and a third padCB corresponding to the sixth terminalB. The semiconductor deviceincludes a third wire WA that connects the sixth terminalA and the third padCA to each other, and a third wire WB that connects the sixth terminalB and the third padCB to each other. The first padA, the second padB, the third padCA, a fourth padDA, and a fifth padEA are provided in the fourth chip front surfaceS and disposed closer to the sealing side surfaceof the sealing resin. The third padCB, the fourth padDB, and the fifth padEB are provided in the fourth chip front surfaceS and disposed closer to the sealing side surfaceof the sealing resin.

63 63 63 21 63 63 63 21 63 63 22 The first padA, the second padB, and the third padCA are electrically connected to the first pulse signal generation circuitA. The first padA, the second padB, and the third padCB are electrically connected to the second pulse signal generation circuitB. The first padA and the second padB are electrically connected to the oscillation circuit.

60 63 63 21 63 63 21 The drive circuit chipincludes the fourth padDA and the fifth padEA that are electrically connected to the first pulse signal generation circuitA, and the fourth padDB and the fifth padEB that are electrically connected to the second pulse signal generation circuitB.

70 31 31 31 31 31 70 125 120 The insulating chipincludes the first transformerA and the second transformerB. The first transformerA and the second transformerB are arranged side by side in the Y direction in a plan view, for example. The first transformerA is provided in the third chip front surfaceS and disposed closer to the sealing side surfaceof the sealing resin.

31 70 126 120 31 31 31 The second transformerB is provided in the third chip front surfaceS and disposed closer to the sealing side surfaceof the sealing resin. A configuration of each of the transformersA andB may be the same as that of the transformerof the first embodiment, for example.

70 73 73 73 73 73 73 31 73 73 31 73 73 70 125 120 73 73 70 126 120 The insulating chipincludes first to fourth padsAA toDA andAB toDB. The first to fourth padsAA toDA are pads corresponding to the first transformerA, and the first to fourth padsAB toDB are pads corresponding to the second transformerB. The first to fourth padsAA toDA are provided in the third chip front surfaceS and disposed closer to the sealing side surfaceof the sealing resin. The first to fourth padsAB toDB are provided in the third chip front surfaceS and disposed closer to the sealing side surfaceof the sealing resin.

73 73 32 31 73 73 33 31 73 73 32 31 73 73 33 31 The first padAA and the second padBA are electrically connected to the first coilof the first transformerA. The third padCA and the fourth padDA are electrically connected to the second coilof the first transformerA. The first padAB and the second padBB are electrically connected to the first coilof the second transformerB. The third padCB and the fourth padDB are electrically connected to the second coilof the second transformerB.

10 4 4 5 5 4 63 60 73 70 5 63 60 73 70 4 63 60 73 70 5 63 60 73 70 21 32 31 21 32 31 The semiconductor deviceincludes fourth wires WA and WB and fifth wires WA and WB. The fourth wire WA connects the fourth padDA of the drive circuit chipand the first padAA of the insulating chipto each other. The fifth wire WA connects the fifth padEA of the drive circuit chipand the second padBA of the insulating chipto each other. The fourth wire WB connects the fourth padDB of the drive circuit chipand the first padAB of the insulating chipto each other. The fifth wire WB connects the fifth padEB of the drive circuit chipand the second padBB of the insulating chipto each other. Thus, the first pulse signal generation circuitA and the first coilof the first transformerA are electrically connected to each other, and the second pulse signal generation circuitB and the first coilof the second transformerB are electrically connected to each other.

80 80 80 80 80 80 80 81 82 Each of the first control circuit chipA and the second control circuit chipB has the same configuration as that of the control circuit chipof the first embodiment. That is, each of the first control circuit chipA and the second control circuit chipB includes the second chip front surfaceS, the second chip rear surfaceR, the second semiconductor substrate, and the second insulator.

80 80 101 80 80 101 2 80 80 3 FIG. Both the first control circuit chipA and the second control circuit chipB are mounted on the first die pad. Both the first control circuit chipA and the second control circuit chipB are bonded to the first die padby the second conductive bonding material SD(see). The first control circuit chipA and the second control circuit chipB are disposed at the same position in the X direction and spaced apart from each other in the Y direction.

80 83 83 83 83 41 83 83 42 83 81 80 83 81 80 The first control circuit chipA includes first to fourth padsAA toDA. The first padAA and the second padBA are electrically connected to the first rectifier circuitA. The third padCA and the fourth padDA are electrically connected to the first gate voltage control circuitA. The fourth padDA is electrically connected to the second semiconductor substrate(not shown) of the first control circuit chipA. The third padCA is not electrically connected to the second semiconductor substrateof the first control circuit chipA.

80 83 83 83 83 41 83 83 42 83 81 80 83 81 80 The second control circuit chipB includes first to fourth padsAB toDB. The first padAB and the second padBB are electrically connected to the second rectifier circuitB. The third padCB and the fourth padDB are electrically connected to the second gate voltage control circuitB. The fourth padDB is electrically connected to the second semiconductor substrate(not shown) of the second control circuit chipB. The third padCB is not electrically connected to the second semiconductor substrateof the second control circuit chipB.

10 6 6 7 7 6 73 70 83 80 7 73 70 83 80 6 73 70 83 80 7 73 70 83 80 The semiconductor deviceincludes sixth wires WA and WB and seventh wires WA and WB. The sixth wire WA connects the third padCA of the insulating chipand the first padAA of the first control circuit chipA to each other. The seventh wire WA connects the fourth padDA of the insulating chipand the second padBA of the first control circuit chipA to each other. The sixth wire WB connects the third padCB of the insulating chipand the first padAB of the second control circuit chipB to each other. The seventh wire WB connects the fourth padDB of the insulating chipand the second padBB of the second control circuit chipB to each other.

90 90 90 90 90 101 90 90 101 1 90 90 3 FIG. Each of the first switch circuit chipA and the second switch circuit chipB has the same configuration as that of the switch circuit chipof the first embodiment. Both the first switch circuit chipA and the second switch circuit chipB are mounted on the first die pad. Both the first switch circuit chipA and the second switch circuit chipB are bonded to the first die padby the first conductive bonding material SD(see). The first switch circuit chipA and the second switch circuit chipB are disposed at the same position in the X direction and spaced apart from each other in the Y direction.

90 93 93 93 51 52 50 93 51 52 50 93 51 50 93 52 50 The first switch circuit chipA includes first to fourth padsAA toDA. The first padAA is electrically connected to the gate of the first transistorand the gate of the second transistorof the first switch circuitA. The second padBA is electrically connected to the node ND between the source of the first transistorand the source of the second transistorof the first switch circuitA. The third padCA is electrically connected to the drain of the first transistorof the first switch circuitA. The fourth padDA is electrically connected to the drain of the second transistorof the first switch circuitA.

90 93 93 93 51 52 50 93 51 52 50 93 51 50 93 52 50 The second switch circuit chipB includes first to fourth padsAB toDB. The first padAB is electrically connected to the gate of the first transistorand the gate of the second transistorof the second switch circuitB. The second padBB is electrically connected to the node ND between the source of the first transistorand the source of the second transistorof the second switch circuitB. The third padCB is electrically connected to the drain of the first transistorof the second switch circuitB. The fourth padDB is electrically connected to the drain of the second transistorof the second switch circuitB.

10 8 11 8 11 8 83 80 93 90 9 83 80 93 90 10 93 90 102 11 93 90 103 8 83 80 93 90 9 83 80 93 90 10 93 90 102 11 93 90 103 The semiconductor deviceincludes eighth to eleventh wires WA to WA and WB to WB. The eighth wire WA connects the third padCA of the first control circuit chipA and the first padAA of the first switch circuit chipA to each other. The ninth wire WA connects the fourth padDA of the first control circuit chipA and the second padBA of the first switch circuit chipA to each other. The tenth wire WA connects the third padCA of the first switch circuit chipA and the first terminalA to each other. The eleventh wire WA connects the fourth padDA of the first switch circuit chipA and the second terminalA to each other. The eighth wire WB connects the third padCB of the second control circuit chipB and the first padAB of the second switch circuit chipB to each other. The ninth wire WB connects the fourth padDB of the second control circuit chipB and the second padBB of the first switch circuit chipA to each other. The tenth wire WB connects the third padCB of the second switch circuit chipB and the first terminalB to each other. The eleventh wire WB connects the fourth padDA of the second switch circuit chipB and the second terminalB to each other.

93 90 93 93 90 93 83 80 83 83 80 8 9 8 9 6 6 7 7 4 4 5 5 112 113 114 114 1 3 3 93 90 93 90 93 90 93 90 10 10 11 11 Here, the first padAA of the first switch circuit chipA corresponds to a “first input pad,” and the second padBA corresponds to a “second input pad.” The first padAB of the second switch circuit chipB corresponds to a “third input pad,” and the second padBB corresponds to a “fourth input pad.” The third padCA of the first control circuit chipA corresponds to a “first output pad,” the fourth padDA corresponds to a “second output pad,” the third padCB of the second control circuit chipB corresponds to a “third output pad,” and the fourth pad 83 DB corresponds to a “fourth output pad.” The eighth wire WA corresponds to a “first connector,” the ninth wire WA corresponds to a “second connector,” the eighth wire WB corresponds to a “third connector,” and the ninth wire WB corresponds to a “fourth connector.” The sixth wires WA and WB and the seventh wires WA and WB correspond to a “relay connector.” The fourth wires WA and WB and the fifth wires WA and WB correspond to an “intermediate connector.” The fourth terminalcorresponds to a “power supply terminal,” the fifth terminalcorresponds to a “ground terminal,” and the sixth terminalsA andB correspond to a “signal terminal.” The first wire Wcorresponds to a “power supply connector,” and the third wires WA and WB correspond to a “signal connector.” The third padCA of the first switch circuit chipA and the third padCB of the second switch circuit chipB correspond to a “first power supply pad.” The fourth padDA of the first switch circuit chipA and the fourth padDB of the second switch circuit chipB correspond to a “second power supply pad.” The tenth wires WA and WB correspond to a “first power supply connector,” and the eleventh wires WA and WB correspond to a “second power supply connector.”

10 The semiconductor deviceaccording to the third embodiment provides the following effects.

10 90 90 90 90 51 52 51 52 51 52 90 90 101 80 (3-1) The semiconductor deviceincludes, as switch circuit chips, the first switch circuit chipA and the second switch circuit chipB. Each of the first switch circuit chipA and the second switch circuit chipB includes the first transistorand the second transistorhaving sources connected in series to each other. Both the first transistorand the second transistorare high electron mobility transistors including nitride semiconductors. The source of the first transistorand the source of the second transistorof each of the first switch circuit chipA and the second switch circuit chipB are electrically connected to the first die padvia the control circuit chip.

51 52 90 91 90 80 2 101 1 51 52 91 90 91 90 90 With this configuration, the source of the first transistorand the source of the second transistorof the first switch circuit chipA are electrically connected to the first semiconductor substrateof the first switch circuit chipA via the control circuit chip, the second conductive bonding material SD, the first die pad, and the first conductive bonding material SD. Therefore, the source potential of each of the transistorsandand the potential of the first semiconductor substrateof the first switch circuit chipA become equal to each other, which stabilizes the potential of the first semiconductor substrateof the first switch circuit chipA. Accordingly, it is possible to stabilize electrical characteristics of the first switch circuit chipA.

51 52 90 91 90 80 2 101 1 51 52 91 90 91 90 90 Further, the source of the first transistorand the source of the second transistorof the second switch circuit chipB are electrically connected to the first semiconductor substrateof the second switch circuit chipB via the control circuit chip, the second conductive bonding material SD, the first die pad, and the first conductive bonding material SD. Therefore, the source potential of each of the transistorsandand the potential of the first semiconductor substrateof the second switch circuit chipB become equal to each other, which stabilizes the potential of the first semiconductor substrateof the second switch circuit chipB. Accordingly, it is possible to stabilize electrical characteristics of the second switch circuit chipB.

The third embodiment may be combined with the second embodiment. 104 100 104 125 120 102 104 126 103 104 125 126 124 102 104 102 104 100 In the first and second embodiments, the position of the third terminalof the first supportmay be changed arbitrarily. In one example, the third terminalmay be disposed closer to the sealing side surfaceof the sealing resinthan the first terminalin a plan view. In one example, the third terminalmay be disposed closer to the sealing side surfacethan the second terminalin a plan view. In one example, the third terminalmay be exposed from the sealing side surfaceor the sealing side surfaceinstead of the sealing side surface. Further, the arrangement of the first to third terminalsA toA and the arrangement of the first to third terminalsB toB in the first supportof the third embodiment may also be changed in a similar manner. 104 100 In the first and second embodiments, a plurality of third terminalsof the first supportmay be provided. 104 104 100 In the third embodiment, one of the third terminalsA andB of the first supportmay be omitted. 112 114 110 113 112 114 In the first and second embodiments, the arrangement of the fourth to sixth terminalstoof the second supportmay be changed arbitrarily. In one example, the fifth terminalmay be disposed between the fourth terminaland the sixth terminalin the Y direction. 112 113 114 114 110 In the third embodiment, the arrangement of the fourth terminal, the fifth terminal, and the sixth terminalsA andB of the second supportmay be changed arbitrarily. 2 92 2 92 1 91 In each embodiment, the thickness Tof the insulating layermay be changed arbitrarily. In one example, the thickness Tof the insulating layermay be equal to or larger than the thickness Tof the first semiconductor substrate. 92 In each embodiment, the material constituting the insulating layermay be changed arbitrarily as long as it is an insulating material. 94 90 In each embodiment, the doped layerBA may be omitted from the switch circuit chip. 92 94 92 94 94 94 91 51 52 94 94 94 94 92 94 91 51 52 94 94 94 90 90 91 94 In each embodiment, the configurations of the insulating layerand the nitride semiconductor layermay be changed arbitrarily. In one example, the insulating layerand the buffer layerA and the doped layerBA of the nitride semiconductor layermay serve as an insulating layer that insulates the first semiconductor substrateand the first and second transistorsand. In this case, the nitride semiconductor layeris formed by the electron transit layerB and the electron supply layerC. In another example, the buffer layerA may include the insulating layer. In this case, the buffer layerA may serve as an insulating layer that insulates the first semiconductor substrateand the first and second transistorsand. In another example, the doped layerBA may be omitted from the nitride semiconductor layer. In another example, the buffer layerA may be omitted from the switch circuit chip. In these cases, the switch circuit chipmay include an insulating layer interposed between the first semiconductor substrateand the electron transit layerB in the Z direction. 90 90 90 97 97 99 90 90 90 93 97 51 97 52 83 80 83 80 9 In each embodiment, the configuration of the switch circuit chip(the first switch circuit chipA and the second switch circuit chipB) may be changed arbitrarily. In one example, source electrodesS may be provided for individual transistor elements. In this case, the source electrodesS may be electrically connected to one another by the source wiringS. In another example, the switch circuit chip(the first switch circuit chipA and the second switch circuit chipB) may include, instead of the second padB, a first source pad electrically connected to the source electrodeS of the first transistorand a second source pad electrically connected to the source electrodeS of the second transistor. The first source pad may be connected to the fourth padD of the control circuit chipby a first source connector such as a wire. The second source pad may be connected to the fourth padD of the control circuit chipby a second source connector such as a wire. In this case, the ninth wire Wmay be omitted. 60 70 10 31 70 60 70 62 60 62 61 62 62 31 62 32 31 21 33 63 63 14 FIG. In the first embodiment, the configurations of the drive circuit chipand the insulating chipmay be changed arbitrarily. In one example, the semiconductor devicemay be configured such that the transformerof the insulating chipis built in the drive circuit chip. That is, the insulating chipmay be omitted. More specifically, as shown in, the fourth insulatorof the drive circuit chipincludes an insulating layerA provided over the fourth semiconductor layerA and a protective layerB provided over the insulating layerA. The transformeris provided in the insulating layerA. The first coilof the transformeris electrically connected to the pulse signal generation circuit. The second coilis electrically connected to the third padC and the fourth padD. 31 31 41 42 In the second embodiment, the position of the transformerin a plan view may be changed arbitrarily. In one example, the transformermay be disposed to overlap with at least one of the rectifier circuitor the gate voltage control circuitin a plan view. 70 31 70 130 31 130 131 132 131 132 131 71 132 131 73 141 141 74 132 73 142 142 75 70 73 73 10 5 7 15 FIG. 4 FIG. 4 FIG. In each embodiment, the configurations of the first insulating element and the second insulating element of the insulating chipare not limited to the transformer, and may be changed arbitrarily. In one example, as shown in, the insulating chipmay include a capacitorinstead of the transformer. The capacitormay include a first electrode plateas the first insulating element and a second electrode plateas the second insulating element. The first electrode plateand the second electrode plateare disposed to face each other in the Z direction. The first electrode plateis disposed closer to the third semiconductor substratein the Z direction than the second electrode plate. The first electrode plateis electrically connected to the first padA by a first connection wiring. A configuration of the first connection wiringmay be the same as that of the first inner wiring(see), for example. The second electrode plateis electrically connected to the third padC by a second connection wiring. A configuration of the second connection wiringmay be the same as that of the first outer wiring(see), for example. In the first and second embodiments, the insulating chipmay omit the second padB and the fourth padD. Accordingly, the semiconductor devicemay omit the fifth wire Wand the seventh wire W. 61 60 61 60 61 In each embodiment, the material constituting the fourth semiconductor substrateof the drive circuit chipmay be changed arbitrarily. In one example, the fourth semiconductor substratemay be formed by a nitride semiconductor. In addition, the drive circuit chipmay use a conductive substrate or an insulating substrate instead of the fourth semiconductor substrate. 71 70 71 70 71 In each embodiment, the material constituting the third semiconductor substrateof the insulating chipmay be changed arbitrarily. In one example, the third semiconductor substratemay be formed by a nitride semiconductor. In addition, the insulating chipmay use a conductive substrate or an insulating substrate instead of the third semiconductor substrate. 81 80 81 80 81 In each embodiment, the material constituting the second semiconductor substrateof the control circuit chipmay be changed arbitrarily. In one example, the second semiconductor substratemay be formed by a nitride semiconductor. In addition, the control circuit chipmay use a conductive substrate instead of the second semiconductor substrate. 70 60 In the first embodiment, the insulating chipmay be disposed at a position adjacent to the drive circuit chipin the Y direction. 70 101 70 80 In the first embodiment, the insulating chipmay be mounted on the first die pad. In this case, the insulating chipmay be disposed at a position adjacent to the control circuit chipin the Y direction. 60 10 1 3 114 110 4 112 63 60 5 113 63 60 In the first embodiment, the drive circuit chipmay be omitted from the semiconductor device. Accordingly, the first to third wires Wto Wmay be omitted. In this case, the sixth terminalmay be omitted from the second support. Further, the fourth wire Wconnects the fourth terminaland the first padA of the drive circuit chipto each other. The fifth wire Wconnects the fifth terminaland the second padB of the drive circuit chipto each other. 110 60 70 10 10 101 80 90 101 120 101 80 90 10 102 104 105 106 102 104 105 106 102 104 101 105 106 101 105 106 120 16 FIG. In each embodiment, the second support, the drive circuit chip, and the insulating chipmay be omitted from the semiconductor device. That is, as shown in, the semiconductor devicemay include the first die pad, the control circuit chipand the switch circuit chipmounted on the first die pad, and the sealing resinthat seals the first die pad, the control circuit chip, and the switch circuit chip. In this case, the semiconductor devicemay include, as external terminals, the first to third terminalsto, the fourth terminal, and the fifth terminal. The first to third terminalstoare the same as those in each embodiment. The fourth terminaland the fifth terminalare disposed on an opposite side of the first to third terminalstowith respect to the first die pad. The fourth terminaland the fifth terminalare disposed to be spaced apart from the first die pad. The fourth terminaland the fifth terminalare partially sealed by the sealing resin. The above-described embodiments may be modified as follows. The above-described embodiments and the following modifications may be implemented in combination to the extent that they are not technically inconsistent.

10 14 15 14 15 14 15 120 The semiconductor deviceincludes a fourteenth wire Wand a fifteenth wire W. The fourteenth wire Wand the fifteenth wire Ware, for example, bonding wires, and are formed of a material including Au, Al, Cu, Ag, or the like. The fourteenth wire Wand the fifteenth wire Ware sealed by the sealing resin.

14 83 80 105 83 105 15 83 80 106 83 106 105 106 41 40 1 FIG. The fourteenth wire Wconnects the first padA of the control circuit chipand the fourth terminalto each other. Thus, the first padA and the fourth terminalare electrically connected to each other. The fifteenth wire Wconnects the second padB of the control circuit chipand the fifth terminalto each other. Thus, the second padB and the fifth terminalare electrically connected to each other. Therefore, the fourth terminaland the fifth terminalare electrically connected to the rectifier circuitof the control circuit(see).

16 FIG. 80 80 80 31 In each embodiment, the connectors for connecting the semiconductor chips to one another or connecting the semiconductor chips to the terminals are not limited to wires, and may be changed arbitrarily. For example, the connectors may be clips. In the modification shown in, the configuration of the control circuit chipmay be changed arbitrarily. In one example, like the control circuit chipof the second embodiment, the control circuit chipmay include a transformer.

One or more of the various examples described in the present disclosure may be combined to the extent that they are not technically contradictory. The term “over” used in the present disclosure includes the meanings of “on” and “above” unless the context clearly indicates otherwise. Thus, for example, the expression “a first element is disposed over a second element” is intended to mean that in a certain embodiment, the first element may be disposed directly on the second element in contact with the second element, and in another embodiment, the first element may be disposed above the second element without being in contact with the second element. In other words, the term “over” does not exclude a structure in which another element is formed between the first element and the second element.

The term Z direction used in the present disclosure does not necessarily need to be the vertical direction, nor completely coincide with the vertical direction. Therefore, in various structures according to the present disclosure, “up” and “down” in the Z axis direction described in the present disclosure are not limited to “up” and “down” in the vertical direction. For example, the X direction may be the vertical direction or the Y direction may be the vertical direction.

Technical ideas that can be recognized from the present disclosure are set forth below. For the purpose of aiding understanding without any limiting purpose, components set forth in the supplementary notes are indicated by the reference numerals of the corresponding components in the above-described embodiments. The reference numerals are shown as examples to aid understanding, and the components set forth in each supplementary note should not be limited to the components indicated by the reference numerals.

10 101 a first die pad (); 90 101 a switch circuit chip () mounted on the first die pad (); 80 101 40 90 a control circuit chip () mounted on the first die pad (), and including a control circuit () configured to control driving the switch circuit chip (); 1 101 90 a first conductive bonding material (SD) configured to bond the first die pad () and the switch circuit chip (); 2 101 80 a second conductive bonding material (SD) configured to bond the first die pad () and the control circuit chip (); 102 103 101 a first terminal () and a second terminal (), which are disposed to be spaced apart from the first die pad (); and 120 1 2 90 80 102 103 a sealing resin () configured to seal at least the first conductive bonding material (SD), the second conductive bonding material (SD), the switch circuit chip (), and the control circuit chip (), and configured to at least partially expose both the first terminal () and the second terminal (), 90 90 a first chip front surface (S); 90 90 a first chip rear surface (R) opposite the first chip front surface (S); 91 90 101 1 a first semiconductor substrate () constituting the first chip rear surface (R) and bonded to the first die pad () by the first conductive bonding material (SD); 92 91 an insulating layer () provided over the first semiconductor substrate (); and 51 52 92 90 90 a first transistor () and a second transistor (), which are provided between the insulating layer () and the first chip front surface (S) in a thickness direction of the switch circuit chip () (Z direction) and have sources connected to each other, wherein the switch circuit chip () includes: 51 52 wherein both the first transistor () and the second transistor () are high electron mobility transistors including nitride semiconductors, and 51 52 101 80 wherein the source of the first transistor () and the source of the second transistor () are electrically connected to the first die pad () via the control circuit chip (). A Semiconductor Device (), Including:

80 80 a second chip front surface (S); 80 80 a second chip rear surface (R) opposite the second chip front surface (S); 81 80 101 2 a second semiconductor substrate () constituting the second chip rear surface (R) and bonded to the first die pad () by the second conductive bonding material (SD); 83 80 a first output pad (C) exposed from the second chip front surface (S); and 83 81 80 a second output pad (D) electrically connected to the second semiconductor substrate () and exposed from the second chip front surface (S), wherein the control circuit chip () includes: 90 93 90 51 52 a first input pad (A) exposed from the first chip front surface (S) and electrically connected to both a gate of the first transistor () and a gate of the second transistor (); and 93 90 51 52 a second input pad (B) exposed from the first chip front surface (S) and electrically connected to the source of the first transistor () and the source of the second transistor (), and wherein the switch circuit chip () includes: 8 83 93 a first connector (W) configured to connect the first output pad (C) and the first input pad (A) to each other; and 9 83 93 a second connector (W) configured to connect the second output pad (D) and the second input pad (B) to each other. wherein the semiconductor device further includes: The semiconductor device of Supplementary Note 1,

104 101 104 120 wherein a portion of the third terminal () is exposed from the sealing resin (). The semiconductor device of Supplementary Note 1 or 2, further including a third terminal () integrated with the first die pad (),

104 102 103 101 The semiconductor device of Supplementary Note 3, wherein the third terminal () is disposed on a side where the first terminal () and the second terminal () are disposed with respect to the first die pad ().

104 102 103 The semiconductor device of Supplementary Note 4, wherein the third terminal () is provided between the first terminal () and the second terminal ().

2 92 1 91 The semiconductor device of any one of Supplementary Notes 1 to 5, wherein a thickness (T) of the insulating layer () is smaller than a thickness (T) of the first semiconductor substrate ().

92 The semiconductor device of any one of Supplementary Notes 1 to 6, wherein the insulating layer () is formed of a material containing AlN.

90 94 92 94 94 94 wherein the buffer layer (A) is formed of a material containing AlGaN, 94 94 wherein the electron transit layer (B) includes a doped layer (BA) formed of a material containing GaN doped with acceptor-type impurities, and 94 94 94 wherein the doped layer (BA) is provided in the electron transit layer (B) and disposed closer to the buffer layer (A). The semiconductor device of Supplementary Note 7, wherein the switch circuit chip () includes a buffer layer (A) provided over the insulating layer (), and an electron transit layer (B) provided over the buffer layer (A),

90 94 94 94 an electron supply layer (C) provided over the electron transit layer (B) and formed by a nitride semiconductor having a larger band gap than the electron transit layer (B); 97 94 a source electrode (S) provided over the electron supply layer (C); 97 97 94 97 a first drain electrode (DA) and a second drain electrode (DB), which are provided over the electron supply layer (C) and disposed to be spaced apart from each other on both sides of the source electrode (S); and 97 94 97 97 97 97 a gate electrode (G) provided over the electron supply layer (C) and disposed between the source electrode (S) and the first drain electrode (DA) and between the source electrode (S) and the second drain electrode (DB) in a plan view. The semiconductor device of Supplementary Note 8, wherein the switch circuit chip () includes:

90 96 97 94 The semiconductor device of Supplementary Note 9, wherein the switch circuit chip () includes a gate layer () interposed between the gate electrode (G) and the electron supply layer (C).

111 101 a second die pad () disposed to be spaced apart from the first die pad (); 70 111 an insulating chip () mounted on the second die pad (); and 6 7 70 80 a relay connector (W, W) configured to electrically connect the insulating chip () and the control circuit chip () to each other, 120 70 6 7 wherein the sealing resin () seals the insulating chip () and the relay connector (W, W). The semiconductor device of any one of Supplementary Notes 1 to 10, further including:

60 111 a drive circuit chip () mounted on the second die pad (); and 4 5 70 60 an intermediate connector (W, W) configured to connect the insulating chip () and the drive circuit chip () to each other, 120 60 4 5 wherein the sealing resin () seals the drive circuit chip () and the intermediate connector (W, W). The semiconductor device of Supplementary Note 11, further including:

70 60 80 101 102 The semiconductor device of Supplementary Note 12, wherein the insulating chip () is disposed between the drive circuit chip () and the control circuit chip () in an arrangement direction (X) of the first die pad () and the second die pad ().

70 70 a third chip front surface (S); 70 70 a third chip rear surface (R) opposite the third chip front surface (S); 71 70 a third semiconductor substrate () constituting the third chip rear surface (R); 72 71 a third insulator () provided over the third semiconductor substrate (); 32 131 72 a first insulating element (/) provided in the third insulator (); and 33 132 72 32 131 a second insulating element (/) provided in the third insulator () and disposed to face the first insulating element (/). The semiconductor device of any one of Supplementary Notes 11 to 13, wherein the insulating chip () includes:

111 101 a second die pad () disposed to be spaced apart from the first die pad (); 60 111 a drive circuit chip () mounted on the second die pad (); and 12 13 80 60 a chip connector (W, W) configured to connect the control circuit chip () and the drive circuit chip () to each other, 60 20 80 wherein the drive circuit chip () includes a drive circuit () configured to output a signal to the control circuit chip (), 40 41 42 41 wherein the control circuit () includes a rectifier circuit () and a gate voltage control circuit () electrically connected to the rectifier circuit (), 80 32 131 20 33 132 32 131 41 wherein the control circuit chip () includes a first insulating element (/) electrically connected to the drive circuit (), and a second insulating element (/) disposed to face the first insulating element (/) and electrically connected to the rectifier circuit (), and 120 60 12 13 wherein the sealing resin () seals the drive circuit chip () and the chip connector (W, W). The semiconductor device of any one of Supplementary Notes 1 to 10, further including:

111 101 a second die pad () disposed to be spaced apart from the first die pad (); 60 111 a drive circuit chip () mounted on the second die pad (); and 12 13 80 60 a chip connector (W, W) configured to connect the control circuit chip () and the drive circuit chip () to each other, 60 32 131 a first insulating element (/); 33 132 32 131 a second insulating element (/) disposed to face the first insulating element (or); and 20 32 131 a drive circuit () configured to output a signal to the first insulating element (/), wherein the drive circuit chip () includes: 80 40 42 41 wherein the control circuit chip () includes, as the control circuit (), a gate voltage control circuit () and a rectifier circuit (), and 120 60 12 13 wherein the sealing resin () seals the drive circuit chip () and the chip connector (W, W). The semiconductor device of any one of Supplementary Notes 1 to 10, further including:

112 114 111 a power supply terminal () and a signal terminal (), which are disposed to be spaced apart from the second die pad (); 113 111 a ground terminal () integrated with the second die pad (); 1 60 112 a power supply connector (W) configured to connect the drive circuit chip () and the power supply terminal () to each other; and 3 60 114 a signal connector (W) configured to connect the drive circuit chip () and the signal terminal () to each other, 120 1 3 112 114 113 wherein the sealing resin () seals the power supply connector (W) and the signal connector (W), and partially seals the power supply terminal (), the signal terminal (), and the ground terminal (). The semiconductor device of Supplementary Note 12 or 13, further including:

112 114 113 101 111 The semiconductor device of Supplementary Note 17, wherein the power supply terminal (), the signal terminal (), and the ground terminal () are disposed on an opposite side of the first die pad () with respect to the second die pad ().

90 93 90 51 93 90 52 10 93 102 a first power supply connector (W) configured to connect the first power supply pad (C) and the first terminal () to each other; and 11 93 103 a second power supply connector (W) configured to connect the second power supply pad (D) and the second terminal () to each other, and wherein the semiconductor device further includes: 120 10 11 wherein the sealing resin () seals both the first power supply connector (W) and the second power supply connector (W). The semiconductor device of any one of Supplementary Notes 1 to 18, wherein the switch circuit chip () includes a first power supply pad (C) exposed from the first chip front surface (S) and electrically connected to a drain of the first transistor (), and a second power supply pad (D) exposed from the first chip front surface (S) and electrically connected to a drain of the second transistor (),

91 The semiconductor device of any one of Supplementary Notes 1 to 19, wherein the first semiconductor substrate () is formed of a material containing Si.

81 The semiconductor device of Supplementary Note 2, wherein the second semiconductor substrate () is formed of a material containing Si.

71 The semiconductor device of Supplementary Note 14, wherein the third semiconductor substrate () is formed of a material containing Si.

32 33 The semiconductor device of any one of Supplementary Notes 14 to 16, wherein both the first insulating element and the second insulating element are a coil (,).

131 132 The semiconductor device of any one of Supplementary Notes 14 to 16, wherein both the first insulating element and the second insulating element are an electrode plate (,).

60 60 60 60 61 60 61 wherein the fourth semiconductor substrate () is formed of a material containing Si. The semiconductor device of any one of Supplementary Notes 12, 13, and 15 to 18, wherein the drive circuit chip () includes a fourth chip front surface (S), a fourth chip rear surface (R) opposite the fourth chip front surface (S), and a fourth semiconductor substrate () constituting the fourth chip rear surface (R), and

10 90 90 90 90 51 52 wherein each of the first switch circuit chip (A) and the second switch circuit chip (B) includes a first transistor () and a second transistor () having sources connected in series to each other, and 51 52 90 90 101 80 wherein the source of the first transistor () and the source of the second transistor () of each of the first switch circuit chip (A) and the second switch circuit chip (B) are electrically connected to the first die pad () via the control circuit chip (). The semiconductor device of any one of Supplementary Notes 1 to 25, wherein the semiconductor device () further includes, as the switch circuit chips, a first switch circuit chip (A) and a second switch circuit chip (B),

80 80 80 80 80 80 80 80 81 80 101 2 wherein each of the first control circuit chip (A) and the second control circuit chip (B) includes a second chip front surface (S), a second chip rear surface (R) opposite the second chip front surface (S), and a second semiconductor substrate () constituting the second chip rear surface (R) and bonded to the first die pad () by the second conductive bonding material (SD), 80 83 80 80 83 81 80 80 80 wherein the first control circuit chip (A) includes a first output pad (CA) exposed from the second chip front surface (S) of the first control circuit chip (A), and a second output pad (DA) electrically connected to the second semiconductor substrate () of the first control circuit chip (A) and exposed from the second chip front surface (S) of the first control circuit chip (A), 80 83 80 80 83 81 80 80 80 wherein the second control circuit chip (B) includes a third output pad (CB) exposed from the second chip front surface (S) of the second control circuit chip (B), and a fourth output pad (DB) electrically connected to the second semiconductor substrate () of the second control circuit chip (B) and exposed from the second chip front surface (S) of the second control circuit chip (B), 90 93 90 51 52 90 93 90 51 52 90 wherein the first switch circuit chip (A) includes a first input pad (AA) exposed from the first chip front surface (S) and electrically connected to both a gate of the first transistor () and a gate of the second transistor () of the first switch circuit chip (A), and a second input pad (BA) exposed from the first chip front surface (S) and electrically connected to the source of the first transistor () and the source of the second transistor () of the first switch circuit chip (A), 90 93 90 51 52 90 93 90 51 52 90 wherein the second switch circuit chip (B) includes a third input pad (AB) exposed from the first chip front surface (S) and electrically connected to both a gate of the first transistor () and a gate of the second transistor () of the second switch circuit chip (B), and a fourth input pad (BB) exposed from the first chip front surface (S) and electrically connected to the source of the first transistor () and the source of the second transistor () of the second switch circuit chip (B), and 8 83 93 a first connector (WA) configured to connect the first output pad (CA) and the first input pad (AA) to each other; 9 83 93 a second connector (WA) configured to connect the second output pad (DA) and the second input pad (BA) to each other; 8 83 93 a third connector (WB) configured to connect the third output pad (CB) and the third input pad (AB) to each other; and 9 83 93 a fourth connector (WB) configured to connect the fourth output pad (DB) and the fourth input pad (BB) to each other; wherein the semiconductor device further includes: The semiconductor device of Supplementary Note 26, wherein the control circuit chip () includes a first control circuit chip (A) and a second control circuit chip (B),

40 40 40 80 40 wherein the first control circuit chip (A) includes the first control circuit (A), 80 40 wherein the second control circuit chip (B) includes the second control circuit (B), 40 41 42 90 wherein the first control circuit (A) includes a first rectifier circuit (A) and a first gate voltage control circuit (A), which are electrically connected to the first switch circuit chip (A), and 40 41 42 90 wherein the second control circuit (B) includes a second rectifier circuit (B) and a second gate voltage control circuit (B), which are electrically connected to the second switch circuit chip (B). The semiconductor device of Supplementary Note 27, wherein the control circuit () includes a first control circuit (A) and a second control circuit (B),

800 10 the semiconductor device () of any one of Supplementary Notes 1 to 28; 821 10 10 a power supply circuit () electrically connected to the semiconductor device () and configured to supply an operating voltage to the semiconductor device (); and 822 10 1 810 10 a signal generation circuit () electrically connected to the semiconductor device () and configured to output a control signal (S) for controlling a load () electrically connected to the semiconductor device (). An insulating switch (), including:

The above descriptions are merely exemplary. Those skilled in the art may recognize that many more possible combinations and replacements can be adopted other than the components and methods (manufacturing processes) listed for the purpose of describing the technique of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and changes that fall within the scope of the present disclosure, including the claims.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the embodiments described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions, and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures.