Semiconductor Structure and Method of Fabricating the Same

Silicon photonic technologies are emerging as important roles for high-speed optical data communication. For instance, optical transceiver modules including high-speed phase modulators, grating couplers and waveguides are used in high-speed optical communication systems. The optical transceiver modules comply with various international standard specifications at communication speeds ranging up to more than 100 Gbps. The performance of the optical transceiver modules is determined by coupling efficiency of the grating couplers in the optical transceiver modules. Although structures of existing grating couplers used for optical transceiver modules have been generally adequate, they are not entirely satisfactory in all aspects.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

1 FIG. 100 100 117 113 115 121 100 105 123 111 101 107 109 105 123 100 103 131 129 illustrates a block diagram of an example optical transceiver. The optical transceivermay include optical modulators, monitor photodiode, and grating couplersand. The optical transceivermay also include electrical devices and circuits including amplifiersand, an analog to digital converter circuit, a digital control circuit, a photodiode(s)and control section. The amplifiersandmay include transimpedance and limiting amplifiers (TIA/LAs), for example. In some embodiments, the optical transceiverfurther includes a photonic diewith a laser assembly. In some embodiments, the laser assembly includes one or more laser, lenses, rotators for directing one or more continuous-wave (CW) optical signals, and one or more laser driver.

100 137 131 133 133 117 133 137 102 133 137 In further embodiments, the optical transceiverincludes an input grating couplerthat is configured to receive an optical signal from the laserand an optical splitterthat is configured to split the optical signal into four roughly equal power optical signals. In various embodiments, the split power signals are transmitted from the optical splitterto the optical modulatorsthrough optical waveguides. In some embodiments, the optical splitteris coupled to the input grating couplerand at least four output waveguides. In some embodiments, the optical splitterincludes a low-loss Y-junction power splitter. In some embodiments, the input grating couplerincludes a single-polarization grating coupler (SPGC). In some embodiments, the SPGC is a one-dimensional (1D) grating coupler.

117 117 109 117 120 115 115 117 113 117 109 In some embodiments, the optical modulatorsinclude Mach-Zehnder or ring modulators, for example, and enable the modulation of the CW laser input signal. The optical modulatorsmay also include high-speed and low-speed phase modulation sections and are controlled by the control sections. In some embodiments, at least one of outputs of each of the optical modulatorsis optically coupled to an optical outputsuch as an optical fiber via the grating coupler. In some embodiments, the grating couplerincludes an SPGC. The other outputs of the optical modulatorsmay be optically coupled to the monitor photodiodethat is configured to provide a feedback path from the output of the optical modulatorsto the control section.

100 121 400 400 121 107 3 FIG. Furthermore, the optical transceivermay also utilize a grating couplerfor receiving optical signals from an optical fiber(see) or an array of optical fibers. In the present embodiments, the grating couplerincludes a polarization splitting grating coupler (PSGC) that utilizes two waveguides (or output waveguides) to transmit received optical signals to the photodiode(s).

100 107 107 107 121 123 125 127 100 101 135 135 In some embodiments, the optical transceiveremploys the photodiode(s), which may be implemented with epitaxial germanium (Ge)/silicon germanium (SiGe) films deposited directly on silicon (Si). In some embodiments, the photodiode(s)may include high-speed heterojunction phototransistors, for example, and may include Ge in the collector and base regions for absorption in the 1200 nm to 1600 nm wavelength range (e.g., in the range of 1310 nm to 1550 nm), and may be integrated on a complementary metal-oxide-semiconductor (CMOS) silicon-on-insulator (SOI) wafer. The photodiode(s)may be configured to convert optical signals received from the grating couplerinto electrical signals that are communicated to a receiver (Rx)which may be configured to combine data streams, and demultiplex the received optical signals. Furthermore, the received optical signals may be amplified by a transimpedance amplifier, for example, and subsequently communicated to a small form-factor pluggable (SFP) interface circuitry. In some embodiments, the optical transceiveralso includes a digital control circuitcoupled to a serial interfaceand configured to communicate received optical data through the serial interface.

1 FIG. 115 137 100 100 115 137 As shown in, the grating couplersandof the optical transceiverenable coupling of light into and out of the integrated circuit comprising the optical transceiver. In some embodiments, the geometry parameters of the grating couplersandmay be parametrized during the routing and layout of the photonically-enabled integrated circuit and optimized based on the performance index.

2 FIG. 3 FIG. 200 200 224 228 114 226 226 228 224 230 400 228 226 224 228 226 228 224 228 206 206 206 206 illustrates a top view of a photonic die, or a portion thereof, according to some embodiments of the present disclosure. The photonic dieincludes at least a grating couplercoupled to a waveguide. The grating couplerincludes a tapered structure(also referred to as a tapered region) that is disposed adjacent to the waveguide. A portion of the grating coupler(e.g., grating linesdescribed below) is configured to receive and modulate optical input from an optical fiber (e.g., optical fiber(or an array thereof); see), and the modulated optical input is subsequently transmitted to the waveguidethrough the tapered structure. In the depicted embodiments, the grating couplerand the waveguideare arranged adjacent to one another along a first lateral direction (e.g., the X axis). In some embodiments, the tapered structureis disposed immediately adjacent to the waveguidealong the first lateral direction. The grating couplerand the waveguideare disposed over (or in) a semiconductor layer. In this regard, the semiconductor layeris alternatively referred to as a device layer(or photonic device layer).

3 FIG. 2 FIG. 1 FIG. 200 206 204 212 200 100 224 115 137 228 102 226 224 230 228 Referring to, which is a cross-sectional view of the photonic diealong line AA’ of, the semiconductor layeris formed over (or provided on) a dielectric layer, which overlays a semiconductor substrate. In some embodiments, the photonic diecorresponds to a portion of the optical transceiveras depicted within each dashed enclosure in. For example, the grating couplermay correspond to the grating couplerorand the waveguidecorrespond to the waveguide. The tapered structureextends between the portion of the grating couplerthat receives and modulates optical input (e.g., the grating linesdescribed below) and the waveguide.

2 FIG. 2 FIG. 224 224 230 230 230 230 230 230 230 230 230 230 230 230 200 230 a b c d e f g h In the present embodiments, referring back to, the grating coupleris a one-dimensional (1D) grating coupler, such as a single-polarization grating coupler. The grating couplerincludes a set of grating lines,,,,,,, and(collectively referred to as the grating lineshereafter). The grating linesare concentrically arranged in a pattern and spaced apart from one another along the first lateral direction. As will be described in detail below, dimensions may vary between the grating linesalong the first lateral direction. It is noted that, although a set of eight grating linesare depicted in, embodiments of the photonic diedescribed in the present disclosure are not limited as such and may include, for example, more or less grating lines.

230 230 232 232 232 232 232 230 232 230 232 230 232 230 232 230 232 230 232 230 232 230 232 232 234 236 234 232 236 226 232 200 230 a h a h a h a a b b c c d d e e f f g g h h In the present embodiments, each of the grating lines-extends along a curve that conforms to a segment of a respective ellipse-(or elliptical shapes-; collectively referred to as ellipseshereafter). For example, the grating lineextends along a curve that conforms to a segment of the ellipse; the grating lineextends along a curve that conforms to a segment of the ellipse; the grating lineextends along a curve that conforms to a segment of the ellipse; the grating lineextends along a curve that conforms to a segment of the ellipse; the grating lineextends along a curve that conforms to a segment of the ellipse; the grating lineextends along a curve that conforms to a segment of the ellipse; the grating lineextends along a curve that conforms to a segment of the ellipse; and the grating lineextends along a curve that conforms to a segment of the ellipse. The ellipsesare arranged in a concentric pattern, where a centerof the concentric pattern(i.e., a center of each of the ellipses) lies on an axis that extends along the first lateral direction. In some embodiments, the centeris disposed in the tapered structure. It is noted that the ellipsesare not physically present in the photonic diebut are rather guides configured to describe shapes and dimensions of their corresponding grating lines.

2 FIG. 232 1 2 1 2 1 2 232 1 2 1 2 1 232 1 2 232 232 1 2 232 232 232 234 232 1 2 h a h g f Still referring to, each of the ellipsesis defined by a major radius Rand a minor radius R. The major radius Rextends along the first lateral direction and the minor radius Rextends along a second lateral direction (e.g., the Y axis) perpendicular to the first lateral direction. The major radius Ris greater than the minor radius Rin magnitude for each of the ellipsessuch that a ratio S of the major radius Rto the minor radius R(S = R/R) is greater than. In this regard, each of the ellipsesis elongated along the first lateral direction relative to the second lateral direction. In the present embodiments, the major radius Rand the minor radius Rboth decrease from the ellipsetowards the ellipsealong the first lateral direction. In other words, the major radius Rand the minor radius Rof the ellipseare each greater than the corresponding dimensions of the ellipse, which are greater than the corresponding dimensions of the ellipse, and so on. In some embodiments, the ratio S remains substantially constant within the concentric pattern. In some embodiments, the ratio S varies between the ellipsesalong the first lateral direction. In some non-limiting examples, the major radius Rand the minor radius Reach range from about 10 nm to about 100 nm. In some non-limiting examples, the ratio S ranges from about 1.5 to about 2.6 corresponding to certain optical input conditions described in detail below.

3 FIG. 2 FIG. 500 500 200 500 400 200 200 402 400 1 1 402 213 200 212 206 1 400 illustrates an apparatus, or a portion thereof, according to some embodiments of the present disclosure. The apparatusincludes at least an embodiment of the photonic dieas shown in a cross-sectional view taken along line AA’ of. The apparatusfurther includes an optical fiberdisposed over the photonic dieand configured to provide optical input to the photonic die. In some embodiments, an incident light emitted through a fiber coreof the optical fiberis applied at an incident angle θ. In the present embodiments, the incident angle θis defined as an angle between an axis along which the fiber coreextends and a normalof the photonic die(i.e., a normal of a top surface of the semiconductor substrateor the semiconductor layer). In some non-limiting examples, the incident angle θmay range from about 0° to about 15°, such as from about 5° to about 15°. In some embodiments, the optical fiberis a single-mode fiber (SMF).

3 4 FIGS.and 4 FIG. 402 224 410 224 410 402 402 402 410 1 2 1 2 1 1 402 213 200 410 1 2 1 2 1 2 410 As shown in, the fiber coreilluminates the grating couplerand forms a beam spotover the grating coupler. The size of the beam spotis related to an effective area of the fiber core, which is proportional to an optical power of the fiber coreupon illumination. The effective area of the fiber corecan be further defined by a mode field diameter (MFD). For example, referring to, the beam spotprovided to the grating coupler has a first radius Dextending along the first lateral direction and a second radius Dextending along the second lateral direction. In various embodiments, the radii Dand Dvary based on the incident angle θdefined herein. For embodiments in which the incident angle θis about 0°(i.e., the fiber coreis substantially parallel to the normalof the photonic die), the beam spotis characterized by a substantially circular shape (not depicted herein), with the first radius Dbeing substantially the same as the second radius D. In this regard, a ratio Q of Dto D(Q = D/D) is about 1 and the beam spotis said to have equal MFDs along the first lateral direction and the second lateral direction.

1 402 213 200 224 200 410 224 1 2 410 1 2 410 4 FIG. In existing technologies, however, the incident angle θis generally tuned to be greater than 0° (i.e., the fiber coreis angled with respect to the normalof the photonic die), such as at about 5° to about 15°, in order to lower the reflection of the incident light off the grating coupler, thereby increasing the coupling efficiency of the photonic die. As such, referring to, the beam spotilluminated onto the grating couplerdoes not have a circular shape but is characterized by a substantially elliptical shape having the first radius Dbeing greater than the second radius D. Consequently, the ratio Q is greater than 1, and the beam spotis said to have unequal MFDs along the first lateral direction and the second lateral direction. The radii Dand Dmay be alternatively referred to as the major radius and the minor radius, respectively, of the beam spot.

230 224 230 410 1 1 2 232 230 410 1 The present disclosure provides photonic dies having a grating coupler with a geometry that more closely matches the geometry of a beam spot illuminating the grating coupler to enhance the coupling efficiency and thus the overall performance of the photonic device. For example, in comparison to existing technologies, the geometry of the grating coupler provided herein increases the peak loss of the grating coupler from about 75% to about 81%, for example. In the present embodiments, the geometry (e.g., the shape and dimensions) of the grating linesof the grating couplerare configured such that a curvature of each of the grating linesat least partially overlaps the curvature of the beam spotat a given incident angle θ. In other words, the major radius Rand the minor radius Rfor each of the ellipsesare configured such that a curvature of each corresponding grating linematches with or otherwise traverses the curvature of the beam spotgenerated at a given incident angle θ.

232 1 2 410 1 2 400 1 1 2 230 In this regard, according to various embodiments, the ratio S of the ellipses, defined as the ratio of the major radius Rto the minor radius R, is configured to closely match or resemble the ratio Q of the beam spot, defined as the ratio of the major radius Dand the minor radius Dfor a given optical fiberat a given incident angle θ. In some embodiments, the ratio S is substantially equal to the ratio Q. In some embodiments, the major radius Rand the minor radius Rof the grating linesare configured such that a difference between the ratio S and the ratio Q is within ± 5% numerically.

1 1 1 1 1 In some embodiments, the value of the ratio S increases as the incident angle θincreases. To obtain values (or ranges of values) of the ratio S based on a given incident angle θ, the ratio Q corresponding to the incident angle θis first determined (e.g., empirically) based on the correlation defined herein. The ratio Q may then be used to determine the ratio S as described above. For embodiments in which the incident angle θranges from about 0° to about 15°, the ratio S may range from about 1 to about 2.6. Specifically, for embodiments in which the incident angle θranges from about 5° to about 15°, the ratio S ranges from about 1.5 to about 2.6.

1 230 410 1 230 224 In some examples, the correlation between the incident angle θand the ratio S of the grating linesmay be determined empirically or by direct measurement. For example, the dimensions of the beam spotcan be directly measured at a given incident angle θ. In some embodiments, the ratio S for each of the grating linesof a grating couplerremains substantially constant within the concentric .

5 FIG. 2 FIG. 200 230 230 250 250 250 250 250 250 250 250 250 250 206 230 226 250 230 230 250 230 230 250 230 230 250 230 230 250 230 230 250 230 230 250 230 230 250 230 225 206 250 225 226 a h a b c d e f g h i a a b a b c b c d c d e d e f e f g f g h g h h i depicts a cross-sectional view of an embodiment of the photonic die, or a portion thereof, taken along the line AA’ of. As shown, the grating lines-are defined (or separated) by recesses,,,,,,,, and(collectively referred to as recesseshereafter) into the semiconductor layer. For example, the grating lineis separated from the tapered structureby the recess; the grating lineis separated from the grating lineby the recess; the grating lineis separated from the grating lineby the recess; the grating lineis separated from the grating lineby the recess; the grating lineis separated from the grating lineby the recess; the grating lineis separated from the grating lineby the recess; the grating lineis separated from the grating lineby the recess; the grating lineis separated from the grating lineby the recess; and the grating lineis separated from an edge portionof the semiconductor layerby the recess, where the edge portionis opposite to the tapered structurealong the first lateral direction.

230 250 224 230 In the present embodiments, structures of the grating linesand the corresponding recessesmay be defined by various shapes and dimensions and may vary within the grating coupler. In some instances, depending on factors such as the peak loss and bandwidth (e.g., narrow bandwidth or wide bandwidth) of the grating coupler, the shapes and the dimensions of the grating linesmay be adjusted accordingly.

5 FIG. 204 206 1 1 In some embodiments, referring to, the dielectric layerhas a thickness BH, and the semiconductor layerhas a thickness Hthat is less than the thickness BH. In some non-limiting examples, the thickness Hmay be about 200 nm to about 500 nm, such as at least about 270 nm and less than about 500 nm. In some non-limiting examples, the thickness BH may be a non-zero value that is less than about 3 µm, such as at least about 2 µm.

5 FIG. 250 250 250 2 250 250 3 2 2 3 1 250 206 2 3 230 a e f i In some embodiments, still referring to, depths of the recessesvary along the first lateral direction, where the depths each extend along a vertical direction (e.g., the Z axis). For example, the recesses-may each have a depth H, while the recesses-may each have a depth Hthat is less than the depth H. As provided herein, the depths Hand Hare both less than the thickness Hsuch that the recessesdo not penetrate through the semiconductor layer. The depths Hand Hmay be alternatively considered as heights of the grating lines.

250 206 230 206 250 250 250 2 250 250 3 2 3 2 3 250 250 2 250 3 a e f i a b The various depths of the recessesmay be achieved by varying parameters of an etching process used to pattern the semiconductor layerto form the grating lines. For example, the various depths are achieved by changing the duration of the etching process applied to different portions of the semiconductor layerthat correspond to positions of the different recesses. In this regard, the recesses-with a greater depth (e.g., the depth H) are etched for a longer duration than the recesses-with a shallower depth (e.g., the depth H). In some non-limiting examples, the depths Hand Hmay each be about 70 nm to about 210nm. In some non-limiting examples, the depth Hmay be at least about 200 nm and the depth Hmay be at least about 100 nm. Though not depicted herein, two adjacent recessesmay be configured with different depths. For example, the recesshas the depth Hand the recesshas the depth H.

250 250 1 250 2 250 3 1 2 3 1 2 3 230 250 250 a b c d i In some embodiments, widths of the recessesmay vary along the first lateral direction, where the widths each extend along the first lateral direction. For instance, the recesshas a width L, the recesshas a width L, and the recesshas a width L, where the width Lis greater than the width L, which is greater than the width L. The widths L, l, and Lmay be alternatively considered as spacings between adjacent grating lines. Though not described in detail herein, the additional recesses-may also have varying widths along the first lateral direction.

5 FIG. 230 230 1 230 2 230 3 1 2 3 230 230 a b c d h In some embodiments, still referring to, widths of the grating linesalso vary along the first lateral direction, where the widths each extend along the first lateral direction. For example, the grating linehas a width W, the grating linehas a width W, and the grating linehas a width W, where the width Wis less than the width W, which is greater than the width W. Though not described in detail herein, the additional grating lines-may also have varying widths along the first lateral direction.

1 2 3 1 2 3 230 1 2 3 230 1 2 3 250 230 1 1 1 2 2 2 3 3 3 In some non-limiting examples, the widths W, W, and Wmay each be about 10 nm to about 600 nm. In some non-limiting examples, a pitch Pn (e.g., P, P, P, etc.) of each grating line, which defined as a sum of a width Wn (e.g., W, W, W, etc.) of each grating lineand a width Ln (e.g., L, L, L, etc.) of each recessadjacent to the grating line, may also vary along the first lateral direction. In the depicted embodiments, for example, Pis a sum of the width Wand the width L; Pis a sum of the width Wand the width L; and Pis a sum of the width Wand the width L. In some non-limiting examples, the pitch Pn is less than about 600 nm for an incident light having a wavelength of about 1310 nm.

230 8 230 260 230 2 262 224 262 212 260 262 2 260 2 2 264 260 264 6 7 FIGS., 6 FIG. 7 8 FIGS.and 7 FIG. 8 FIG. In addition, the grating linemay include various profiles. For example, referring to, and, which each illustrate an example embodiment of a cross-sectional view of a grating line, each sidewallof the grating lineforms a non-zero angle θwith a horizontal surfaceof the grating coupler, where the horizontal surfaceis parallel to a top surface of the semiconductor substrate(not shown). In some embodiments, referring to, the sidewallis substantially perpendicular to the horizontal surfacesuch that the angle θis about 90°. In some embodiments, referring to, top portions of the opposing sidewallsare slanted towards one another such that the angle θis an acute angle (i.e., less than about 90°). In some non-limiting examples, the angle θmay be about 60° to about 90°, such as at least about 85° and less than about 90°. In some embodiments, referring to, a bottom portionof the sidewallhas an angled (or sharp) profile. Alternatively, referring to, the bottom portionhas a rounded (or smooth) profile.

2 3 230 250 224 200 230 230 230 224 200 a h It is noted that the present disclosure does not limit the various dimensions (e.g., the depths Hand H, the widths Wn, and the width Ln, etc.) of the grating linesand the recessesdescribed above to any particular values, nor to any particular patterns of variation. In fact, according to some embodiments of the present disclosure, these dimensions may be intentionally randomized to reduce optical reflection (e.g., optical noise) of the incident light off the grating coupler, thereby improving the coupling efficiency of the photonic die. For example, the widths Wn may first decrease and then increase, while the widths Ln may continuously decrease, from the grating lineto the grating linealong the first lateral direction. While the aforementioned dimensions of the grating linesare not limited to any specific values, a grating coupler, such as the grating coupler, configured with dimensions within the numeric ranges described herein may exhibit enhanced device performance in terms of peak loss of the photonic die, for example.

9 FIG. 9 FIG. 10 21 FIGS.- 600 700 200 600 600 600 700 illustrates a flowchart of a methodto form a semiconductor structure, which may include (or provide) the photonic die, according to one or more embodiments of the present disclosure. It is noted that the methodis merely an example, and is not intended to limit the present disclosure. Accordingly, it is understood that additional operations may be provided before, during, and after the methodof, and that some other operations may only be briefly described herein. In some embodiments, operations of the methodmay be associated with cross-sectional views of the semiconductor structureat various fabrication stages as shown in, which will be discussed in further detail below.

10 FIG. 600 602 202 204 202 206 204 202 204 206 204 202 206 204 202 204 206 202 204 206 2 Referring to, the methodat operationprovides a semiconductor wafer W including a semiconductor substrate(or semiconductor layer), the dielectric layerdisposed on the semiconductor substrate, and the semiconductor layerdisposed on the dielectric layer. The semiconductor wafer W may be a silicon-on-insulator (SOI) wafer including a silicon substrate (e.g., the semiconductor substrate), a silicon dioxide (SiO) layer (e.g., the dielectric layer) disposed on the silicon substrate, and a silicon layer (e.g., the semiconductor layer) disposed on the silicon dioxide layer, where the silicon layer may be a doped layer. The dielectric layermay entirely cover a top surface (or a frontside) of the semiconductor substrate. The semiconductor layermay entirely cover a top surface of the dielectric layer. A thickness of the semiconductor substratemay range from about 50 µm to about 760 µm, a thickness of the dielectric layermay range from about 0.5 µm to about 5 µm, and a thickness of the semiconductor layermay range from about 100 nm to about 5 µm. For example, the thickness of the semiconductor substratemay be about 100 µm, the thickness of the dielectric layermay be about 2 µm, and the thickness of the semiconductor layermay be about 270 nm. The semiconductor wafer W may include other types of semiconductor material(s) and dielectric material(s) arranged in a configuration as described herein.

11 12 FIGS.and 11 FIG. 600 604 206 700 251 206 206 251 206 251 206 Referring to, the methodat operationpatterns the semiconductor layerto define a photonic device region of the semiconductor structure. Referring to, a patterned photoresist layeris formed over the semiconductor wafer W to cover portions of the semiconductor layer. The semiconductor layermay include the photonic device region covered by the patterned photoresist layer. In some embodiments, the semiconductor layerfurther includes an electric device region for forming semiconductor devices (not shown), such as metal-oxide-semiconductor field effect transistors (MOSFETs), capacitors, inductors, resistors, the like, or combinations thereof. The patterned photoresist layermay be formed on the semiconductor layerthrough a photolithography process, which may include spin coating of photoresist material, baking of the photoresist material, exposure of the baked photoresist material and development of the exposed photoresist material.

12 FIG. 206 251 206 204 206 206 204 251 206 Referring to, a patterning process is performed to remove portions of the semiconductor layerthat are exposed by the patterned photoresist layersuch that the semiconductor layeris formed over the dielectric layer. The patterning process of the semiconductor layermay include an etching process, such as a dry etching process, a reactive ion etching (RIE) process, a wet etching process, the like or combinations thereof, for removing the portions of the semiconductor layeruntil portions of the dielectric layerare revealed. After performing the patterning process, the patterned photoresist layeris removed from the semiconductor layerby any suitable process, such as plasma ashing, resist stripping, or the like.

13 15 FIGS.- 13 14 FIGS.and 600 606 206 224 230 226 228 252 206 204 252 206 204 Referring to, the methodat operationfurther patterns the semiconductor layerto form the grating coupler, which includes the grating linesand the tapered structure, and the waveguide. Referring to, a patterned photoresist layeris formed to cover the semiconductor layerand the dielectric layer. The patterned photoresist layermay be formed on the semiconductor layerand the dielectric layerthrough the photolithography process as provided herein.

252 230 224 252 230 252 230 252 230 230 206 2 FIG. 3 FIG. 5 FIG. In the present embodiments, the patterned photoresist layerincludes slit patterns corresponding to the geometry of the set of grating linesof the grating coupler. In one example, the slit patterns defined in the patterned photoresist layermay correspond to an embodiment of an arrangement of the grating linesas depicted in. In another example, the slit patterns defined in the patterned photoresist layermay correspond to an embodiment of an arrangement of the grating linesas depicted in. In yet another example, the slit patterns defined in the patterned photoresist layermay correspond to an embodiment of an arrangement of the grating linesas depicted in. In particular, the shape, position, and/or dimension of the grating linescorrespond to the shape, position, and/or dimension of the slits to be formed in the semiconductor layerby the subsequently patterning process.

14 FIG. 5 FIG. 206 252 206 224 228 204 224 230 226 230 228 206 252 1 206 2 3 Referring to, a patterning process is performed to remove portions of the semiconductor layerthat are exposed by the patterned photoresist layersuch that the semiconductor layerincluding the grating couplerand the waveguideis formed over a top surface of the dielectric layer, where the grating couplerincludes the set of grating linesand the tapered structureextending from the set of grating linestowards the waveguide. The patterning process may include an etching process for removing portions of the semiconductor layerthat are exposed by the patterned photoresist layer. The etching depth of the removal process may be less than the thickness Hof the semiconductor layer. In the present embodiments, the etching depth of the patterning process may correspond to the depths Hand H, for example, which may be about 70 nm to about 210 nm as described herein (see). In some embodiments, the patterning process may include multiple etching processes, such as a dry etching process, a reactive ion etching (RIE) process, a wet etching process, the like, or combinations thereof.

224 228 206 204 252 206 204 15 FIG. After performing the patterning process, the grating couplerand the waveguideare formed in connection with one another along the first lateral direction over a portion of the semiconductor layerthat overlaps with the dielectric layer. Referring to, after performing the patterning process, the patterned photoresist layeris removed from the semiconductor layerand the dielectric layerby any suitable process provided herein.

16 FIG. 254 206 204 206 254 Referring to, a patterned photoresist layermay be then formed to cover the semiconductor layerand portions of the dielectric layerthrough the photolithography process provided herein. In some embodiments, the semiconductor layeris entirely covered by the patterned photoresist layer.

17 FIG. 204 254 204 202 204 202 254 206 204 204 Referring to, a patterning process is performed to remove portions of the dielectric layerthat are exposed by the patterned photoresist layer, resulting in the dielectric layerto have a predetermined pattern over the semiconductor substrate. The patterning process may include an etching process for removing the portions of the dielectric layeruntil portions of the semiconductor substrateare revealed. After performing the patterning process, the patterned photoresist layeris removed from the semiconductor layerand the dielectric layerby any suitable process provided herein. In some embodiments, the patterning process for removing portions of the dielectric layeris omitted.

18 FIG. 600 608 700 272 270 272 272 270 272 1 202 204 206 272 270 1 272 206 270 272 1 270 Referring to, the methodat operationbonds the semiconductor structureto a carrier(alternatively referred to as a carrier wafer, a handle wafer, etc.) using an adhesive layerformed over the carrier. The carriermay include a glass carrier, and the adhesive layermay be a light-to-heat conversion (or light transfer heat conversion, or LTHC) layer adhered to a surface of the carrier. The resulting semiconductor wafer Wincludes the semiconductor substrate, the dielectric layer, and the semiconductor layer, which is temporarily bonded to the carrierthrough the adhesive layer. After the semiconductor wafer Wis temporarily bonded with the carrier, the semiconductor layeris in contact with the adhesive layer. In other words, the carrierand the semiconductor wafer Ware located at opposite sides of the adhesive layer.

19 FIG. 600 610 202 204 204 700 272 204 202 204 a Referring to, the methodat operationremoves the semiconductor substratefrom a backside(or a bottom surface) of the dielectric layersuch that a frontside (or a top surface) of the semiconductor structureis temporarily carried by the carrier, and the backside of the dielectric layeris revealed. In some embodiments, the semiconductor substrateis removed from the dielectric layerthrough a laser lift-off process, a backside etching process, a grinding process, or the like. The grinding process may include a mechanical grinding process, a chemical-mechanical polishing (CMP) process, the like, or combinations thereof.

20 FIG. 600 612 212 212 204 212 204 a Referring to, the methodat operationbonds a frontside(or top surface) of the semiconductor substrate(or semiconductor layer) to the backside of the dielectric layer. In some embodiments, the frontside of the semiconductor substrateis bonded to the backside of the dielectric layerthrough a wafer-to-wafer fusion bonding process, a hybrid bonding process, or the like. The bonding temperature of the wafer-to-wafer fusion bonding process may range from about 200° C to about 600° C.

21 FIG. 600 614 272 270 700 272 270 206 700 270 272 206 608 614 700 Referring to, the methodat operationperforms a de-bonding process to remove the carrierand the adhesive layerfrom the semiconductor structure. The carrierand the adhesive layermay be de-bonded from the semiconductor layerby irradiating the semiconductor structurewith laser, which heats and subsequently releases the adhesive layerand the carrierfrom the semiconductor layer. In various embodiments of the present disclosure, the operationstodescribed herein are optional and may be omitted for the fabrication of the semiconductor structure.

600 616 700 200 212 204 212 206 204 206 224 228 224 230 200 21 FIG. 3 FIG. 2 3 5 FIGS.,, and/or The methodat operationmay perform additional operations. For example, still referring to, the semiconductor structuremay be singulated along scribe lines SL to obtain the photonic die, which includes the semiconductor substrate, the dielectric layerover the semiconductor substrate, and semiconductor layerover the dielectric layer, as depicted in. The semiconductor layerincludes the grating couplerconnected (or coupled) to the waveguide. In the present embodiments, the grating couplerincludes the set of grating linesas depicted in. The photonic diemay be further packaged, integrated with other dies (e.g., electric dies, photonic dies, etc.), or otherwise processed to form a semiconductor device.

1 2 1 In one aspect, the present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor layer. The semiconductor structure includes a grating coupler disposed on the semiconductor layer. The semiconductor structure further includes a waveguide disposed on the semiconductor layer and adjacent to the grating coupler along a lateral direction. The grating coupler includes a plurality of grating lines. Each of the grating lines extends along a curve that conforms to a segment of an ellipse, where the ellipse is defined by a radius Rand a radius Rthat is less than the radius R.

In another aspect, the present disclosure provides a photonic die. The photonic die includes a substrate. The photonic die further includes a device layer disposed over the substrate. The device layer includes a grating coupler and a waveguide adjacent to the grating coupler. The grating coupler includes a plurality of grating lines arranged in a concentric pattern on the device layer along a lateral direction. Each of the grating lines extends along a segment of an ellipse, where the ellipse is defined by a major radius and a minor radius. A ratio of the major radius to the minor radius is greater than one.

In yet another aspect, the present disclosure provides a method that includes providing a first semiconductor layer over a dielectric layer, where the dielectric layer includes a bottom surface. The method includes forming a grating coupler and a waveguide in the first semiconductor layer. The grating coupler includes a plurality of curved grating lines spaced apart from one another in a lateral direction. Each of the curved grating lines extends along a segment of an ellipse, where the ellipse is defined by a first radius and a second radius that is different from the first radius. The method includes providing a second semiconductor layer having a second top surface. The method further includes bonding the bottom surface to the second top surface to form a semiconductor structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.