Configurable Reference Voltage Generator

Computing and other electronic devices play integral roles in manufacturing, communication, transportation, healthcare, commerce, social interaction, entertainment, and other services. For example, electronic devices power the server farms that provide cloud-based, distributed computing functionality for commerce, communication, and artificial intelligence (AI). Electronic devices are also embedded in many different types of modern equipment, from medical devices to home appliances and from vehicles to industrial tools. Personal electronic devices enable portable video viewing and convenient access to intelligent digital assistants. Additionally, one versatile electronic device—the smartphone—has practically become a necessity to have within arm's reach.

To provide these diverse functionalities, electronic devices typically include various circuitries, such as reference voltage generators. Reference voltage generators are used to generate relatively stable and precise reference voltage signals for other components within an integrated circuit (IC). For example, a reference voltage is often utilized by voltage regulator circuits to maintain a constant output voltage irrespective of changes in the supply voltage or load conditions. Accordingly, computer engineers, electrical engineers, and other designers of electronic devices endeavor to improve the operation of reference voltage generators to support their use in electronic devices.

This document describes hardware and techniques that enable the components of electronic devices to operate with a stable reference voltage. Reference voltage generators are employed to generate a reference voltage (or “voltage reference”) for use by components of an integrated circuit within an electronic device. Such components include voltage regulators, sensors, and analog-to-digital converters (ADCs), just to name a few examples. These components operate more accurately using a reference voltage that is stable over process, voltage, and temperature variations. Reference voltage generators that rely on bandgap physics are becoming less feasible as process nodes become smaller and as gate-all-around (GAA) devices are adopted.

Implementations described herein provide for a reference voltage generator for generating a reference voltage that need not rely on bandgap effects and that can operate reliably at voltages below one volt, which better accommodates GAA processes. Moreover, multiple described reference voltage generator configurations provide stability under variations with process, voltage, and/or temperature. To do so, the reference voltage generator combines a first voltage that is complementary to absolute temperature with a second voltage that is proportional to absolute temperature. Different configurations can counteract fluctuations in a supply voltage and/or variations in process across different temperatures.

In described implementations, a configurable reference voltage generator is provided having components that may be selectably configured and/or tuned to provide an improved reference voltage. In some implementations, one or more cascode transistors are provided within one or more current branches of a reference voltage generator to account for supply voltage changes while generating a more stable reference voltage. In some cases, the cascode transistors can be biased with different bias voltages, or the bias voltage for the cascode transistors may be dependent on a value of the supply voltage. In other implementations, a variable resistor or a transistor with a tunable quantity of stacked gates can be adjusted (e.g., during a circuit testing phase) to account for process variations and thereby increase an accuracy of the generated reference voltage. In these manners, a stable reference voltage can be generated without relying on bandgap physics and/or within an environment having smaller devices, including GAA transistor devices.

In example implementations, an apparatus for generating a reference voltage includes a current generator having at least one current branch configured to receive a supply voltage. The at least one current branch includes at least one cascode transistor configured to receive a first bias voltage value. The apparatus also includes a first voltage generator configured to receive a first bias current from the current generator and provide a first voltage value. The first voltage value is complementary to absolute temperature. The apparatus further includes a second voltage generator configured to receive a second bias current from the current generator and provide a second voltage value. The second voltage value is proportional to absolute temperature. The apparatus is configured to provide a third voltage value based on a combination of the first voltage value and the second voltage value.

In example implementations, an apparatus for generating a reference voltage includes a current generator having a first current branch, a second current branch, a third current branch, and a fourth current branch. The first current branch is configured to receive a supply voltage, with the first current branch including a first cascode transistor configured to receive a first bias voltage. The second current branch is also configured to receive the supply voltage, with the second current branch including a second cascode transistor configured to receive the first bias voltage. The third current branch is additionally configured to receive the supply voltage, with the third current branch including a third cascode transistor configured to receive the first bias voltage. The fourth current branch is further configured to receive the supply voltage, with the fourth current branch including a fourth cascode transistor configured to receive the first bias voltage. The apparatus also includes a first voltage generator configured to receive a first bias current from the fourth cascode transistor and provide a first voltage value, with the first voltage value being complementary to absolute temperature. The apparatus further includes a second voltage generator configured to receive a second bias current from the third cascode transistor and provide a second voltage value, with the second voltage value being proportional to absolute temperature. The apparatus is configured to generate the reference voltage based on the first voltage value and the second voltage value.

In example implementations, a method for generating a reference voltage includes receiving, by at least one current branch of a current generator, a supply voltage, with the at least one current branch including at least one cascode transistor. The method also includes receiving, by the least one cascode transistor, a first bias voltage value. The method additionally includes receiving, by a first voltage generator, a first bias current from the current generator. The method includes providing, by the first voltage generator, a first voltage value, with the first voltage value being complementary to absolute temperature. The method also includes receiving, by a second voltage generator, a second bias current from the current generator. The method additionally includes providing, by the second voltage generator, a second voltage value, with the second voltage value being proportional to absolute temperature. The method further includes generating the reference voltage based on a combination of the first voltage value and the second voltage value.

Electronic devices provide features and perform functions to make important contributions to modern society, such as those related to communication, safety, manufacturing, and content creation. Each electronic device often includes one or more integrated circuits (ICs), and a given IC can include multiple components. These components within an IC often use a reference voltage generator to provide a stable reference voltage over process, voltage, and temperature variations for proper operation of these components, such as voltage regulators, processors, and sensors. Errors introduced in the reference voltage provided to the voltage regulator can be amplified and reflected in the regulated supply voltage provided by the voltage regulator to downstream components.

An example type of reference voltage circuit used in ICs is a bandgap reference voltage circuit. A bandgap reference voltage circuit is typically constructed using bipolar devices such as bipolar junction transistors (BJTs). The bandgap reference voltage circuit can provide a relatively constant voltage with minimal fluctuation from variations of power supply, electrical load, and temperature over time. The transistor devices typically used in the bandgap reference voltage circuit are “non-core voltage devices” that operate at higher, non-core voltage levels (e.g., 1.2 volt (V)) and that may be suitable for driving I/O operations beyond the core of the circuit, including off-chip. Such non-core voltage devices with these voltage levels may not be available in cutting-edge technology nodes.

Further, it is anticipated that bipolar transistors, such as BJTs, may eventually be replaced by more advanced technologies. Analog circuit designers, in particular, confront more formidable design challenges as transistor device technology advances. The introduction of the gate-all-around (GAA) fabrication process for transistor devices has provided digital circuits with higher speeds and densities. The GAA transistor structure allows for the gate to be in contact with the channel region on all sides, allowing for improved channel control. However, the GAA creates significant design challenges for analog designers. Notably, in the GAA process, no “true” 1.2V devices are available due to GAA device constraints, such as the maximum allowed voltage between gate and source terminals (Vas), gate and drain terminals (VDG), and drain and source terminals (VDS).

If the goal were to scale the transistors and migrate all higher-voltage or non-core device designs to using GAA core transistors at lower supply voltages, significant challenges are faced in the design of reference voltage generator circuits. If, on the other hand, the goal were to use GAA core transistors to operate the reference voltage circuit under an I/O-level supply voltage of 1.2V or higher, many GAA transistors would be operating outside of their safe operation area (SOA), at least during the power down state. Additionally, in some designs, digital logic operates at the I/O or other higher-voltage domain for dynamic element matching and chopping to reduce offset and noise. However, implementing the I/O or other higher-voltage logic with the GAA process presents challenges due to the SOA concerns.

Alternatively, operating the reference voltage circuit at a lower supply voltage, thereby adhering to the SOA requirements, would introduce significant headroom limitations. This would result in operating the BJTs at a significantly reduced current density leading to potential issues with proper circuit operation. One of these issues is that the accuracy of the device model may be compromised because semiconductor foundries typically intend for BJTs to operate at a specific current density based on a fabrication specification. Another issue is that the reference voltage circuit may exhibit an unacceptably slow start-up time, thus failing to meet design specifications for the IC. In addition, the area occupied by BJT-based reference voltage circuits tends to be significant, and this conflicts with a constant drive to minimize the area dedicated to analog circuit components while preserving the performance and addressing cost considerations.

In example implementations as described herein, a reference voltage generator architecture is provided that differs from ones that rely on device bandgap voltage. Instead, the reference voltage generator combines a complementary to absolute temperature (CTAT) voltage component and a proportional to absolute temperatures (PTAT) voltage component to produce a reference voltage. This architecture offers advantages over the device bandgap voltage architecture including the ability to operate under very low supply voltages making it suitable for low-power applications. Further, this architecture offers a compact design as compared to BJT-based solutions, and this enables efficient utilization of area on an IC chip and space within a housing of an electronic device.

In example implementations, a reference voltage generator includes a current generator component, a CTAT voltage generator component, and a PTAT voltage generator component. The CTAT voltage generator component receives a first bias current from the current generator component and provides a CTAT voltage. The PTAT voltage generator component receives a second bias current from the current generator component and provides a PTAT voltage. A CTAT voltage has a negative temperature coefficient such that the value of the CTAT voltage decreases as the operational temperature increases. A PTAT voltage has a positive temperature coefficient such that the value of the PTAT voltage increases as the operational temperature increases. The reference voltage generator combines the CTAT voltage and the PTAT voltage to produce a reference voltage that is more stable at different temperature ranges (e.g., that exhibits a measure of temperature independence). In some implementations, the current generator component includes a current mirror circuit. In some cases, the values of the first bias current and the second bias current are substantially the same based on being mirrored from the same current. In other cases, the values of the first bias current and the second bias current are different.

In example implementations, the current generator component includes one or more current branches. At least one of the current branches includes at least one cascode transistor to improve the supply voltage regulation of the current branches of the current generator component as described herein. Thus, described implementations can accommodate supply voltage fluctuations while still maintaining a stable reference voltage. Other example implementations include a tunable resistor or tunable number of stacked gates for a transistor within the reference voltage generator. These components can be tuned to improve the temperature behavior of the reference voltage across process variations.

In these manners, a reference voltage generator for generating a stable reference voltage is provided in which the behavior of the reference voltage is more stable across changes to the supply voltage and/or process variations. The described hardware and techniques can be implemented across a single reference voltage generator circuit within a single IC or across multiple reference voltage generator circuits. These and other example implementations are described herein.

1 FIG. 100 102 104 104 106 108 106 110 110 108 106 110 108 104 106 106 102 104 106 106 102 illustrates, atgenerally, an example apparatuswith at least one integrated circuit(IC) that includes a reference voltage generatorand a voltage regulator. As shown, the reference voltage generatorgenerates a reference voltageand provides the reference voltageto the voltage regulator. However, the reference voltage generatorcan provide the reference voltageto one or more other components instead of or in addition to the voltage regulator. The integrated circuitcan include or realize a system-on-chip(SoC). The apparatus, the integrated circuit, the SoC, and/or the reference voltage generatorcan implement a configurable reference voltage generator as described herein. The apparatusmay, however, be implemented as any suitable computing or other electronic device as described herein.

102 102 102 1 102 2 102 3 102 4 102 5 102 6 102 7 Examples of the apparatusinclude a mobile electronic device or mobile device, mobile communication device, modem, cellular or mobile phone, mobile station, gaming device, navigation device, media or entertainment device (e.g., a media streamer or gaming controller), laptop computer, desktop computer, tablet computer, smart appliance, vehicle-based electronic system, wearable computing device (e.g., clothing, watch, or reality-altering glasses), Internet of Things (IoTs) device, sensor, stock management device, electronic portion of a machine or piece of equipment (e.g., a vehicle or robot), memory storage device (e.g., a solid-state drive (SSD)), server computer or portion thereof (e.g., a server blade or rack or another part of a datacenter), and the like. Illustrated examples of the apparatusinclude a tablet device-, a smart television-, a desktop computer-, a server computer-, a smartwatch-, a smartphone (or document reader)-, and intelligent glasses-.

102 104 104 106 108 In example implementations, the apparatusincludes at least one integrated circuit. The integrated circuitcan be part of or realized as a chip, a package, a module, an assembly, or at least one printed circuit board (PCB) (not shown). Examples of a PCB include a flexible PCB, a rigid PCB, a single or multi-layered PCB, a surface-mounted or through-hole PCB, combinations thereof, and so forth. In some instances, one or more integrated circuit (IC) chips can be mounted on a PCB, and the reference voltage generatorand/or voltage regulatorcan be disposed on the PCB to couple two or more chips together.

Each IC chip can be realized as a general-purpose processor, a microcontroller, an application-specific IC (ASIC), and so forth. Other examples of IC chips include a system-on-a-chip (SoC), a security-oriented IC chip, a memory chip, a communications IC chip (e.g., a modem or radio-frequency IC), a graphics processor, an artificial intelligence (AI) accelerator, sensor chips, combinations thereof, and so forth. Sensor chips may include, for example, an accelerometer, a camera or other light sensor, a thermometer or temperature sensor, a satellite positioning system (e.g., a satellite positioning system (SPS) like a Global Positioning System (GPS)) chip, and the like. An integrated circuit chip can be packaged alone or together with other IC chips.

2 FIG. 106 106 202 202 204 204 206 206 202 212 212 206 206 214 214 208 216 is a block diagram illustrating an example reference voltage generatorfor producing a reference voltage. As shown, the reference voltage generatorincludes a current generator component(or current generator), a PTAT voltage generator component(or PTAT voltage generator), and a CTAT voltage generator component(or CTAT voltage generator). The current generator componentis configured to generate a first bias current (I.BIAS)and provide the first bias current (I.BIAS)to the CTAT voltage generator component. The CTAT voltage generator componentgenerates a first voltage valuehaving a characteristic of being complementary to the absolute temperature (CTAT). The first voltage valuecan be multiplied by a CTAT gainto produce a CTAT voltage value (V.CTAT).

202 218 218 204 204 220 220 210 222 216 222 110 208 210 110 206 204 208 210 216 222 110 The current generator componentis further configured to generate a second bias current (I.BIAS)and provide the second bias current (I.BIAS)to the PTAT voltage generator component. The PTAT voltage generator componentgenerates a second voltage valuehaving a characteristic of being proportional to absolute temperature (PTAT). The second voltage valuecan be multiplied by a PTAT gainto produce a PTAT voltage value (V.PTAT). The V.CTAT voltage valueand the V.PTAT voltage valuecan be combined to produce a reference voltage. For example, the two voltage values can be added together (including adding a negative of one of the voltage values to the other voltage value). By choosing an appropriate value of the CTAT gainor an appropriate value of the PTAT gain(including by choosing two appropriate gain values in accordance with a permitted, but optional, inclusive-or interpretation of the word “or”), the resultant reference voltagemay be tuned to be substantially constant over the desired temperature range of operation. For instance, at least one gain may be established such that as one voltage value increases by a given amount over a particular temperate range, the other voltage value decreases by the given amount over the particular temperature range. Accordingly, in example implementations, the CTAT voltage generator component, the PTAT voltage generator component, the CTAT gain, the PTAT gain, and resulting values of V.CTATand V.PTATare architected to provide a reference voltagehaving improved temperature stability.

3 1 FIG.- 204 106 204 304 306 308 306 308 304 302 304 306 306 306 308 306 306 308 310 is a circuit diagram illustrating an example PTAT voltage generator componentof a reference voltage generator. As shown, the PTAT voltage generator componentincludes a first current source, a first N-type metal-oxide-semiconductor (NMOS) transistorand a second NMOS transistor. The first and second NMOS transistorsandmay be realized as field-effect transistors (FETs) as depicted. An input terminal of the first current sourceis connected to a supply voltage (V.Supply), and an output terminal of the first current sourceis connected to a drain terminal of the first NMOS transistor. The drain terminal of the first NMOS transistoris further connected to a gate terminal of the first NMOS transistorand a gate terminal of the second NMOS transistor. Accordingly, the first NMOS transistoris connected in a diode configuration. A source terminal of the first NMOS transistoris connected to a drain terminal of the second NMOS transistor, and a source terminal of the second NMOS transistor is connected to a ground.

304 302 312 304 312 306 306 308 314 306 308 314 The first current sourceis configured to receive V.Supplyand generate a first bias current (I.BIAS1). The first current sourcealso provides the first bias currentto the drain terminal of the first NMOS transistor. The first NMOS transistorand the second NMOS transistoroperate to generate a PTAT voltage (V.P)at the source terminal of the first NMOS transistorand at the drain terminal of the second NMOS transistor. The PTAT voltage (V.P)has a positive temperature coefficient such that the value of the voltage increases as the temperature increases.

3 2 FIG.- 206 106 206 316 318 318 316 302 316 318 318 318 318 318 310 is a circuit diagram illustrating an example CTAT voltage generator componentof the reference voltage generator. As shown, the CTAT voltage generator componentincludes a second current sourceand a third N-type metal-oxide-semiconductor (NMOS) transistor. The third NMOS transistormay be realized as a field-effect transistor (FET) as depicted. An input terminal of the second current sourceis connected to the supply voltage (V.Supply), and an output terminal of the second current sourceis connected to a drain terminal of the third NMOS transistor. The drain terminal of the third NMOS transistoris further connected to a gate terminal of the third NMOS transistor. Accordingly, the third NMOS transistoris connected in a diode configuration. A source terminal of the third NMOS transistoris connected to a ground.

316 302 320 316 320 318 318 322 318 318 322 The second current sourceis configured to receive V.Supplyand generate a second bias current (I.BIAS2). The second current sourceprovides the second bias currentto the drain terminal of the third NMOS transistor. The third NMOS transistoroperates to generate a CTAT voltage (V.C)between the gate terminal of the third NMOS transistorand the source terminal of the third NMOS transistor. The CTAT voltage (V.C)has a negative temperature coefficient such that the value of the voltage decreases as the temperature increases.

4 FIG. 2 3 1 3 2 FIGS.,-, and- 3 1 FIG.- 3 2 FIG.- 4 FIG. 3 2 FIG.- 400 400 204 206 318 306 308 400 314 322 402 318 is a circuit diagram illustrating an example reference voltage generator portionincluding the circuit components of. The example reference voltage generator portionincludes the PTAT voltage generator componentofand the CTAT voltage generator componentof. In the circuit of, the source terminal of the third NMOS transistoris connected to the source terminal of the first NMOS transistor(and the drain terminal of the second NMOS transistor) rather than to ground as depicted in. During operation of the reference voltage generator portion, the PTAT voltage (V.P)and the CTAT voltage (V.C)are combined to generate a temperature-compensated reference voltage (V.TC)at the drain terminal of the third NMOS transistor.

5 1 FIG.- 5 2 FIG.- 5 1 FIG.- 2 FIG. 500 500 500 202 204 206 202 530 503 503 202 503 503 503 503 202 1 204 206 is a circuit diagram illustrating an example reference voltage generator circuit.is a circuit diagram illustrating the example reference voltage generator circuitas inwith examples of the components ofoverlaid thereon. As shown, the reference voltage generator circuitcan include a current generator, a PTAT voltage generator, and a CTAT voltage generator. The current generatorcan include a current mirrorhaving four current branchesA-D. The “core” of the current generatorincludes the current branchesA andB. The current branchesC andD, as indicated at-, mirror the generated current over to the PTAT voltage generatorand the CTAT voltage generator, respectively.

204 514 516 206 518 202 503 504 506 510 504 520 504 506 504 504 506 510 510 512 The PTAT voltage generatorincludes a first NMOS transistorand a second NMOS transistor. The CTAT voltage generatorincludes a third NMOS transistor. As part of the current generator, a first current branchA includes a first p-type metal-oxide-semiconductor (PMOS) transistorA, a fourth NMOS transistor, and a resistor. A source terminal of the first PMOS transistorA is connected to a supply voltage (V.DD), and a drain terminal of the first PMOS transistorA is connected to a drain terminal of the fourth NMOS transistor. A gate terminal of the first PMOS transistorA is coupled to the drain terminal of the first PMOS transistorA. A source terminal of the fourth NMOS transistoris coupled to a first terminal of the resistor, and a second terminal of the resistoris coupled to a ground.

503 202 504 508 504 520 504 508 508 508 508 512 508 506 A second current branchB of the current generatorincludes a second PMOS transistorB and a fifth NMOS transistor. A source terminal of the second PMOS transistorB is connected to the supply voltage (V.DD), and a drain terminal of the second PMOS transistorB is connected to a drain terminal of the fifth NMOS transistor. A gate terminal of the fifth NMOS transistoris connected to the drain terminal of the fifth NMOS transistor. A source terminal of the fifth NMOS transistoris connected to the ground. The gate terminal of the fifth NMOS transistoris further connected to the gate terminal of the fourth NMOS transistor.

503 202 504 514 204 516 204 504 520 504 514 514 514 516 514 516 516 512 A third current branchC of the current generatorincludes a third PMOS transistorC, the first NMOS transistorof the PTAT voltage generator, and the second NMOS transistorof the PTAT voltage generator. A source terminal of the third PMOS transistorC is connected to the supply voltage (V.DD), and a drain terminal of the third PMOS transistorC is connected to a drain terminal of the first NMOS transistor. A gate terminal of the first NMOS transistoris connected to the drain terminal of the first NMOS transistorand a gate terminal of the second NMOS transistor. A source terminal of the first NMOS transistoris connected to a drain terminal of the second NMOS transistor. A source terminal of the second NMOS transistoris connected to the ground.

503 202 504 518 206 504 520 504 518 518 518 518 516 514 518 518 A fourth current branchD of the current generatorincludes a fourth PMOS transistorD and the third NMOS transistorof the CTAT voltage generator. A source terminal of the fourth PMOS transistorD is connected to the supply voltage (V.DD), and a drain terminal of the fourth PMOS transistorD is connected to a drain terminal of the third NMOS transistor. A gate terminal of the third NMOS transistoris connected to the drain terminal of the third NMOS transistor. A source terminal of the third NMOS transistoris connected to the drain terminal of the second NMOS transistorand to the source terminal of the first NMOS transistor. The drain terminal of the third NMOS transistoris further connected to a gate terminal of the third NMOS transistor.

504 504 506 508 510 514 516 503 518 503 514 516 503 518 503 504 504 506 508 506 508 510 503 503 The first PMOS transistorA, the second PMOS transistorB, the fourth NMOS transistor, the fifth NMOS transistor, and the resistorare configured to generate respective bias currents for the first NMOS transistorand the second NMOS transistorin the third current branchC and the third NMOS transistorin the fourth current branchD. The first NMOS transistorand the second NMOS transistorin the third current branchC are configured to generate a PTAT voltage. The third NMOS transistorin the fourth current branchD is configured to generate a CTAT voltage. In some implementations, the first PMOS transistorA and the second PMOS transistorB are of the same size such that the currents flowing through the fourth NMOS transistorand the fifth NMOS transistorare substantially the same. In at least some of such implementations, the fourth NMOS transistorand the fifth NMOS transistorare of a different size from each other. These different physical sizes produce a voltage differential between the gate-source voltages (Vgs) of the two devices. The voltage differential is produced across the resistorwhich generates a current that is mirrored across the third current branchC and the fourth current branchD.

500 522 514 204 518 206 522 514 516 518 524 518 522 524 526 518 During operation of the example reference voltage generator circuit, a PTAT voltage (V.P)is provided from the source terminal of the first NMOS transistorof the PTAT voltage generatorto the source terminal of the third NMOS transistorof the CTAT voltage generator. The PTAT voltage (V.P)has a PTAT characteristic due to a threshold voltage of the first NMOS transistorand the second NMOS transistorhaving a PTAT characteristic. The third NMOS transistorproduces a CTAT voltage (V.C)between the gate terminal and the source terminal of the third NMOS transistor. The PTAT voltage (V.P)is combined with the CTAT voltage (V.C)to produce a reference voltage (V.REF)at the gate and source terminals of the third NMOS transistor.

500 500 500 The reference voltage provided by the example reference voltage generator circuitdeparts from a conventional bandgap reference voltage generator by combining a CTAT voltage with a PTAT voltage. An advantage offered by the example reference voltage generator circuitis that it can operate under low supply voltage, making it suitable for low-power applications. Another advantage offered by the example reference voltage generator circuitis that it provides a compact design compared to BJT-based solutions, enabling efficient utilization of circuit area.

500 500 526 500 However, the topology of the example reference voltage generator circuitmay exhibit problems under certain circumstances. For instance, the example reference voltage generator circuitmay produce inconsistence reference voltages in response to changing supply voltage levels. In an example, as the supply voltage changes, the output voltage (V.REF) can fluctuate appreciably. Since this reference voltage may be subjected to, for example, a dynamic-voltage-frequency-scaling (DVFS) supply voltage, significant supply variations can be expected in such situations. Substantial reference voltage variations may introduce significant errors in downstream components that are powered based on the reference voltage. For example, if the example reference voltage generator circuitis employed in a current sensor or temperature sensor circuit, these fluctuations may translate into non-negligible sensor measurement errors.

500 500 The reference voltage provided by the example reference voltage generator circuitexhibits some temperature dependency due to its reliance on PTAT and CTAT voltage-temperature coefficient cancellation rather than a fundamental bandgap voltage. Consequently, it is possible that the example topology of the reference voltage generator circuitmay yield favorable outcomes in one process corner in a given temperature range and less satisfactory outcomes in other process corners. For example, at the typical process corners and slow-slow process corners, the temperature behavior of the reference voltage may be substantially stable over a given temperature range, while the fast-fast process corner temperature curve may exhibit an upward bend at high temperatures. Although calibration for this temperature variation is conceivable, significant complexity would be introduced due to the differing shapes of the temperature curves at different process corners.

6 11 FIGS.to This document instead describes different configurations for a reference voltage generator that can account for different process corners. Generally, described implementations configure the example reference voltage generator in different manners such that a stable reference voltage is produced while accommodating supply voltage fluctuations and process variations across a range of temperatures. These different configurations can be used individually or in any combination with each other and are described with reference to.

6 FIG. 5 FIG. 600 600 500 604 503 504 506 604 504 604 506 604 606 is a circuit diagram illustrating another example reference voltage generator circuitincluding a cascode transistor to improve operation under supply voltage changes. The reference voltage generator circuitis similar to the reference voltage generator circuitofexcept that a first cascode NMOS transistoris inserted in the first current branchA (e.g., in series) between the first PMOS transistorA and the fourth NMOS transistor. In particular, a drain terminal of the first cascode NMOS transistoris connected to the drain terminal of the first PMOS transistorA, and a source terminal of the first cascode NMOS transistoris connected to the drain terminal of the fourth NMOS transistor. A gate terminal of the first cascode NMOS transistoris connected to a first bias voltage (V.BIAS).

604 506 604 506 520 506 606 604 604 The first cascode NMOS transistorfunctions to improve supply voltage regulation by protecting the current source provided by the fourth NMOS transistor. In operation, the first cascode NMOS transistorreduces the impact of supply voltage changes by maintaining the drain-source voltage of the fourth NMOS transistorat a substantially constant voltage regardless of the supply voltage (V.DD). Instead, the voltage maintained at the fourth NMOS transistoris dependent upon the value of the first bias voltage (V.BIAS)and is equal to V.BIAS minus the Vgs of the first cascode NMOS transistor. In some cases, the ability of the reference voltage generator to counteract supply voltage changes may be improved by approximately 20% by including the first cascode NMOS transistor.

604 504 506 604 600 600 6 FIG. Although the first cascode NMOS transistoris shown in the example implementation ofas being coupled between the first PMOS transistorA and the fourth NMOS transistor, in other implementations the first cascode NMOS transistormay be positioned at other suitable locations in the reference voltage generator circuit. In addition, although the reference voltage generator circuitis shown as utilizing PMOS and NMOS FET technologies, in other implementations other suitable transistor technologies may be used.

7 FIG. 6 FIG. 700 700 600 503 503 704 504 503 704 506 is a circuit diagram illustrating another example reference voltage generator circuitincluding multiple cascode transistors to improve operation under supply voltage changes. The reference voltage generator circuitis similar to the reference voltage generator circuitofexcept that an additional PMOS cascode transistor is inserted in each current branchA-D to improve the performance of the current sources even if the supply voltage (V.DD) changes. A source terminal of a first cascode PMOS transistorA is connected to the drain terminal of the first PMOS transistorA in the first current branchA, and a drain terminal of the first cascode PMOS transistorA is connected to the drain terminal of the fourth NMOS transistor.

704 504 503 704 508 704 504 503 704 514 704 504 503 704 518 A source terminal of a second cascode PMOS transistorB is connected to the drain terminal of the second PMOS transistorB in the second current branchB, and a drain terminal of the second cascode PMOS transistorB is connected to the drain terminal of the fifth NMOS transistor. A source terminal of a third cascode PMOS transistorC is connected to the drain terminal of the third PMOS transistorC in the third current branchC, and a drain terminal of the third cascode PMOS transistorC is connected to the drain terminal of the first NMOS transistor. A source terminal of a fourth cascode PMOS transistorD is connected to the drain terminal of the fourth PMOS transistorD in the fourth current branchD, and a drain terminal of the fourth cascode PMOS transistorD is connected to the drain terminal of the third NMOS transistor.

704 704 704 704 706 704 704 704 704 503 503 503 503 520 526 700 5 FIG. Gate terminals of each of the first cascode PMOS transistorA, the second cascode PMOS transistorB, the third cascode PMOS transistorC, and the fourth cascode PMOS transistorD are connected to a second or cascode bias voltage (PBIAS.CAS). The addition of the first cascode PMOS transistorA, the second cascode PMOS transistorB, the third cascode PMOS transistorC, and the fourth cascode PMOS transistorD in the respective current branchesA,B,C, andD increases the output impedance of the current sources. This results in a reduced dependency on the supply voltage (V.DD)of the output current associated with the reference voltage (V.REF). In some cases, the output variation of the reference voltage induced by variations in the supply voltage is improved by the reference voltage generator circuitby approximately 2.5 times relative to the circuit of.

7 FIG. 8 FIG. 604 604 503 704 506 604 503 700 Although the implementation illustrated inomits the first cascode NMOS transistor, in other implementations the first cascode NMOS transistoris also included in the first current branchA. Thus, in at least some of such implementations, the drain terminal of the first cascode PMOS transistorA is indirectly connected to the drain terminal of the fourth NMOS transistorvia the first cascode NMOS transistor. An example of this configuration with two cascode transistors in the first current branchA is depicted inand described below. In addition, although the reference voltage generator circuitis shown as utilizing PMOS and NMOS FET technologies in particular manners, in other implementations other suitable transistor technologies may be used.

8 FIG. 7 FIG. 6 FIG. 800 800 700 800 804 604 804 704 704 704 704 is a circuit diagram illustrating another example reference voltage generator circuitincluding multiple cascode transistors with a selectable voltage bias to improve operation under supply voltage changes. The reference voltage generator circuitis similar to the reference voltage generator circuitofexcept that the reference voltage generator circuitfurther includes a multiplexerand the first cascode NMOS transistorof. The multiplexerincludes an output connected to the gate terminals of each of the first cascode PMOS transistorA, the second cascode PMOS transistorB, the third cascode PMOS transistorC, and the fourth cascode PMOS transistorD.

520 704 704 704 704 704 704 704 704 Under conditions when the supply voltage falls below a particular level, a significant drop in performance may occur due to a lack of voltage supply headroom. At a low supply voltage (V.DD)level, the first cascode PMOS transistorA, the second cascode PMOS transistorB, the third cascode PMOS transistorC, and the fourth cascode PMOS transistorD consume a portion of the limited headroom of the circuit, thereby diminishing performance. In such situations, the presence of the first cascode PMOS transistorA, the second cascode PMOS transistorB, the third cascode PMOS transistorC, and the fourth cascode PMOS transistorD may be a detriment to the operation of the circuit.

804 704 704 704 704 520 804 706 810 520 804 806 704 704 704 704 810 804 8 FIG. The multiplexerprovides for selective enablement or disablement of the first cascode PMOS transistorA, the second cascode PMOS transistorB, the third cascode PMOS transistorC, and the fourth cascode PMOS transistorD based on the value of the supply voltage (V.DD). The multiplexerreceives an intermediate bias voltage value (PBIAS_CAS)and a ground (e.g., 0V) at respective first and second inputs and receives a low supply enable signalbased on the value of the supply voltage (V.DD). In the implementation of, the multiplexerprovides either the bias voltage (PBIAS.CAS) or the ground voltage (e.g., 0V) as a cascode bias signal (PBIAS.CAS_IN)to the gates of each of the first cascode PMOS transistorA, the second cascode PMOS transistorB, the third cascode PMOS transistorC, and the fourth cascode PMOS transistorD based on the low supply enable signal. In other implementations, the multiplexermay be configured to provide a selection between more than two bias voltages.

520 806 706 704 704 704 704 704 704 704 704 When the value of the supply voltage (V.DD)is below a predetermined threshold value (e.g., is at a “low” value), the value of PBIAS.CAS_INis set equal to ground (0V) rather than the bias voltage (PBIAS.CAS). Accordingly, the first cascode PMOS transistorA, the second cascode PMOS transistorB, the third cascode PMOS transistorC, and the fourth cascode PMOS transistorD are fully turned on and effectively shorted between their respective source and drain terminals. Thus, the first cascode PMOS transistorA, the second cascode PMOS transistorB, the third cascode PMOS transistorC, and the fourth cascode PMOS transistorD are operationally removed from the circuit as each transistor is functioning like a closed switch with a negligible voltage drop along their channels.

520 704 704 704 704 800 7 FIG. 8 FIG. 5 FIG. When the value of the supply voltage (V.DD)is greater than the predetermined threshold value, the first cascode PMOS transistorA, the second cascode PMOS transistorB, the third cascode PMOS transistorC, and the fourth cascode PMOS transistorD are operationally enabled and operate substantially in the manner as described with reference to. In some cases, the output variation of the reference voltage generator circuitofcan be significantly reduced as compared to that ofwith an over three times improvement by reducing the impact of supply voltage variations on the stability of the output reference voltage.

8 FIG. 604 604 704 506 800 Although the implementation illustrated inis shown as including the first cascode NMOS transistor, in other implementations the first cascode NMOS transistoris omitted and the drain terminal of the first cascode PMOS transistorA can be directly connected to the drain terminal of the fourth NMOS transistor. In addition, although the reference voltage generator circuitis shown as utilizing PMOS and NMOS FET technologies, in other implementations other suitable transistor technologies may be used.

9 FIG. 8 FIG. 900 900 800 510 904 904 904 900 904 503 503 526 526 904 900 is a circuit diagram illustrating another example reference voltage generator circuitincluding a tunable resistor component in a current branch to improve temperature behavior of the reference voltage. The reference voltage generator circuitis similar to the reference voltage generator circuitofexcept that the resistoris replaced by a tunable (or variable) resistor component. The tunable resistor componentis configured to allow the resistance value of the tunable resistor componentto be varied to improve the temperature variation characteristics of the reference voltage generator circuitacross process variations. By adjusting the resistance of the tunable resistor, the biasing current within the third branchC and fourth branchD can be changed to adjust the temperature curve characteristics of the reference voltageto a desired level. For example, the temperature curve can be flatted such that the reference voltagechanges less across a relevant temperature range. To account for process variation, the tunable resistorcan be adjusted during a manufacturing or testing process. In implementations in which the reference voltage generator circuitis used to provide a reference voltage for a low dropout (LDO) regulator, for instance, the resulting relatively slight deviations in voltage level can be effectively compensated by adjusting the gain of the LDO.

9 FIG. 9 FIG. 8 FIG. 604 704 704 704 704 604 704 704 704 704 804 900 Although the implementation illustrated inis shown as including the first cascode NMOS transistor, the first cascode PMOS transistorA, the second cascode PMOS transistorB, the third cascode PMOS transistorC, and the fourth cascode PMOS transistorD, in other implementations one or more of the first cascode NMOS transistor, the first cascode PMOS transistorA, the second cascode PMOS transistorB, the third cascode PMOS transistorC, or the fourth cascode PMOS transistorD can be omitted. Although the implementation illustrated inis shown as omitting the multiplexershown in, other implementations may include a multiplexer to provide for a selectable bias voltage. In addition, although the reference voltage generator circuitis shown as utilizing PMOS and NMOS FET technologies, in other implementations other suitable transistor technologies may be used.

10 1 FIG.- 9 FIG. 1000 1000 1000 516 1002 1004 1004 1002 526 1002 1002 526 1004 is a circuit diagram illustrating another example reference voltage generator circuitincluding a transistor having a tunable number of stacked gates to improve the behavior of the reference voltage across a range of temperatures and process variations. The reference voltage generator circuitis similar to the reference voltage generator circuitofexcept that the second NMOS transistoris replaced by an NMOS transistorhaving a tunable number of stacked gates. That is, the number of stacked gatesforming the NMOS transistoris adjustable to adjust the length of the channel to modify the portion of the reference voltage (V.REF)that is contributed by the PTAT voltage generator. The effective channel length of the transistor is based on a quantity of individual gates that are selected for use for the transistor. The change in channel length of the transistoralters the temperature-dependent behavior of the PTAT portion by varying the gain of the PTAT voltage. In a particular implementation, the configurable number of gates are programmable to change the number of stacked gates that are coupled together to form a single gate for the device. The tunable number of stacked gates can be set to produce a relatively flat temperature curve, thereby facilitating tuning using a low-side switch to ground. In operation, small shifts in the reference voltagecan be compensated for using an LDO regulator with tunable gain once a flatter temperature curve has been established with the tunable number of stacked gates.

10 2 FIG.- 10 1 FIG.- 10 2 FIG.- 1002 1004 1002 1006 1008 1010 1010 1010 1010 526 is a diagram illustrating a schematic view of an example of the NMOS transistorhaving tunable number of stacked gatesof. The NMOS transistorincludes a drain portion, a source portionand multiple gate portions. As shown, the multiple gate portions include a first gate portionA and a second gate portionB, but the multiple gate portionscan include more gates. Although the example illustrated inshows two gates, it should be understood that other implementations may have any desired number of gates (e.g., a few to several dozen gates) to improve the temperature variation characteristics of the reference voltage (V.REF).

10 1 FIG.- 10 1 FIG.- 8 FIG. 604 704 704 704 704 604 704 704 704 704 804 1002 Although the implementation illustrated inis shown as including the first cascode NMOS transistor, the first cascode PMOS transistorA, the second cascode PMOS transistorB, the third cascode PMOS transistorC, and the fourth cascode PMOS transistorD, in other implementations one or more of the first cascode NMOS transistorand the first cascode PMOS transistorA, the second cascode PMOS transistorB, the third cascode PMOS transistorC, and the fourth cascode PMOS transistorD is omitted. Although the implementation illustrated inis shown as omitting the multiplexershown in, other implementations may include a multiplexer to provide selectable bias. In addition, although the reference voltage generator circuitis shown as utilizing PMOS and NMOS transistor technologies, in other implementations other suitable transistor technologies may be used.

Having generally described schemes, techniques, and hardware for implementing configurable reference voltage generators, this discussion now turns to example methods.

11 FIG. 6 10 2 FIGS.to- 1100 1100 1102 1114 is a flow diagram illustrating an example processfor generating a reference voltage. The flow chartincludes seven blocks-. The operations of example processes can be performed by electronic circuit components as described herein. For example, the operations may be performed by at least one instance of the example reference voltage generators of.

1102 202 520 604 704 704 704 704 604 704 704 704 704 6 FIG. 7 FIG. 8 FIG. At block, at least one current branch of a current generator receives a supply voltage. The at least one current branch includes at least one cascode transistor. For instance, the current generatorcan receive the supply voltage (V.DD). For example, at least one cascode transistor may include the first cascode NMOS transistorof. In another example, the at least one cascode transistor may include the first cascode PMOS transistorA, the second cascode PMOS transistorB, the third cascode PMOS transistorC, or the fourth cascode PMOS transistorD of, or any combination of these cascode PMOS transistors including up to four transistors. In still another example, the at least one cascode transistor may include the first cascode NMOS transistor, the first cascode PMOS transistorA, the second cascode PMOS transistorB, the third cascode PMOS transistorC, or the fourth cascode PMOS transistorD of, or any combination of these cascode transistors including up to five transistors.

1104 604 606 604 704 704 704 704 706 At block, the least one cascode transistor of the current generator receives a first bias voltage. For example, in an implementation, the first cascode NMOS transistorcan receive the first bias voltage (V.BIAS)at a gate terminal of the first cascode NMOS transistor. In another implementation, at least one of the first cascode PMOS transistorA, the second cascode PMOS transistorB, the third cascode PMOS transistorC, or the fourth cascode PMOS transistorD can receive the first bias voltage (PBIAS.CAS)at respective gate terminals.

804 706 704 704 704 704 706 520 520 In an implementation, a multiplexermay selectively provide a first voltage value or a second voltage value as the first bias voltage (PBIAS.CAS)to the first cascode PMOS transistorA, the second cascode PMOS transistorB, the third cascode PMOS transistorC, or the fourth cascode PMOS transistorD (including two or more of such cascode PMOS transistors) based on a value of the supply voltage received by the current generator. For example, in an implementation, the first bias voltage value (e.g., PBIAS.CAS) can be provided based on the value of the supply voltage (V.DD)being greater than a first threshold value, and the second bias voltage value (e.g. 0 Volts) can be provided based on the value of the supply voltage (V.DD)being less than the first threshold value.

1106 206 518 503 1108 524 At block, a first voltage generator receives a first bias current from the current generator. In an example implementation, the first voltage generator can be realized with a CTAT voltage generatorincluding the third NMOS transistorthat receives the first bias current via the fourth current branchD. At block, the first voltage generator provides a first voltage value, with the first voltage value being complementary to absolute temperature. For example, in an implementation, the first voltage generator can provide the CTAT voltage (V.C).

1110 204 514 516 503 1112 522 At block, a second voltage generator receives a second bias current from the current generator. In an example implementation, the second voltage generator can be realized with a PTAT voltage generatorincluding the first NMOS transistorand the second NMOS transistorthat receive the second bias current via the third current branchC. At block, the second voltage generator provides a second voltage value, with the second voltage value being proportional to absolute temperature. For example, in an implementation, the second voltage generator can provide the PTAT voltage (V.P).

904 503 204 1002 503 202 1004 Further, in an example implementation, a gain of the second voltage generator can be adjusted using a variable resistorin the first current branchA. In another example implementation, the second voltage generator (e.g., the PTAT voltage generator) can include a first transistorhaving a configurable channel length coupled into a current branch (e.g., the third current branchC) of the current generator (e.g., the current generator) to adjust a gain of the second voltage generator. In at least some cases in accordance with this other example implementation, the configurable channel length can be set using a selected quantity of a tunable number of stacked gates.

1114 526 At block, a reference voltage is generated based on a combination of the first voltage value and the second voltage value. For example, in an implementation, the first voltage value can be added to the second voltage value to produce the reference voltage. In an implementation, the reference voltage (V.REF)can be provided to other circuitry, such as a voltage regulator circuit, a sensor circuit, or an ADC circuit. In other implementations, other mathematical or logical operations or processes may be used to combine the first voltage value and the second voltage value to produce the reference voltage value instead of, or in addition to, an addition operation.

1 4 6 10 2 FIGS.toandto- 5 1 5 2 FIGS.-and- Aspects of these methods may be implemented in, for example, hardware (e.g., fixed logic circuitry, a controller, a finite state machine, or a processor in conjunction with a memory), firmware, software, or some combination thereof. The methods may be realized using one or more of the apparatuses or components shown in(as illuminated by the description of), which components may be further divided, combined, and so on. The devices and components of these figures generally represent hardware, such as electronic devices, PCBs, packaged modules, IC chips, components, or circuits; firmware; software; or a combination thereof. Thus, these figures illustrate some of the many possible systems or apparatuses capable of implementing the described methods.

For the methods described herein and the associated flow chart(s) and/or flow diagram(s), the orders in which operations are shown and/or described are not intended to be construed as a limitation. Instead, any number or combination of the described method operations can be combined in any order to implement a given method or an alternative method, including by combining operations from different ones of the flow chart(s) and flow diagram(s) and the earlier-described schemes and techniques into one or more methods. Operations may also be omitted from or added to the described methods. Further, described operations can be implemented in fully or partially overlapping manners.

12 FIG. 1 FIG. 1200 1200 1200 102 1200 illustrates various components of an example electronic devicethat can implement a configurable reference voltage generator in accordance with one or more described aspects. The electronic devicemay be implemented as any one or combination of a fixed, mobile, stand-alone, or embedded device or in any form of a consumer, computer, portable, user, server, communication, phone, navigation, gaming, audio, camera, messaging, media playback, and/or other type of electronic device, such as the smartphone that is depicted inas the apparatus. One or more of the illustrated components may be realized as discrete components or as integrated components on at least one integrated circuit of the electronic device.

1200 1202 1204 1202 The electronic devicecan include one or more communication transceiversthat enable wired and/or wireless communication of device data, such as received data, transmitted data, or other information identified above. Example communication transceiversinclude near-field communication (NFC) transceivers, wireless personal area network (PAN) (WPAN) radios compliant with various IEEE 802.15 (Bluetooth®) standards, wireless local area network (LAN) (WLAN) radios compliant with any of the various IEEE 802.11 (Wi-Fi®) standards, wireless wide area network (WAN) (WWAN) radios (e.g., those that are 3GPP-compliant) for cellular telephony, wireless metropolitan area network (MAN) (WMAN) radios compliant with various IEEE 802.16 (WiMAX™) standards, infrared (IR) transceivers compliant with an Infrared Data Association (IrDA) protocol, and wired local area network (WLAN) Ethernet transceivers.

1200 1206 1206 1206 The electronic devicemay also include one or more data input portsvia which any type of data, media content, and/or other inputs can be received, such as user-selectable inputs, messages, applications, music, television content, recorded video content, and any other type of audio, video, and/or image data received from any content and/or data source, including a sensor like a microphone or a camera. The data input portsmay include USB ports, coaxial cable ports, fiber optic ports for optical fiber interconnects or cabling, and other serial or parallel connectors (including internal connectors) for flash memory, DVDs, CDs, and the like. These data input portsmay be used to couple the electronic device to components, peripherals, or accessories such as keyboards, microphones, cameras, or other sensors.

1200 1208 1208 The electronic deviceof this example includes at least one processor(e.g., any one or more of application processors, microprocessors, digital-signal processors (DSPs), controllers, and the like), which can include a combined processor and memory system (e.g., implemented as part of an SoC), that processes (e.g., executes) computer-executable instructions to control operation of the device. The processormay be implemented as an application processor, embedded controller, microcontroller, security processor, artificial intelligence (AI) accelerator, graphics processor, and the like. Generally, a processor or processing system may be implemented at least partially in hardware, which can include components of an integrated circuit or on-chip system, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), and other implementations in silicon and/or other materials.

1200 1210 1210 1210 12 FIG. Alternatively or additionally, the electronic devicecan be implemented with any one or combination of electronic circuitry, which may include software, hardware, firmware, or fixed logic circuitry that is implemented in connection with processing and control circuits, which are generally indicated at(as electronic circuitry). This electronic circuitrycan implement executable or hardware-based modules (not shown in), such as through processing/computer-executable instructions stored on computer-readable media, through logic circuitry and/or hardware (e.g., such as an FPGA), and so forth.

1200 1212 1212 1212 1204 1220 1214 1212 1208 The electronic devicealso includes one or more memory devicesthat enable data storage, examples of which include random-access memory (RAM), non-volatile memory (e.g., read-only memory (ROM), flash memory, EPROM, and EEPROM), and a disk storage device. Thus, the memory device(s)can be distributed across different logical storage levels of a system as well as at different physical components. The memory device(s)provide data storage mechanisms to store the device data, other types of code and/or data, and various device applications(e.g., software applications or programs). For example, an operating systemcan be maintained as software instructions within the memory deviceand executed by the processor.

1200 1216 1218 1222 1218 1222 1224 1218 1222 1200 1222 1200 In some implementations, the electronic devicealso includes an audio and/or video processing systemthat processes audio and/or video data and/or that passes through the audio and/or video data to an audio systemand/or to a display system(e.g., a video buffer or a screen of a smartphone or camera). The audio systemand/or the display systemmay include any devices that process, display, and/or otherwise render audio, video, display, and/or image data. Display data and audio signals can be communicated to an audio component and/or to a display component via an RF (radio-frequency) link, an S-video link, an HDMI (high-definition multimedia interface) link, a composite video link, a component video link, a DVI (digital video interface) link, an analog audio connection, a video bus, or another similar communication link, such as a media data port. In some implementations, the audio systemand/or the display systemare external or separate components of the electronic device. Alternatively, the display system, for example, can be an integrated component of the example electronic device, such as part of an integrated touch interface.

104 104 104 106 110 108 106 1 FIG. 1 4 6 10 2 FIGS.toandto- 5 1 5 2 FIGS.-and- Any illustrated component can include, or be included as part of, the IC. Additionally or alternatively, a component that is not explicitly illustrated, such as a sensor (e.g., a temperature sensor) or a wireless modem, can include, or be included as part of, the IC. As described above with reference to, the ICincludes the reference voltage generatorthat provides the reference voltageto the voltage regulator. In various implementations, the reference voltage generatormay include one or more of the reference voltage circuits as described herein with respect to(as illuminated by the description of).

1200 102 12 FIG. 1 FIG. 2 4 FIGS.to 6 10 2 FIGS.to- 11 FIG. The electronic deviceofillustrates example implementations of the apparatusof, of a device that can implement the example components of, of a device that can implement the example circuitries of, and of a device that can implement the example method of.

In the following, some example aspects and implementations are described:

Example aspect 1: An apparatus for generating a reference voltage, the apparatus comprising: a current generator comprising at least one current branch configured to receive a supply voltage, the at least one current branch comprising at least one cascode transistor configured to receive a first bias voltage value; a first voltage generator configured to receive a first bias current from the current generator and provide a first voltage value, the first voltage value being complementary to absolute temperature; and a second voltage generator configured to receive a second bias current from the current generator and provide a second voltage value, the second voltage value being proportional to absolute temperature; the apparatus configured to provide a third voltage value based on a combination of the first voltage value and the second voltage value.

Example aspect 2: The apparatus of example aspect 1 or any other example aspect, wherein the at least one cascode transistor comprises a first cascode transistor and a second cascode transistor; and the at least one current branch comprises a first current branch comprising the first cascode transistor and a second current branch comprising the second cascode transistor.

Example aspect 3: The apparatus of example aspect 2 or any other example aspect, wherein the first cascode transistor and the second cascode transistor are each configured to receive the first bias voltage value.

Example aspect 4: The apparatus of example aspect 2 or any other example aspect, wherein the first current branch further comprises a variable resistor configured to adjust a gain of the second voltage generator. Additionally or alternatively, the first current branch further comprises a third cascode transistor configured to receive a third bias voltage value different from the first bias voltage value.

Example aspect 5: The apparatus of example aspect 1 or any other example aspect, further comprising a multiplexer comprising a first input configured to receive the first bias voltage value; a second input configured to receive a second bias voltage value; and an output configured to selectively provide the first bias voltage value or the second bias voltage value to the at least one cascode transistor based on a value of the supply voltage.

Example aspect 6: The apparatus of example aspect 5 or any other example aspect, wherein the output is configured to: provide the first bias voltage value based on the value of the supply voltage being greater than a first threshold value; and provide the second bias voltage value based on the value of the supply voltage being less than the first threshold value.

Example aspect 7: The apparatus of example aspect 1 or any other example aspect, wherein: the at least one current branch comprises a third current branch configured to provide the second bias current; and the second voltage generator comprises a first transistor having a configurable channel length coupled to the third current branch of the current generator, the first transistor configured to adjust a gain of the second voltage generator.

Example aspect 8: An apparatus for generating a reference voltage, the apparatus comprising: a current generator comprising: a first current branch configured to receive a supply voltage, the first current branch comprising a first cascode transistor configured to receive a first bias voltage; a second current branch configured to receive the supply voltage, the second current branch comprising a second cascode transistor configured to receive the first bias voltage; a third current branch configured to receive the supply voltage, the third current branch comprising a third cascode transistor configured to receive the first bias voltage; and a fourth current branch configured to receive the supply voltage, the fourth current branch comprising a fourth cascode transistor configured to receive the first bias voltage; a first voltage generator configured to receive a first bias current from the fourth cascode transistor and provide a first voltage value, the first voltage value being complementary to absolute temperature; and a second voltage generator configured to receive a second bias current from the third cascode transistor and provide a second voltage value, the second voltage value being proportional to absolute temperature; the apparatus configured to generate the reference voltage based on the first voltage value and the second voltage value.

Example aspect 9: The apparatus of example aspect 8 or any other example aspect, further comprising: a multiplexer including: a first input configured to receive the first bias voltage value; a second input configured to receive a second bias voltage value; and an output configured to selectively provide the first bias voltage value or the second bias voltage value to the first cascode transistor, the second cascode transistor, the third cascode transistor, and the fourth cascode transistor based on a value of the supply voltage.

Example aspect 10: The apparatus of example aspect 8 or any other example aspect, wherein the first current branch further comprises a fifth cascode transistor coupled in series with the first cascode transistor, the fifth cascode transistor configured to receive a third bias voltage.

Example aspect 11: The apparatus of example aspect 8 or any other example aspect, wherein the first current branch further comprises a variable resistor configured to adjust a gain of the second voltage generator.

Example aspect 12: The apparatus of example aspect 8 or any other example aspect, wherein the second voltage generator comprises a first transistor coupled to the third current branch of the current generator and having a configurable channel length, the configurable channel length corresponding to a tunable quantity of stacked gates to adjust a gain of the second voltage generator.

Example aspect 13: The apparatus of example aspect 12 or any other example aspect, wherein the second voltage generator further comprises a second transistor coupled to the first transistor.

Example aspect 14: The apparatus of example aspect 8 or any other example aspect, wherein the current generator comprises a current mirror configured to mirror at least one current in the first current branch to produce the first bias current in the fourth current branch and the second bias current in the third current branch.

Example aspect 15: The apparatus of example aspect 8 or any other example aspect, wherein: the second voltage generator is configured to provide the second voltage value to the first voltage generator; and the first voltage generator is configured to add the first voltage value to the second voltage value to generate the reference voltage.

Example aspect 16: A method for generating a reference voltage, the method comprising: receiving, by at least one current branch of a current generator, a supply voltage, the at least one current branch comprising at least one cascode transistor; receiving, by the least one cascode transistor, a first bias voltage value; receiving, by a first voltage generator, a first bias current from the current generator; providing, by the first voltage generator, a first voltage value, the first voltage value being complementary to absolute temperature; receiving, by a second voltage generator, a second bias current from the current generator; providing, by the second voltage generator, a second voltage value, the second voltage value being proportional to absolute temperature; and generating the reference voltage based on a combination of the first voltage value and the second voltage value.

Example aspect 17: The method of example aspect 16 or any other example aspect, further comprising: receiving, at a first input of a multiplexer, the first bias voltage value; receiving, at a second input of the multiplexer, a second bias voltage value; and selectively providing, at an output of the multiplexer, the first bias voltage value or the second bias voltage value to the at least one cascode transistor based on a value of the supply voltage.

Example aspect 18: The method of example aspect 17 or any other example aspect, wherein selectively providing the first bias voltage value or the second basis voltage value comprises: providing the first bias voltage value based on the value of the supply voltage being greater than a first threshold value; and providing the second bias voltage value based on the value of the supply voltage being less than the first threshold value.

Example aspect 19: The method of example aspect 16 or any other example aspect, further comprising: propagating a current through a variable resistor of the at least one current branch.

Example aspect 20: The method of example aspect 16 or any other example aspect, wherein generating the reference voltage based on a combination of the first voltage value and the second voltage value comprises: adding the first voltage value to the second voltage value to generate the reference voltage.

Features described in the context of one aspect (e.g., a method or an apparatus) may be used in combination with other aspects (e.g., an apparatus or a method, respectively, or a different method or a different apparatus).

Unless context dictates otherwise, use herein of the word “or” may be considered use of an “inclusive or,” or a term that permits inclusion or application of one or more items that are linked by the word “or” (e.g., a phrase “A or B” may be interpreted as permitting just “A,” as permitting just “B,” or as permitting both “A” and “B”). Also, as used herein, a phrase referring to “at least one of” a list of items refers to any combination of those items, including single members. For instance, “at least one of a, b, or c” can cover a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c, or any other ordering of a, b, and c). Further, items represented in the accompanying figures and terms discussed herein may be indicative of one or more items or terms, and thus reference may be made interchangeably to single or plural forms of the items and terms in this written description.

Although implementations for realizing reference voltage generation have been described in language specific to certain features and/or methods, the subject of the appended claims is not necessarily limited to the specific features or methods described. Rather, the specific features and methods are disclosed as example implementations for realizing reference voltage generation.