Display Panel, Driving Chip, and Display Apparatus

The present application claims priority to Chinese patent application No. 202411501672.0, entitled “DISPLAY PANEL, DRIVING CHIP, AND DISPLAY APPARATUS”, filed on Oct. 25, 2024, the entire contents of which are incorporated here by reference.

The present application relates to the field of display technology, and particularly, to a display panel, a driving chip, and a display apparatus.

A display panel typically includes pixels and a gate driving circuit that is configured to provide gate control signals for the pixels to control the writing of data signals into the pixels, and the like.

With the development of display technology, requirements for reliability of the display panels have been increasing. Under a condition that transistors in the gate driving circuit are easily damaged, the normal operation of the gate driving circuit is affected, thereby affecting the reliability of the display panel.

Embodiments of the present application provide a display panel, a driving chip, and a display apparatus, so that the problem that the transistor is easily damaged can be reduced.

In a first aspect, embodiments of the present application provide a display panel, and the display panel includes a gate driving circuit including a plurality of shift registers in a cascaded connection, and the shift register includes a first transistor that is provided with a power supply voltage through a resistor structure.

Based on the same inventive concept, in a second aspect, embodiments of the present application provide a driving chip configured to provide a power supply voltage for a gate driving circuit in a display panel, the power supply voltage provided by the driving chip is at a first level in the first phase, at a second level in a second phase, and at a third level in a third phase, the third phase is located between the first phase and the second phase, the third level is between the first level and the second level, and at the first level, a first transistor in the gate driving circuit is turned on.

Based on the same inventive concept, in a third aspect, embodiments of the present application provide a driving chip including a signal generation circuit and a signal delay structure, the signal generation circuit is configured to generate a power supply voltage, one end of the signal delay structure is electrically connected to an output of the signal generation circuit, and the other end of the signal delay structure is electrically connected to a gate driving circuit in a display panel.

Based on the same inventive concept, in a fourth aspect, embodiments of the present application provide a display apparatus including the display panel according to any one of the embodiments in the first aspect, and/or the driving circuit according to any one of the embodiments in the second aspect or the third aspect.

The above description is merely an overview of the technical solutions of the present application. In order to make the technical means of the present application understood more clearly and implemented according to the contents of the description, and in order to make the above and other objects, features and advantages of the present application understood more obviously, specific detailed description of the present application are particularly provided below.

Features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the objects, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating examples of the present application.

It should be noted that, in the present disclosure, the relational terms, such as first and second, are used merely to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any actual such relationships or orders for these entities or operations. Moreover, the terms “comprise”, “include”, or any other variants thereof, are intended to represent a non-exclusive inclusion, such that a process, method, article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed or elements inherent to such a process, method, article or device. Without more constraints, the elements following an expression “comprise/include . . . ” do not exclude the existence of additional identical elements in the process, method, article or device that includes the elements.

It should be understood that when the structure of a component is described, if a layer/area is referred to as being “on” or “above” another layer/region, it may mean that the layer/area is directly on the other layer/region or that other layers/regions may be included between the layer/area and the other layer/area. Moreover, if the component is turned over, the layer/area will be “below” or “under” the other layer/area.

It should be understood the term “and/or” used herein refers to only an association relationship for describing associated objects, and means that there may be three kinds of relationships. For example, “A and/or B” may represent three cases including: “A exists alone”, “A and B exist simultaneously”, and “B exists alone”. In addition, the character “/” herein generally indicates that the associated objects have an “or” relationship.

In the description of the embodiments of the present application, the technical terms “mounted”, “connected”, “connection”, “fixed”, and the like should be interpreted in a broad sense, for example, they may refer to a fixed connection, a detachable connection or integration; a mechanical connection, or an electrical connection; a direct connection, an indirect connection through an intermediate medium, or an internal connection or an interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above-mentioned terms in the embodiments of the present application can be understood in accordance with specific conditions.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the gist or scope of the present application. Accordingly, the present application is intended to encompass the modifications and variations to the present application that fall within the scope of the appended claims (the claimed technical solutions) and equivalents thereof. It should be noted that the implementations provided by the embodiments of the present application can be combined with one another if there is no conflict.

Before the technical solutions provided by the embodiments of the present application are described, related technical problems are first described in the present application to facilitate the understanding of the embodiments of the present application.

The inventor of the present application has found that, under a condition that a display panel is in a high temperature operating environment, a bias voltage in a gate driving circuit is relatively high, and a transistor device that is turned on for a long duration is easily damaged.

For a transistor that needs to be provided with a power supply voltage (VDD signal), under a condition that the VDD signal changes from an OFF-level to an On-level (herein, the OFF-level refers to the level that controls the transistor to be turned off, and the ON-level refers to the level that controls the transistor to be turned on), the transistor that is controlled by the VDD signal is directly impacted by a high level and a great current, and under a condition that the transistor is turned on for a long duration, the transistor is easily damaged. However, after the transistor is damaged, corresponding nodes in the gate driving circuit cannot be controlled, causing the gate driving circuit to lose corresponding functions, resulting in abnormal operation of the gate driving circuit, and further causing display abnormality of the display panel (for example, transverse stripes appear on the display screen).

In view of the above research findings of the inventor, changing the power supply voltage actually received by the transistor is considered in embodiments of the present application; under a condition that potential of the power supply voltage changes, it is avoided that the transistor actually receives instant excessively high potential and is impacted by the great instantaneous current to reduce the instantaneous current passing through the transistor, reducing the problem that the transistor is easily damaged, and improving reliability of the gate driving circuit and the display panel.

A display panel, a driving chip, and a display apparatus according to embodiments of the present application will be described below with reference to the drawings.

1 FIG. 2 FIG. 100 10 11 11 11 11 As shown inor, the display panelaccording to embodiments of the present application includes the gate driving circuitincluding a plurality of shift registersin a cascaded connection. In the drawing, an example is given in which an output signal of the shift registerof the previous stage is used as a trigger signal of the shift registerof the next stage, and a cascade relationship among the shift registersis not limited to herein; the output signal of the shift register of the current stage may be used as the trigger signal of the shift register after several stages.

100 10 20 11 20 11 20 In an example, the display panelincludes the display area AA and the non-display area NA surrounding the display area AA. The gate driving circuitis located in the non-display area NA. The display area AA includes a plurality of pixels. An output of the shift registeris electrically connected to the pixels, and a signal output by the shift registeris used for driving the pixels.

11 The signal output by the shift registermay include a scanning signal, a light-emitting control signal, and the like.

20 11 Under a condition that the display panel is a liquid crystal display panel, the pixelmay include a switching tube, and the signal output by the shift registercontrols the switching tube to be turned on, so that a data line provides a data voltage for a pixel electrode through the switching tube.

11 111 30 200 200 111 30 The shift registerseach include the first transistorthat is provided with the power supply voltage VDD through the resistor structure. The power supply voltage VDD is provided by a driving circuit such as the driving chip; and it may be understood that a path across which the power supply voltage VDD is transmitted from an output of the driving chipto the first transistorspasses through the resistor structure.

111 30 111 111 111 111 In an example, a gate of the first transistoris provided with the power supply voltage VDD through the resistor structure. The power supply voltage VDD is used for controlling states of the first transistors. For example, under a condition that the power supply voltage VDD is at the first level, the first transistorsare turned on; under a condition that the power supply voltage VDD is at the second level, the first transistorsare turned off. Under a condition that the first transistorsare N-type transistors, the second level is lower than the first level, the first level is the high level vgh, and the second level is the low level vgl. Correspondingly, under a condition that the first transistors are P-type transistors, the first level is the low level vgl, and the second level is the high level vgh.

100 41 200 200 111 41 30 In an example, the display panelfurther includes the power supply tracefor transmitting the power supply voltage VDD. The driving chipis configured to provide the power supply voltage VDD, and the power supply voltage VDD output by the driving chipis transmitted to the first transistorsthrough the power supply traceand the resistor structure.

1 FIG. 30 11 41 200 41 30 111 As an example, as shown in, the resistor structuresare connected between the shift registersand the power supply trace. Under this condition, the power supply voltage VDD output by the driving chipis first transmitted to the power supply trace, next to the resistor structures, and then to the first transistors.

2 FIG. 30 200 41 200 30 41 111 As another example, as shown in, the resistor structureis connected between the driving chipand the power supply trace. Under this condition, the power supply voltage VDD output by the driving chipis first transmitted to the resistor structure, next to the power supply trace, and then to the first transistors.

Some structures of the shift register will be exemplarily described below.

11 11 1 2 3 4 5 1 2 3 4 5 3 FIG. 3 FIG. In an example, circuit architectures of the shift registerinclude, but are not limited to, the circuit architecture shown in. As shown in, the circuit architecture of the shift registermay include the pull-up control module, the pull-up module, the main pull-down module, the pull-down maintenance module, and the bootstrap capacitor. The pull-up control moduleis configured to pre-charge the shift register, the pull-up moduleis configured to drive the pixels of the display area, the main pull-down moduleis configured to pull down the node Gn and the node netA, the pull-down maintenance moduleis configured to maintain the potential of the point PD to be stable, and the bootstrap capacitoris configured to raise the potential of the node netA. Herein, the node netA and the point PU may be understood as the nodes that have the same potential.

11 6 In an example, the shift registermay be designed to include other functional modulesbased on other needs.

4 FIG. 11 As shown in, the operation of the shift registermay generally be divided into four phases.

1 1 In phase {circle around ()}, the pull-up control modulecontrols the trigger signal STV to enter, the point PU is raised for the first time, and the point PD is pulled low;

2 5 In phase {circle around ()}, the bootstrap capacitoroperates, and the point PU is raised for the second time;

3 3 In phase {circle around ()}, the main pull-down moduleoperates, the reset signal RESET enters, the point PU is pulled low, and the point PD starts to rise;

4 4 In phase {circle around ()}, the pull-down maintenance moduleoperates, the point PD maintains to be at the high potential and continues to empty the charge of the circuit, and is not pulled low until the next time the point PU rises.

The power supply voltage VDD is used for providing the potential of the point PD. The variation frequency of the power supply voltage VDD may not be high; for example, under a condition that the transistor controlled by the power supply voltage VDD is the N-type transistor, the power supply voltage VDD may be maintained at high potential for a long duration.

11 16 17 16 1 17 2 111 16 17 1 2 30 5 FIG. In some optional examples, the specific circuit structure of the shift registermay be as shown in, and the transistor Mand the transistor Mneed to be provided with the power supply voltage VDD; in order to distinguish, the power supply voltage VDD provided for the transistor Mis labeled as the first power supply voltage VDD, and the power supply voltage VDD provided for the transistor Mis labeled as the second power supply voltage VDD. Herein, the first transistorincludes the transistor Mand the transistor Mthat may be provided with the first power supply voltage VDDand the second power supply voltage VDDthrough different resistor structures, respectively.

11 4 111 4 30 6 FIG. In some other optional examples, the specific circuit structure of the shift registermay be as shown in, and the transistor Tneeds to be provided with the power supply voltage VDD; herein, the first transistorincludes the transistor Tthat is provided with the power supply voltage VDD through the resistor structure.

11 5 111 5 30 7 FIG. In yet some other optional examples, the specific circuit structure of the shift registermay be as shown in, and the transistor Mneeds to be provided with the power supply voltage VDD; herein, the first transistorincludes the transistor Mthat is provided with the power supply voltage VDD through the resistor structure.

3 FIG. 7 FIG. 5 FIG. 7 FIG. It should be noted that the technical concept of the present application has general applicability, and specific structures of the shift register are not limited, and the structures and time sequences shown intoare only some examples and are not intended to limit the present application. For example, the circuit structures of the shift register shown intoare 19T1C, 11T1C, and 9T1C, respectively, and structures of the shift register include, but are not limited to, 19T1C, 11T1C, 9T1C, 9T2C, 12T1C, 17T1C, 21T1C, and the like; herein “19T1C” means that the shift register has 19 transistors and 1 capacitor, which is similar for other structures and will not be repeated.

30 30 Under a condition that the power supply voltage changes, the instantaneous current I is generated in the transmission path of the power supply voltage. For example, under a condition that the power supply voltage changes from the low potential vgl to the high potential vgh, the instantaneous current I is generated in the transmission path of the power supply voltage; under a condition that the power supply voltage is directly provided for the first transistor without passing through the resistor structure, the first transistor receives the high potential vgh, the source-drain voltage difference Vds of the first transistor is relatively big, and the current passing through the first transistor is relatively great, easily damaging the first transistor. However, in the embodiments of the present application, the first transistor is provided with the power supply voltage VDD through the resistor structure; under a condition that the power supply voltage VDD changes from the low potential vgl to the high potential vgh, the instantaneous current generated in the transmission path of the power supply voltage VDD generates the voltage drop ΔV on the resistor structure; the resistance of the resistor structureis labeled as R, ΔV=I*R, the potential received by the first transistor is reduced to vgh −ΔV, and the current passing through the first transistor is correspondingly reduced. As such, the the great current impact on the first transistor due to the instantaneous change of the provided power supply voltage VDD may be reduced, that is, the direct impact of the change of the power supply voltage VDD on the first transistor is avoided to reduce the instantaneous current passing through the first transistor, reducing the problem that the first transistor is easily damaged and improving the reliability of the gate driving circuit and the display panel.

30 It may be understood that the instantaneous current is generated in the transmission path of the power supply voltage VDD only when the power supply voltage VDD changes, so that the resistor structurereduce the voltage only when the power supply voltage VDD changes. Under a condition that the power supply voltage VDD does not change any more, almost no current passes through the transmission path of the power supply voltage VDD, and the resistor structure will not have the function of reducing the voltage any more. Therefore, providing the resistor structure is equivalent to adding a delay when the signal changes abruptly, and the resistor structure acts as a buffer and does not affect the normal operating potential of the device and the normal operation of the shift register.

For example, under a condition that the first transistor is the N-type transistor, and the voltage difference Vgs between the gate and the source thereof is greater than the threshold voltage Vth thereof, the first transistor is turned on, and the current passes through; and under a condition that the power supply voltage VDD changes from the low potential vgl to the high potential vgh, the resistor structure has the delay effect. Under a condition that the power supply voltage VDD changes from the high potential vgh to the low potential vgl, the N-type first transistor is turned off and no current passes through.

For another example, under a condition that the first transistor is the P-type transistor, and the voltage difference Vgs between the gate and the source thereof is less than the threshold voltage Vth thereof, the first transistor is turned on, and the current passes through; and under a condition that the power supply voltage VDD changes from the high potential vgh to the low potential vgl, the resistor structure has the delay effect. Under a condition that the power supply voltage VDD changes from the low potential vgl to the high potential vgh, the P-type first transistor is turned off and no current passes through.

Some examples of the resistor structure will be exemplarily described below.

1 FIG. 2 FIG. 41 30 301 301 41 111 301 111 41 In some embodiments, as shown inor, the display panel includes the power supply tracefor transmitting the power supply voltage VDD, and the resistor structureincludes the first trace. The first tracemay be connected between the power supply traceand the first transistor, or the first tracemay be connected to the first transistorthrough the power supply trace.

301 41 301 301 301 41 301 As an example, an impedance of per unit length of at least a part of the segments of the first traceis greater than an impedance of per unit length of the power supply trace. Herein, the impedance of the first tracemay be designed to be uniform, that is, the impedance of per unit length of the segments of the first traceat different locations is the same; or the impedance of per unit length of one part of the segments of the first traceis greater than the impedance of per unit length of the power supply trace, and the impedance of per unit length of the other part of the segments of the first tracemay not be limited.

301 41 301 41 301 41 It may be understood that both the first traceand the power supply traceare used for transmitting the power supply voltage VDD. Within the same length, the impedance of the first traceis greater than the impedance of the power supply trace. In an example, the total impedance of the first traceis greater than the total impedance of the power supply trace.

41 In order to reduce the effect of the signal voltage drop on the display performance, the total impedance of the power supply traceis typically set to be relatively small and even negligible. In the embodiments of the present application, the resistor structure includes the first trace, that is, the resistor structure is designed as a trace structure, so that the first trace may be manufactured by directly using the existing trace manufacturing process, which is relatively easy to achieve; in addition, the impedance of per unit length of the first trace is relatively big, which is more beneficial to reduce the impact of the change of the power supply voltage VDD on the first transistor, thereby protecting the first transistor from being damaged.

1 FIG. 2 FIG. 41 30 301 301 41 In some embodiments, as shown inor, the display panel includes the power supply tracefor transmitting the power supply voltage VDD, and the resistor structureincludes the first trace. A trace width of the first traceis less than a trace width of the power supply trace. Under a condition that the materials are the same, the less the trace width is, the greater the impedance of the trace will be. In the embodiments of the present application, designing the trace width of the first trace to be relatively small can increase the impedance of the transmission path of the power supply voltage VDD to the first transistor to reduce the impact of the change of the power supply voltage VDD on the first transistor, thereby protecting the first transistor from being damaged.

200 301 In some other embodiments, the transmission path of the power supply voltage VDD output from the driving chipto the first transistor may be increased. For example, trace lengths of traces on a part of locations (such as the location where the first traceis located) on the transmission path may be increased.

8 FIG. 301 As an example, as shown in, the resistor structure includes the first tracethat includes a meander line. Designing the first trace to extend in meander line can increase the total length of the first trace in a limited space to increase the impedance of the transmission path of the power supply voltage VDD to the first transistor and reduce the impact of the change of the power supply voltage VDD on the first transistor, thereby protecting the first transistor from being damaged.

8 FIG. 301 In some examples, as shown in, the meandering pattern of the first tracemay include, but is not limited to, any one of a square wave, a zigzag, and a serpentine in shape.

200 301 As an example, under a condition that the total length of the transmission path of the power supply voltage VDD output from the driving chipto the first transistor is constant, only trace lengths of traces on a part of locations (such as the location where the first traceis located) on the transmission path may be reduced.

As another example, under a condition that the width of the transmission path of the power supply voltage VDD is constant, the total length of the transmission path of the power supply voltage VDD to the first transistor may be increased (for example, the length of the first trace may be increased).

301 As another example, the trace lengths of the traces on a part of the locations (such as the location where the first traceis located) on the transmission path may be reduced, and the total length of the transmission path of the power supply voltage VDD to the first transistor may be increased (for example, the length of the first trace may be increased).

301 41 301 41 301 41 301 301 41 It may be understood that under a condition that the trace width of the first traceis less than the trace width of the power supply trace, the impedance of per unit length of the first traceis greater than the impedance of per unit length of the power supply trace. In some other examples, different materials may be used for manufacturing the first traceand the power supply trace, respectively, and the impedance of the material used for the first traceis greater to satisfy that the impedance of per unit length of the first traceis greater than the impedance of per unit length of the power supply trace.

1 FIG. 2 FIG. 9 FIG. 41 30 30 30 41 a a In some embodiments, as shown inor, the display panel includes the power supply tracefor transmitting the power supply voltage VDD. With reference to, the resistor structureincludes at least the first segment, and the first segmentand the power supply traceare located in different layers.

9 FIG. 30 41 1 1 41 30 a a. Traces in different film layers are shown with different fillings in. Under a condition that the first segmentand the power supply traceare located in different layers, the two may be connected through the via h. One end of the via his overlapped with the power supply trace, and the other end is overlapped with the first segment

30 41 30 41 30 30 a a a a. Since the first segmentand the power supply traceare located in different layers, the first segmentmay not be limited by the power supply trace, and structural features and/or material features of the first segmentmay be designed more freely, facilitating more flexible designing of the first segment

30 a In an example, the material of the first segmentincludes a transparent conductive material or a semiconductor material.

41 As an example, the transparent conductive material includes indium tin oxide (ITO). The material of the power supply tracetypically includes a metal element (such as copper, aluminum, molybdenum, and titanium) or alloy, the metal element or the alloy has a relatively low impedance. The impedance of the ITO is much greater, and typically, the impedance of the ITO is 500 times or more that of the metal such as copper and aluminum.

41 30 30 a a Under a condition that the power supply traceis a conductor, and the first segmentincludes the semiconductor material, the first segmentis the semiconductor, the resistance of the semiconductor is greater than the resistance of the conductor, and the conductivity of the semiconductor is lower than the conductivity of the conductor.

30 30 30 a a a As an example, the semiconductor material in the first segmentmay be the same as the semiconductor material in the transistor in the gate driving circuit. For example, the first segmentincludes doped A-Si. Herein, the first segmentmay refer to a conductorized semiconductor trace that has been doped; it may be understood that the doped semiconductor trace does not conductorize the trace directly and can pass the current, but has a relatively great resistance, so that the current passing through is relatively small.

10 FIG. 30 30 30 30 30 b a b a In some embodiments, as shown in, the resistor structurefurther includes the second segmentthat is electrically connected to the first segment, and the second segmentand the first segmentare located in different layers.

30 30 30 30 30 30 30 2 a b a b a b In an example, the resistor structuremay include a plurality of first segmentsand a plurality of second segments. The first segmentand the second segmentare alternately arranged, and the first segmentand the second segmentare connected to each other through the via h.

30 41 30 41 b b As an example, the second segmentis located in the same film layer as the power supply trace. Under a condition that the two are located in the same film layer, materials of the two may be the same, so that the second segmentand the power supply tracemay be manufactured simultaneously.

30 41 30 30 41 b b a As another example, the second segmentand the power supply traceare located in different film layers. Under this condition, the second segment, the first segment, and the power supply traceare located in different film layers.

30 30 30 a b In the embodiments of the present application, the resistor structureis provided as including the first segmentand the second segmentthat are located in different film layers, so that it is beneficial to increase the length of the trace of the resistor structure in the same area and increase the total impedance of the resistor structure, thereby increasing the impedance of the transmission path of the power supply voltage VDD to the first transistor, reducing the impact of the change of the power supply voltage VDD on the first transistor, and protecting the first transistor from being damaged.

11 FIG. 14 FIG. 51 52 In some embodiments, as shown in any one ofto, the display panel further includes the pixel electrodeand the common electrode.

53 51 52 The display panel may be used as a display panel of a liquid crystal display and includes liquid crystal molecules. The pixel electrodeand the common electrodeprovide an electric field for controlling the rotation of the liquid crystal molecules.

Pixels of the display panel include pixel circuits, and the pixel electrode is connected to the transistor in the pixel circuit for receiving the data voltage transmitted by the transistor in the pixel circuit. The common electrode is used for receiving a common voltage. In an example, the pixel includes sub-pixels, and the common electrodes in the plurality of sub-pixels may be electrically connected to each other.

1 FIG. 11 FIG. 14 FIG. 30 30 30 41 51 30 52 a a a With reference to any one of, andto, the resistor structureincludes at least the first segment, the first segmentand the power supply traceare located in different film layers, the first segment is located in the same layer as the pixel electrode, and/or, the first segmentis located in the same layer as the common electrode.

54 51 52 54 In an example, the display panel further includes the base plate, and the pixel electrodeand the common electrodeare located on one side of the base plate.

11 FIG. 51 52 51 52 As an example, as shown in, the pixel electrodesare located in the same layer as the common electrodes. Herein, the first segment, the pixel electrode, and the common electrodemay be located in the same layer.

12 FIG. 13 FIG. 51 52 54 As another example, as shown inor, the film layer on which the pixel electrodesare located is located between the film layer on which the common electrodeis located and the base plate.

55 53 54 55 51 54 53 52 55 53 51 52 54 53 51 52 54 51 52 1 51 52 13 FIG. For example, the display panel further includes the counter plate, the liquid crystal moleculesare located between the base plateand the counter plate, the pixel electrodesare located on a side of the base platefacing the liquid crystal molecules, and the common electrodeis located on a side of the counter platefacing the liquid crystal molecules. For another example, as shown in, the pixel electrodesand the common electrodesare located on a side of the base platefacing the liquid crystal molecules; along the thickness direction of the display panel, the film layer where the pixel electrodesare located is located between the film layer where the common electrodesare located and the base plate, and the pixel electrodesand the common electrodesare spaced apart by the insulation layer. Herein, the film layer where the pixel electrodesare located may be provided with the first segments, and/or the film layer where the common electrodesare located may be provided with the first segments.

14 FIG. 52 51 54 51 52 54 53 52 51 54 51 52 As yet another example, as shown in, the film layer where the common electrodesare located is located between the film layer where the pixel electrodesare located and the base plate. For example, the pixel electrodesand the common electrodesare located on a side of the base platefacing the liquid crystal molecules; along the thickness direction of the display panel, the film layer where the common electrodesare located is located between the film layer where the pixel electrodesare located and the base plate. Herein, the film layer where the pixel electrodesare located may be provided with the first segments, and/or the film layer where the common electrodesare located may be provided with the first segments.

In the embodiments of the present application, the first segments of the resistor structures are located in the same film layer as the pixel electrodes and/or the common electrodes, so that the first segments and the pixel electrodes and/or the common electrodes may be manufactured simultaneously, and an additional manufacturing process is not added under a condition that additional first segments are added.

It may be understood that under a condition that the pixel electrodes and/or the common electrodes are metal electrodes, and the first segments are in the same film layer as the pixel electrodes and/or the common electrodes, the first segments are metal traces. In another embodiment, under a condition that the materials of the pixel electrodes and/or the common electrodes are ITO, and the first segments are in the same film layer as the pixel electrodes and/or the common electrodes, the materials of the first segments are ITO.

In some other embodiments, the first segments are semiconductor traces. For example, the first transistor includes an active layer, and the first segment and the active layer of the first transistor are located in the same film layer. Under this condition, the materials of the first segments and the active layers of the first transistors are the same, so that the first segments and the active layers of the first transistors may be manufactured simultaneously, and the additional manufacturing process is not added under a condition that the additional first segments are added.

15 FIG. 56 57 56 2 3 57 57 As an example, as shown in, the display panel includes the substrate, the gate metal layer Gate, the semiconductor layer B, the source/drain metal layer S/D, and the transparent conductive layerare stacked on a side of the substrate, andandrepresent insulation layers. In an example, the material of the semiconductor layer B includes A-Si, the material of the transparent conductive layerincludes ITO, the material of the gate metal layer Gate, and the material of the source/drain metal layer S/D includes metals such as copper, aluminum, molybdenum. Impedances of the materials of the source/drain metal layer S/D, the gate metal layer Gate, the transparent conductive layer, and the semiconductor layer B increase in sequence. Any one or more of these film layers may be provided with the first segments of the resistor structures, traces to be connected threreto are connected by vias.

57 In an example, the active layer of the first transistor is located in the semiconductor layer B, and the power supply trace is located in the gate metal layer Gate. For example, the semiconductor layer B and/or the transparent conductive layerwith relatively great material impedances may be provided with the first segment of the resistor structure.

16 FIG. 40 40 41 40 In some embodiments, as shown in, the display panel includes a plurality of transmission signal traceselectrically connected to the gate driving circuit, the transmission signal tracesinclude the power supply tracesfor transmitting the power supply voltage VDD, and other transmission signal tracesmay be used for transmitting the clock signal (CK), the trigger signal (STV), the reset signal (TRSET), the low level (LVGL), and the like.

30 40 41 a Along the direction perpendicular to the plane where the display panel is located, the first segmentoverlaps with the transmission signal tracesadjacent to the power supply traces. Herein, “the direction perpendicular to the plane where the display panel is located” may be understood as the thickness direction of the display panel.

40 40 41 30 40 41 30 40 41 a a For example, the plurality of transmission signal tracesextend along the first direction X and are arranged along the second direction Y, at least one transmission signal traceis provided on each side of the power supply tracealong the second direction Y, and the first segmentoverlaps with the transmission signal traceson two sides of the power supply trace, or the first segmentoverlaps with the transmission signal traceon at least one side of the power supply trace. In this scheme, there is no need to provide an additional area for providing the first segments, preventing an increase in the area of the circuit layout.

30 40 41 a The first segmentoverlaps with the transmission signal tracesother than the power supply traces, and at least the overlapped part may form an overlapped capacitor which can also add the delay effect, thereby avoiding the direct impact of the change of the power supply voltage VDD on the first transistor to reduce the problem that the first transistor is easily damaged.

40 30 a 16 FIG. It should be noted that the number of the transmission signal tracesand the shape of the first segmentshown inare not intended to limit the present application.

17 FIG. 30 41 30 41 30 30 30 40 a a a a a In some other examples, as shown in, the first segmentmay be provided in the same layer as the power supply traces; under a condition that the first segmentmay be provided in the same layer as the power supply traces, the first segmentmay be designed to be as the meander line in the shape of the square wave, the zigzag, the serpentine, and the like to increase the length of the first segment. Under this condition, along the direction perpendicular to the plane where the display panel is located, the first segmentdoes not overlap with the transmission signal traces.

18 FIG. 40 10 40 41 11 10 1 3 2 40 1 10 3 30 2 2 1 3 In yet some other embodiments, as shown in, the display panel includes a plurality of transmission signal traceselectrically connected to the gate driving circuit, and the transmission signal tracesinclude the power supply trace. The plurality of shift registersof the gate driving circuitare arranged along the first direction X. The display panel includes the trace area Q, the circuit area Q, and the resistor area Q, the transmission signal tracesare located in the trace area Q, the gate driving circuitis located in the circuit area Q, and the resistor structuresare located in the resistor area Q; along second direction Y, the resistor area Qis located between the trace area Qand the circuit area Q, and the second direction Y intersects the first direction X.

1 40 In the trace area Q, the plurality of transmission signal tracesextend along first direction X and are distributed along the second direction Y.

11 30 30 2 In an example, under a condition that different shift registersare connected to different resistor structures, the plurality of resistor structuresmay be arranged along the first direction X in the resistor area Q.

2 40 41 10 2 In an example, under a condition that the resistor area Qis located in the middle along the second direction Y, connection lines between the transmission signal tracesother than the power supply traceand the gate driving circuitmay pass through the resistor area Q.

1 40 3 2 30 In this embodiment, the trace area Qis used for providing the transmission signal traces, the circuit area Qis used for providing the gate driving circuit, the resistor area Qis used for providing the resistor structure, and providing different areas facilitates flexible design of structures in various areas.

1 2 3 1 1 3 2 Of course, in other examples, along the second direction Y, the trace area Qis located in the middle, and the resistor area Qand the circuit area Qare located on two sides of the trace area Q. Alternatively, the trace area Q, the circuit area Q, and the resistor area Qmay be provided based on other positional relationships.

1 FIG. 30 11 41 41 42 41 11 10 41 42 41 111 42 30 In some embodiments, as shown in, the resistor structuresare connected between the shift registersand the power supply trace. As an example, the display panel includes the power supply traceand the connection lines, the power supply traceis used for transmitting the power supply voltage VDD, the plurality of shift registersof the gate driving circuitare arranged along the first direction X, the power supply traceextends along the first direction X, and the connection linesare connected between the power supply traceand the first transistors; the connection linesinclude the resistor structures.

42 41 In an example, the impedances of the connection linesare greater than the impedance of the power supply trace.

42 In an example, at least a part of the segments of the connection linemay be the meander line of the square wave, the zigzag, the serpentine, and the like in shape.

1 FIG. 11 41 42 30 As shown in, the shift registersare electrically connected to the power supply tracethrough the connection lineseach including the resistor structure. In this example, it is ensured that the first transistor of each shift register is provided with the power supply voltage VDD through the resistor structure, so that the first transistor in each shift register is protected from being easily damaged.

19 FIG. 30 11 41 30 111 11 30 111 11 30 11 As another example, as shown in, under a condition that the resistor structuresare connected between the shift registersand the power supply trace, one resistor structuremay be connected to the first transistorsof the plurality of shift registers. For example, one resistor structuremay be connected to the first transistorsof two shift registers. In this embodiment, one resistor structureis shared by the plurality of shift registers.

2 FIG. 30 200 41 41 41 11 30 111 200 200 30 41 111 30 In some other embodiments, as shown in, the resistor structureis connected between the driving chipand the power supply trace. Specifically, the display panel includes the power supply tracefor transmitting the power supply voltage VDD, and the power supply traceis electrically connected to at least two stages of shift registersand connected between the resistor structureand the first transistors. The driving chipis configured to provide the power supply voltage VDD, and the power supply voltage VDD output by the driving chipis first transmitted to the resistor structure, next to the power supply trace, and then to each first transistor. It may be understood that, in this embodiment, the resistor structureis shared by the plurality of shift registers, so that the first transistors of the plurality of shift registers can be protected while reducing the total number of the resistor structures.

In an example, under a condition that the resistor structures are connected between the power supply trace and the first transistors, or under a condition that the power supply trace is connected between the resistor structure and the first transistors, traces of the resistor structures include, but are not limited to, the square wave, the zigzag, the serpentine, and the like in shape; the positions of the film layers of the resistor structures include, but are not limited to: at least a part of the segments of the resistor structure and the power supply trace being located in different film layers, at least a part of the segments of the resistor structure being located in the same film layer as the active layer of the first transistor, at least a part of the segments of the resistor structure being located in the transparent conductive layer, at least a part of the segments of the resistor structure being located in the same film layer as the pixel electrode and/or the common electrode of the display panel, and the like.

41 In some embodiments, the effect of the impedance of the power supply traceon the shift registers of each stage is considered, so that the resistance of the resistor structures connected to at least two different shift registers may be set to be different.

20 FIG. 11 11 1 11 2 30 1 30 2 30 1 41 11 1 30 2 41 11 2 11 1 41 11 2 41 30 1 30 2 In an example, as shown in, the plurality of shift registersinclude the first shift register-and the second shift register-, and the resistor structures include the first sub-resistor structure-and the second sub-resistor structure-; the first sub-resistor structure-is connected between the power supply traceand the first shift register-, and the second sub-resistor structure-is connected between the power supply traceand the second shift register-; the transmission path length of the power supply voltage VDD provided for the first shift register-in the power supply traceis less than the transmission path length of the power supply voltage VDD provided for the second shift register-in the power supply trace, and the resistance of the first sub-resistor structure-is greater than the resistance of the second sub-resistor structure-.

11 1 11 200 41 30 1 30 n n For example, the shift registers from the first shift register() to the n-th shift register() are arranged along the first direction X and the direction away from the driving chipand connected to the power supply tracethrough the resistor structures from the first resistor structure() to the n-th resistor structure(), respectively, the first shift register may be the i-th shift register, the second shift register may be the j-th shift register, 1≤i<j≤n, i and j are integers.

11 1 11 41 30 1 30 n n In an example, lengths of the transmission paths of the power supply voltage VDD provided for the shift registers from the first shift register() to the n-th shift register() in the power supply traceare increased in sequence, and resistance of the resistance structures from the first resistance structure() to the n-th resistance structure() may be decreased in sequence.

It may be understood that, in the embodiments of the present application, the impedances of the transmission paths of the power supply voltage received by different shift registers may be equalized, thereby improved the display uniformity while protecting the first transistors in the shift registers.

In some embodiments, the impedance of the resistor structure may be stable.

In some other embodiments, the impedance of the resistor structure may be variable. For example, the resistor structure has different impedances under different operating conditions of the display panel. In this way, different protection requirements for the first transistors in the shift registers under different operating conditions are satisfied.

The inventor has found that the higher the temperature is, the greater the conductivity of the active layer in the transistor is, the greater the current passing through the transistor is, and the greater the damage to the first transistor due to the change in the power supply voltage is. As an example, as the temperature increases, the impedance of the resistor structure becomes greater. Thus, the problem that the first transistors are easily damaged under the high temperature is reduced.

5 FIG. 7 FIG. 111 111 30 In some embodiments, as shown into, the gate of the first transistorand the first electrode thereof need to be provided with the power supply voltage VDD, and at least the gate of the first transistoris provided with the supply voltage VDD through the resistor structure. Whether the first transistor is turned on or not is mainly affected by the potential of the gate thereof, therefore, the gate thereof is provided with the power supply input signal through the resistor structure, so that the impact of the great current on the gate of the first transistor due to an excessive instantaneous change of the provided power supply voltage may be reduced, that is, the direct impact of the change of the power supply voltage on the gate of the first transistor is avoided to reduce the problem that the first transistor is easily damaged.

21 FIG. 22 FIG. 21 FIG. 22 FIG. 111 30 111 30 111 30 In other examples, as shown inand, the gate of the first transistorand the first electrode thereof are provided with the power supply voltage VDD through the resistor structure. For example, as shown in, the gate of the first transistorand the first electrode thereof are provided with the power supply voltage VDD through one resistor structure; or as shown in, the gate of the first transistorand the first electrode thereof are provided with the power supply voltage VDD through different resistor structures.

111 111 111 In some embodiments, the operation phase of the display panel includes the first phase in which the power supply voltage VDD is at the first level, and the first level controls the first transistorto be turned on. For example, the first transistoris the N-type transistor, and the first level is the high potential vgh; or the first transistoris the P-type transistor, and the first level is the low potential vgl. Herein, the high potential vgh may be approximately 30V, and the low potential vgl may be approximately −10V.

6 FIG. 7 FIG. In an example, under a condition that the operation phase of the display panel includes the first phase, as shown inor, the shift register may include only one first transistor.

5 FIG. 16 17 30 31 32 1 2 16 1 31 17 2 32 In some embodiments, as shown in, the shift register includes two first transistors which are the transistor Mand the transistor M, respectively; the resistor structureincludes the first resistor structureand the second resistor structure, and the power supply voltage VDD includes the first power supply voltage VDDand the second power supply voltage VDD, one of the first transistors (such as the transistor M) is provided with the first power supply voltage VDDthrough the first resistor structure, and the other of the first transistor (such as the transistor M) is provided with the second power supply voltage VDDthrough the second resistor structure.

5 FIG. 1 2 The shift register shown inincludes two pull-down maintenance modules, and the first power supply voltage VDDand the second power supply voltage VDDare each responsible for controlling one pull-down maintenance module.

23 FIG. 1 2 1 2 1 1 2 2 1 2 For example, as shown in, the first power supply voltage VDDand the second power supply voltage VDDare signals with interleaved high level and low level; specifically, the operation phase of the display panel includes the first phase pand the second phase pwhich are provided alternately, in the first phase p, the first power supply voltage VDDis at the first level, the second power supply voltage VDDis at the second level, in the second phase p, the first power supply voltage VDDis at the second level, and the second power supply voltage VDDis at the first level; the second level is lower than the first level, the first level controls the first transistor to be turned on, and the second level controls the first transistor to be turned off. In this embodiment, an example in which the first transistor is the N-type transistor is given for illustration. It may be understood that the same applies for the P-type first transistor, and under a condition that the first transistor is the P-type transistor, the first level is less than the second level.

1 2 The first power supply voltage VDDand the second power supply voltage VDDare signals with interleaved high level and low level, so that one of the pull-down maintenance modules is in operation while the other of the pull-down maintenance modules is at rest, and each of the two pull-down maintenance modules is at rest for half of the given duration, thereby increasing the reliability of the shift registers.

1 2 41 41 411 1 412 2 5 FIG. The first power supply voltage VDDand the second power supply voltage VDDare signals with different time sequences and may be transmitted by different traces. For example, as shown in, the display panel further includes the power supply traces, and the power supply tracesinclude the first power supply tracefor transmitting the first power supply voltage VDDand the second power supply tracefor transmitting the second power supply voltage VDD.

31 411 411 31 In an example, the first resistor structuremay be connected between the first power supply traceand one of the first transistors, or the first power supply tracemay be connected between the first resistor structureand one of the first transistors.

32 412 412 32 The second resistor structuremay be connected between the second power supply traceand the other of the first transistors, or the second power supply tracemay be connected between the second resistor structureand the other of the first transistors.

31 32 30 Shape features, material features, film layers, and the like of the first resistor structureand/or the second resistor structuremay be described as the resistor structurein the above embodiments, which is not repeated herein.

23 FIG. 3 1 2 3 1 2 1 2 3 In some embodiments, still referring to, the operation phase of the display panel further includes the third phase pin which the level of the first power supply voltage VDDand the level of the second supply voltage VDDare changed, the third phase pis located between the first phase pand the second phase p, the first phase pand the second phase pinclude frame phases, and the third phase pincludes the blanking phase located between adjacent two of the frame phases. The blanking phase may be referred to as the blank phase.

1 2 In the frame phases, each stage of shift registers of the gate driving circuit output effective pulse signals one by one to carry out progressive scanning of the pixels and write data voltages into the corresponding pixels, so that the display panel displays normally. In the blanking phase, the gate driving circuit does not output the effective pulse signals and does not write the data voltages, therefore, the first power supply voltage VDDand the second power supply voltage VDDare provided in the blanking phase for the level changing, which does not affect the normal display of the display panel.

1 3 2 3 In an example, the duration of the first phase pis great than the duration of the third phase p, and the duration of the second phase pis greater than the duration of the third phase p.

1 2 In an example, the duration of the first phase pis equal to the duration of the second phase p.

In the above embodiments, the voltage changing process of the power supply voltage actually received by the first transistors is elongated by adding resistor structures in the display panel to reduce the impact of the great current on the first transistors due to the excessive instantaneous change of the provided power supply voltage.

Based on the same inventive concept, the power supply voltage output by the driving chip may be changed directly; for example, the delay of the change of the power supply voltage output by the driving chip is increased, that is, the duration for changing the levels of the power supply voltage output by the driving chip is increased to directly avoid the impact of the direct jump of the power supply voltage in a short duration on the first transistor, thereby protecting the first transistor from being damaged.

24 FIG. 27 FIG. 1 2 3 3 1 2 Specifically, embodiments of the present application further provide a driving chip, as shown into, the driving chip is configured to provide the power supply voltage VDD for the gate driving circuit in the display panel, the power supply voltage VDD provided by the driving chip is at the first level in the first phase p, at the second level in the second phase p, and at the third level in the third phase p, the third phase pis located between the first phase pand the second phase p, the third level is between the first level and the second level, and at the first level, the first transistor in the gate driving circuit is turned on.

It should be noted that, in the time sequence chart of the present application, the first level is the high potential, the second level is the low potential, and the first transistor is the N-type transistor, which is not intended to limit the present application. The same applies for the P-type first transistor, under a condition that the first transistor is the P-type transistor, the first level is the low level, and the second level is the high level.

3 The third phase pis the changing phase in which the power supply voltage VDD is changed between the first level and the second level, that is, in the embodiments of the present application, the power supply voltage output by the driving chip is changed directly, and the duration for changing the levels of the power supply voltage output by the driving chip is increased to directly avoid the impact of the direct jump of the power supply voltage in a short duration on the first transistor, thereby protecting the first transistor from being damaged.

In some embodiments, the gate driving circuit is further provided with the clock signal, the duration for the clock signal to jump from the first level to the second level is t2, the duration of the third phase is t1, and t1>t2 That is, the duration for changing the levels of the power supply voltage VDD output by the driving chip is greater than the duration for changing the levels of the clock signal.

In other examples, the specific duration of the third phase may be set as needed.

blank blank In some embodiments, the blanking stage is included between adjacent frames of the display panel, the third stage is subordinate to the blanking stage, the duration of the third phase is t1, the duration of the blanking phase is t, and t1≤t.

In the frame phases, each stage of shift registers of the gate driving circuit output effective pulse signals one by one to carry out progressive scanning of the pixels and control the pixels to emit light, so that the display panel displays normally. In the blanking phase, the gate driving circuit does not output effective pulse signals, therefore, the power supply voltage VDD is provided in the blanking phase for the level changing, which does not affect the normal display of the display panel.

In some embodiments, the third level is the gradually changing level. That is, the power supply voltage VDD gradually transitions from the first level to the second level, and the less the variation of the power supply voltage VDD is, the less the current on the transmission path thereof is, which is more beneficial to protect the first transistor.

24 FIG. 3 As an example, as shown in, the third level of the power supply voltage VDD in the third phase pchanges in a step-like manner.

3 1 2 3 Specifically, under a condition that the third level of the power supply voltage VDD in the third phase pchanges in the step-like manner, the variation of the third level may be the same each time. For example, ΔV=ΔV=ΔV.

This embodiment may ensures that under a condition that the power supply voltage VDD changes each time, the Vgs of the first transistor is the same, that is, the impact on the first transistor is the same, so that the greater impact on the first transistor is avoided.

25 FIG. 3 As another example, as shown in, the third level of the power supply voltage VDD in the third phase pchanges in a diagonal line.

26 FIG. 27 FIG. 3 As yet another example, as shown inor, the third level of the power supply voltage VDD in the third phase pchanges in a curve.

26 FIG. 3 Optionally, as shown in, the slope of the changing curve of the third level of the power supply voltage VDD in the third phase pis gradually reduced.

3 24 FIG. 26 FIG. It should be noted that the changing forms of the third level of the power supply voltage VDD in the third phase pinclude, but are not limited to, the changing forms shown into.

Based on the same inventive concept, the signal delay structure may be added in the driving chip; for example, the signal delay structure includes the resistor structure to elongate the voltage changing process of the power supply voltage actually received by the first transistor, so as to reduce the impact of the great current on the first transistors due to the excessive instantaneous change of the provided power supply voltage.

28 FIG. 200 201 202 201 202 201 202 Specifically, as shown in, the driving chipincludes the signal generation circuitand the signal delay structure, the signal generation circuitis configured to generate the power supply voltage, one end of the signal delay structureis electrically connected to an output of the signal generation circuit, and the other end of the signal delay structureis electrically connected to the gate driving circuit in the display panel.

202 The signal delay structurecan elongate the voltage changing process of the power supply voltage actually received by the first transistor to reduce the impact of the great current on the first transistors due to the excessive instantaneous change of the provided power supply voltage.

202 For example, the signal delay structureincludes the resistor structure.

29 FIG. 29 FIG. 29 FIG. 1000 100 200 1000 The present application further provides a display apparatus including the display panel according to the present application, and/or including the driving chip according to the embodiments of the present application. With reference towhich is a schematic structural view of the display apparatus according to the embodiments of the present application. The display apparatusinincludes the display panelaccording to any one of the above embodiments of the present application and/or the driving chipaccording to any one of the above embodiments of the present application. In the embodiment of, the mobile phone is only given as an example to illustrate the display apparatus, and it may be understood that, the display apparatus according to the embodiments of the present application may be other display apparatus with the display function, such as, a wearable product, a computer, a television, and a vehicle-mounted display apparatus, which are not are not particularly limited by the embodiments of the present application. The display apparatus according to the embodiments of the present application has the beneficial effects of the display panel according to the embodiments of the present application, reference is made to the specific description of the display panel in the above embodiments for details, which are not repeated herein.

It should be noted that the transistors in the embodiments of the present application may be the N-type transistors or the P-type transistors. For the N-type transistors, the ON-level is the high level and the OFF-level is the low level. That is, the N-type transistors are turned on under a condition that gate potential of the N-type transistors is at the high level and are turned off under a condition that gate potential of the N-type transistors is at the low level. For the P-type transistors, the ON-level is the low level and the OFF-level is the high level. That is, the P-type transistors are turned on under a condition that gate potential of the P-type transistors is at the low level and are turned off under a condition that gate potential of the P-type transistors is at the high level.

In specific embodiments, the gate of the transistor is used as its control terminal, and depending on a signal of the gate and the type of the transistor, its first terminal may be used as the source and its second terminal may be used as the drain, or alternatively, its first terminal may be used as the drain and its second terminal may be used as the source, which is not limited herein. Further, the ON-level and the OFF-level are used in a general sense in the embodiments of the present application, the ON-level refers to any level that can turn on the transistor, and the OFF-level refers to any level that can cut off/turn off the transistor.

It should be noted that in the above embodiments shown in the drawings, the resistor is represented by a single resistor, and the capacitor is represented by a single capacitor. In other embodiments, the resistor may be an integration of resistors in series, resistors in parallel, resistors in or series-parallel, and the capacitor may be an integration of capacitors in series, capacitors in parallel, or capacitors in series-parallel. The specific parameters of various devices may be set based on actual requirements, which is not limited in the present application.

The above embodiments of the present application do not exhaustively describe all the details and do not limit the present application to only the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in the description to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and make modifications based on the present application. The present application is limited only by the claims, along with their full scope and equivalents.