Semiconductor Device

This application claims benefit of priority 35 U.S.C. § 119 to Korean Patent Application No. 10-2024-0147390 filed on Oct. 25, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

A memory device may provide a function of storing and erasing data, or reading stored data and transmitting the same externally. The memory device may include a plurality of memory dies packaged as one, and some of the memory dies included in the memory device may share a channel for communicating with an external memory controller or the like. When an amount of current consumption increases excessively in one of the memory dies sharing the channel, an amount of power consumption of the memory device may exceed an effective power range that a power circuit supplying power voltage to the memory device can supply. Accordingly, performance of a memory device and/or performance of a system including the memory device may be degraded, and unintended malfunctions, data loss, or the like may occur.

An aspect of the present disclosure is to provide a memory device that may suppress a problem situation that may occur when power consumption of the memory device exceeds an effective power range by respectively allowing memory dies sharing a channel to share a peak value of current consumption.

According to an aspect of the present disclosure, a memory device includes a first memory die including a first monitoring pad connected to a monitoring line, and a first current monitoring logic outputting a first current monitoring signal to the first monitoring pad; and a second memory die including a second monitoring pad connected to the monitoring line, and a second current monitoring logic outputting a second current monitoring signal to the second monitoring pad, wherein the first current monitoring signal includes first current data of N bits (where N is a natural number equal to greater than 2) encoding a peak value of a consumption current of the first memory die, and the second current monitoring signal includes second current data of N bits encoding a peak value of a consumption current of the second memory die, the first current monitoring logic and the second current monitoring logic alternately occupy the monitoring line, and the first current monitoring logic recovers a first clock signal using the second current monitoring signal output to the monitoring line, and the second current monitoring logic recovers a second clock signal using the first current monitoring signal output to the monitoring line.

According to an aspect of the present disclosure, a memory device includes a package substrate; and a plurality of memory dies mounted on the package substrate and configured to share a channel, wherein each of the plurality of memory dies includes a monitoring pad electrically isolated from the channel, wherein the monitoring pad is connected to a monitoring line, and the plurality of memory dies output a current monitoring signal including current data encoding a peak value of a consumption current to the monitoring line, while alternately occupying the monitoring line.

According to an aspect of the present disclosure, a memory device includes a plurality of memory dies configured to share a channel, wherein each of the plurality of memory dies includes a monitoring pad, and the monitoring pad is connected to a monitoring line,

wherein the plurality of memory dies alternately occupy the monitoring line and output a current monitoring signal including a peak value of a consumption current to the monitoring line, wherein the current monitoring signal output by one memory die, among the plurality of memory dies, to the monitoring line is transmitted to remaining memory dies among the plurality of memory dies, and wherein each of the remaining memory dies stops a control operation when the peak value of the consumption current of the one memory die is equal to greater than a predetermined reference value.

Hereinafter, preferred implementations will be described with reference to the attached drawings as follows.

1 FIG. is a view simply illustrating a memory device according to an implementation.

1 FIG. 10 11 18 20 11 18 20 22 20 21 11 18 20 Referring to, a memory deviceaccording to an implementation may include a plurality of memory diestoand a package substrate. The plurality of memory diestomay be mounted in a stack structure on an upper surface of the package substrate, and a plurality of solder ballsmay be formed on a lower surface of the package substrate. A protective layercovering the plurality of memory diestomay be formed on the upper surface of the package substrate.

1 FIG. 11 18 11 14 15 18 11 14 23 20 1 15 18 24 20 2 In an implementation illustrated in, the plurality of memory diestomay be stacked to form a step shape in one direction. First to fourth memory diestomay be stacked to form a step shape in a first direction, and fifth to eighth memory diestomay be stacked to form a step shape in a direction, opposite to the first direction. The first to fourth memory diestomay be connected to padsexposed on the upper surface of the package substrateby a first wire W, and the fifth to eighth memory diestomay be connected to padsexposed on the upper surface of the package substrateby a second wire W.

11 18 11 18 20 11 18 10 1 2 1 FIG. The stack structure of the plurality of memory diestois not limited as illustrated in. For example, the plurality of memory diestomay be stacked in a vertical direction, and may be electrically connected to the package substrateby through-silicon via structures penetrating at least a portion of the plurality of memory diesto. In a structure of the above-described implementation, the memory devicemay not include the wires Wand W.

1 FIG. 11 14 15 18 In an implementation illustrated in, the first to fourth memory diestomay share a first channel, and the fifth to eighth memory diestomay share a second channel. The first and second channels may include signal paths for transmitting a command signal, an address signal, a data signal, a chip enable signal, a write/read enable signal, or the like, respectively.

11 14 15 18 22 20 The first to fourth memory diestosharing the first channel may monitor each other's peak values of consumption current through a monitoring line. In addition, the fifth to eighth memory diestosharing the second channel may also monitor each other's peak values of consumption current through a monitoring line. The monitoring lines may be electrically separated from the first channel and the second channel, and may also be electrically separated from the solder ballsformed on the lower surface of the package substrate.

11 14 11 12 14 11 For example, the first to fourth memory diestomay alternately and sequentially output peak values of consumption current through a monitoring line. When the first memory dieoutputs a peak value of consumption current, the second to fourth memory diestomay control whether to execute a control operation, timing of execution of the control operation, or the like, while monitoring the peak value of consumption current of the first memory die.

11 14 10 10 10 10 For example, when an operation of consuming a large amount of current is performed in each of two or more of the first to fourth memory diesto, power consumption of the memory devicemay exceed an effective range of power that a power circuit may supply to the memory device. In this case, a phenomenon, such as performance of the memory deviceand/or performance of a system including the memory devicedeteriorates, an operation is temporarily suspended, or the like, may occur.

11 18 11 12 14 11 10 10 In an implementation, such a phenomenon may be effectively suppressed by each of the memory diestosharing one channel monitoring the peak value of the current consumption with each other. For example, when a control operation of consuming a relatively large amount of current, such as a program operation or an erase operation, may be performed in the first memory die, the second to fourth memory diestomay temporarily suspend the control operation and then resume the same again with reference to the peak value of the current consumption of the first memory die, respectively. Therefore, the power consumption of the memory devicemay be managed such that the power circuit does not exceed the effective range of power that may be supplied to the memory device.

11 18 11 18 11 18 11 18 In an implementation, the memory diestosharing the channel may monitor the peak value of the current consumption with each other through a monitoring line without a separate clock signal. Therefore, the separate clock line for monitoring and sharing the peak value of the current consumption with each other may not be required, and each of the memory diestomay monitor current consumption of other memory dies of the memory diestosimply by adding one pad connected to the monitoring line to each of the memory diesto.

2 3 FIGS.and are block diagrams simply illustrating a system including a memory device according to an implementation.

2 FIG. 2 FIG. 30 40 50 50 51 58 40 51 58 1 2 40 51 54 1 55 58 2 First, referring to, a systemaccording to an implementation may include a memory controllerand a memory device. The memory devicemay include a plurality of memory diesto, and the memory controllermay be connected to the plurality of memory diestothrough a plurality of channels CHand CH. In an implementation illustrated in, the memory controllermay be connected to first to fourth memory diestothrough a first channel CH, and may be connected to fifth to eighth memory diestothrough a second channel CH.

1 2 1 2 The first channel CHand the second channel CHmay include a plurality of signal paths through which a signal is transmitted, respectively. For example, the first channel CHand the second channel CHmay include a plurality of signal paths for transmitting a chip enable signal, a write/read enable signal, a data signal, a data strobe signal, a command signal, an address signal, or the like, respectively.

51 58 51 58 51 54 1 51 54 51 54 51 53 54 In an implementation, each of the plurality of memory diestomay include a current monitoring logic monitoring consumption current of other memory diesto. For example, the first to fourth memory diestosharing the first channel CHmay be commonly connected to one monitoring line, respectively, and may sequentially output peak values of consumption current alternately through the monitoring line, respectively. For example, the peak values of consumption current output by each of the first to fourth memory diestoto the monitoring line may be monitored by the other memory diesto. For example, the first to third memory diestomay monitor the peak values of consumption current output by the fourth memory dieto the monitoring line.

51 58 54 51 53 50 Each of the memory diestomay stop and/or postpone execution of a control operation with reference to the results of monitoring the peak values of consumption current. For example, when the peak value of the consumption current output by the fourth memory dieto the monitoring line may be greater than a predetermined reference value, each of the first to third memory diestomay stop and/or postpone execution of the control operation. Therefore, the total power consumption of the memory devicemay be controlled within a range not exceeding a maximum value of allowable power consumption.

3 FIG. 2 FIG. 100 110 120 120 51 58 50 120 121 123 125 127 125 115 110 Referring to, a systemaccording to an implementation may include a memory controllerand a memory die. The memory diemay be one of the plurality of memory diestoincluded in the memory devicedescribed above with reference to. The memory diemay include a cell region, a peripheral circuit region, a memory interface circuit, a current monitoring logic, and the like. The memory interface circuitmay be connected to a controller interface circuitof the memory controller.

125 115 123 120 121 110 123 121 121 The memory interface circuitmay receive a chip enable signal nCE, a write enable signal nWE, a read enable signal nRE, a command latch enable signal CLE, an address latch enable signal ALE, and a data strobe signal DQS, from the controller interface circuitthrough a plurality of pads. The peripheral circuit regionof the memory diemay control the cell regionin response to a command/address signal CMD/ADDR included in a signal received from the memory controller. For example, the peripheral circuit regionmay store data DATA received as a data signal DQ in the cell regionor read data DATA stored in the cell region.

127 120 120 127 123 127 The current monitoring logicof the memory diemay detect and output a peak value of current consumed by the memory die. For example, the current monitoring logicmay output a current monitoring signal CMS including a peak value of current consumption determined according to a control operation executed by the peripheral circuit regionto a monitoring line. For example, the current monitoring logicmay encode the peak value of the current consumption into current data of N bits (where N is a natural number equal to greater than 2), and may output a current monitoring signal CMS including the current data to the monitoring line.

120 120 120 Using the current monitoring signal CMS output by the memory die, a peak value of current consumed by other memory dies may be monitored in the memory die. In the same manner, the memory diemay monitor the peak value of the current consumed by each of the other memory dies based on a current monitoring signal CMS output by each of the other memory dies.

120 123 121 120 110 120 120 123 For example, in a program operation, an erase operation, or the like of the memory die, the peripheral circuit regionmay apply a relatively large amount of voltage to the cell region, and current consumption of the memory diemay increase. Therefore, when the program operation, the erase operation, and the like are simultaneously performed in memory dies connected to the same channel as the memory controller, power consumption of a memory device including the memory diemay exceed an allowable range. When a peak value of current consumed by another memory die is equal to or exceeds a predetermined reference value, the memory diemay temporarily suspend or postpone a control operation performed by the peripheral circuit region, thereby managing the power consumption of the memory device such that it does not exceed the allowable range.

4 5 FIGS.and are views illustrating operations of memory dies included in a memory device according to an implementation.

4 FIG. 4 FIG. 200 210 240 210 240 First, referring to, a memory deviceaccording to an implementation may include a plurality of memory diesto. In an implementation illustrated in, the plurality of memory diestomay be connected to a memory controller through a channel, and may be commonly connected to a monitoring line ML.

210 240 1 4 1 4 210 240 5 FIG. The plurality of memory diestomay sequentially occupy the monitoring line ML, and may output current data CDto CDto the monitoring line ML. Referring to, current monitoring signals CMSto CMSof each of the plurality of memory diestomay be sequentially output to the monitoring line ML alternately.

210 1 220 2 230 3 240 4 For example, a first memory diemay output a first current monitoring signal CMSwhile occupying the monitoring line ML for a first time period, and a second memory diemay output a second current monitoring signal CMSwhile occupying the monitoring line ML for a second time period after the first time period. A third memory diemay output a third current monitoring signal CMSwhile occupying the monitoring line ML for a third time period after the second time period, and a fourth memory diemay output a fourth current monitoring signal CMSwhile occupying the monitoring line ML for a fourth time period after the third time period.

210 240 1 4 210 1 1 2 210 220 The plurality of memory diestomay output the current monitoring signals CMSto CMSto the monitoring line ML, respectively, while changing a transmission/reception mode. For example, the first memory diemay operate in the transmission mode, and may output the first current monitoring signal CMSto the monitoring line ML. After a last bit of the first current monitoring signal CMSis output to the monitoring line ML and before a first bit of the second current monitoring signal CMSis output to the monitoring line ML, the first memory diemay switch from the transmission mode to the reception mode, and the second memory diemay switch from the reception mode to the transmission mode.

220 240 1 210 230 240 2 210 220 240 3 210 230 4 During the first time, the second to fourth memory diestomay receive the first current monitoring signal CMS, and during the second time, the first, third, and fourth memory dies,, andmay receive the second current monitoring signal CMS. During the third time, the first, second, and fourth memory dies,, andmay receive the third current monitoring signal CMS, and during the fourth time, the first to third memory diestomay receive the fourth current monitoring signal CMS.

220 240 210 1 210 230 240 220 2 The second to fourth memory diestomay detect a first peak value of current consumed by the first memory diewith reference to the first current monitoring signal CMS, and when the first peak value is equal to greater than a predetermined reference value, execution of a control operation may be temporarily suspended. The first, third and fourth memory dies,, andmay detect a second peak value of current consumed by the second memory diewith reference to the second current monitoring signal CMS, and when the second peak value is equal to greater than the predetermined reference value, the execution of the control operation may be temporarily suspended.

210 220 240 230 3 210 230 240 4 The first, second, and fourth memory dies,, andmay detect a third peak value of current consumed by the third memory diewith reference to the third current monitoring signal CMS, and when the third peak value is equal to greater than the predetermined reference value, the execution of the control operation may be temporarily suspended. The first to third memory diestomay detect a fourth peak value of current consumed by the fourth memory diewith reference to the fourth current monitoring signal CMS, and when the fourth peak value is equal to greater than the predetermined reference value, the execution of the control operation may be temporarily suspended.

210 240 210 230 240 4 210 230 According to an implementation, each of the plurality of memory diestomay temporarily suspend the execution of the control operation when a sum of peak values of current is equal to greater than a reference value. For example, each of the first to third memory diestomay detect the fourth peak value of the current consumed by the fourth memory diewith reference to the fourth current monitoring signal CMS. Each of the first to third memory diestomay temporarily suspend the execution of the control operation when a sum of internally calculated peak values of the current consumed plus the fourth peak value is equal to greater than the reference value.

210 240 200 200 In the above manner, each of the plurality of memory diestomay adjust execution time of the control operation with reference to the peak value of the current consumed by the other memory dies. Therefore, the power consumption of the memory deviceis limited not to exceed an allowable range specified in a predetermined specification, and operational stability of the memory devicemay be improved and power consumption may be reduced.

4 FIG. 210 240 1 4 210 240 210 240 As illustrated in, in an implementation, the plurality of memory diestomay output only the current monitoring signals CMSto CMSto the monitoring line ML without a separate clock signal. Therefore, in implementing a current monitoring function between the plurality of memory diestosharing a channel, only one monitoring pad may be added to each of the plurality of memory diesto.

210 240 1 4 210 240 1 4 For example, each of the plurality of memory diestomay include a clock recovery circuit recovering the clock signal from the current monitoring signals CMSto CMSoutput to the monitoring line ML. Each of the plurality of memory diestomay obtain the peak value of the consumption current included in the current monitoring signals CMSto CMSusing the recovered clock signal.

6 FIG. is a block diagram simply illustrating a memory device according to an implementation.

6 FIG. 300 310 320 330 340 350 360 310 320 330 Referring to, a memory dieaccording to an implementation may include a cell region, a row decoder, a page buffer circuit, a memory interface circuit, a current monitoring logic, a control logic, and the like. The cell regionmay include memory cells disposed in a cell array form. The memory cells may be connected to the row decoderthrough word lines, common source lines, ground select lines, and string select lines, and may be connected to the page buffer circuitthrough bit lines.

340 330 330 350 300 320 330 340 350 360 The memory interface circuitmay transmit data read from memory cells by the page buffer circuitexternally, or may transfer data received from the outside to the page buffer circuit. The current monitoring logicmay monitor a peak value of current consumed by another memory die by using current data output by another memory die sharing the same channel as the memory die. The row decoder, the page buffer circuit, the memory interface circuit, and the current monitoring logicmay be controlled by the control logic.

350 351 353 353 351 In an implementation, the current monitoring logicmay include a clock recovery circuit, a current data input/output circuit, and the like. The current data input/output circuitmay output a current monitoring signal to a monitoring line ML or receive the current monitoring signal from the monitoring line ML. The clock recovery circuitmay recover a clock signal using the current monitoring signal received from the monitoring line ML.

300 300 300 300 Therefore, the memory dieand other memory dies sharing the same channel as the memory diemay send and receive current monitoring signals to the monitoring line ML without a separate clock signal. It may be sufficient to add only one monitoring pad to the memory dieto share a peak value of consumed current, and an increase in area of the memory diemay be minimized.

350 300 360 350 360 360 320 330 300 The current monitoring logicmay output a current monitoring signal including a peak value of current consumed by the memory dieto the outside, in response to control of the control logic. The current monitoring logicmay receive a current monitoring signal of another memory die, and may transmit a received current monitoring signal to the control logic. When a peak value of current consumed by another memory die exceeds a reference value, the control logicmay temporarily suspend a control operation performed by the row decoderand the page buffer circuiton the memory cells. Therefore, it is possible to control power consumption of a memory device including memory dies sharing the same channel with the memory dienot to exceed an allowable range, and to secure a stable operation of the memory device and a system including the memory device.

7 9 FIGS.to are views illustrating an operation of a memory device according to an implementation.

7 FIG. 1 4 1 4 may be a view illustrating current monitoring signals CMSto CMSoutput by memory dies included in a memory device and sharing the same channel. As described above with reference to other implementations, memory dies sharing a channel may be commonly connected to a monitoring line, and may alternately output current monitoring signals CMSto CMSto the monitoring line.

7 FIG. 7 FIG. 1 2 3 4 1 4 In an implementation illustrated in, first to fourth memory dies included in a memory device may be commonly connected to a monitoring line. The first memory die may output a first current monitoring signal CMS, the second memory die may output a second current monitoring signal CMS, the third memory die may output a third current monitoring signal CMS, and the fourth memory die may output a fourth current monitoring signal CMS. Therefore, as illustrated in, the first to fourth current monitoring signals CMSto CMSmay be output in sequence in an alternating manner.

1 4 1 4 1 1 4 7 FIG. The first to fourth current monitoring signals CMSto CMSmay be a return-to-zero (RZ) signal. Referring to, the first to fourth current monitoring signals CMSto CMSmay return to a first voltage V, which may be a reference voltage, every cycle (TPto TP).

1 4 1 4 1 4 7 FIG. Each of the first to fourth memory dies may encode a peak value of a consumption current into N-bit current data. Each of the first to fourth memory dies may occupy the monitoring line for a time corresponding to N cycles (TPto TP), and may output 1 bit of the N-bit current data in each of the N cycles (TPto TP). In an implementation illustrated in, each of the first to fourth memory dies may output 4-bit current data to the monitoring line, 1 bit per cycle, for four cycles (TPto TP). The number of bits of the current data may be changed depending on an implementation.

1 4 1 2 1 4 1 2 1 3 1 4 3 2 1 A minimum voltage of the current monitoring signals CMSto CMSmay be the first voltage V, and a maximum voltage may be a second voltage V. The current monitoring signals CMSto CMSmay swing between the first voltage Vand the second voltage V, or between the first voltage Vand a third voltage V, in each of the four cycles (TPto TP) that output 4-bit current data to the monitoring line. The third voltage Vmay be an intermediate voltage, less than the second voltage Vand greater than the first voltage V.

7 FIG. 1 4 1 2 1 4 1 3 In an implementation illustrated in, the current monitoring logic of the memory die may output data of logic ‘1’ by outputting the current monitoring signals CMSto CMSthat swing between the first voltage Vand the second voltage Vduring one cycle. In addition, the current monitoring logic may output data of logic ‘0’ by outputting the current monitoring signals CMSto CMSthat swing between the first voltage Vand the third voltage Vduring one cycle.

1 1 2 1 3 4 1 4 1 3 2 1 For example, the first current monitoring signal CMSmay swing between the first voltage Vand the second voltage Vduring each of a first cycle TP, a third cycle TP, and a fourth cycle TPamong the four cycles (TPto TP), and may swing between the first voltage Vand the third voltage Vduring a second cycle TP. A first current monitoring logic included in the first memory die may output first current data of [1011], which encodes a peak value of current consumed by the first memory die, as the first current monitoring signal CMS.

2 3 4 1 4 7 FIG. Similarly, a second current monitoring logic of the second memory die may output second current data of [0110], which encodes a peak value of current consumed by the second memory die, as the second current monitoring signal CMS, and a third current monitoring logic of the third memory die may output third current data of [0010], which encodes a peak value of current consumed by the third memory die, as the third current monitoring signal CMS. A fourth current monitoring logic of the fourth memory die may output fourth current data of [1001], which encodes a peak value of current consumed by the fourth memory die, as the fourth current monitoring signal CMS. As illustrated in, it can be understood that during a time when the first to fourth memory dies output the current monitoring signals CMSto CMS, the peak values of the current consumption in the first memory die and the fourth memory die may be relatively large.

1 4 1 Each of the first to fourth memory dies may monitor peak values of current consumed by other memory dies with reference to the current monitoring signals CMSto CMSand, based thereon, determine whether to execute/stop a control operation. For example, assuming that the first current data included in the first current monitoring signal CMSoutput by the first memory die may be greater than a predetermined reference value, each of the second to fourth memory dies may temporarily stop executing the control operation such as a program operation, an erase operation, a read operation, or the like. Therefore, while the first memory die consumes a large amount of current, current consumption of the other second to fourth memory dies may be reduced, and power consumption of the memory device including the first to fourth memory dies may be limited to an acceptable range.

7 FIG. 1 1 4 1 4 In an implementation illustrated in, both logic ‘1’ and logic ‘0’ may be expressed as voltage levels greater than the first voltage V. The current monitoring logic included in each of the first to fourth memory dies may recover a clock signal from the current monitoring signal CMSto CMSreceived through the monitoring line, and may decode current data encoded as the current monitoring signal CMSto CMSusing a recovered clock signal.

8 FIG. 9 FIG. 8 FIG. 1 2 1 1 may be an enlarged view of a first current monitoring signal CMS, andmay be an enlarged view of a second current monitoring signal CMS. In an implementation illustrated in, while a first current monitoring logic of a first memory die occupies a monitoring line and outputs a first current monitoring signal CMS, a current monitoring logic of each of second to fourth memory dies may receive the first current monitoring signal CMS.

1 1 1 2 1 1 2 3 The current monitoring logic of each of the second to fourth memory dies may determine a clock cycle TCLK required to recover a clock signal by counting a time between a first rising edge of the first current monitoring signal CMScorresponding to a time point of a first cycle TPand a second rising edge of the first current monitoring signal CMScorresponding to a time point of a second cycle TP. The current monitoring logic of each of the second to fourth memory dies may generate a clock signal having the clock cycle TCLK, and may decode the first current data of [1011] by comparing the first current monitoring signal CMSwith a predetermined reference voltage at each time point synchronized with the clock signal. For example, the reference voltage compared with the first current monitoring signal CMSat a rising edge and/or a falling edge of the clock signal to decode first current data may be less than a second voltage Vand greater than a third voltage V.

9 FIG. 2 2 In an implementation illustrated in, while a second current monitoring logic of a second memory die occupies a monitoring line and outputs a second current monitoring signal CMS, a current monitoring logic of each of first, third, and fourth memory dies may receive the second current monitoring signal CMS.

1 1 1 2 3 1 2 1 1 2 2 The current monitoring logic of each of the first, third and fourth memory dies may determine a clock cycle TCLK required to recover a clock signal by counting a time between a first rising edge of the first current monitoring signal CMScorresponding to a time point of a first cycle TPand a second rising edge of the first current monitoring signal CMScorresponding to a time point of a second cycle TP. Since logic ‘0’ corresponds to a third voltage V, greater than a first voltage V, and logic ‘1’ corresponds to a second voltage V, greater than the first voltage V, the current monitoring logic may determine the clock cycle TCLK regardless of whether a bit transmitted in each of the first cycle TPand the second cycle TPis logic ‘0’ or logic ‘1’. The current monitoring logic of each of the first, third and fourth memory dies may decode second current data of [0110] by comparing a second current monitoring signal (CD) with a reference voltage in synchronization with a recovered clock signal.

10 12 FIGS.to are views illustrating an operation of a memory device according to an implementation.

1 4 1 4 4 10 12 FIGS.to In an implementation, memory dies may generate and output current monitoring signals CMSto CMSas a pulse amplitude modulation (PAM)-N signal, respectively. In implementations described with reference to, the current monitoring signals CMSto CMSmay be generated as a PAM-4 signal, and depending on an implementation, N of the PAM-N signal may be determined as a value different from.

10 FIG. 10 FIG. 1 4 1 4 may be a view illustrating current monitoring signals CMSto CMSoutput by memory dies included in a memory device and sharing the same channel. In an implementation illustrated in, first to fourth memory dies included in the memory device may alternately output the current monitoring signals CMSto CMSto a monitoring line.

10 FIG. 1 4 1 2 1 4 1 2 1 1 2 2 Referring to, current monitoring signals CMSto CMSmay swing between a first voltage Vwhich may be a minimum voltage and a second voltage Vwhich may be a maximum voltage. First to fourth memory dies may output the current monitoring signals CMSto CMSwhile occupying a monitoring line for two cycles TPand TP, respectively. In a first cycle TPof the two cycles TPand TP, a reference signal may be output, and in a second cycle TP, a valid signal representing current data may be output.

1 2 10 FIG. The reference signal may be a signal not including current data generated by each of the first to fourth memory dies, and may be an RZ signal swinging between the first voltage Vand the second voltage Vregardless of the current data. The valid signal may be a signal including current data generated by each of the first to fourth memory dies. In an implementation illustrated in, each of the first to fourth memory dies may generate and output the valid signal as a multi-level signal in a pulse amplitude modulation (PAM)-4 manner.

1 4 2 1 4 1 4 Each of the first to fourth memory dies may output the current monitoring signals CMSto CMScorresponding to 2-bit current data in the second cycle TPoccupying the monitoring line. The current monitoring logic of each of the first to fourth memory dies may encode a peak value of consumed current to generate the 2-bit current data, and may output the current monitoring signals CMSto CMSthat may be a multi-level signal matching the 2-bit current data to one of the first to fourth voltages Vto V.

2 1 2 3 4 A first current monitoring logic of the first memory die may output first current data of [10], which encodes a peak value of current consumed in the second cycle TPof a time of occupying the monitoring line, as a first current monitoring signal CMS. A second current monitoring logic of the second memory die may output second current data of [11] as a second current monitoring signal CMS, and a third current monitoring logic of the third memory die may output third current data of [01] as a third current monitoring signal CMS. A fourth current monitoring logic of the fourth memory die may output fourth current data of [00] as a fourth current monitoring signal CMS.

1 4 10 FIG. Each of the first to fourth memory dies may monitor a peak value of current consumed by the other memory die with reference to the current monitoring signals CMSto CMS, and may determine whether to execute/stop a control operation based on the current monitoring signals. For example, when one of the first to fourth memory dies outputs a current monitoring signal including current data of [11] to the monitoring line, the other memory dies may stop executing the control operation. In an implementation illustrated in, while the second memory die occupies the monitoring line first, it outputs the second current monitoring signal including the second current data of [11], and the first, third, and fourth memory dies may stop executing the control operation. In addition, since the fourth memory die occupies the monitoring line second and outputs the fourth current monitoring signal including the fourth current data of [11], the first to third memory dies may stop executing the control operation in this case.

10 FIG. 1 4 1 2 1 In an implementation illustrated in, each of the first to fourth memory dies may include a clock recovery circuit, and the clock recovery circuit may recover a clock signal from the current monitoring signal CMSto CMS. For example, the clock recovery circuit may recover the clock signal using a reference signal swinging between the first voltage Vand the second voltage Vduring the first cycle TP.

11 FIG. 10 FIG. 1 4 may be an enlarged graph illustrating the current monitoring signals CMSand CMSoutput to the monitoring line during a time when the fourth memory die occupies the monitoring line in the implementation illustrated in, and subsequently during a time when the first memory die occupies the monitoring line. A clock cycle TCLK of the clock signal that each of the first to fourth memory dies is to be recovered may be equal to the first cycle TPL.

11 FIG. 11 FIG. 2 1 1 As illustrated in, when the current data is [00], since a valid signal output in the second cycle TPmay be maintained as a first voltage, it may be difficult to recover the clock cycle TCLK using only the reference signal of the first cycle TP, as illustrated in. In this case, the memory die may recover the clock cycle TCLK by counting a time interval TDET between first cycles TP, which are consecutive.

12 FIG. 1 4 1 2 1 4 1 3 1 4 1 1 3 1 4 2 3 Referring to, current monitoring signals CMSto CMSmay swing between a first voltage Vwhich may be a minimum voltage and a second voltage Vwhich may be a maximum voltage. First to fourth memory dies may output the current monitoring signals CMSto CMSwhile occupying a monitoring line for three cycles TPto TP, respectively, and may output the current monitoring signals CMSto CMS, respectively. In a first cycle TPof the three cycles TPto TPin which the current monitoring signals CMSto CMSare output, a reference signal may be output, and in a second cycle TPand a third cycle TP, a valid signal representing current data may be output. For example, the reference signal and the valid signal may have a duty ratio of 50%, respectively.

1 2 The reference signal does not include current data generated by each of the first to fourth memory dies, and may be a signal swinging between the first voltage Vand the second voltage Vregardless of the current data. The valid signal may include the current data generated by each of the first to fourth memory dies.

1 4 2 3 2 1 4 3 2 1 4 3 Each of the first to fourth memory dies may output the current monitoring signals CMSto CMScorresponding to 4-bit current data as multi-level signals in the second cycle TPand the third cycle TPthat occupy the monitoring line. For example, upper 2 bits of the 4-bit current data may be output in the second cycle TPof the current monitoring signals CMSto CMS, and remaining lower 2 bits thereof may be output in the third cycle TP. According to an implementation, the lower 2 bits of the 4-bit current data may be output in the second cycle TPof the current monitoring signals CMSto CMS, and the remaining upper 2 bits may be output in the third cycle TP.

1 1 4 2 1 2 3 1 2 1 2 2 1 3 3 2 The first current monitoring signal CMSoutput by a first current monitoring logic of the first memory die may swing between the first voltage Vand a fourth voltage Vduring the second cycle TP, and may swing between the first voltage Vand the second voltage Vduring the third cycle TP. Therefore, first current data of [1011] may be output as the first current monitoring signal CMS. The second current monitoring signal CMSmay swing between the first voltage Vand the second voltage Vduring the second cycle TP, and may swing between the first voltage Vand the third voltage Vduring the third cycle TP. Therefore, second current data of [1101] may be output as the second current monitoring signal CMS.

3 1 2 1 2 3 3 4 1 2 2 1 4 3 4 The third current monitoring signal CMSmay be maintained at the first voltage Vduring the second cycle TPand may swing between the first voltage Vand the second voltage Vduring the third cycle TP. Therefore, third current data of [0011] may be output as the third current monitoring signal CMS. The fourth current monitoring signal CMSmay swing between the first voltage Vand the second voltage Vduring the second cycle TP, and may swing between the first voltage Vand the fourth voltage Vduring the third cycle TP. Therefore, fourth current data of [1110] may be output as the fourth current monitoring signal CMS.

13 14 FIGS.and are views illustrating an operation of a memory device according to an implementation.

13 14 FIGS.and 1 4 1 4 may be views illustrating current monitoring signals CMSto CMSoutput by memory dies included in a memory device and connected to a memory controller through a channel, as a monitoring line, respectively. Each of the memory dies may include a monitoring pad electrically separated from the memory controller, and the monitoring pad may be connected to the monitoring line. The memory dies may alternately occupy the monitoring line in sequence. Each of the memory dies may alternately output the current monitoring signals CMSto CMSincluding current data encoding a peak value of consumption current to the monitoring line.

13 14 FIGS.and 1 4 1 4 In each of the implementations illustrated in, a current monitoring logic of respective first to fourth memory dies may encode a peak value of consumption current into N-bit current data. Each of the first to fourth memory dies may output current monitoring signals CMSto CMSwhile occupying a monitoring line for a time corresponding to N+1 cycles (TPto TP).

13 FIG. 1 4 1 4 1 2 1 Referring to, the current monitoring logic of each of the first to fourth memory dies may output the current monitoring signals CMSto CMSincluding 3-bit current data during four cycles (TPto TP). For example, the current monitoring logic may output a reference signal swinging between a first voltage Vand a second voltage Vduring a first cycle TP. The reference signal may not be a signal generated from the current data, but may be a signal provided such that the current monitoring logic of each of the other memory dies may recover a clock signal.

2 4 1 3 1 4 13 FIG. The current monitoring logic of each of the first to fourth memory dies may output 1 bit of the 3-bit current data during the second to fourth cycles TPto TP. In an implementation illustrated in, data of logic ‘0’ may be output as a signal swinging between the first voltage Vand a third voltage V, and data of logic ‘1’ may be output as a signal swinging between the first voltage Vand a fourth voltage V.

13 FIG. 1 1 4 1 4 1 2 In an implementation illustrated in, both logic ‘0’ and logic ‘1’ may be matched with a signal swinging to a voltage level greater than the first voltage V. The current monitoring logic included in each of the first to fourth memory dies may recover a clock signal from current monitoring signals CMSto CMSreceived through the monitoring line, and may extract current data from the current monitoring signal CMSto CMSusing a recovered clock signal. In an implementation, the current monitoring logic may determine a clock cycle of the clock signal by counting a time from a rising edge of a reference signal output in each first cycle TPto a rising edge of a valid signal output in the second cycle TP.

14 FIG. 14 FIG. 1 4 1 4 1 2 1 2 4 1 2 Referring to, a current monitoring logic of respective first to fourth memory dies may output current monitoring signals CMSto CMSincluding 3 bits of current data for four cycles (TPto TP). For example, the current monitoring logic may output a reference signal that swings between a first voltage Vand a second voltage Vduring a first cycle TP. The current monitoring logic may output 1 bit of 3-bit current data encoding a peak value of current consumed during the second to fourth cycles TPto TP. In an implementation illustrated in, data of logic ‘0’ may be matched with the first voltage V, and data of logic ‘1’ may be matched with the second voltage V.

15 16 FIGS.and are views illustrating an operation of a memory device according to an implementation.

15 FIG. 10 First, referring to, an operation of a memory device according to an implementation may start with outputting a first current monitoring signal to a monitoring line by a first memory die (S). The first current monitoring signal may be output by a first current monitoring logic of the first memory die, and the first memory die may include a first monitoring pad connected to the monitoring line. The first current monitoring logic may output the first current monitoring signal while occupying the monitoring line for a predetermined first time.

11 12 13 A second memory die may receive the first current monitoring signal through the monitoring line (S). For example, a second current monitoring logic of the second memory die may receive the first current monitoring signal through the monitoring line during the first time that the first current monitoring logic occupies the monitoring line, and may recover a second clock signal using the first current monitoring signal (S). The second clock signal may be a clock signal generated by a clock recovery circuit of the second current monitoring logic using the first current monitoring signal, and the second current monitoring logic may detect a peak value of consumption current of the first memory die encoded with the first current monitoring signal using the second clock signal (S).

13 14 14 14 14 15 The second current monitoring logic may determine whether the peak value of the consumption current of the first memory die detected in Smay be equal to or greater than a reference value (S). The reference value applied in Smay be a value stored at a time of manufacturing the memory die or at a time of manufacturing the memory device packaging the memory dies. Alternatively, according to an implementation, the reference value applied in Smay be determined by a storage controller, a power management integrated circuit (PMIC), or the like included in a storage device such as a solid state drive (SSD) device or the like, together with the memory die, or a host communicating with the storage device may determine the reference value. When the peak value is equal to or greater than the reference value as a determination result in S, the second memory die may stop a control operation for a predetermined reference time (S). The control operation may be at least one of a program operation, an erase operation, or a read operation.

16 17 14 17 Thereafter, the second memory die may determine whether the reference time has elapsed (S), and when it is determined that the reference time has elapsed, the control operation may be executed (S). When the peak value is less than the reference value as the determination result in S, the second memory die may execute the control operation (S).

15 FIG. In an implementation described with reference to, under a condition that the peak value of the consumption current of the first memory die is equal to greater than the reference value, the second memory die connected to the memory controller through the same channel as the first memory die may stop executing the control operation for the predetermined reference time. This may be a control method that takes into account characteristic that the peak value of the consumption current appears for a very short time. By adding consumption current of the second memory die to the channel during a time when the consumption current of the first memory die has a peak value, it is possible to prevent a situation in which power consumption of a memory device exceeds an allowable range.

16 FIG. 16 FIG. 1 1 1 may be a graph illustrating consumption current of a first memory die over time. In an implementation illustrated in, during a first time T, consumption current of a first memory die may have a very small first peak value CP. Therefore, during the first time T, a second memory die sharing a channel with the first memory die may perform a control operation without interruption.

2 2 2 2 2 During a second time T, the consumption current of the first memory die may increase to a second peak value CPhigher than a reference value REF. Therefore, the second memory die may temporarily suspend execution of the control operation during the second time Twith reference to a first current monitoring signal including current data encoding the second peak value CP. When the second time Telapses, the second memory die may resume the control operation.

3 3 3 3 4 4 During a third time T, the consumption current of the first memory die may also increase to a third peak value CPhigher than the reference value REF. Therefore, the second memory die may stop executing the control operation during the third time T, and may execute the control operation after the third time Thas elapsed. During a fourth time T, since the consumption current of the first memory die has a fourth peak value CPsmaller than the reference value REF, the second memory die may execute the control operation without interruption.

17 18 FIGS.and are views illustrating an operation of a memory device according to an implementation.

17 FIG. 20 Referring to, an operation of a memory device according to an implementation may start with outputting a first current monitoring signal to a monitoring line by a first memory die (S). The first current monitoring signal may be output by a first current monitoring logic of the first memory die, and the first memory die may include a first monitoring pad connected to the monitoring line. The first current monitoring logic may output the first current monitoring signal while occupying the monitoring line for a predetermined first time.

21 22 23 A second memory die may receive the first current monitoring signal through the monitoring line (S). For example, a second current monitoring logic of the second memory die may receive the first current monitoring signal through the monitoring line during the first time that the first current monitoring logic occupies the monitoring line, and may recover a second clock signal using the first current monitoring signal (S). The second clock signal may be a clock signal generated by a clock recovery circuit of the second current monitoring logic using the first current monitoring signal, and the second current monitoring logic may detect a peak value of consumption current of the first memory die encoded with the first current monitoring signal using the second clock signal (S).

23 24 24 24 25 The second current monitoring logic may determine whether the peak value of the consumption current of the first memory die detected in Smay be equal to greater than a reference value (S). The reference value applied in Smay be a value stored at a time of manufacturing the memory die or at a time of manufacturing the memory device packaging the memory dies. When the peak value is equal to greater than the reference value as a determination result in S, the second memory die may stop a control operation (S). The control operation may be at least one of a program operation, an erase operation, or a read operation.

26 27 26 After the second memory die stops the control operation, the second current monitoring logic may determine whether the peak value of the consumption current of the first memory die decreases below a reference value by using the first current monitoring signal output to the monitoring line (S). When it is determined that the peak value of the consumption current of the first memory die extracted from the first current monitoring signal is smaller than the reference value, the second memory die may execute the control operation (S). When it is determined as the determination result in Sthat the peak value of the consumption current of the first memory die extracted from the first current monitoring signal is greater than the reference value, the second memory die may maintain a state of stopping the control operation.

17 FIG. In an implementation described with reference to, under a condition that the peak value of the consumption current of the first memory die is equal to greater than the reference value, the second memory die may stop executing the control operation. Thereafter, under a condition that the peak value of the consumption current of the first memory die is confirmed to decrease below the reference value through the monitoring line, the second memory die may re-execute the control operation. Therefore, consumption current of the second memory die may not be added to the channel during a time when the consumption current of the first memory die has a peak value, and it is possible to prevent a situation in which power consumption of a memory device including the first memory die and the second memory die exceeds an allowable range.

18 FIG. 18 FIG. 16 FIG. may be a graph illustrating consumption current of a first memory die over time. The graph ofmay be equal to the graph illustrated in.

18 FIG. 1 2 2 1 Referring to, a first memory die may output a first current monitoring signal CMSto a monitoring line ML at least once during a second time T. The second time Tmay be a time that a peak value of consumption current of the first memory die is greater than a reference value REF, and therefore, current data included in the first current monitoring signal CMSmay be greater than the reference value REF.

2 1 1 18 FIG. When the second time Telapses, the first memory die may output the first current monitoring signal CMSincluding current data smaller than the reference value REF. In an implementation illustrated in, a second memory die may resume a control operation after confirming through the monitoring line ML that the current data included in the first current monitoring signal CMShas become smaller than the reference value REF.

2 1 1 2 1 2 1 According to an implementation, during the second time Twhen the current data of the first current monitoring signal CMSis greater than the reference value REF, only the first current monitoring signal CMSmay be repeatedly output through the monitoring line ML. During the second time T, the second memory die may not output a current monitoring signal to the monitoring line ML, and the first memory die may repeatedly output the first current monitoring signal CMSwhile occupying the monitoring line ML during the second time T. When the current data included in the first current monitoring signal CMSis smaller than the reference value REF, the first memory die and the second memory die may alternately occupy the monitoring line ML again.

According to an implementation, memory dies sharing a channel may be commonly connected to a monitoring line, and may sequentially and repeatedly output peak values of consumption current through the monitoring line without a separate clock signal. Each of the memory dies may monitor peak values of consumption current of other memory dies, and may stop or delay execution of a control operation with reference to a peak value of consumption current of at least one of the other memory dies. Therefore, power consumption of a memory device may be controlled within an effective range of power that may be supplied, and performance of the memory device may be improved.

Various advantages and effects of the present disclosure are not limited to the above-described contents, and may be more easily understood in the process of explaining specific implementations.

While this disclosure contains many specific implementation details, these should not be construed as limitations on the scope of what may be claimed. Certain features that are described in this disclosure in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations, one or more features from a combination can in some cases be excised from the combination, and the combination may be directed to a subcombination or variation of a subcombination.