Pre-Charge Monitoring of Power Stage Circuit for Multiphase Voltage Regulator

The present disclosure relates generally to power circuits, and more particularly but not exclusively to multiphase voltage regulators.

Multiphase voltage regulator has been widely used in high power applications. The multiphase voltage regulator includes multiple (e.g., n) power stage circuits, where n is a positive integer greater than 1. Specifically, the n power stage circuits are coupled in parallel, and each of the power stage circuit to provide a higher output current to the load. Each power stage circuits is configured to share the input voltage and the output voltage and provide a phase current to a load. In one embodiment, the n power stage circuits are interleaved in n phases to reduce current ripple at the input and output and improve efficiency. Typically, each of the n power stage circuits is an integrated circuit (IC), and a multiphase controller is also an IC configured to provide the n phase control signals to respectively control the n power stage ICs. Therefore, it is important for the multiphase controller IC to monitor the status of the power stage ICs to provide the regulated output voltage. As a result, it is desirable to provide the status report of power stage IC.

According to an embodiment of the present disclosure, a control circuit for a multiphase voltage regulator is provided. The control circuit includes a switching control circuit and a monitor circuit. The switching control circuit is configured to provide a control signal to control a plurality of power stage circuits. Each of the power stage circuit is configured to provide a phase current. The monitor circuit is configured to receive a report signal from at least one of the power stage circuits, and determine whether the report signal indicates a pre-charge period of the corresponding power stage circuit is finished. After the report signal indicates that the pre-charge period of the corresponding power stage circuit is finished, the control signal is provided to power on the corresponding power stage circuit.

According to yet another embodiment of the present disclosure, a power stage circuit is provided. The power stage circuit includes a switch circuit, a driving control circuit, a pre-charge monitor circuit, and a report circuit. The switch circuit has at least one switch, and one of the at least one switch is configured to be coupled to a flying capacitor. The driving control circuit is configured to receive a control signal and provide at least one driving signal to a control terminal of the at least one switch. The pre-charge monitor circuit is configured to monitor a voltage across the flying capacitor. The report circuit is configured to provide a report signal indicating a pre-charge period of the flying capacitor is finished.

According to yet another embodiment of the present disclosure, a multiphase voltage regulator is provided. The multiphase voltage regulator includes a plurality of power stage circuits, and a control circuit. Each of the power stage circuits is configured to provide a phase current, and each power stage circuit includes at least one power switch and a report circuit. The report circuit is configured to provide a report signal. The control circuit is coupled to the power stage circuits. The control circuit is configured to receive the report signal from at least one of the power stage circuits, determine whether the report signal indicates the pre-charge period of the corresponding power stage circuit is finished; and provide a control signal to the corresponding power stage circuit after it is determined that the report signal indicates the pre-charge period of the corresponding power stage circuit is finished.

According to yet another embodiment of the present disclosure, a method for controlling a multiphase voltage regulator is provided. The method includes the following actions. Reporting signals are received from power stage circuits. Whether the reporting signal indicates a pre-charge period of the corresponding power stage circuit is finished is determined. After the reporting signal indicating the pre-charge period of the corresponding power stage circuit is finished, a control signal is provided to power on the corresponding power stage circuit.

Various embodiments of the present disclosure will now be described. In the following description, some specific details, such as example circuits and example values for these circuit components, are included to provide a thorough understanding of embodiments. One skilled in the relevant art will recognize, however, that the present disclosure can be practiced without one or more specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, processes or operations are not shown or described in detail to avoid obscuring aspects of the present disclosure.

Throughout the specification and claims, the phrases “in one embodiment”, “in some embodiments”, “in one implementation”, and “in some implementations” as used includes both combinations and sub-combinations of various features described herein as well as variations and modifications thereof. These phrases used herein do not necessarily refer to the same embodiment, although it may. Those skilled in the art should understand that the meanings of the terms identified above do not necessarily limit the terms, but merely provide illustrative examples for the terms. It is noted that when an element is “connected to” or “coupled to” the other element, it means that the element is directly connected to or coupled to the other element, or indirectly connected to or coupled to the other element via another element. Particular features, structures or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable components that provide the described functionality. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale.

1 FIG. 100 100 11 12 1 12 1 2 11 n PWM1 PWM2 PWMn is a schematic block diagram of a multiphase voltage regulatorin accordance with an embodiment of the present disclosure. The multiphase voltage regulatorincludes a control circuitand multiple (e.g., n) power stage circuits-to-, where n is a positive integer greater than 1. The n power stage circuits are coupled in parallel, and each of the power stage circuit to provide a phase current to the load. Each power stage circuits is configured to share the input voltage Vin and the output voltage Vout and provide a phase current (e.g., I, I, . . . , In) to a load. In one embodiment, the n power stage circuits are interleaved in n phases to reduce current ripple at the input and output and improve efficiency. The control circuitis configured to provide the n phase control signals (e.g., S, S, . . . , S) to respectively control the n power stage circuits.

100 100 100 100 In one implementation, the multiphase voltage regulatoris a multiphase buck converter. However, the present disclosure is not limited thereto. The multiphase voltage regulatormay be a multiphase boost converter, a trans-inductor voltage regulator (TLVR), a multiphase DC-DC converters, or any multiphase converters. In some implementations, the multiphase voltage regulatoris an isolated converter. In some other implementations, the multiphase voltage regulatoris a non-isolated converter.

11 1 12 1 12 12 1 12 11 11 n n 1 2 n PWM1 PWM2 PWMn In one embodiment, the control circuitis a multiphase controller integrated circuit (IC) having n switching control pins (e.g., PWM-PWMn) and a monitor pin (e.g., MON). In one embodiment, each of the power stage circuits-to-is an IC. Each of the power stage circuits-to-includes a VIN pin configured to receive the input voltage Vin, a SW pin configured to provide the output voltage Vout via the inductor (e.g., L, L, . . . , L), a switching control pin (e.g., PWM) configured to receive the control signals (e.g., S, S, . . . , S) from the multiphase controller IC, and a report pin (e.g., RP) configured to transmit a report signal (e.g., Pre) to the multiphase controller IC. The report signal indicates whether the pre-charge period of the corresponding power stage circuit is finished.

100 200 200 1 2 1 4 1 4 1 4 1 2 1 2 1 1 3 4 1 200 1 3 2 4 1 2 2 FIG.A 2 FIG.A 2 FIG.A FLY FLY FLY FLY FLY FLY FLY In one embodiment, the multiphase voltage regulatoris a converter including one or more flying capacitors. For instance,is a schematic circuit diagram of a switching converterA in accordance with an embodiment of the present disclosure. As shown in, the switching converterA includes a switching circuit, inductors Land L, and a flying capacitor C. In one embodiment, an output capacitor Cout is coupled between the output terminal Vout and a ground. As shown in, the switching circuit has 4 power switches M-M. In one embodiment, the power switches M-Mmay include Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFETs). In some embodiments, the power switches M-Mmay include, but not limited to, a bipolar transistor (BJT), a field-effect transistor (FET), or an insulated-gate bipolar transistor (IGBT), a high electron mobility transistor (HEMT), a junction field-effect transistor (JFET), a Gate Turn-off Thyristor (GTO) or a Gate-Commutated Thyristor (GCT). The power switch Mand the power switch Mare coupled in series between the input terminal Vin and the ground, and the flying capacitor Cis coupled between the power switch Mand the power switch M. Specifically, the flying capacitor Cis coupled to between the node Nand the node SW. The power switches Mand Mis coupled in series between the node Nand the ground. The switching converterA is a 2-phase converter. Each phase includes a high side switch (e.g., M, M) and a low side switch (e.g., M, M), and configured to provide the output voltage via each inductor (L, or L). The flying capacitor Cacts as a voltage divider to divide the input voltage VIN. The flying capacitor Ctemporarily stores energy during a switching cycle and transfer energy to the output stage, and the temporarily stored energy is proportional to the duty cycle. During steady state, the voltage across the flying capacitor Cis the output voltage Vo divided by the duty cycle D. In one implementation, the voltage across the flying capacitor Cis approximately half of the input voltage (½*VIN) at steady state.

1 4 2 3 1 1 2 4 1 2 FLY IN FLY For example, in a first interval, the power switches Mand Mare turned on, and the power switches Mand Mare turned off. In this interval, the input current flows through the power switch M, the flying capacitor C, and the inductor Lto the output terminal Vout, while the current in inductor Lflows through power switch Mto the output terminal Vout. The current in inductor Lincreases, and the current in inductor Ldecreases. The input voltage Vis divided between the flying capacitor Cand the output stage.

1 2 1 2 1 2 In a second interval, the power switch Mis turned off and the power switch Mis turned on, the current in inductor Lflows through the power switch M, and therefore the energy stored in inductor Lstarts to discharge to the output terminal Vout, while the current in inductor Lcontinues to decrease.

3 4 2 2 3 2 1 2 2 1 FLY In a third interval, the power switch Mis turned on and the power switch Mis turned off. During this interval, the current in inductor Lflows through the power switch M, the flying capacitor C, the power switch M, and the inductor Lto the output terminal Vout, while the current in inductor Lflows through the power switch Mto the output terminal Vout. The current in inductor Lincreases, and the current in inductor Ldecreases.

3 1 3 2 4 1 In a fourth interval, the power switch Mis turned off, which is identical to the second interval. During this interval, both power switches Mand Mare off and both power switches Mand Mare on, and both inductor currents decrease. Afterwards, the circuit enters a new switching cycle when the power switch Mis turned on again.

222 1 1 200 FLY FLY In one embodiment, a pre-charge circuitis coupled to the input terminal Vin and at least one terminal (e.g., Nand/or SW) of the flying capacitor Cto charge the flying capacitor Cduring start-up of the switching converterA.

200 1 4 1 4 In one embodiment, the switching converterA further includes a control circuit (not shown) is configured to provide switching control signals Vg-Vgto control the power switch devices M-Mrespectively.

2 FIG.B 2 FIG.B 200 200 1 2 1 6 200 1 1 5 6 2 4 2 2 3 1 224 1 2 1 2 200 is a schematic circuit diagram of a switching converterB in accordance with another embodiment of the present disclosure. In this embodiment, the switching converterB includes two flying capacitors Cand C. As shown in, the switching circuit has 6 power switches M-M. The switching converterB is a 2-phase converter. The first phase includes the power switch M, the flying capacitor C, the power switches Mand M, and the inductor L. The second phase includes the power switch M, the flying capacitor C, the power switches Mand M, and the inductor L. In one embodiment, a pre-charge circuitis coupled to the input terminal Vin and at least one terminal of the flying capacitor (e.g., Cand/or C) to charge the flying capacitor (e.g., Cand/or C) during start-up of the switching converterB.

2 2 FIGS.A andB show buck type switching converter with one and two flying capacitor. However, the present disclosure is not limited thereto. In another embodiment, the switching converter is a boost type converter. In some embodiments, the switching converter is a buck-boost type converter. In some other embodiments, the switching converter is a switched capacitor type converter. In one implementation, the switching converter includes one or more flying capacitor coupled between at least one of the power switch. In one example, one or more flying capacitor is coupled at the input circuit that is between the input terminal and the inductor. In another example, one or more flying capacitor is coupled at the output circuit that is coupled to the output terminal.

3 FIG. 300 300 310 320 310 1 2 320 320 320 320 is a schematic block diagram of a multiphase controller ICin accordance with an embodiment of the present disclosure. The multiphase controller ICincludes a switching control circuit, and a monitor circuit. The switching control circuitis configured to provide control signals via the switching control pins (e.g., PWM, PWM, . . . , PWMn) to control the power stage circuits. The monitor circuitis configured to receive a report signal (e.g., Pre) via the monitor pin (e.g., MON), and determine whether the report signal Pre indicates a pre-charge period of the corresponding power stage circuit is finished. In one embodiment, the monitor pin MON is configured to receive the status of one of the power stage circuits, and the report signal Pre is received via the monitor pin MON. For example, the status of the power stage circuit indicates an event or a warning. In one implementation, different voltage levels of the monitor pin MON are configured to indicate different events or warnings, and whether the pre-charge period of the corresponding power stage circuit is finished. In some implementations, the report signal Pre is a digital signal configured to represent various fault types, warning and whether the pre-charge period of the corresponding power stage circuit is finished. Accordingly, the monitor circuitis configured to receive a report signal Pre via the monitor pin MON, and determine whether the report signal Pre indicates the pre-charge period of the corresponding power stage circuit is finished. In one embodiment, the monitor circuitis configured to compare the report signal with a voltage threshold and generate a comparison signal in response to the report signal and the voltage threshold; and determine whether the pre-charge period of the corresponding power stage circuit is finished according to the comparison signal. For instance a comparator is configured to compare the report signal Pre with a voltage threshold. When the report signal Pre is less than the voltage threshold, the monitor circuitis configured to determine that the pre-charge period of the corresponding power stage circuit is finished.

300 330 1 2 In one embodiment, the multiphase controller ICfurther includes a current sense circuitconfigured to receive current sense signals indicating the respective phase currents of the power stage circuits via the current sense pin (e.g., CS, CS, . . . , CSn). In one embodiment, the current sense signals are used to provide a total load current sense signal via the pin IMON.

300 340 340 In one embodiment, the multiphase controller ICfurther includes a control loop circuitconfigured to regulate the output voltage Vout. For example, the control loop circuitsense the feedback voltage via the feedback pin FB. The feedback voltage represents the output voltage Vout. In one embodiment, the feedback voltage is compared with a reference signal to generate a compensation signal (e.g., via an error amplifier EA), and the compensation signal is compared with a ramp signal received via the pin RAMP to generate a control signal (e.g., via a PWM comparator). In another embodiment, the feedback voltage is compared with a reference signal to generate a compensation signal (e.g., via an error amplifier EA), and the compensation signal is compared with the inductor current to generate the control signal (e.g., via a PWM comparator). In yet another embodiment, the feedback voltage is compared with a reference signal to generate a compensation signal (e.g., via a PWM comparator), and the control signal is generated in response to the compensation signal and an on-time.

4 FIG. 2 FIG.A 400 400 440 410 420 430 440 400 200 1 1 2 2 1 1 1 1 1 2 1 2 2 2 2 FLY FLY is a schematic block diagram of a power stage ICin accordance with an embodiment of the present disclosure. The power stage ICincludes a switching circuit, a driving control circuit, a pre-charge monitor circuit, and a report circuit. The switch circuithas at least one switch, and one of the at least one switch is configured to be coupled to a flying capacitor. In one embodiment, the power stage ICare used to form the converterA as shown in. In one implementation, the power switches HS, LS, HSand LSare n-type MOSFETs. The first terminal (e.g., drain) of a first high-side switch HSis coupled to the VIN pin configured to receive the input voltage, the second terminal (e.g., source) of the first high-side switch HSis coupled to a flying capacitor Cvia the FLY pin, and the first terminal (e.g., drain) of the first low-side switch LSis coupled to the second terminal (e.g., source) of the first high-side switch HSvia the flying capacitor C. The second terminal (e.g., source) of the first low-side switch LSis coupled to the GND pin configured to be coupled to a reference voltage level (e.g., the ground). The first terminal (e.g., drain) of the second high-side switch HSis coupled to the second terminal (e.g., source) of the first high-side switch HS, the second terminal (e.g., source) of the second high-side switch HSis coupled to the SWpin and the first terminal (e.g., drain) of the second low-side switch LS. The second terminal (e.g., source) of the second low-side switch LSis configured to be coupled to the reference voltage level (e.g., the ground).

1 1 2 2 410 410 1 4 1 1 2 2 1 1 2 2 1 4 1 2 420 1 430 The control terminals (e.g., gate) of the power switches (e.g., HS, LS, HSand LS) are coupled to the driving control circuit. The driving control circuitis configured to receive a control signal from the switching control pin PWM and provide the driving signals G-Gto the gate terminals of the power switches HS, LS, HSand LS, respectively. Specifically, the power switches HS, LS, HSand LSare turned on and turned off in response to the driving signals G-G, respectively, and provide switching signals at the SWpin and the SWpin. The pre-charge monitor circuitis configured to monitor a voltage across the flying capacitor (i.e., the voltage between FLY pin and SWpin). The report circuitis configured to provide a report signal Pre indicating a pre-charge period of the flying capacitor is finished.

400 200 440 400 2 FIG.B In another embodiment, the power stage ICare used to form the converterB as shown in. However, the present disclosure is not limited thereto. The switching circuitof the power stage ICincludes multiple switches with at least one of the switches is configured to be coupled to one or more flying capacitor. That is, the power stage IC may be used to form various types of converter topology.

5 FIG. 500 1 500 52 1 52 51 1 1 570 2 1 1 1 n is a schematic circuit diagram of a multiphase voltage regulatorin accordance with one embodiment of the present disclosure. In this embodiment, the report signal Pre is realized by the voltage signal received via the current sense pin (e.g., CSto CSn). For instance, during an initial period, that is before the multiphase voltage regulatoris powered on, all of the power stage ICs-to-are not powered on. Each power stage IC needs to pre-charge the flying capacitor before power-on. The power stage IC monitors the voltage across the flying capacitor, and issues the report signal Pre to notify the multiphase controller ICthat the pre-charge period of the flying capacitor is finished. For instance, the report circuit of the power stage IC includes a switch DScoupled to a reference voltage V(e.g., the supply voltage Vcc). Specifically, during the initial period, the current report circuitis disconnected, for example, by turning off the switch DS. Meanwhile, the switch DSis turned on, and thus the voltage of the corresponding current sense pin (CS) is pulled up to the reference voltage V. When the power stage IC determines that the pre-charge period of the flying capacitor is finished, the switch DSis turned off to provide no driving voltage on the current sense pin CS.

51 1 1 1 1 2 1 1 522 1 1 1 1 530 1 1 530 CS1 CSn CS CS1 REFCS CS CS1 CS1 On the other hand, during the initial period, the multiphase controller ICdetects the voltage of the corresponding current sense pin (CS-CSn). Specifically, each of the current sense pin (CS-CSn) is configured to receive a current sense signal (e.g., Vto V) from the corresponding power stage IC. In one embodiment, the current sense circuit includes a current sense resistor R, and the current could be calculated according to the voltage across the current sense resistor (e.g., V-V) and the resistance of the current sense resistor R. In one embodiment, the monitor circuit includes multiple voltage reference circuits coupled to the current sense pins CS-CSn. The voltage reference circuit is configured to connect the corresponding current sense pin CSx to a voltage reference. In one implementation, the voltage reference circuit includes a current source Ir. In another implementation, the voltage reference circuit includes a resistor. In some implementations, the voltage reference circuit includes a transistor. During the initial period, the switch Sis turned off to disable the current sense circuit. Meanwhile, the switch Sis turned on, and the current source Ir is coupled to the current sense pin (e.g., CS) to pull down the voltage of the corresponding current sense pin (e.g., CS). In one embodiment, the monitor circuit includes a comparatorconfigured to compare the report signal with a voltage threshold Vth. Since the voltage of the corresponding current sense pin (CS) is pulled up to the reference voltage Vof the power stage IC during the pre-charge period, the current source Ir could not pull down the voltage of the corresponding current sense pin (CS). Therefore, the voltage signal V(i.e., equals to the reference voltage V) is greater than the voltage threshold Vth, and the control circuitdetermines that the pre-charge period of the corresponding power stage circuit is not finished. When the pre-charge period of the corresponding power stage circuit is finished, the switch DSis turned off, and the voltage of the corresponding current sense pin (e.g., CS) is pulled down by the current source Ir. That is, when the Vis less than the voltage threshold Vth, the control circuitdetermines that the pre-charge period of the corresponding power stage IC is finished. In one implementation, the signal CMP with a high logic level (e.g., “1”) indicates that the pre-charge period of the corresponding power stage IC is finished, while a low logic level (e.g., “0”) of the signal CMP indicates that the pre-charge period of the corresponding power stage IC is not finished.

52 1 51 52 522 1 x x CS1 In one embodiment, the current sense of the power stage ICs-is connected to the reference voltage Vand the corresponding current sense pin CSx of the multiphase controller ICis connected to the ground, and the current source Ir is configured to pull down the voltage of the switching control pin. However, in another embodiment, the current sense of the power stage ICs-is connected to the ground and the current source Ir is configured to pull up the voltage of the switching control pin to the supply voltage (e.g., Vcc). Accordingly, the comparatordetermines that the voltage signal Vis greater than the voltage threshold Vth (e.g., 2.5V), it is determined that the pre-charge period of the corresponding power stage IC is finished. In this implementation, the signal CMP with a high logic level (e.g., “1”) indicates the pre-charge period is not finished, while a low logic level (e.g., “0”) of the signal CMPindicates the pre-charge period is finished.

530 52 1 51 52 51 x x CSX CSX In another embodiment, the monitor circuit detects the falling edge of the report signal. When a falling edge of the report signal is detected, the control circuitdetermines that the pre-charge period of the corresponding power stage IC is finished. For instance, in the embodiment that the current sense of the power stage ICs-is connected to the reference voltage Vand the corresponding current sense pin CSx of the multiphase controller ICis connected to the ground, a falling edge of the voltage signal Vindicates that the pre-charge period is finished. In another embodiment that the current sense of the power stage ICs-is connected to the ground and the corresponding current sense pin CSx of the multiphase controller ICis connected to the supply voltage Vcc, a rising edge of the voltage signal Vindicates that the pre-charge period is finished.

510 51 1 500 During the initial period, the switching control circuitof the controller ICprovides the control signal with a high impedance (Hi-Z) mode to all of the switching control pins (e.g., PWM-PWMn). For example, the voltage of the switching control pin of the power stage IC is at a middle voltage level or a tri-state logic level. In one implementation, the control signal (i.e., the voltage of the switching control pin PWMx) has three states, a high logic level (e.g., 2-3.3V) to turn on the high-side switch, a low logic level (e.g., 0-1V) to turn on the low-side switch, and a tri-state logic level (e.g., 1-2V) to make the multiphase voltage regulatorin the Hi-Z mode (or inactive).

CS1 51 510 51 1 2 1 After it is determined that the report signal (e.g., V) indicates that the pre-charge period of the power stage IC is finished, the controller ICperforms the power-on sequence. For example, the switching control circuitof the controller ICprovides the control signal to the corresponding power stage IC via the switching control pin (e.g., PWM-PWMn). After the initial period, the switch Sis turned off to disable the pull down current, and the switch Sis turned on to enable the current sense circuit in normal operation.

1 2 522 524 52 52 51 52 51 52 52 1 52 x x x x n In one embodiment, there are multiple switches Sand S, current sources Ir, and comparatorsandcoupled between the corresponding current sense pins CSx of each power stage IC-to determine whether the pre-charge period of each power stage IC-is finished. In one implementation, the multiphase controller ICprovides the control signal to power on the corresponding power stage IC-when the pre-charge period of at least one of the power stage IC is finished. In some implementations, the multiphase controller ICprovides the control signal to power on the corresponding power stage IC-when the pre-charge period of all of the power stage ICs-to-are finished.

6 FIG. 1 3 5 FIGS.,and 600 600 11 300 51 610 620 630 is a flowchart of a methodfor controlling a multiphase voltage regulator in accordance with one embodiment of the present disclosure. The methodmay be performed by a multiphase controller IC,,as shown in. The method includes the following actions. In action, one or more report signals are received from at least one of the power stage circuits. In action, whether the report signal indicates that pre-charge period of the corresponding power stage circuit is finished is determined. In action, a control signal is provided to power on the corresponding power stage circuit after the report signal indicates the pre-charge period of the corresponding power stage circuit is finished.

7 FIG. 1 3 5 FIGS.,and 1 4 5 FIGS., and- 700 700 11 300 51 12 400 52 710 720 730 x x is a flowchart of a methodfor controlling a multiphase voltage regulator in accordance with one embodiment of the present disclosure. The methodmay be performed by a multiphase controller IC,,as shown inwith power stage ICs-,,-as shown in. The method includes the following actions. In one embodiment, the method is performed when the supply voltage (e.g., Vcc) and the enable signal (e.g., EN) of the multiphase controller IC are both ready, and after the multiphase controller send the enable signal (e.g., DRON) to the power stage ICs. In action, the voltage of the current sense pin of the power stage IC is connect to a voltage level. In action, the pre-charge monitoring is performed by the power stage IC. As stated before, the voltage across the flying capacitor is detected by the power stage IC. After the pre-charge is completed, the current sense pin of the power stage IC is disconnected to the voltage level in action.

740 750 760 760 7 FIG. On the other hand, in action, the multiphase controller IC disables the current sense circuit and connect the current sense pin to a voltage reference. In action, the multiphase controller IC determines whether the pre-charge period of the corresponding power stage IC is finished according to the voltage of the current sense pin and a voltage threshold. For example, when the voltage of the current sense pin is less than a voltage threshold, it means that the pre-charge period of the corresponding power stage IC is finished, actionis performed. In action, the connection between the current sense pin and the voltage reference is disconnected and the current sense circuit is enabled. Although the flowchart ofshows a sequential action. It is obvious to persons skilled the art that these actions could be performed in any order.

It should be understood that, the circuit and the related components, circuit structures, signals, and waveforms described or shown above in the present disclosure are only for illustration purpose. However, the present disclosure is not limited thereto. Persons having ordinary skill in the art may understood that the control circuit of the present disclosure could be realized, according to practical applications, by any other circuits with different circuit structures, and thus controlled by different types of the corresponding signals to achieve the corresponding functions. For example, the compensation circuit, the ramp generation circuit, the comparison circuit and the logic circuit could be realized by a digital circuit, an analog circuit, a software, an automatic generation circuit by hardware description language, or a combination of the above.

It will be appreciated by persons skilled in the art that the present disclosure is not limited to what has been particularly shown and described herein above. Rather the scope of the present disclosure is defined by the claims and includes both combinations and sub-combinations of the various features described hereinabove as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not in the prior art.