Point Cloud Coding Standard Conformance Definition in Computing Environments

This patent arises from a continuation of U.S. patent application Ser. No. 18/677,514, filed May 29, 2024, which is a continuation of U.S. patent application Ser. No. 18/466,590, filed Sep. 13, 2023, which is a continuation of U.S. patent application Ser. No. 17/333,772, filed May 28, 2021, which is a continuation of U.S. Application No. Ser. No. 16/596,204, filed Oct. 8, 2019, which claims priority from U.S. Provisional Application No. 62/744,014, filed Oct. 10, 2018. U.S. patent application Ser. No. 18/677,514, U.S. patent application Ser. No. 18/466,590, U.S. Ser. No. 17/333,772, U.S. application Ser. No. 16/596,204, and U.S. Provisional Application No. 62/744,014 are incorporated herein by reference in their respective entireties.

Embodiments described herein generally relate to computers. More particularly, embodiments are described for facilitating defining interoperability signaling and conformance points for the Point Cloud Coding standard in computing environments.

Conventionally, there has not been a definition as to how the Point Cloud Coding (PCC) draft standard should define interoperability signaling and conformance points.

In the following description, numerous specific details are set forth. However, embodiments, as described herein, may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

Embodiments provide for a novel technique for defining interoperability signaling and conformance points to enable ecosystem specification of PCC products, which allows for flexible video decode and graphics processing unit (GPU) capability.

It is contemplated that terms like “request”, “query”, “job”, “work”, “work item”, and “workload” may be referenced interchangeably throughout this document. Similarly, an “application” or “agent” may refer to or include a computer program, a software application, a game, a workstation application, etc., offered through an application programming interface (API), such as a free rendering API, such as Open Graphics Library (OpenGL®), Open Computing Language (OpenCL®), CUDA®, DirectX® 11, DirectX® 12, etc., where “dispatch” may be interchangeably referred to as “work unit” or “draw” and similarly, “application” may be interchangeably referred to as “workflow” or simply “agent”. For example, a workload, such as that of a three-dimensional (3D) game, may include and issue any number and type of “frames” where each frame may represent an image (e.g., sailboat, human face). Further, each frame may include and offer any number and type of work units, where each work unit may represent a part (e.g., mast of sailboat, forehead of human face) of the image (e.g., sailboat, human face) represented by its corresponding frame. However, for the sake of consistency, each item may be referenced by a single term (e.g., “dispatch”, “agent”, etc.) throughout this document.

In some embodiments, terms like “display screen” and “display surface” may be used interchangeably referring to the visible portion of a display device while the rest of the display device may be embedded into a computing device, such as a smartphone, a wearable device, etc. It is contemplated and to be noted that embodiments are not limited to any particular computing device, software application, hardware component, display device, display screen or surface, protocol, standard, etc. For example, embodiments may be applied to and used with any number and type of real-time applications on any number and type of computers, such as desktops, laptops, tablet computers, smartphones, head-mounted displays and other wearable devices, and/or the like. Further, for example, rendering scenarios for efficient performance using this novel technique may range from simple scenarios, such as desktop compositing, to complex scenarios, such as 3D games, augmented reality applications, etc.

1 FIG. 100 100 102 108 102 107 100 is a block diagram of a processing system, according to an embodiment. In various embodiments, the systemincludes one or more processorsand one or more graphics processors, and may be a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processorsor processor cores. In one embodiment, the systemis a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

100 100 100 100 102 108 In one embodiment, the systemcan include, or be incorporated within a server-based gaming platform, a game console, including a game and media console, a mobile gaming console, a handheld game console, or an online game console. In some embodiments, the systemis a mobile phone, smart phone, tablet computing device or mobile Internet device. The processing systemcan also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, smart eyewear device, augmented reality device, or virtual reality device. In some embodiments, the processing systemis a television or set top box device having one or more processorsand a graphical interface generated by one or more graphics processors.

102 107 107 109 109 107 109 107 In some embodiments, the one or more processorseach include one or more processor coresto process instructions which, when executed, perform operations for system and user software. In some embodiments, each of the one or more processor coresis configured to process a specific instruction set. In some embodiments, instruction setmay facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via a Very Long Instruction Word (VLIW). Multiple processor coresmay each process a different instruction set, which may include instructions to facilitate the emulation of other instruction sets. Processor coremay also include other processing devices, such a Digital Signal Processor (DSP).

102 104 102 102 102 107 106 102 102 In some embodiments, the processorincludes cache memory. Depending on the architecture, the processorcan have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor. In some embodiments, the processoralso uses an external cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared among processor coresusing known cache coherency techniques. A register fileis additionally included in processorwhich may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). Some registers may be general-purpose registers, while other registers may be specific to the design of the processor.

102 110 102 100 110 102 116 130 116 100 130 In some embodiments, one or more processor(s)are coupled with one or more interface bus(es)to transmit communication signals such as address, data, or control signals between processorand other components in the system. The interface bus, in one embodiment, can be a processor bus, such as a version of the Direct Media Interface (DMI) bus. However, processor busses are not limited to the DMI bus, and may include one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express), memory busses, or other types of interface busses. In one embodiment, the processor(s)include an integrated memory controllerand a platform controller hub. The memory controllerfacilitates communication between a memory device and other components of the system, while the platform controller hub (PCH)provides connections to I/O devices via a local I/O bus.

120 120 100 122 121 102 116 112 108 102 111 102 111 111 The memory devicecan be a dynamic random-access memory (DRAM) device, a static random-access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. In one embodiment, the memory devicecan operate as system memory for the system, to store dataand instructionsfor use when the one or more processorsexecutes an application or process. Memory controlleralso couples with an optional external graphics processor, which may communicate with the one or more graphics processorsin processorsto perform graphics and media operations. In some embodiments, a display devicecan connect to the processor(s). The display devicecan be one or more of an internal display device, as in a mobile electronic device or a laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). In one embodiment, the display devicecan be a head mounted display (HMD) such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications.

130 120 102 146 134 128 126 125 124 124 125 126 128 134 110 146 100 140 130 142 143 144 In some embodiments, the platform controller hubenables peripherals to connect to memory deviceand processorvia a high-speed I/O bus. The I/O peripherals include, but are not limited to, an audio controller, a network controller, a firmware interface, a wireless transceiver, touch sensors, a data storage device(e.g., hard disk drive, flash memory, etc.). The data storage devicecan connect via a storage interface (e.g., SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCI Express). The touch sensorscan include touch screen sensors, pressure sensors, or fingerprint sensors. The wireless transceivercan be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. The firmware interfaceenables communication with system firmware, and can be, for example, a unified extensible firmware interface (UEFI). The network controllercan enable a network connection to a wired network. In some embodiments, a high-performance network controller (not shown) couples with the interface bus. The audio controller, in one embodiment, is a multi-channel high definition audio controller. In one embodiment, the systemincludes an optional legacy I/O controllerfor coupling legacy (e.g., Personal System 2 (PS/2)) devices to the system. The platform controller hubcan also connect to one or more Universal Serial Bus (USB) controllersconnect input devices, such as keyboard and mousecombinations, a camera, or other USB input devices.

100 116 130 112 130 116 102 100 116 130 102 It will be appreciated that the systemshown is exemplary and not limiting, as other types of data processing systems that are differently configured may also be used. For example, an instance of the memory controllerand platform controller hubmay be integrated into a discreet external graphics processor, such as the external graphics processor. In one embodiment, the platform controller huband/or memory controllermay be external to the one or more processor(s). For example, the systemcan include an external memory controllerand platform controller hub, which may be configured as a memory controller hub and peripheral controller hub within a system chipset that is in communication with the processor(s).

2 FIG. 2 FIG. 200 202 202 214 208 200 202 202 202 204 204 206 is a block diagram of an embodiment of a processorhaving one or more processor coresA-N, an integrated memory controller, and an integrated graphics processor. Those elements ofhaving the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. Processorcan include additional cores up to and including additional coreN represented by the dashed lined boxes. Each of processor coresA-N includes one or more internal cache unitsA-N. In some embodiments, each processor core also has access to one or more shared cached units.

204 204 206 200 206 204 204 The internal cache unitsA-N and shared cache unitsrepresent a cache memory hierarchy within the processor. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as the LLC. In some embodiments, cache coherency logic maintains coherency between the various cache unitsandA-N.

200 216 210 216 210 210 214 In some embodiments, processormay also include a set of one or more bus controller unitsand a system agent core. The one or more bus controller unitsmanage a set of peripheral buses, such as one or more PCI or PCI express busses. System agent coreprovides management functionality for the various processor components. In some embodiments, system agent coreincludes one or more integrated memory controllersto manage access to various external memory devices (not shown).

202 202 210 202 202 210 202 202 208 In some embodiments, one or more of the processor coresA-N include support for simultaneous multi-threading. In such embodiment, the system agent coreincludes components for coordinating and operating coresA-N during multi-threaded processing. System agent coremay additionally include a power control unit (PCU), which includes logic and components to regulate the power state of processor coresA-N and graphics processor.

200 208 208 206 210 214 210 211 211 208 In some embodiments, processoradditionally includes graphics processorto execute graphics processing operations. In some embodiments, the graphics processorcouples with the set of shared cache units, and the system agent core, including the one or more integrated memory controllers. In some embodiments, the system agent corealso includes a display controllerto drive graphics processor output to one or more coupled displays. In some embodiments, display controllermay also be a separate module coupled with the graphics processor via at least one interconnect, or may be integrated within the graphics processor.

212 200 208 212 213 In some embodiments, a ring based interconnect unitis used to couple the internal components of the processor. However, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques, including techniques well known in the art. In some embodiments, graphics processorcouples with the ring interconnectvia an I/O link.

213 218 202 202 208 218 The exemplary I/O linkrepresents at least one of multiple varieties of I/O interconnects, including an on package I/O interconnect which facilitates communication between various processor components and a high-performance embedded memory module, such as an eDRAM module. In some embodiments, each of the processor coresA-N and graphics processoruse embedded memory modulesas a shared Last Level Cache.

202 202 202 202 202 202 202 202 200 In some embodiments, processor coresA-N are homogenous cores executing the same instruction set architecture. In another embodiment, processor coresA-N are heterogeneous in terms of instruction set architecture (ISA), where one or more of processor coresA-N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment processor coresA-N are heterogeneous in terms of microarchitecture, where one or more cores having a relatively higher power consumption couple with one or more power cores having a lower power consumption. Additionally, processorcan be implemented on one or more chips or as an SoC integrated circuit having the illustrated components, in addition to other components.

3 FIG. 300 300 314 314 is a block diagram of a graphics processor, which may be a discrete graphics processing unit, or may be a graphics processor integrated with a plurality of processing cores. In some embodiments, the graphics processor communicates via a memory mapped I/O interface to registers on the graphics processor and with commands placed into the processor memory. In some embodiments, graphics processorincludes a memory interfaceto access memory. Memory interfacecan be an interface to local memory, one or more internal caches, one or more shared external caches, and/or to system memory.

300 302 320 302 320 320 300 306 In some embodiments, graphics processoralso includes a display controllerto drive display output data to a display device. Display controllerincludes hardware for one or more overlay planes for the display and composition of multiple layers of video or user interface elements. The display devicecan be an internal or external display device. In one embodiment, the display deviceis a head mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In some embodiments, graphics processorincludes a video codec engineto encode, decode, or transcode media to, from, or between one or more media encoding formats, including, but not limited to Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264/MPEG-4 AVC, as well as the Society of Motion Picture & Television Engineers (SMPTE) 421M/VC-1, and Joint Photographic Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats.

300 304 310 310 In some embodiments, graphics processorincludes a block image transfer (BLIT) engineto perform two-dimensional (2D) rasterizer operations including, for example, bit-boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of graphics processing engine (GPE). In some embodiments, GPEis a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

310 312 312 315 312 310 316 In some embodiments, GPEincludes a 3D pipelinefor performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act upon 3D primitive shapes (e.g., rectangle, triangle, etc.). The 3D pipelineincludes programmable and fixed function elements that perform various tasks within the element and/or spawn execution threads to a 3D/Media sub-system. While 3D pipelinecan be used to perform media operations, an embodiment of GPEalso includes a media pipelinethat is specifically used to perform media operations, such as video post-processing and image enhancement.

316 306 316 315 315 In some embodiments, media pipelineincludes fixed function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video de-interlacing, and video encode acceleration in place of, or on behalf of video codec engine. In some embodiments, media pipelineadditionally includes a thread spawning unit to spawn threads for execution on 3D/Media sub-system. The spawned threads perform computations for the media operations on one or more graphics execution units included in 3D/Media sub-system.

315 312 316 315 315 In some embodiments, 3D/Media subsystemincludes logic for executing threads spawned by 3D pipelineand media pipeline. In one embodiment, the pipelines send thread execution requests to 3D/Media subsystem, which includes thread dispatch logic for arbitrating and dispatching the various requests to available thread execution resources. The execution resources include an array of graphics execution units to process the 3D and media threads. In some embodiments, 3D/Media subsystemincludes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory, including registers and addressable memory, to share data between threads and to store output data.

4 FIG. 3 FIG. 4 FIG. 3 FIG. 410 410 310 312 316 316 410 410 410 is a block diagram of a graphics processing engineof a graphics processor in accordance with some embodiments. In one embodiment, the graphics processing engine (GPE)is a version of the GPEshown in. Elements ofhaving the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. For example, the 3D pipelineand media pipelineofare illustrated. The media pipelineis optional in some embodiments of the GPEand may not be explicitly included within the GPE. For example, and in at least one embodiment, a separate media and/or image processor is coupled to the GPE.

410 403 312 316 403 403 312 316 312 316 312 312 316 312 316 414 414 415 415 In some embodiments, GPEcouples with or includes a command streamer, which provides a command stream to the 3D pipelineand/or media pipelines. In some embodiments, command streameris coupled with memory, which can be system memory, or one or more of internal cache memory and shared cache memory. In some embodiments, command streamerreceives commands from the memory and sends the commands to 3D pipelineand/or media pipeline. The commands are directives fetched from a ring buffer, which stores commands for the 3D pipelineand media pipeline. In one embodiment, the ring buffer can additionally include batch command buffers storing batches of multiple commands. The commands for the 3D pipelinecan also include references to data stored in memory, such as but not limited to vertex and geometry data for the 3D pipelineand/or image data and memory objects for the media pipeline. The 3D pipelineand media pipelineprocess the commands and data by performing operations via logic within the respective pipelines or by dispatching one or more execution threads to a graphics core array. In one embodiment, the graphics core arrayinclude one or more blocks of graphics cores (e.g., graphics core(s)A, graphics core(s)B), each block including one or more graphics cores. Each graphics core includes a set of graphics execution resources that includes general-purpose and graphics specific execution logic to perform graphics and compute operations, as well as fixed function texture processing and/or machine learning and artificial intelligence acceleration logic.

312 414 414 415 414 414 In various embodiments, the 3D pipelineincludes fixed function and programmable logic to process one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing the instructions and dispatching execution threads to the graphics core array. The graphics core arrayprovides a unified block of execution resources for use in processing these shader programs. Multi-purpose execution logic (e.g., execution units) within the graphics core(s)A-B of the graphic core arrayincludes support for various 3D API shader languages and can execute multiple simultaneous execution threads associated with multiple shaders.

414 107 202 202 1 FIG. 2 FIG. In some embodiments, the graphics core arrayalso includes execution logic to perform media functions, such as video and/or image processing. In one embodiment, the execution units additionally include general-purpose logic that is programmable to perform parallel general-purpose computational operations, in addition to graphics processing operations. The general-purpose logic can perform processing operations in parallel or in conjunction with general-purpose logic within the processor core(s)ofor coreA-N as in.

414 418 418 418 414 418 420 Output data generated by threads executing on the graphics core arraycan output data to memory in a unified return buffer (URB). The URBcan store data for multiple threads. In some embodiments, the URBmay be used to send data between different threads executing on the graphics core array. In some embodiments, the URBmay additionally be used for synchronization between threads on the graphics core array and fixed function logic within the shared function logic.

414 410 In some embodiments, graphics core arrayis scalable, such that the array includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of GPE. In one embodiment, the execution resources are dynamically scalable, such that execution resources may be enabled or disabled as needed.

414 420 420 414 420 421 422 423 425 420 The graphics core arraycouples with shared function logicthat includes multiple resources that are shared between the graphics cores in the graphics core array. The shared functions within the shared function logicare hardware logic units that provide specialized supplemental functionality to the graphics core array. In various embodiments, shared function logicincludes but is not limited to sampler, math, and inter-thread communication (ITC)logic. Additionally, some embodiments implement one or more cache(s)within the shared function logic.

414 420 414 414 414 420 414 416 414 416 414 420 420 416 414 420 416 414 A shared function is implemented where the demand for a given specialized function is insufficient for inclusion within the graphics core array. Instead a single instantiation of that specialized function is implemented as a stand-alone entity in the shared function logicand shared among the execution resources within the graphics core array. The precise set of functions that are shared between the graphics core arrayand included within the graphics core arrayvaries across embodiments. In some embodiments, specific shared functions within the shared function logicthat are used extensively by the graphics core arraymay be included within shared function logicwithin the graphics core array. In various embodiments, the shared function logicwithin the graphics core arraycan include some or all logic within the shared function logic. In one embodiment, all logic elements within the shared function logicmay be duplicated within the shared function logicof the graphics core array. In one embodiment, the shared function logicis excluded in favor of the shared function logicwithin the graphics core array.

5 FIG. 5 FIG. 4 FIG. 500 500 414 500 500 500 530 501 501 is a block diagram of hardware logic of a graphics processor core, according to some embodiments described herein. Elements ofhaving the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such. The illustrated graphics processor core, in some embodiments, is included within the graphics core arrayof. The graphics processor core, sometimes referred to as a core slice, can be one or multiple graphics cores within a modular graphics processor. The graphics processor coreis exemplary of one graphics core slice, and a graphics processor as described herein may include multiple graphics core slices based on target power and performance envelopes. Each graphics processor corecan include a fixed function blockcoupled with multiple sub-coresA-F, also referred to as sub-slices, that include modular blocks of general-purpose and fixed function logic.

530 536 500 536 312 418 3 FIG. 4 FIG. 4 FIG. In some embodiments, the fixed function blockincludes a geometry/fixed function pipelinethat can be shared by all sub-cores in the graphics processor core, for example, in lower performance and/or lower power graphics processor implementations. In various embodiments, the geometry/fixed function pipelineincludes a 3D fixed function pipeline (e.g., 3D pipelineas inand) a video front-end unit, a thread spawner and thread dispatcher, and a unified return buffer manager, which manages unified return buffers, such as the unified return bufferof.

530 537 538 539 537 500 538 500 539 316 539 501 501 3 FIG. 4 FIG. In one embodiment, the fixed function blockalso includes a graphics SoC interface, a graphics microcontroller, and a media pipeline. The graphics SoC interfaceprovides an interface between the graphics processor coreand other processor cores within a system on a chip integrated circuit. The graphics microcontrolleris a programmable sub-processor that is configurable to manage various functions of the graphics processor core, including thread dispatch, scheduling, and pre-emption. The media pipeline(e.g., media pipelineofand) includes logic to facilitate the decoding, encoding, pre-processing, and/or post-processing of multimedia data, including image and video data. The media pipelineimplement media operations via requests to compute or sampling logic within the sub-cores-F.

537 500 537 500 537 500 500 537 539 536 514 In one embodiment, the SoC interfaceenables the graphics processor coreto communicate with general-purpose application processor cores (e.g., CPUs) and/or other components within an SoC, including memory hierarchy elements such as a shared last level cache memory, the system RAM, and/or embedded on-chip or on-package DRAM. The SoC interfacecan also enable communication with fixed function devices within the SoC, such as camera imaging pipelines, and enables the use of and/or implements global memory atomics that may be shared between the graphics processor coreand CPUs within the SoC. The SoC interfacecan also implement power management controls for the graphics processor coreand enable an interface between a clock domain of the graphic processor coreand other clock domains within the SoC. In one embodiment, the SoC interfaceenables receipt of command buffers from a command streamer and global thread dispatcher that are configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. The commands and instructions can be dispatched to the media pipeline, when media operations are to be performed, or a geometry and fixed function pipeline (e.g., geometry and fixed function pipeline, geometry and fixed function pipeline) when graphics processing operations are to be performed.

538 500 538 502 502 504 504 501 501 500 538 500 500 500 The graphics microcontrollercan be configured to perform various scheduling and management tasks for the graphics processor core. In one embodiment, the graphics microcontrollercan perform graphics and/or compute workload scheduling on the various graphics parallel engines within execution unit (EU) arraysA-F,A-F within the sub-coresA-F. In this scheduling model, host software executing on a CPU core of an SoC including the graphics processor corecan submit workloads one of multiple graphic processor doorbells, which invokes a scheduling operation on the appropriate graphics engine. Scheduling operations include determining which workload to run next, submitting a workload to a command streamer, pre-empting existing workloads running on an engine, monitoring progress of a workload, and notifying host software when a workload is complete. In one embodiment, the graphics microcontrollercan also facilitate low-power or idle states for the graphics processor core, providing the graphics processor corewith the ability to save and restore registers within the graphics processor coreacross low-power state transitions independently from the operating system and/or graphics driver software on the system.

500 501 501 500 510 512 514 516 510 420 500 512 501 501 500 514 536 530 4 FIG. The graphics processor coremay have greater than or fewer than the illustrated sub-coresA-F, up to N modular sub-cores. For each set of N sub-cores, the graphics processor corecan also include shared function logic, shared and/or cache memory, a geometry/fixed function pipeline, as well as additional fixed function logicto accelerate various graphics and compute processing operations. The shared function logiccan include logic units associated with the shared function logicof(e.g., sampler, math, and/or inter-thread communication logic) that can be shared by each N sub-cores within the graphics processor core. The shared and/or cache memorycan be a last-level cache for the set of N sub-coresA-F within the graphics processor core, and can also serve as shared memory that is accessible by multiple sub-cores. The geometry/fixed function pipelinecan be included instead of the geometry/fixed function pipelinewithin the fixed function blockand can include the same or similar logic units.

500 516 500 516 516 536 516 516 In one embodiment, the graphics processor coreincludes additional fixed function logicthat can include various fixed function acceleration logic for use by the graphics processor core. In one embodiment, the additional fixed function logicincludes an additional geometry pipeline for use in position only shading. In position-only shading, two geometry pipelines exist, the full geometry pipeline within the geometry/fixed function pipeline,, and a cull pipeline, which is an additional geometry pipeline which may be included within the additional fixed function logic. In one embodiment, the cull pipeline is a trimmed down version of the full geometry pipeline. The full pipeline and the cull pipeline can execute different instances of the same application, each instance having a separate context. Position only shading can hide long cull runs of discarded triangles, enabling shading to be completed earlier in some instances. For example, and in one embodiment the cull pipeline logic within the additional fixed function logiccan execute position shaders in parallel with the main application and generally generates critical results faster than the full pipeline, as the cull pipeline fetches and shades only the position attribute of the vertices, without performing rasterization and rendering of the pixels to the frame buffer. The cull pipeline can use the generated critical results to compute visibility information for all the triangles without regard to whether those triangles are culled. The full pipeline (which in this instance may be referred to as a replay pipeline) can consume the visibility information to skip the culled triangles to shade only the visible triangles that are finally passed to the rasterization phase.

516 In one embodiment, the additional fixed function logiccan also include machine-learning acceleration logic, such as fixed function matrix multiplication logic, for implementations including optimizations for machine learning training or inferencing.

501 501 501 501 502 502 504 504 503 503 505 505 506 506 507 507 508 508 502 502 504 504 503 503 505 505 506 506 501 501 501 501 508 508 Within each graphics sub-coreA-F includes a set of execution resources that may be used to perform graphics, media, and compute operations in response to requests by graphics pipeline, media pipeline, or shader programs. The graphics sub-coresA-F include multiple EU arraysA-F,A-F, thread dispatch and inter-thread communication (TD/IC) logicA-F, a 3D (e.g., texture) samplerA-F, a media samplerA-F, a shader processorA-F, and shared local memory (SLM)A-F. The EU arraysA-F,A-F each include multiple execution units, which are general-purpose graphics processing units capable of performing floating-point and integer/fixed-point logic operations in service of a graphics, media, or compute operation, including graphics, media, or compute shader programs. The TD/IC logicA-F performs local thread dispatch and thread control operations for the execution units within a sub-core and facilitate communication between threads executing on the execution units of the sub-core. The 3D samplerA-F can read texture or other 3D graphics related data into memory. The 3D sampler can read texture data differently based on a configured sample state and the texture format associated with a given texture. The media samplerA-F can perform similar read operations based on the type and format associated with media data. In one embodiment, each graphics sub-coreA-F can alternately include a unified 3D and media sampler. Threads executing on the execution units within each of the sub-coresA-F can make use of shared local memoryA-F within each sub-core, to enable threads executing within a thread group to execute using a common pool of on-chip memory.

6 6 FIGS.A-B 6 6 FIGS.A-B 6 FIG.A 5 FIG. 6 FIG.B 600 600 501 501 illustrate thread execution logicincluding an array of processing elements employed in a graphics processor core according to embodiments described herein. Elements ofhaving the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.illustrates an overview of thread execution logic, which can include a variant of the hardware logic illustrated with each sub-coreA-F of.illustrates exemplary internal details of an execution unit.

6 FIG.A 600 602 604 606 608 608 610 612 614 608 608 608 608 608 1 608 600 606 614 610 608 608 608 608 608 As illustrated in, in some embodiments thread execution logicincludes a shader processor, a thread dispatcher, instruction cache, a scalable execution unit array including a plurality of execution unitsA-N, a sampler, a data cache, and a data port. In one embodiment, the scalable execution unit array can dynamically scale by enabling or disabling one or more execution units (e.g., any of execution unitA,B,C,D, throughN-andN) based on the computational requirements of a workload. In one embodiment, the included components are interconnected via an interconnect fabric that links to each of the components. In some embodiments, thread execution logicincludes one or more connections to memory, such as system memory or cache memory, through one or more of instruction cache, data port, sampler, and execution unitsA-N. In some embodiments, each execution unit (e.g.A) is a stand-alone programmable general-purpose computational unit that is capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In various embodiments, the array of execution unitsA-N is scalable to include any number individual execution units.

608 608 602 604 608 608 604 In some embodiments, the execution unitsA-N are primarily used to execute shader programs. A shader processorcan process the various shader programs and dispatch execution threads associated with the shader programs via a thread dispatcher. In one embodiment, the thread dispatcher includes logic to arbitrate thread initiation requests from the graphics and media pipelines and instantiate the requested threads on one or more execution unit in the execution unitsA-N. For example, a geometry pipeline can dispatch vertex, tessellation, or geometry shaders to the thread execution logic for processing. In some embodiments, thread dispatchercan also process runtime thread spawning requests from the executing shader programs.

608 608 608 608 608 608 In some embodiments, the execution unitsA-N support an instruction set that includes native support for many standard 3D graphics shader instructions, such that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with a minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders) and general-purpose processing (e.g., compute and media shaders). Each of the execution unitsA-N is capable of multi-issue single instruction multiple data (SIMD) execution and multi-threaded operation enables an efficient execution environment in the face of higher latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread-state. Execution is multi-issue per clock to pipelines capable of integer, single and double precision floating point operations, SIMD branch capability, logical operations, transcendental operations, and other miscellaneous operations. While waiting for data from memory or one of the shared functions, dependency logic within the execution unitsA-N causes a waiting thread to sleep until the requested data has been returned. While the waiting thread is sleeping, hardware resources may be devoted to processing other threads. For example, during a delay associated with a vertex shader operation, an execution unit can perform operations for a pixel shader, fragment shader, or another type of shader program, including a different vertex shader.

608 608 608 608 Each execution unit in execution unitsA-N operates on arrays of data elements. The number of data elements is the “execution size,” or the number of channels for the instruction. An execution channel is a logical unit of execution for data element access, masking, and flow control within instructions. The number of channels may be independent of the number of physical Arithmetic Logic Units (ALUs) or Floating Point Units (FPUs) for a particular graphics processor. In some embodiments, execution unitsA-N support integer and floating-point data types.

The execution unit instruction set includes SIMD instructions. The various data elements can be stored as a packed data type in a register and the execution unit will process the various elements based on the data size of the elements. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in a register and the execution unit operates on the vector as four separate 64-bit packed data elements (Quad-Word (QW) size data elements), eight separate 32-bit packed data elements (Double Word (DW) size data elements), sixteen separate 16-bit packed data elements (Word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible.

609 609 607 607 609 609 609 608 608 607 608 608 607 609 609 609 In one embodiment one or more execution units can be combined into a fused execution unitA-N having thread control logic (A-N) that is common to the fused EUs. Multiple EUs can be fused into an EU group. Each EU in the fused EU group can be configured to execute a separate SIMD hardware thread. The number of EUs in a fused EU group can vary according to embodiments. Additionally, various SIMD widths can be performed per-EU, including but not limited to SIMD8, SIMD16, and SIMD32. Each fused graphics execution unitA-N includes at least two execution units. For example, fused execution unitA includes a first EUA, second EUB, and thread control logicA that is common to the first EUA and the second EUB. The thread control logicA controls threads executed on the fused graphics execution unitA, allowing each EU within the fused execution unitsA-N to execute using a common instruction pointer register.

606 600 612 610 610 One or more internal instruction caches (e.g.,) are included in the thread execution logicto cache thread instructions for the execution units. In some embodiments, one or more data caches (e.g.,) are included to cache thread data during thread execution. In some embodiments, a sampleris included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, samplerincludes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to an execution unit.

600 602 602 602 608 604 602 610 During execution, the graphics and media pipelines send thread initiation requests to thread execution logicvia thread spawning and dispatch logic. Once a group of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processoris invoked to further compute output information and cause results to be written to output surfaces (e.g., color buffers, depth buffers, stencil buffers, etc.). In some embodiments, a pixel shader or fragment shader calculates the values of the various vertex attributes that are to be interpolated across the rasterized object. In some embodiments, pixel processor logic within the shader processorthen executes an application programming interface (API)-supplied pixel or fragment shader program. To execute the shader program, the shader processordispatches threads to an execution unit (e.g.,A) via thread dispatcher. In some embodiments, shader processoruses texture sampling logic in the samplerto access texture data in texture maps stored in memory. Arithmetic operations on the texture data and the input geometry data compute pixel color data for each geometric fragment, or discards one or more pixels from further processing.

614 600 614 612 In some embodiments, the data portprovides a memory access mechanism for the thread execution logicto output processed data to memory for further processing on a graphics processor output pipeline. In some embodiments, the data portincludes or couples to one or more cache memories (e.g., data cache) to cache data for memory access via the data port.

6 FIG.B 608 637 624 626 622 630 632 634 635 624 626 608 626 624 626 As illustrated in, a graphics execution unitcan include an instruction fetch unit, a general register file array (GRF), an architectural register file array (ARF), a thread arbiter, a send unit, a branch unit, a set of SIMD floating point units (FPUs), and in one embodiment a set of dedicated integer SIMD ALUs. The GRFand ARFincludes the set of general register files and architecture register files associated with each simultaneous hardware thread that may be active in the graphics execution unit. In one embodiment, per thread architectural state is maintained in the ARF, while data used during thread execution is stored in the GRF. The execution state of each thread, including the instruction pointers for each thread, can be held in thread-specific registers in the ARF.

608 In one embodiment, the graphics execution unithas an architecture that is a combination of Simultaneous Multi-Threading (SMT) and fine-grained Interleaved Multi-Threading (IMT). The architecture has a modular configuration that can be fine-tuned at design time based on a target number of simultaneous threads and number of registers per execution unit, where execution unit resources are divided across logic used to execute multiple simultaneous threads.

608 622 608 630 642 634 624 624 624 In one embodiment, the graphics execution unitcan co-issue multiple instructions, which may each be different instructions. The thread arbiterof the graphics execution unit threadcan dispatch the instructions to one of the send unit, branch unit, or SIMD FPU(s)for execution. Each execution thread can access 128 general-purpose registers within the GRF, where each register can store 32 bytes, accessible as a SIMD 8-element vector of 32-bit data elements. In one embodiment, each execution unit thread has access to 4 Kbytes within the GRF, although embodiments are not so limited, and greater or fewer register resources may be provided in other embodiments. In one embodiment, up to seven threads can execute simultaneously, although the number of threads per execution unit can also vary according to embodiments. In an embodiment in which seven threads may access 4 Kbytes, the GRFcan store a total of 28 Kbytes. Flexible addressing modes can permit registers to be addressed together to build effectively wider registers or to represent strided rectangular block data structures.

630 632 In one embodiment, memory operations, sampler operations, and other longer-latency system communications are dispatched via “send” instructions that are executed by the message passing send unit. In one embodiment, branch instructions are dispatched to a dedicated branch unitto facilitate SIMD divergence and eventual convergence.

608 634 634 634 635 In one embodiment, the graphics execution unitincludes one or more SIMD floating point units (FPU(s))to perform floating-point operations. In one embodiment, the FPU(s)also support integer computation. In one embodiment, the FPU(s)can SIMD execute up to M number of 32-bit floating-point (or integer) operations, or SIMD execute up to 2 M 16-bit integer or 16-bit floating-point operations. In one embodiment, at least one of the FPU(s) provides extended math capability to support high-throughput transcendental math functions and double precision 64-bit floating-point. In some embodiments, a set of 8-bit integer SIMD ALUsare also present, and may be specifically optimized to perform operations associated with machine learning computations.

608 608 608 In one embodiment, arrays of multiple instances of the graphics execution unitcan be instantiated in a graphics sub-core grouping (e.g., a sub-slice). For scalability, product architects can choose the exact number of execution units per sub-core grouping. In one embodiment, the execution unitcan execute instructions across a plurality of execution channels. In a further embodiment, each thread executed on the graphics execution unitis executed on a different channel.

7 FIG. 700 700 is a block diagram illustrating a graphics processor instruction formatsaccording to some embodiments. In one or more embodiment, the graphics processor execution units support an instruction set having instructions in multiple formats. The solid lined boxes illustrate the components that are generally included in an execution unit instruction, while the dashed lines include components that are optional or that are only included in a sub-set of the instructions. In some embodiments, instruction formatdescribed and illustrated are macro-instructions, in that they are instructions supplied to the execution unit, as opposed to micro-operations resulting from instruction decode once the instruction is processed.

710 730 710 730 730 713 710 In some embodiments, the graphics processor execution units natively support instructions in a 128-bit instruction format. A 64-bit compacted instruction formatis available for some instructions based on the selected instruction, instruction options, and number of operands. The native 128-bit instruction formatprovides access to all instruction options, while some options and operations are restricted in the 64-bit format. The native instructions available in the 64-bit formatvary by embodiment. In some embodiments, the instruction is compacted in part using a set of index values in an index field. The execution unit hardware references a set of compaction tables based on the index values and uses the compaction table outputs to reconstruct a native instruction in the 128-bit instruction format.

712 714 710 716 716 730 For each format, instruction opcodedefines the operation that the execution unit is to perform. The execution units execute each instruction in parallel across the multiple data elements of each operand. For example, in response to an add instruction the execution unit performs a simultaneous add operation across each color channel representing a texture element or picture element. By default, the execution unit performs each instruction across all data channels of the operands. In some embodiments, instruction control fieldenables control over certain execution options, such as channels selection (e.g., predication) and data channel order (e.g., swizzle). For instructions in the 128-bit instruction formatan exec-size fieldlimits the number of data channels that will be executed in parallel. In some embodiments, exec-size fieldis not available for use in the 64-bit compact instruction format.

720 722 718 724 712 Some execution unit instructions have up to three operands including two source operands, src0, src1, and one destination. In some embodiments, the execution units support dual destination instructions, where one of the destinations is implied. Data manipulation instructions can have a third source operand (e.g., SRC2), where the instruction opcodedetermines the number of source operands. An instruction's last source operand can be an immediate (e.g., hard-coded) value passed with the instruction.

710 726 In some embodiments, the 128-bit instruction formatincludes an access/address mode fieldspecifying, for example, whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is directly provided by bits in the instruction.

710 726 In some embodiments, the 128-bit instruction formatincludes an access/address mode field, which specifies an address mode and/or an access mode for the instruction. In one embodiment, the access mode is used to define a data access alignment for the instruction. Some embodiments support access modes including a 16-byte aligned access mode and a 1-byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in a first mode, the instruction may use byte-aligned addressing for source and destination operands and when in a second mode, the instruction may use 16-byte-aligned addressing for all source and destination operands.

726 In one embodiment, the address mode portion of the access/address mode fielddetermines whether the instruction is to use direct or indirect addressing. When direct register addressing mode is used bits in the instruction directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands may be computed based on an address register value and an address immediate field in the instruction.

712 740 742 742 744 746 748 748 750 In some embodiments instructions are grouped based on opcodebit-fields to simplify Opcode decode. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The precise opcode grouping shown is merely an example. In some embodiments, a move and logic opcode groupincludes data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, move and logic groupshares the five most significant bits (MSB), where move (mov) instructions are in the form of 0000xxxxb and logic instructions are in the form of 0001xxxxb. A flow control instruction group(e.g., call, jump (jmp)) includes instructions in the form of 0010xxxxb (e.g., 0×20). A miscellaneous instruction groupincludes a mix of instructions, including synchronization instructions (e.g., wait, send) in the form of 0011xxxxb (e.g., 0×30). A parallel math instruction groupincludes component-wise arithmetic instructions (e.g., add, multiply (mul)) in the form of 0100xxxxb (e.g., 0×40). The parallel math groupperforms the arithmetic operations in parallel across data channels. The vector math groupincludes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0×50). The vector math group performs arithmetic such as dot product calculations on vector operands.

8 FIG. 8 FIG. 800 is a block diagram of another embodiment of a graphics processor. Elements ofhaving the same reference numbers (or names) as the elements of any other figure herein can operate or function in any manner similar to that described elsewhere herein, but are not limited to such.

800 820 830 840 850 870 800 800 802 802 800 802 803 820 830 In some embodiments, graphics processorincludes a geometry pipeline, a media pipeline, a display engine, thread execution logic, and a render output pipeline. In some embodiments, graphics processoris a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to graphics processorvia a ring interconnect. In some embodiments, ring interconnectcouples graphics processorto other processing components, such as other graphics processors or general-purpose processors. Commands from ring interconnectare interpreted by a command streamer, which supplies instructions to individual components of the geometry pipelineor the media pipeline.

803 805 803 805 807 805 807 852 852 831 In some embodiments, command streamerdirects the operation of a vertex fetcherthat reads vertex data from memory and executes vertex-processing commands provided by command streamer. In some embodiments, vertex fetcherprovides vertex data to a vertex shader, which performs coordinate space transformation and lighting operations to each vertex. In some embodiments, vertex fetcherand vertex shaderexecute vertex-processing instructions by dispatching execution threads to execution unitsA-B via a thread dispatcher.

852 852 852 852 851 In some embodiments, execution unitsA-B are an array of vector processors having an instruction set for performing graphics and media operations. In some embodiments, execution unitsA-B have an attached L1 cachethat is specific for each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

820 811 817 813 811 820 811 813 817 In some embodiments, geometry pipelineincludes tessellation components to perform hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shaderconfigures the tessellation operations. A programmable domain shaderprovides back-end evaluation of tessellation output. A tessellatoroperates at the direction of hull shaderand contains special purpose logic to generate a set of detailed geometric objects based on a coarse geometric model that is provided as input to geometry pipeline. In some embodiments, if tessellation is not used, tessellation components (e.g., hull shader, tessellator, and domain shader) can be bypassed.

819 852 852 829 819 807 819 In some embodiments, complete geometric objects can be processed by a geometry shadervia one or more threads dispatched to execution unitsA-B, or can proceed directly to the clipper. In some embodiments, the geometry shader operates on entire geometric objects, rather than vertices or patches of vertices as in previous stages of the graphics pipeline. If the tessellation is disabled the geometry shaderreceives input from the vertex shader. In some embodiments, geometry shaderis programmable by a geometry shader program to perform geometry tessellation if the tessellation units are disabled.

829 829 873 870 850 873 823 Before rasterization, clipperprocesses vertex data. The clippermay be a fixed function clipper or a programmable clipper having clipping and geometry shader functions. In some embodiments, a rasterizer and depth test componentin the render output pipelinedispatches pixel shaders to convert the geometric objects into per pixel representations. In some embodiments, pixel shader logic is included in thread execution logic. In some embodiments, an application can bypass the rasterizer and depth test componentand access un-rasterized vertex data via a stream out unit.

800 852 852 851 854 858 856 854 851 858 852 852 858 The graphics processorhas an interconnect bus, interconnect fabric, or some other interconnect mechanism that allows data and message passing amongst the major components of the processor. In some embodiments, execution unitsA-B and associated logic units (e.g., L1 cache, sampler, texture cache, etc.) interconnect via a data portto perform memory access and communicate with render output pipeline components of the processor. In some embodiments, sampler, caches,and execution unitsA-B each have separate memory access paths. In one embodiment, the texture cachecan also be configured as a sampler cache.

870 873 878 879 877 841 843 875 In some embodiments, render output pipelinecontains a rasterizer and depth test componentthat converts vertex-based objects into an associated pixel-based representation. In some embodiments, the rasterizer logic includes a windower/masker unit to perform fixed function triangle and line rasterization. An associated render cacheand depth cacheare also available in some embodiments. A pixel operations componentperforms pixel-based operations on the data, though in some instances, pixel operations associated with 2D operations (e.g. bit block image transfers with blending) are performed by the 2D engine, or substituted at display time by the display controllerusing overlay display planes. In some embodiments, a shared L3 cacheis available to all graphics components, allowing the sharing of data without the use of main system memory.

830 837 834 834 803 830 834 837 837 850 831 In some embodiments, graphics processor media pipelineincludes a media engineand a video front-end. In some embodiments, video front-endreceives pipeline commands from the command streamer. In some embodiments, media pipelineincludes a separate command streamer. In some embodiments, video front-endprocesses media commands before sending the command to the media engine. In some embodiments, media engineincludes thread spawning functionality to spawn threads for dispatch to thread execution logicvia thread dispatcher.

800 840 840 800 802 840 841 843 840 843 In some embodiments, graphics processorincludes a display engine. In some embodiments, display engineis external to processorand couples with the graphics processor via the ring interconnect, or some other interconnect bus or fabric. In some embodiments, display engineincludes a 2D engineand a display controller. In some embodiments, display enginecontains special purpose logic capable of operating independently of the 3D pipeline. In some embodiments, display controllercouples with a display device (not shown), which may be a system integrated display device, as in a laptop computer, or an external display device attached via a display device connector.

820 830 In some embodiments, the geometry pipelineand media pipelineare configurable to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, driver software for the graphics processor translates API calls that are specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL), Open Computing Language (OpenCL), and/or Vulkan graphics and compute API, all from the Khronos Group. In some embodiments, support may also be provided for the Direct3D library from the Microsoft Corporation. In some embodiments, a combination of these libraries may be supported. Support may also be provided for the Open Source Computer Vision Library (OpenCV). A future API with a compatible 3D pipeline would also be supported if a mapping can be made from the pipeline of the future API to the pipeline of the graphics processor.

9 FIG.A 9 FIG.B 9 FIG.A 9 FIG.A 900 910 900 902 904 906 905 908 is a block diagram illustrating a graphics processor command formataccording to some embodiments.is a block diagram illustrating a graphics processor command sequenceaccording to an embodiment. The solid lined boxes inillustrate the components that are generally included in a graphics command while the dashed lines include components that are optional or that are only included in a sub-set of the graphics commands. The exemplary graphics processor command formatofincludes data fields to identify a client, a command operation code (opcode), and datafor the command. A sub-opcodeand a command sizeare also included in some commands.

902 904 905 906 908 In some embodiments, clientspecifies the client unit of the graphics device that processes the command data. In some embodiments, a graphics processor command parser examines the client field of each command to condition the further processing of the command and route the command data to the appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a render unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline that processes the commands. Once the command is received by the client unit, the client unit reads the opcodeand, if present, sub-opcodeto determine the operation to perform. The client unit performs the command using information in data field. For some commands an explicit command sizeis expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands based on the command opcode. In some embodiments commands are aligned via multiples of a double word.

9 FIG.B 910 The flow diagram inillustrates an exemplary graphics processor command sequence. In some embodiments, software or firmware of a data processing system that features an embodiment of a graphics processor uses a version of the command sequence shown to set up, execute, and terminate a set of graphics operations. A sample command sequence is shown and described for purposes of example only as embodiments are not limited to these specific commands or to this command sequence. Moreover, the commands may be issued as batch of commands in a command sequence, such that the graphics processor will process the sequence of commands in at least partially concurrence.

910 912 922 924 912 In some embodiments, the graphics processor command sequencemay begin with a pipeline flush commandto cause any active graphics pipeline to complete the currently pending commands for the pipeline. In some embodiments, the 3D pipelineand the media pipelinedo not operate concurrently. The pipeline flush is performed to cause the active graphics pipeline to complete any pending commands. In response to a pipeline flush, the command parser for the graphics processor will pause command processing until the active drawing engines complete pending operations and the relevant read caches are invalidated. Optionally, any data in the render cache that is marked ‘dirty’ can be flushed to memory. In some embodiments, pipeline flush commandcan be used for pipeline synchronization or before placing the graphics processor into a low power state.

913 913 912 913 In some embodiments, a pipeline select commandis used when a command sequence requires the graphics processor to explicitly switch between pipelines. In some embodiments, a pipeline select commandis required only once within an execution context before issuing pipeline commands unless the context is to issue commands for both pipelines. In some embodiments, a pipeline flush commandis required immediately before a pipeline switch via the pipeline select command.

914 922 924 914 914 In some embodiments, a pipeline control commandconfigures a graphics pipeline for operation and is used to program the 3D pipelineand the media pipeline. In some embodiments, pipeline control commandconfigures the pipeline state for the active pipeline. In one embodiment, the pipeline control commandis used for pipeline synchronization and to clear data from one or more cache memories within the active pipeline before processing a batch of commands.

916 916 In some embodiments, return buffer state commandsare used to configure a set of return buffers for the respective pipelines to write data. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which the operations write intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and to perform cross thread communication. In some embodiments, the return buffer stateincludes selecting the size and number of return buffers to use for a set of pipeline operations.

920 922 930 924 940 The remaining commands in the command sequence differ based on the active pipeline for operations. Based on a pipeline determination, the command sequence is tailored to the 3D pipelinebeginning with the 3D pipeline stateor the media pipelinebeginning at the media pipeline state.

930 930 The commands to configure the 3D pipeline stateinclude 3D state setting commands for vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that are to be configured before 3D primitive commands are processed. The values of these commands are determined at least in part based on the particular 3D API in use. In some embodiments, 3D pipeline statecommands are also able to selectively disable or bypass certain pipeline elements if those elements will not be used.

932 932 932 932 922 In some embodiments, 3D primitivecommand is used to submit 3D primitives to be processed by the 3D pipeline. Commands and associated parameters that are passed to the graphics processor via the 3D primitivecommand are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitivecommand data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, 3D primitivecommand is used to perform vertex operations on 3D primitives via vertex shaders. To process vertex shaders, 3D pipelinedispatches shader execution threads to graphics processor execution units.

922 934 In some embodiments, 3D pipelineis triggered via an executecommand or event. In some embodiments, a register write triggers command execution. In some embodiments execution is triggered via a ‘go’ or ‘kick’ command in the command sequence. In one embodiment, command execution is triggered using a pipeline synchronization command to flush the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for the 3D primitives. Once operations are complete, the resulting geometric objects are rasterized and the pixel engine colors the resulting pixels. Additional commands to control pixel shading and pixel back end operations may also be included for those operations.

910 924 924 In some embodiments, the graphics processor command sequencefollows the media pipelinepath when performing media operations. In general, the specific use and manner of programming for the media pipelinedepends on the media or compute operations to be performed. Specific media decode operations may be offloaded to the media pipeline during media decode. In some embodiments, the media pipeline can also be bypassed and media decode can be performed in whole or in part using resources provided by one or more general-purpose processing cores. In one embodiment, the media pipeline also includes elements for general-purpose graphics processor unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using computational shader programs that are not explicitly related to the rendering of graphics primitives.

924 922 940 942 940 940 In some embodiments, media pipelineis configured in a similar manner as the 3D pipeline. A set of commands to configure the media pipeline stateare dispatched or placed into a command queue before the media object commands. In some embodiments, commands for the media pipeline stateinclude data to configure the media pipeline elements that will be used to process the media objects. This includes data to configure the video decode and video encode logic within the media pipeline, such as encode or decode format. In some embodiments, commands for the media pipeline statealso support the use of one or more pointers to “indirect” state elements that contain a batch of state settings.

942 942 942 924 944 924 922 924 In some embodiments, media object commandssupply pointers to media objects for processing by the media pipeline. The media objects include memory buffers containing video data to be processed. In some embodiments, all media pipeline states must be valid before issuing a media object command. Once the pipeline state is configured and media object commandsare queued, the media pipelineis triggered via an execute commandor an equivalent execute event (e.g., register write). Output from media pipelinemay then be post processed by operations provided by the 3D pipelineor the media pipeline. In some embodiments, GPGPU operations are configured and executed in a similar manner as media operations.

10 FIG. 1000 1010 1020 1030 1030 1032 1034 1010 1020 1050 illustrates exemplary graphics software architecture for a data processing systemaccording to some embodiments. In some embodiments, software architecture includes a 3D graphics application, an operating system, and at least one processor. In some embodiments, processorincludes a graphics processorand one or more general-purpose processor core(s). The graphics applicationand operating systemeach execute in the system memoryof the data processing system.

1010 1012 1014 1034 1016 In some embodiments, 3D graphics applicationcontains one or more shader programs including shader instructions. The shader language instructions may be in a high-level shader language, such as the High Level Shader Language (HLSL) or the OpenGL Shader Language (GLSL). The application also includes executable instructionsin a machine language suitable for execution by the general-purpose processor core. The application also includes graphics objectsdefined by vertex data.

1020 1020 1022 1020 1024 1012 1010 1012 In some embodiments, operating systemis a Microsoft® Windows® operating system from the Microsoft Corporation, a proprietary UNIX-like operating system, or an open source UNIX-like operating system using a variant of the Linux kernel. The operating systemcan support a graphics APIsuch as the Direct3D API, the OpenGL API, or the Vulkan API. When the Direct3D API is in use, the operating systemuses a front-end shader compilerto compile any shader instructionsin HLSL into a lower-level shader language. The compilation may be a just-in-time (JIT) compilation or the application can perform shader pre-compilation. In some embodiments, high-level shaders are compiled into low-level shaders during the compilation of the 3D graphics application. In some embodiments, the shader instructionsare provided in an intermediate form, such as a version of the Standard Portable Intermediate Representation (SPIR) used by the Vulkan API.

1026 1027 1012 1012 1026 1026 1028 1029 1029 1032 In some embodiments, user mode graphics drivercontains a back-end shader compilerto convert the shader instructionsinto a hardware specific representation. When the OpenGL API is in use, shader instructionsin the GLSL high-level language are passed to a user mode graphics driverfor compilation. In some embodiments, user mode graphics driveruses operating system kernel mode functionsto communicate with a kernel mode graphics driver. In some embodiments, kernel mode graphics drivercommunicates with graphics processorto dispatch commands and instructions.

One or more aspects of at least one embodiment may be implemented by representative code stored on a machine-readable medium which represents and/or defines logic within an integrated circuit such as a processor. For example, the machine-readable medium may include instructions which represent various logic within the processor. When read by a machine, the instructions may cause the machine to fabricate the logic to perform the techniques described herein. Such representations, known as “IP cores,” are reusable units of logic for an integrated circuit that may be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be supplied to various customers or manufacturing facilities, which load the hardware model on fabrication machines that manufacture the integrated circuit. The integrated circuit may be fabricated such that the circuit performs operations described in association with any of the embodiments described herein.

11 FIG.A 1100 1100 1130 1110 1110 1112 1112 1115 1112 1115 1115 is a block diagram illustrating an IP core development systemthat may be used to manufacture an integrated circuit to perform operations according to an embodiment. The IP core development systemmay be used to generate modular, re-usable designs that can be incorporated into a larger design or used to construct an entire integrated circuit (e.g., an SOC integrated circuit). A design facilitycan generate a software simulationof an IP core design in a high-level programming language (e.g., C/C++). The software simulationcan be used to design, test, and verify the behavior of the IP core using a simulation model. The simulation modelmay include functional, behavioral, and/or timing simulations. A register transfer level (RTL) designcan then be created or synthesized from the simulation model. The RTL designis an abstraction of the behavior of the integrated circuit that models the flow of digital signals between hardware registers, including the associated logic performed using the modeled digital signals. In addition to an RTL design, lower-level designs at the logic level or transistor level may also be created, designed, or synthesized. Thus, the particular details of the initial design and simulation may vary.

1115 1120 1165 1140 1150 1160 1165 rd The RTL designor equivalent may be further synthesized by the design facility into a hardware model, which may be in a hardware description language (HDL), or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design can be stored for delivery to a 3party fabrication facilityusing non-volatile memory(e.g., hard disk, flash memory, or any non-volatile storage medium). Alternatively, the IP core design may be transmitted (e.g., via the Internet) over a wired connectionor wireless connection. The fabrication facilitymay then fabricate an integrated circuit that is based at least in part on the IP core design. The fabricated integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein.

11 FIG.B 1170 1170 1170 1172 1174 1180 1172 1174 1172 1174 1180 1173 1173 1172 1174 1180 1173 1172 1174 1180 1180 1170 1183 1183 1180 illustrates a cross-section side view of an integrated circuit package assembly, according to some embodiments described herein. The integrated circuit package assemblyillustrates an implementation of one or more processor or accelerator devices as described herein. The package assemblyincludes multiple units of hardware logic,connected to a substrate. The logic,may be implemented at least partly in configurable logic or fixed-functionality logic hardware, and can include one or more portions of any of the processor core(s), graphics processor(s), or other accelerator devices described herein. Each unit of logic,can be implemented within a semiconductor die and coupled with the substratevia an interconnect structure. The interconnect structuremay be configured to route electrical signals between the logic,and the substrate, and can include interconnects such as, but not limited to bumps or pillars. In some embodiments, the interconnect structuremay be configured to route electrical signals such as, for example, input/output (I/O) signals and/or power or ground signals associated with the operation of the logic,. In some embodiments, the substrateis an epoxy-based laminate substrate. The package substratemay include other suitable types of substrates in other embodiments. The package assemblycan be connected to other electrical devices via a package interconnect. The package interconnectmay be coupled to a surface of the substrateto route electrical signals to other electrical devices, such as a motherboard, other chipset, or multi-chip module.

1172 1174 1182 1172 1174 1182 1182 1172 1174 In some embodiments, the units of logic,are electrically coupled with a bridgethat is configured to route electrical signals between the logic,. The bridgemay be a dense interconnect structure that provides a route for electrical signals. The bridgemay include a bridge substrate composed of glass or a suitable semiconductor material. Electrical routing features can be formed on the bridge substrate to provide a chip-to-chip connection between the logic,.

1172 1174 1182 1182 Although two units of logic,and a bridgeare illustrated, embodiments described herein may include more or fewer logic units on one or more dies. The one or more dies may be connected by zero or more bridges, as the bridgemay be excluded when the logic is included on a single die. Alternatively, multiple dies or units of logic can be connected by one or more bridges. Additionally, multiple logic units, dies, and bridges can be connected together in other possible configurations, including three-dimensional configurations.

12 14 FIGS.- illustrated exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included, including additional graphics processors/cores, peripheral interface controllers, or general-purpose processor cores.

12 FIG. 1200 1200 1205 1210 1215 1220 1200 1225 1230 1235 1240 1245 1250 1255 1260 1265 1270 2 2 is a block diagram illustrating an exemplary system on a chip integrated circuitthat may be fabricated using one or more IP cores, according to an embodiment. Exemplary integrated circuitincludes one or more application processor(s)(e.g., CPUs), at least one graphics processor, and may additionally include an image processorand/or a video processor, any of which may be a modular IP core from the same or multiple different design facilities. Integrated circuitincludes peripheral or bus logic including a USB controller, UART controller, an SPI/SDIO controller, and an IS/IC controller. Additionally, the integrated circuit can include a display devicecoupled to one or more of a high-definition multimedia interface (HDMI) controllerand a mobile industry processor interface (MIPI) display interface. Storage may be provided by a flash memory subsystemincluding flash memory and a flash memory controller. Memory interface may be provided via a memory controllerfor access to SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine.

13 13 FIGS.A-B 13 FIG.A 13 FIG.B 13 FIG.A 13 FIG.B 12 FIG. 1310 1340 1310 1340 1310 1340 1210 are block diagrams illustrating exemplary graphics processors for use within an SoC, according to embodiments described herein.illustrates an exemplary graphics processorof a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment.illustrates an additional exemplary graphics processorof a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to an embodiment. Graphics processorofis an example of a low power graphics processor core. Graphics processorofis an example of a higher performance graphics processor core. Each of the graphics processors,can be variants of the graphics processorof.

13 FIG.A 1310 1305 1315 1315 1315 1315 1315 1315 1315 1 1315 1310 1305 1315 1315 1305 1315 1315 1305 1315 1315 As shown in, graphics processorincludes a vertex processorand one or more fragment processor(s)A-N (e.g.,A,B,C,D, throughN-, andN). Graphics processorcan execute different shader programs via separate logic, such that the vertex processoris optimized to execute operations for vertex shader programs, while the one or more fragment processor(s)A-N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs. The vertex processorperforms the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. The fragment processor(s)A-N use the primitive and vertex data generated by the vertex processorto produce a framebuffer that is displayed on a display device. In one embodiment, the fragment processor(s)A-N are optimized to execute fragment shader programs as provided for in the OpenGL API, which may be used to perform similar operations as a pixel shader program as provided for in the Direct 3D API.

1310 1320 1320 1325 1325 1330 1330 1320 1320 1310 1305 1315 1315 1325 1325 1320 1320 1205 1215 1220 1205 1220 1330 1330 1310 12 FIG. Graphics processoradditionally includes one or more memory management units (MMUs)A-B, cache(s)A-B, and circuit interconnect(s)A-B. The one or more MMU(s)A-B provide for virtual to physical address mapping for the graphics processor, including for the vertex processorand/or fragment processor(s)A-N, which may reference vertex or image/texture data stored in memory, in addition to vertex or image/texture data stored in the one or more cache(s)A-B. In one embodiment, the one or more MMU(s)A-B may be synchronized with other MMUs within the system, including one or more MMUs associated with the one or more application processor(s), image processor, and/or video processorof, such that each processor-can participate in a shared or unified virtual memory system. The one or more circuit interconnect(s)A-B enable graphics processorto interface with other IP cores within the SoC, either via an internal bus of the SoC or via a direct connection, according to embodiments.

13 FIG.B 13 FIG.A 1340 1320 1320 1325 1325 1330 1330 1310 1340 1355 1355 1455 1355 1355 1355 1355 1355 1355 1 1355 1340 1345 1355 1355 1358 As shown, graphics processorincludes the one or more MMU(s)A-B, cachesA-B, and circuit interconnectsA-B of the graphics processorof. Graphics processorincludes one or more shader core(s)A-N (e.g.,A,B,C,D,E,F, throughN-, andN), which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and/or compute shaders. The exact number of shader cores present can vary among embodiments and implementations. Additionally, graphics processorincludes an inter-core task manager, which acts as a thread dispatcher to dispatch execution threads to one or more shader coresA-N and a tiling unitto accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches.

14 14 FIGS.A-B 14 FIG.A 12 FIG. 13 FIG.B 14 FIG.B 1400 1210 1355 1355 1430 illustrate additional exemplary graphics processor logic according to embodiments described herein.illustrates a graphics corethat may be included within the graphics processorof, and may be a unified shader coreA-N as in.illustrates an additional general-purpose graphics processing unit, which is a highly-parallel general-purpose graphics processing unit suitable for deployment on a multi-chip module.

14 FIG.A 1400 1402 1418 1420 1400 1400 1401 1401 1400 1401 1401 1404 1404 1406 1406 1408 1408 1410 1440 1401 1401 1412 1412 1414 1414 1416 1416 1413 1413 1415 1415 1417 1417 As shown in, the graphics coreincludes a shared instruction cache, a texture unit, and a cache/shared memorythat are common to the execution resources within the graphics core. The graphics corecan include multiple slicesA-N or partition for each core, and a graphics processor can include multiple instances of the graphics core. The slicesA-N can include support logic including a local instruction cacheA-N, a thread schedulerA-N, a thread dispatcherA-N, and a set of registersA-N. To perform logic operations, the slicesA-N can include a set of additional function units (AFUsA-N), floating-point units (FPUA-N), integer arithmetic logic units (ALUs-N), address computational units (ACUA-N), double-precision floating-point units (DPFPUA-N), and matrix processing units (MPUA-N).

1414 1414 1415 1415 1416 1416 1417 1417 1417 1417 1412 1412 Some of the computational units operate at a specific precision. For example, the FPUsA-N can perform single-precision (32-bit) and half-precision (16-bit) floating point operations, while the DPFPUsA-N perform double precision (64-bit) floating point operations. The ALUsA-N can perform variable precision integer operations at 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed precision operations. The MPUsA-N can also be configured for mixed precision matrix operations, including half-precision floating point and 8-bit integer operations. The MPUs-N can perform a variety of matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix to matrix multiplication (GEMM). The AFUsA-N can perform additional logic operations not supported by the floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

14 FIG.B 1430 1430 1430 1432 1432 1430 1434 1436 1436 1436 1436 1438 1438 1436 1436 As shown in, a general-purpose processing unit (GPGPU)can be configured to enable highly-parallel compute operations to be performed by an array of graphics processing units. Additionally, the GPGPUcan be linked directly to other instances of the GPGPU to create a multi-GPU cluster to improve training speed for particularly deep neural networks. The GPGPUincludes a host interfaceto enable a connection with a host processor. In one embodiment, the host interfaceis a PCI Express interface. However, the host interface can also be a vendor specific communications interface or communications fabric. The GPGPUreceives commands from the host processor and uses a global schedulerto distribute execution threads associated with those commands to a set of compute clustersA-H. The compute clustersA-H share a cache memory. The cache memorycan serve as a higher-level cache for cache memories within the compute clustersA-H.

1430 1444 1444 1436 1436 1442 1442 1444 1444 The GPGPUincludes memoryA-B coupled with the compute clustersA-H via a set of memory controllersA-B. In various embodiments, the memoryA-B can include various types of memory devices including dynamic random-access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

1436 1436 1400 1436 1436 14 FIG.A In one embodiment, the compute clustersA-H each include a set of graphics cores, such as the graphics coreof, which can include multiple types of integer and floating point logic units that can perform computational operations at a range of precisions including suited for machine learning computations. For example, and in one embodiment at least a subset of the floating point units in each of the compute clustersA-H can be configured to perform 16-bit or 32-bit floating point operations, while a different subset of the floating point units can be configured to perform 64-bit floating point operations.

1430 1430 1432 1430 1439 1430 1440 1440 1430 1440 1430 1432 1440 1432 Multiple instances of the GPGPUcan be configured to operate as a compute cluster. The communication mechanism used by the compute cluster for synchronization and data exchange varies across embodiments. In one embodiment, the multiple instances of the GPGPUcommunicate over the host interface. In one embodiment, the GPGPUincludes an I/O hubthat couples the GPGPUwith a GPU linkthat enables a direct connection to other instances of the GPGPU. In one embodiment, the GPU linkis coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of the GPGPU. In one embodiment, the GPU linkcouples with a high-speed interconnect to transmit and receive data to other GPGPUs or parallel processors. In one embodiment, the multiple instances of the GPGPUare located in separate data processing systems and communicate via a network device that is accessible via the host interface. In one embodiment, the GPU linkcan be configured to enable a connection to a host processor in addition to or as an alternative to the host interface.

1430 1430 1430 1436 1436 1434 1434 1430 While the illustrated configuration of the GPGPUcan be configured to train neural networks, one embodiment provides alternate configuration of the GPGPUthat can be configured for deployment within a high performance or low power inferencing platform. In an inferencing configuration, the GPGPUincludes fewer of the compute clustersA-H relative to the training configuration. Additionally, the memory technology associated with the memoryA-B may differ between inferencing and training configurations, with higher bandwidth memory technologies devoted to training configurations. In one embodiment, the inferencing configuration of the GPGPUcan support inferencing specific instructions. For example, an inferencing configuration can provide support for one or more 8-bit integer dot product instructions, which are commonly used during inferencing operations for deployed neural networks.

There is not yet a definition of how the PCC draft standard should define interoperability signaling and conformance points. Embodiments provide for a novel technique for defining interoperability signaling and conformance points, to enable ecosystem specification of PCC products, which allow for flexible video decode and GPU capability.

Conventionally, more immersive forms of interaction and communication are being enabled for three-dimensional (3D) representation of the world to allow for processing devices and machines to better understand and interpret the world, where 3D point clouds are regarded as an enabling representation of such information. For example, a point cloud is regarded as a set of points in a 3D space, where each point is associated attributes, such as properties, colors, etc. Point clouds may be used to reconstruct a scene or an object as a composition of these points, where such points are captured using multiple camera and depth sensors in various setups and having made up of from thousands to billions of points to realistically represent reconstructed scenes. Similarly, geometry may refer to locations in 3D space of points in a point cloud, such as (x, y, z) coordinates of the points, while attribute may refer to a value or a set of values, other than geometry, associated with a point, such as RGB color values, where I reflects reflectance. Spatial random access refers to decoding a point cloud corresponding to a pre-defined region from a compressed point cloud, while progressive/scalable refers to first decode of a coarse point cloud and then refining it with additional data from a compressed bit stream. An operating point may refer to a performance point of a particular codec for a particular data at a target bit rate or compression ratio. Further, 1 Mbit/s means 1,000,000 bits per second.

There are a number of conventional technologies associated with point clouds, such as compression technologies to reduce the amount of data needed to represent a point cloud for lossy compression of point clouds for use in real-time communications and six degrees of freedom (6DoF) virtual reality, etc. For example, standards can address compression of geometry and attributes, such as colors and reflectance, coding of sequences of point clouds, random access to subsets of point clouds, etc. Similarly, standards are needed to address other areas associated with point clouds, such as, in one embodiment, defining interoperability signaling and conformance points to enable ecosystem specification of PCC products that allow for flexible video decode and GPU capability.

It is contemplated that a point cloud may be defined as a set of (x, y, z) coordinates, where x, y, and z have a finite precision and dynamic range, where each (x, y, z) has multiple attributes (color, properties, reflectance, etc.) associated with it (such as a1, a2, a3, . . .), where each point has the same number of attributes associated with it as the other points. An attribute refers to a value or set of values, other than geometry, associated with a point, such as red green blue (RGB) color values and I for reflectance. Further, for example, geometry may refer to locations in 3D space of points in a point cloud, such as (x, y, z) coordinates of the points. A point cloud frame may refer to a given time instant or a time range, such as for a dynamically acquired point clouds. In some implementations, six projection angles are used in the PCC standard test model, with the projection angles corresponding to angles pointing to the centers of six faces of a rectangular solid that bound the object represented by the point cloud data. While six projection angles are described, other number of angles could possibly be used in different implementations.

Video codecs, such as advanced video coding (AVC) and high efficiency video coding (HEVC), have profiles and levels to define interoperability points. Each coded video sequence contains profile and level indicator syntax elements in the sequence parameter set, where a profile indicates a set of tools needed to decode the coded video bitstream, while a level indicates a performance level needed to decode the coded video bitstream, such as in terms of maximum picture size and pixel rate. For example, an output of the video decoder is considered a conformance point, which means that video decoders which conform to a particular profile and level are needed to output pictures that match a specified decoder.

Further, the PCC draft standard uses multiple projections of point clouds onto planes for texture and depth. For example, any projected texture images are combined into a single texture image, while any projected depth images are combined into a single depth image, which are then encoded using a normal two-dimensional (2D) video codec, such as HEVC, along with some metadata.

Any existing video codec interoperability point definitions do not apply directly to PCC coding, where it is expected that different GPUs would likely use different algorithms for converting any decoded PCC pictures to points, so different implementations may yield different numbers of points in the point cloud when decoding the same compressed PCC bitstream. It would be useful to allow variation in performance, but in such a way that client quality capability can be expressed.

In the PCC standard, in one embodiment, a conformance point is defined as a video decoder output, as is done in typical video codecs, such as including in the standard description of a reference point cloud reconstructor. Further, in one embodiment, a syntax element is added with an encoder in a high-level syntax to indicate, for each coded picture, a number of points created by the reference point cloud reconstructor. The added syntax element can be used by a decoder to determine if it is able to decode a bitstream and reconstruct the point cloud when the decoder has limited reconstruction capability. In one embodiment, any client point cloud reconstructor levels are defined relative to the reference point cloud reconstructor.

Embodiments provide for a novel technique for offering the ecosystem with a way to specify quality and performance levels of PCC products, while allowing decoupling of video decode capability and point cloud reconstructing capability. Embodiments would allow for adoption of this novel technique to the PCC standard and being used in all implementations of the standard.

In the PCC standard, in one embodiment, the normal HEVC profile and level signaling are used, while the conformance point is defined in the normal way as the output of the video decoder. For example, that decoded picture output is not in a form that is to be viewed directly by viewers. Further, in one embodiment, a specification of a reference point cloud reconstructor is included in the PCC standard (such as in an informative section) that describes how to convert the decoded PCC bitstreams (including texture and depth decoded images and metadata) into points in a point cloud.

Further, in one embodiment, somewhere in High Level Syntax (Supplemental Enhancement Information message, parameters set, picture header, etc.) of the PCC bitstream, there may be included a syntax element to indicate how many points that the reference point cloud reconstructor may create for the coded picture, such as number of points, or for the coded sequence, etc., where, for example, a fixed length code syntax element may be used for the number of points.

Furthermore, in one embodiment, client reconstructor levels may be defined in the PCC standard specification, where the client reconstructor levels may be used to specify the capability of the decoder/client relative to the reference point cloud reconstructor. The capability may be defined using a number of points created by the client reconstructor, such as a percentage of the reference reconstructor's num_points, and point geometry distortion metrics of the client generated point cloud.

The same geometric distortion metrics may be utilized as they are used in the PCC development effort for assessing the quality and accuracy of the decoded point cloud versus that of the source point cloud; but instead, using the reference reconstructor's points as the basis for that comparison. For example, the PCC Call for Proposals document (N16763) defines two geometric distortion metrics, such as D1 and D2, where D1 represents point-to-point distances, and D2 represents point-to-plane distances.

In one embodiment, the following may be regarded as a client reconstruct level definition: client reconstruct level 1 is able to create 100% of num_points, at matching positions; client reconstruct level 2 can create at least 75% of num_points with a D1>X and D2>Y; and client reconstruct level 3 can create at least 50% of num_points with a D1>U and D2>V.

A third-party group, such as an ultra-high definition (UHD) Alliance, may be given the responsibility to specify minimum performance capabilities, such as for certification, either using the client reconstruct level or a ratio of points to the reference reconstructor and the geometric distortion metrics.

15 FIG.A 1502 1504 1506 1506 1507 1508 illustrates multiple forms of immersive video. Immersive video can be presented in multiple forms depending on the degrees of freedom available to a viewer. Degrees of freedom refers to the number of different directions that an object can move in 3D space. Immersive video can be viewed via a head mounted display that includes tracking for position and orientation. Example forms of immersive video include 3DoF, 3DoF Plus, and full 6DoF. In addition to immersive video in full 6DoF, 6DoF immersive video includes omni-directional 6DoF, and windowed 6DoF.

1502 1504 1506 For video in 3DoF(e.g., 360-degree video), a viewer can change orientation (e.g., yaw, pitch, roll) but not position. For video in 3DoF Plus, a viewer can change orientation and make small changes to position. For video in 6DoF, a viewer can change orientation and change position. More limited forms of 6DoF video are also available.

1507 1508 Video in omni-directional 6DoFenables a viewer being able to take multiple steps in the virtual scene. Video in windowed 6DoFallows a viewer to change orientation and position, but the viewers is constrained to a limited view area. Increasing the available degrees of freedom in an immersive video generally includes increasing the amount and complexity of data involved in video generation, encode, decode, and playback.

15 FIG.B 1510 1512 1514 1512 1514 1512 illustrates image projection and texture planes for immersive video. A 3D viewof video content can be generated using data from multiple cameras. Multiple projection planescan be used to generate geometry data for video content. Multiple texture planescan be derived for the projection planesused to generate the geometry data. The texture planescan be applied to 3D models that are pre-generated or generated based on a point cloud derived from video data. The multiple projection planescan be used to generate multiple 2D projections, each projection associated with a projection plane.

16 FIG. 1620 1630 1630 1620 1601 1602 1604 1605 1606 1606 1603 1605 1606 1607 1608 1620 1630 1609 1610 1630 1609 1611 1613 1612 1614 1616 1630 illustrates a client-server system by which immersive video content can be generated and encoded by a serverinfrastructure for transmission to one or more clientdevices. The clientdevices can then decompress and render the immersive video content. In one embodiment, one or more serverdevices can include inputs from one or more optical camerashaving depth sensors. Parallel compute resourcescan decompose the video and depth data into point cloudsand/or texture triangles. Data to generate textured trianglescan also be provided by pre-generated 3D modelsof a scene. The point cloudsand/or textured trianglescan be compressed for transmission to one or more client devices, which can locally render the content. In one embodiment, a variety of compression units,, using a variety of compression algorithms, can compress generated content for transmission over a delivery medium from the serverto one or more clientdevices. Decompression circuitry,on the clientdevices can decompress and decode incoming bitstreams into video/texture and geometry data. For example, decompression circuitrycan decode compressed point cloud data and provide the decompressed point cloud data to a viewpoint interpolation circuitry. The interpolated viewpoint data can be used to generate bitmap data. The decompressed point cloud data can be provided to a geometry reconstruction circuitryto reconstruct geometry data for a scene. The reconstructed geometry data can be textured by decoded texture data (textured triangles) to generate a 3D renderingfor viewing by the client.

17 17 FIGS.A-B 16 FIG. 1700 1700 1620 illustrate a systemfor encoding and decoding 3DoF Plus content. The systemcan be implemented by hardware and software of a serverinfrastructure, for example, as in.

17 FIG.A 1702 1701 1705 1705 1704 1706 1707 1708 1708 1709 1702 1701 1703 1703 1709 1703 As shown in, multiple cameras can be used to capture video datafor a base viewand video dataA-C for additional views. Each camera can provide video data and depth data, where each frame of video data can be converted into a texture. A set of reprojectionand occlusion detectioncircuitry can operate on received video data and output processed data to patch formationcircuitry. Patches formed by the patch formationcircuitry can be provided to a patch packingcircuitry. Video datafor the base viewcan be encoded, for example, via a high efficiency video coding (HEVC) encoderA. A variant of the HEVC encoderA can also be used to encode patch video data output from the patch packingcircuitry. Metadata to reconstruct video from the encoded patches can be encoded by a metadata encodeB circuitry. Multiple encoded video and metadata streams can then be transmitted to a client device for viewing. At least one encoded video and metadata stream may include at least one added syntax element that has been added by an encoder. As discussed above, the added syntax element can be used by a decoder to determine if it is able to decode a bitstream and reconstruct the point cloud when the decoder has limited reconstruction capability.

17 FIG.B 16 FIG. 1713 1713 1719 1712 1714 1715 1701 1704 1718 1630 1712 1715 1715 1714 1711 1716 1714 1711 As shown in, multiple streams of video data can be received, decoded, and reconstructed into immersive video. The multiple streams of video include a stream for the base video, along with a stream containing packed data for the additional views. Encoded metadata is also received. The multiple video streams can be decoded, in one embodiment, via an HEVCA decoder. Metadata can be decoded via a metadataB decoder. The decoded metadata is then used to unpack the decoded additional views via patch un-packinglogic. Decoded texture and depth data (video 0, video 1-3A-C) of the base viewand the additional viewsare reconstructed by view generation logicon the client (e.g., clientas in). The decoded video,A-C can be provided as texture and depth data to an intermediate view rendererthat can be used to render intermediate views for a head mounted display. Head mounted display position informationis provided as feedback to the intermediate view renderer, which can render updated views for the displayed viewport presented via the head mounted display.

18 18 FIGS.A-B 18 FIG.A 18 FIG.B 1800 1820 illustrate a system for encoding and decoding 6DoF content using textured geometry data.shows a 6DoF textured geometry encoding system.shows a 6DoF textured geometry decoding system. 6DoF textured geometry encoding and decoding can be used to enable a variant of 6DoF immersive video in which video data is applied as a texture to geometry data, allowing new intermediate views to be rendered based on the position and orientation of a head mounted display. Data recorded by multiple video cameras can be combined with 3D models, particularly for static objects.

18 FIG.A 1800 1802 1805 1805 1802 1805 1805 1806 1806 1807 1808 1807 1809 1813 1809 1808 1810 1811 1812 As shown in, a 6DoF textured geometry encoding systemcan receive video datafor a base view and video dataA-C for additional views. The video data,A-C includes texture and depth data that can be processed by a reprojection and occlusion detection circuitry. Output from the reprojection and occlusion detection circuitrycan be provided to a patch decomposition circuitryand a geometry image generator. Output from the patch decomposition circuitryis provided to a patch packing circuitryand an auxiliary patch information compressor. The auxiliary patch information (patch-info) provides information used to reconstruct patches of video texture and depth data. The patch packing circuitryoutputs packed patch data to the geometry image generator, a texture image generator, an attribute image generator, and an occupancy map compressor.

1808 1810 1811 1814 1808 1806 1807 1809 1810 1809 1806 1811 1806 1809 The geometry image generator, texture image generator, and attribute image generatoroutput data to a video compressor. The geometry image generatorcan receive input from the reprojection and occlusion detection circuitry, patch decomposition circuitry, and patch packing circuitryand generates geometry image data. The texture image generatorcan receive packed patch data from the patch packing circuitryand video texture and depth data from the reprojection and occlusion detection circuitry. The attribute image generatorgenerates an attribute image from video texture and depth data received from the reprojection and occlusion detection circuitryand patched patch data received from the patch packing circuitry.

1812 1809 1813 1816 1815 1814 1814 1816 An occupancy map can be generated by an occupancy map compressorbased on packed patch data output from the patch packing circuitry. Auxiliary patch information can be generated by the auxiliary patch information compressor. Compressed occupancy map and auxiliary patch information data can be multiplexed into a compressed bitstreamby a multiplexeralong with compressed and/or encoded video data output from the video compressor. The compressed video data output from the video compressorincludes compressed geometry image data, texture image data, and attribute image data. The compressed bitstreamcan be stored or provided to a client device for decompression and viewing.

18 FIG.B 18 FIG.A 18 FIG.A 1820 1800 1816 1835 1816 1802 1820 1834 1834 1832 1834 1834 1832 1829 1809 1833 1826 1822 1825 1825 1826 1823 1824 1824 As shown in, a 6DoF textured geometry decoding systemcan be used to decode 6DoF content generated using the encoding systemof. The compressed bitstreamis received and demultiplexed by a demultiplexerinto multiple video decode streams, an occupancy map, and auxiliary patch information. In another example, the bitstreamis received by an optional network elementthat determines whether the client is capable of decoding and reconstructing a point cloud. If not, then no decoding occurs by the decoding system. The multiple video streams are decoded/decompressed by video decodersA-B. Occupancy map data is decoded/decompressed by an occupancy map decoder. The decoded video data and occupancy map data are output by the video decodersA-B and the occupancy map decoderto an unpacking circuitry. The unpacking circuitry unpacks video patch data that is packed by the patch packing circuitryof. Auxiliary patch information from the auxiliary patch-info decoderis provided to an occlusion filling circuitry, which can be used to fill in patches from occluded portions of an object that may be missing from a particular view of the video data. Respective video streams,A-C having texture and depth data are output from the occlusion filling circuitryand provided to an intermediate view renderer, which can render a view for display on a head mounted displaybased on position and orientation information provided by the head mounted display.

19 19 FIGS.A-B 19 FIG.A 19 FIG.B 1900 1920 illustrate a system for encoding and decoding 6DoF content via point cloud data.illustrates a 6DoF point cloud encoding system.illustrates a 6DoF point cloud decoding system.

19 FIG.A 18 FIG.A 18 FIG.A 1906 1907 1909 1908 1910 1911 1912 1913 1806 1807 1914 1914 1915 1916 As shown in, an input frame of point cloud data can be decomposed into patch data. The point cloud data and decomposed patch data can be encoded in a similar manner as video texture and depth data in. Input data including a point cloud framecan be provided to a patch decomposition circuitry. The input point cloud data and decomposed patches thereof can be processed by a packing circuitry, geometry image generator, texture image generator, attribute image generator, occupancy map compressor, and auxiliary patch information compressorusing techniques similar to the processing of texture depth and video data output by the reprojection and occlusion detection circuitryand patch decomposition circuitryof. A video compressorcan encode and/or compress geometry image, texture image, and attribute image data. The compressed and/or encoded video data from the video compressorcan be multiplexed by a multiplexerwith occupancy map and auxiliary patch information data into a compressed bitstream, which can be stored or transmitted for display.

1900 1920 1916 1934 1932 1933 19 FIG.A 19 FIG.B 19 FIG.B The compressed bitstream output by the systemofcan be decoded by the point cloud decoding systemshown in. As shown in, a compressed bitstreamcan be demultiplexed into multiple encoded/compressed video streams, occupancy map data, and auxiliary patch information. The video streams can be decoded/decompressed by a multi-stream video decoder, which can output texture and geometry data. Occupancy map and auxiliary patch information can be decompressed/decoded by an occupancy map decoderand an auxiliary patch information decoder.

1900 1936 1934 1932 1933 1937 1934 1938 1938 1939 1926 1900 19 FIG.A 19 FIG.A Geometry reconstruction, smoothing, and texture reconstruction can then be performed to reconstruct the point cloud data provided to the 6DoF point cloud encoding systemof. A geometry reconstruction circuitrycan reconstruct geometry information based on geometry data decoded from a video stream of the multi-stream video decoder, as well as output of the occupancy map decoderand auxiliary patch information decoder. Reconstructed geometry data can be smoothed by a smoothing circuitry. Smoothed geometry and texture image data decoded from a video stream output by the multi-stream video decoderis provided to a texture reconstruction circuitry. The texture reconstruction circuitrycan output a reconstructed point cloud, which is a variant of the input point cloud frameprovided to the 6DoF point cloud encoding systemof.

20 FIG. 1 FIG. 1 19 FIGS.-B 2000 2010 2000 100 2010 2010 illustrates a computing devicehosting PCC standard definition mechanism (“definition mechanism”)according to one embodiment. Computing devicerepresents a communication and data processing device including (but not limited to) smart wearable devices, smartphones, virtual reality (VR) devices, head-mounted display (HMDs), mobile computers, Internet of Things (IoT) devices, laptop computers, desktop computers, server computers, etc., and be similar to or the same as processing deviceof; accordingly, for brevity, clarity, and ease of understanding, many of the details stated above with reference toare not further discussed or repeated hereafter. In one embodiment, definition mechanismprovides for defining interoperability signaling and conformance points for the PCC standard. For example, defining mechanismmay include one or more components to define interoperability signaling and conformance points to enable the ecosystem specification of PCC products to allow for flexible video decode and GPU capability, as described earlier in this document.

2000 Computing devicemay further include (without limitations) an autonomous machine or an artificially intelligent agent, such as a mechanical agent or machine, an electronics agent or machine, a virtual agent or machine, an electro-mechanical agent or machine, etc. Examples of autonomous machines or artificially intelligent agents may include (without limitation) robots, autonomous vehicles (e.g., self-driving cars, self-flying planes, self-sailing boats, etc.), autonomous equipment (self-operating construction vehicles, self-operating medical equipment, etc.), and/or the like. Throughout this document, “computing device” may be interchangeably referred to as “autonomous machine” or “artificially intelligent agent” or simply “robot”.

It contemplated that although “autonomous vehicle” and “autonomous driving” are referenced throughout this document, embodiments are not limited as such. For example, “autonomous vehicle” is not limited to an automobile but that it may include any number and type of autonomous machines, such as robots, autonomous equipment, household autonomous devices, and/or the like, and any one or more tasks or operations relating to such autonomous machines may be interchangeably referenced with autonomous driving.

2000 2000 2100 2000 Computing devicemay further include (without limitations) large computing systems, such as server computers, desktop computers, etc., and may further include set-top boxes (e.g., Internet-based cable television set-top boxes, etc.), global positioning system (GPS)-based devices, etc. Computing devicemay include mobile computing devices serving as communication devices, such as cellular phones including smartphones, personal digital assistants (PDAs), tablet computers, laptop computers, e-readers, smart televisions, television platforms, wearable devices (e.g., glasses, watches, bracelets, smartcards, jewelry, clothing items, etc.), media players, etc. For example, in one embodiment, computing devicemay include a mobile computing device employing a computer platform hosting an integrated circuit (“IC”), such as system on a chip (“SoC” or “SOC”), integrating various hardware and/or software components of computing deviceon a single chip.

2000 2020 2014 2016 2012 2008 2004 2000 2006 2000 2014 2014 2012 2012 102 1 FIG. As illustrated, in one embodiment, computing devicemay include any number and type of hardware and/or software components, such as (without limitation) parser(e.g., syntax element parser), graphics processing unit (“GPU” or simply “graphics processor”), graphics driver (also referred to as “GPU driver”, “graphics driver logic”, “driver logic”, user-mode driver (UMD), UMD, user-mode driver framework (UMDF), UMDF, or simply “driver”), central processing unit (“CPU” or simply “application processor”), memory, network devices, drivers, or the like, as well as input/output (I/O) sources, such as touchscreens, touch panels, touch pads, virtual or regular keyboards, virtual or regular mice, ports, connectors, etc. Computing devicemay include operating system (OS)serving as an interface between hardware and/or physical resources of the computer deviceand a user. It is contemplated that graphics processing unit(or graphics processor) and CPU(or application processor) may be one or more of processor(s)of.

2000 It is to be appreciated that a lesser or more equipped system than the example described above may be preferred for certain implementations. Therefore, the configuration of computing devicemay vary from implementation to implementation depending upon numerous factors, such as price constraints, performance requirements, technological improvements, or other circumstances.

Embodiments may be implemented as any or a combination of: one or more microchips or integrated circuits interconnected using a parentboard, hardwired logic, software stored by a memory device and executed by a microprocessor, firmware, an application specific integrated circuit (ASIC), and/or a field programmable gate array (FPGA). The terms “logic”, “module”, “component”, “engine”, “mechanism”, “tool”, “circuit”, and “circuitry” are referenced interchangeably throughout this document and include, by way of example, software, hardware, firmware, or any combination thereof.

2010 2008 2000 2010 2006 2016 2010 2014 2014 2010 2014 2010 2012 2010 2012 2020 2010 2006 In one embodiment, as illustrated, definition mechanismmay be hosted by memoryof computing device. In another embodiment, definition mechanismmay be hosted by operating systemor graphics driver. In yet another embodiment, definition mechanismmay be hosted by or part of graphics processing unit (“GPU” or simply graphics processor”)or firmware of graphics processor. For example, definition mechanismmay be embedded in or implemented as part of the processing hardware of graphics processor. Similarly, in yet another embodiment, definition mechanismmay be hosted by or part of central processing unit (“CPU” or simply “application processor”). For example, definition mechanismmay be embedded in or implemented as part of the processing hardware of application processor. The parsermay be hosted by or part of any number or type of components of computing device, such as definition mechanismor OS.

2010 2000 2010 2006 2014 2012 2010 2006 2000 2010 2010 In yet another embodiment, definition mechanismmay be hosted by or part of any number and type of components of computing device, such as a portion of definition mechanismmay be hosted by or part of operating system, another portion may be hosted by or part of graphics processor, another portion may be hosted by or part of application processor, while one or more portions of definition mechanismmay be hosted by or part of operating systemand/or any number and type of devices of computing device. It is contemplated that embodiments are not limited to any implementation or hosting of definition mechanismand that one or more portions or components of definition mechanismmay be employed or implemented as hardware, software, or any combination thereof, such as firmware.

2000 rd th Computing devicemay host network interface(s) to provide access to a network, such as a LAN, a wide area network (WAN), a metropolitan area network (MAN), a personal area network (PAN), Bluetooth, a cloud network, a mobile network (e.g., 3Generation (3G), 4Generation (4G), etc.), an intranet, the Internet, etc. Network interface(s) may include, for example, a wireless network interface having antenna, which may represent one or more antenna(e). Network interface(s) may also include, for example, a wired network interface to communicate with remote devices via network cable, which may be, for example, an Ethernet cable, a coaxial cable, a fiber optic cable, a serial cable, or a parallel cable.

21 FIG. 20 FIG. 2100 2010 2010 2000 illustrates a computer implemented methodhaving an exemplary sequence of operations for a PCC standard definition mechanism in accordance with one embodiment. The PCC standard definition mechanism (e.g., mechanism) can be implemented in a computing device as illustrated in. As discussed above, definition mechanismmay be hosted by or part of any number and type of components of computing device.

2102 2100 2104 2106 2020 2108 At operation, the methodincludes decoding a compressed bitstream of patch video data representing a point cloud. At operation, the method includes reconstructing, with point cloud reconstructor circuitry, a point cloud from the decoded patch video data. At operation, the method includes receiving, with a syntax element parser (e.g.,), at least one syntax element representing interoperability signaling in the compressed bitstream to indicate the number of points in one or more pictures of the patch video data. At operation, the method includes determining, with processing hardware, if the number of points in the one or more pictures of the compressed bitstream is within the conformance limits of the point cloud reconstructor circuitry.

The at least one syntax element may be included in a High Level Syntax including a Supplemental Enhancement Information message, parameters set, or picture header of the PCC bitstream. The at least one syntax element may indicate a performance level needed to decode the compressed PCC bitstream with the performance level including a maximum picture size and pixel rate.

Embodiments may be provided, for example, as a computer program product which may include one or more machine-readable media having stored thereon machine-executable instructions that, when executed by one or more machines such as a computer, network of computers, or other electronic devices, may result in the one or more machines carrying out operations in accordance with embodiments described herein. A machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs (Compact Disc-Read Only Memories), and magneto-optical disks, ROMs, RAMs, EPROMs (Erasable Programmable Read Only Memories), EEPROMs (Electrically Erasable Programmable Read Only Memories), magnetic or optical cards, flash memory, or other type of media/machine-readable medium suitable for storing machine-executable instructions.

Moreover, embodiments may be downloaded as a computer program product, wherein the program may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of one or more data signals embodied in and/or modulated by a carrier wave or other propagation medium via a communication link (e.g., a modem and/or network connection).

Throughout the document, term “user” may be interchangeably referred to as “viewer”, “observer”, “person”, “individual”, “end-user”, and/or the like. It is to be noted that throughout this document, terms like “graphics domain” may be referenced interchangeably with “graphics processing unit”, “graphics processor”, or simply “GPU” and similarly, “CPU domain” or “host domain” may be referenced interchangeably with “computer processing unit”, “application processor”, or simply “CPU”.

It is to be noted that terms like “node”, “computing node”, “server”, “server device”, “cloud computer”, “cloud server”, “cloud server computer”, “machine”, “host machine”, “device”, “computing device”, “computer”, “computing system”, and the like, may be used interchangeably throughout this document. It is to be further noted that terms like “application”, “software application”, “program”, “software program”, “package”, “software package”, and the like, may be used interchangeably throughout this document. Also, terms like “job”, “input”, “request”, “message”, and the like, may be used interchangeably throughout this document.

Some embodiments pertain to Example 1 that includes a computing device comprising a decoder to decode a compressed bitstream of patch video data representing a point cloud, point cloud reconstructor circuitry to reconstruct a point cloud from the decoded patch video data, a syntax element parser to receive at least one syntax element representing interoperability signaling in the compressed bitstream to indicate the number of points in one or more pictures of the patch video data, and processing hardware to determine if the number of points in the one or more pictures of the compressed bitstream is within the conformance limits of the point cloud reconstructor circuitry.

Example 2 includes the subject matter of Example 1, wherein the at least one syntax element to indicate a reconstruction level that indicates for each coded picture a number of points to be created by the point cloud reconstructor circuitry.

Example 3 includes the subject matter of any of Examples 1-2, wherein the decoder comprises at least one video decoder to decode video data and a metadata decoder to decode metadata.

Example 4 includes the subject matter of any of Examples 1-3, wherein the video decode capability of the decoder is decoupled from point cloud reconstructing capability of the point cloud reconstructor circuitry.

Example 5 includes the subject matter of any of Examples 1-4, wherein the at least one syntax element is included in a High Level Syntax including a Supplemental Enhancement Information message, parameters set, or picture header of the bitstream.

Example 6 includes the subject matter of any of Examples 1-5, wherein the at least one syntax element to indicate a performance level needed to decode the compressed bitstream with the performance level including a maximum picture size and pixel rate.

Example 7 includes the subject matter of any of Examples 1-6, wherein the processing hardware comprises a graphics processor co-located and in communication with an application processor.

Example 8 includes the subject matter of any of Examples 1-7, wherein the application processor or a network element to determine if the compressed bitstream is decodable based on the at least one syntax element.

Some embodiments pertain to Example 9 that includes a computer implemented method comprising decoding a compressed bitstream of patch video data representing a point cloud, reconstructing, with point cloud reconstructor circuitry, a point cloud from the decoded patch video data, receiving at least one syntax element representing interoperability signaling in the compressed bitstream to indicate the number of points in one or more pictures of the patch video data, and determining, with processing hardware, if the number of points in the one or more pictures of the compressed bitstream is within the conformance limits of the point cloud reconstructor circuitry.

Example 10 includes the subject matter of Example 9, wherein the at least one syntax element to indicate a reconstruction level that indicates for each coded picture a number of points to be created by the point cloud reconstructor circuitry.

Example 11 includes the subject matter of any of Examples 9-10, wherein the profile level comprises a client reconstruct level definition with client reconstruct level 1 being able to create 100% of points, at matching positions; client reconstruct level 2 being able to create at least 75% of points; and client reconstruct level 3 being able to create at least 50% of points.

Example 12 includes the subject matter of any of Examples 9-11, further comprising decompressing the compressed bitstream.

Example 13 includes the subject matter of any of Examples 9-12, wherein a decode capability of a decoder and a point cloud reconstructing capability of the point cloud reconstructor circuitry are decoupled with the at least one syntax element indicating a first level for video decode capability and a second level for point cloud reconstructing capability.

Example 14 includes the subject matter of any of Examples 9-13, wherein the at least one syntax element is included in a High Level Syntax including a Supplemental Enhancement Information message, parameters set, or picture header of the bitstream.

Example 15 includes the subject matter of any of Examples 9-14, wherein the at least one syntax element to indicate a performance level needed to decode the compressed bitstream with the performance level including a maximum picture size and pixel rate.

Example 16 includes the subject matter of any of Examples 9-12, wherein at least one operation of the method is performed by the processing hardware comprising a graphics processor co-located and in communication with an application processor.

Some embodiments pertain to Example 17 that includes a server device comprising compute resources to process video data representing a point cloud and an encoder to add at least one syntax element representing interoperability signaling in a bitstream of the video data to indicate a number of points in one or more pictures of the video data.

Example 18 includes the subject matter of Example 17, wherein the at least one syntax element to indicate a performance level needed to decode the bitstream.

Example 19 includes the subject matter of any of Examples 17-18, wherein the encoder to encode video data and to encode metadata for multiple encoded video and metadata streams to be transmitted to a client device for viewing.

Example 20 includes the subject matter of any of Examples 17-19, wherein the at least one syntax element is included in a High Level Syntax including a Supplemental Enhancement Information message, parameters set, or picture header of the bitstream.

The drawings and the forgoing description give examples of embodiments. Those skilled in the art will appreciate that one or more of the described elements may well be combined into a single functional element. Alternatively, certain elements may be split into multiple functional elements. Elements from one embodiment may be added to another embodiment. For example, orders of processes described herein may be changed and are not limited to the manner described herein. Moreover, the actions of any flow diagram need not be implemented in the order shown; nor do all of the acts necessarily need to be performed. Also, those acts that are not dependent on other acts may be performed in parallel with the other acts. The scope of embodiments is by no means limited by these specific examples. Numerous variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material, are possible. The scope of embodiments is at least as broad as given by the following claims.