Semiconductor Device and Method for Forming the Same

This application claims priority of Taiwan Patent Application No. 113125481 filed on Jul. 8, 2024, and entitled “SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME”, the entirety of which is incorporated by reference herein.

The invention relates to semiconductor technology, and in particular to a semiconductor device that is capable of reducing junction leakage, and a method of forming the same.

As electronic products and semiconductor devices are scaled down, the manufacturing of semiconductor devices faces some challenges.

For example, in a semiconductor device, the contact plugs of the word lines in the memory array area and the gate contact plugs of the peripheral area are processed in the same process. The fabrication of contact plugs typically involves etching contact openings and filling the contact openings with a conductive material. However, when contact openings are etched in the memory array area and the peripheral area, in order to expose the upper surfaces of the word lines embedded in the substrate, over-etching is likely to occur in the peripheral area.

As a result, the over-etched contact opening extends too deep into the silicon substrate, which easily causes junction leakage when the devices in the peripheral area are in operation. Therefore, the reliability of the semiconductor device may decrease.

Embodiments of the present invention provide a semiconductor device and a forming method thereof, which can improve the junction leakage of the semiconductor device.

In some embodiments, a semiconductor device is provided. The semiconductor device includes a substrate and a gate line structure formed in the substrate. The gate line structure includes a first conductive layer that has a first portion and a second portion extending in a vertical direction from the upper surface of the first portion, so that a step height is formed between the upper surface of the first portion and the upper surface of the second portion. The gate line structure also includes a first insulating capping layer that covers the upper surface of the first portion and the upper surface of the second portion. The semiconductor device also includes a conductive plug extending in a vertical direction from the inside of the second portion of the first conductive layer and passing through the first insulating capping layer to protrude above the substrate.

In some embodiments, a method of forming a semiconductor device is provided. The method includes providing a substrate, forming a gate opening in the substrate, and forming a first conductive layer that fills the gate opening. The first conductive layer has a recess, the width of the recess is smaller than the width of the gate opening. The first conductive layer includes: a first portion and a second portion extending upward from the upper surface of the first portion along a sidewall of the gate opening, so that a first step height is formed between the upper surface of the first portion and the upper surface of the second portion. In addition, the method includes forming a first insulating capping layer that covers the upper surface of the first portion and the upper surface of the second portion and forming a conductive plug that passes through the first insulating capping layer and extends into the second portion of the first conductive layer.

In some embodiments, a semiconductor device is provided. The semiconductor device includes: a substrate, an isolation structure formed in the substrate, and a word line structure formed in the substrate and partially laterally extending in the isolation structure. The word line structure includes a stepped conductive layer having a first upper surface and a second upper surface lower than the first upper surface, and an insulating capping layer covering the first upper surface and the second upper surface.

1 FIG.A 100 100 100 102 102 102 100 102 102 102 a b a b In some embodiments, a semiconductor device can be implemented as a buried gate line structure and used in a semiconductor word line structure. Referring to, a substrateis provided. The substratemay be a silicon substrate, a silicon-on-insulator (SOI) substrate, or another suitable substrate. The substratemay be doped with P-type or N-type dopants or may be undoped. Afterwards, isolation structures,andof different sizes can be formed in the substrateto serve as electrical isolation layers. For example, the isolation structures,, andmay be referred to as shallow trench isolation structures. The shallow trench isolation structure may include one or more insulating liners that surround the insulating filling layer or may be formed of the insulating filling layer only. For example, the insulating liner and/or the insulating filling layer may include a silicon oxide, a silicon nitride, a silicon oxynitride, a silicon oxycarbide, or the like or combinations thereof. Furthermore, the insulating liner and/or the insulating filling layer may be formed using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or another suitable deposition processes.

104 100 102 104 104 100 Afterwards, an insulating layer, such as a silicon oxide, is formed on the substrateand the isolation structure. The insulating layermay be formed using a CVD process, an ALD process, a thermal oxidation method, or another suitable deposition processes. In some embodiments, the insulating layermay serve as a gate dielectric layer in a gate structure (not shown) that is formed on the substrate.

100 103 100 102 103 100 Next, the substrateis patterned to form gate openingsin the substrateand a portion of the isolation structurefor subsequent formation of a gate structure in each gate opening. The patterning of the substratecan be performed using lithography and etching processes (e.g., dry or wet etching processes).

103 108 101 100 103 108 108 107 103 108 107 107 After the gate openingsare formed, a first conductive layeris formed on the upper surfaceof the substrateand fills the gate openings. The first conductive layermay include a metal material (e.g., copper, aluminum, tungsten, titanium, tantalum, the like or alloys thereof) or another suitable conductive material. The first conductive layermay be formed using a CVD process, an ALD process, a physical vapor deposition (PVD) process, or another suitable deposition processes. In some embodiments, a barrier layer, such as titanium nitride, tantalum nitride, tungsten nitride or the like, is conformally formed on the bottom and sidewalls of the gate openingprior to the formation of the first conductive layer. For example, the barrier layeris made of titanium nitride and can be formed using an ALD process. The barrier layercan also be used as an adhesive layer to increase the adhesion between the underlying structure and the conductive layer subsequently formed thereon.

1 FIG.B 1 FIG.A 111 108 103 110 108 110 111 111 103 111 103 111 103 108 111 104 111 101 100 Referring to, a recessis formed in the first conductive layerlocated in the gate opening. A masking layer, such as a photoresist layer, may be formed over the structure shown in. Afterwards, the masking layer is patterned using, for example, photolithography and etching processes to form a patterned masking layer. Afterwards, for example, an etching process is employed to remove the first conductive layerexposed by the patterned masking layer, so as to form the recess. In some embodiments, the width of the recessis smaller than the width of the corresponding gate opening, so that the sidewalls of the recessdo not laterally exceed the sidewalls of the corresponding gate opening. Furthermore, the distance between the sidewall of the recessand the corresponding sidewall of the gate openingwill be greater than the bottom width of the conductive plug that is subsequently formed on the first conductive layer. In some embodiments, the lower surface of recessis located above the upper surface of insulating layer. In some other embodiments, the lower surface of the recessis also aligned with or lower than the upper surfaceof the substrate.

1 FIG.C 108 111 110 108 111 108 103 108 107 103 108 103 102 102 109 108 108 108 111 108 b b Referring to, the first conductive layerhaving the recessis etched back. In some embodiments, the patterned masking layeris removed to expose the first conductive layerhaving the recess. Afterwards, an etching process can be used to completely remove the first conductive layeroutside the gate opening, and simultaneously remove portions of the first conductive layerand the barrier layerin the gate opening. As a result, the first conductive layerremaining in the gate openingexposes a portion of the sidewall of the isolation structure. That is, a portion of the isolation structureprotrudes from the upper surfaceof the second portionof the first conductive layer. Furthermore, since the first conductive layerhas the recessbefore the etching back is performed, the remaining first conductive layerhas a stepped profile after the etching back.

108 103 108 108 108 103 108 109 108 103 1 109 108 109 108 2 108 101 100 108 1 2 108 108 108 102 a b a b a a a a b b b a b More specifically, the first conductive layerremaining in the gate openingincludes a first portionand a second portion. The first portionis located at the lower portion of the corresponding gate opening. The second portionextends upward from the upper surfaceof the first portionalong the sidewall of the corresponding gate opening. As a result, a first step height Sis formed between the upper surfaceof the first portionand the upper surfaceof the second portion, and a second step height Sis formed between the upper surface of the second portionand the upper surfaceof the substrate. The first conductive layerforms a stepped profile due to the first step height Sand the second step height S. Furthermore, the first portionand the second portionof the first conductive layerin the gate line structure extend laterally into the isolation structure.

1 FIG.D 1 FIG.C 1 FIG.E 112 112 112 112 112 108 108 102 108 108 112 112 102 108 108 b b b Referring to, a barrier materialis conformally formed on the structure shown in. The barrier materialmay be made of titanium nitride, tantalum nitride, tungsten nitride, or the like. For example, the barrier materialis made of titanium nitride and can be formed using an ALD process. Next, referring to, an etching process (e.g., wet etching) is performed on the barrier materialto remove the barrier materialon the sidewall of the second portionof the first conductive layerand on the sidewall of the isolation structurethat is above the sidewall of the second portionof the first conductive layer. That is, the vertical portions of the barrier materialare removed to leave the horizontal portions of the barrier material, thereby exposing a portion of sidewall of the isolation structureand the sidewall of the second portionof the first conductive layer.

1 FIG.F 114 112 108 108 108 108 114 112 114 108 a b Referring to, a second conductive layeris conformally formed on the barrier materialon the first portionof the first conductive layer, and on the sidewall of the second portionof the first conductive layer. The second conductive layermay include conductive material, for example, polysilicon, which can be formed using a CVD process, an ALD process, a PVD process, or another suitable deposition processes. In this case, the barrier materialcan be used as an adhesive layer to enhance the adhesion between the second conductive layerand the underlying first conductive layer.

114 109 108 108 104 102 108 112 114 112 114 108 112 114 108 114 108 108 108 b b a b 1 FIG.F Next, an etching back process is performed on the second conductive layerto expose the upper surfaceof the second portionof the first conductive layerand the upper surface of the insulating layer, and again expose the sidewall of the isolation structure. In some embodiments, the first conductive layer, the barrier material, and the second conductive layerform a gate electrode layer, where the barrier materialand the second conductive layercan be used to adjust the work function of the gate electrode layer. In some embodiments, the gate electrode layer is only formed of the first conductive layerwithout the barrier materialand the second conductive layeron the first conductive layer. In some embodiments, as shown in, the second conductive layerforms an L-shaped structure that is on the first portionof the first conductive layerand covers the sidewall of the second portion. As a result, the gate-induced-drain-leakage (GIDL) of the device can be improved.

1 FIG.G 103 108 112 114 104 103 Referring to, a gate line structure is formed in each of the gate openings. More specifically, after forming the gate electrode layer (including the first conductive layerhaving a stepped profile, the barrier materialand the second conductive layer), an insulating layer (not shown) is formed on the upper surface of the insulating layerand fills each of the gate openingsto cover the corresponding gate electrode layer. This insulating layer may include a nitrogen-containing insulating layer, such as silicon nitride, silicon oxynitride, silicon carbonitride, or the like. For example, this insulating layer is a silicon nitride layer, and may be formed using a CVD process, an ALD process, or other suitable deposition processes.

104 116 103 116 109 108 109 108 108 112 114 108 116 a a b b Afterwards, a removal process is performed on the insulating layer to expose the upper surface of the insulating layer, and a first insulating capping layeris then formed in the gate openingto cover the corresponding gate electrode layer. For example, the removal process may include a chemical mechanical polishing process, a dry etching or wet etching process, or other similar planarization or etching processes. In some embodiments, the first insulating capping layerand the underlying gate electrode layer form a buried gate line structure. The buried gate line structure can be used as a word line structure in the semiconductor device. The first insulating capping layer covers the upper surfaceof the first portionand the upper surfaceof the second portionof the first conductive layerin the gate line structure. The barrier materialand the second conductive layersin the gate line structure are formed between the first conductive layerand the first insulating capping layer.

2 2 FIGS.A toC 1 FIG.G 2 FIG.A 1 FIG.G 2 FIG.A 1 FIG.G 2 FIG.A 100 100 are cross-sectional views of a semiconductor device showing the buried gate line structure inat various stages of subsequent processes. Referring to, a structure as shown inis provided. For purposes of simplicity and clarity,illustrates a portion of the structure shown in. In some embodiments, the portion of the substratecorresponding to the gate line structure is the array area, and the peripheral area corresponds to the laterally extending portion of the substratein.

130 140 130 140 130 140 122 124 122 126 124 128 126 130 116 140 100 108 108 100 3 FIG. 2 FIG.A 3 FIG. 2 FIG.A 3 FIG. Conventional MOS processes may be used to form one or more gate line structures(also referred to as stacked structures) in the array area of the semiconductor device, and one or more gate line structures(also referred to as stacked structures) are simultaneously formed in the peripheral area of the semiconductor device. The gate line structureand the gate line structurehave the same or similar structure. For example, the gate line structureand the gate line structureeach have a fourth conductive layer, a fifth conductive layerformed on the fourth conductive layer, and a sixth conductive layerformed on the fifth conductive layer, and a second insulating capping layerformed on the sixth conductive layer. In some embodiments, the gate line structureis formed on the first insulating capping layerand serves as a bit line structure in the semiconductor device. The gate line structureis formed over the substratecorresponding to the peripheral area in the semiconductor device and serves as a control gate structure in the semiconductor device. Referring to, which illustrates a plan view of the configuration of the bit line structures and the word line structures shown in the structure shown in. For purposes of simplicity and clarity,does not illustrate all of the features shown in. As shown in, the extending direction WL of the word line structure (including the first conductive layer) may be perpendicular to the extending direction BL of the bit line structure. The active area below the first conductive layerand formed by the substratehas a stripe-shaped pattern, as viewed from a top-view perspective, and its direction is different than the direction WL and the direction BL.

122 114 122 124 112 124 126 108 126 128 116 128 The material and formation method of the fourth conductive layermay be the same or similar to those of the second conductive layer. For example, the fourth conductive layeris made of polysilicon. The material and formation method of the fifth conductive layermay be the same or similar to those of the barrier material. For example, the fifth conductive layeris made of titanium nitride. The material and formation method of the sixth conductive layermay be the same or similar to those of the first conductive layer. For example, the sixth conductive layeris made of tungsten metal. Similarly, the material and formation method of the second insulating capping layermay be the same or similar to those of the first insulating capping layer. For example, the second insulating capping layeris made of silicon nitride.

130 140 129 130 140 148 150 152 148 130 140 129 120 100 150 130 140 152 148 130 140 150 2 FIG.A After forming the gate line structuresand, spacersmay be formed on two opposite sides of the gate line structuresand. Next, a first etch stop layer, an interlayer dielectric (ILD) layer, and a second etch stop layermay be successively formed. As shown in, the first etch stop layerconformally covers the gate line structuresand, the spacers, the isolation structure, and the substrate. The ILD layersurrounds the gate line structuresand. The second etch stop layeris formed on the first etch stop layerabove the gate line structuresandand on the upper surface of the ILD layer.

2 FIG.B 160 160 160 108 108 152 150 148 116 160 100 152 150 148 160 160 a b a b b a b Next, referring to, contact openingsandare formed. The contact openingcorresponds to the array area and extends into the second portionof the first conductive layerthrough the second etching stop layer, the ILD layer, the first etching stop layer, and the first insulating capping layer. Furthermore, the contact openingcorresponds to the peripheral area and extends into the substratethrough the second etching stop layer, the ILD layer, and the first etching stop layer. For example, the contact openingsandmay be formed by photolithography and etching processes.

160 160 148 160 116 108 108 160 100 160 160 160 108 108 160 108 108 108 108 108 101 a b a b b a b a b b a b b It should be noted that the contact openingsandare formed in the same etching process. After etching through the first etch stop layer, the contact openingneeds to pass through the first insulating capping layerso as to extend into the second portionof the first conductive layer, and the contact openingneeds to extend into the substrate. Therefore, the contact openingsandhave different depths due to the etching selectivity. Furthermore, in order to ensure that the contact openingextends into the second portionof the first conductive layer, over-etching may occur in the peripheral area, causing the contact openingto have an undesired depth. As a result, junction leakage may easily occur in the semiconductor device, resulting in reduced performance and/or reliability of the semiconductor device. However, the word line structure in the embodiments has a stepped gate electrode layer (including the first portionand the second portionof the first conductive layer). Therefore, since the level of the upper surface of the second portionof the first conductive layercan be closer to the level of the upper surfaceof the substrate than the level of the upper surface of the flat gate electrode layer, the risk of over-etching occurring in the peripheral area can be mitigated or completely eliminated.

2 3 FIGS.C and 3 FIG. 170 170 160 160 170 116 108 108 170 170 108 108 170 100 140 a b a b a b a a a b Referring to, in some embodiments, conductive plugsandare formed in the contact openingsand, respectively (not shown in). As a result, the conductive plugpasses through the first insulating capping layerand extends into the underlying second portionof the first conductive layer, so that the conductive plugis electrically connected to the word line structure. In one embodiment, the bottom of the conductive plugis higher than the top of the first portionof the first conductive layer. The conductive plugextends into the substratein the peripheral area, serves as a source/drain plug, and forms a control transistor with the control gate structure (i.e., the gate line structure).

108 108 108 101 a b According to the foregoing embodiments, since the first portionand the second portionof the first conductive layerin the word line structure form a gate electrode layer with a stepped profile, the level of the uppermost surface of the gate electrode layer can be closer to the level of the upper surfaceof the substrate than the level of the upper surface of the flat gate electrode layer. Therefore, the risk of over-etching in the peripheral area can be mitigated or completely eliminated during the formation of the conductive plug. As a result, the occurrence of junction leakage in the semiconductor device can be effectively reduced, thereby improving the performance and/or reliability of the semiconductor device.

While the invention has been described by way of example and in terms of the preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.