A semiconductor device includes a semiconductor substrate and a metal film. The metal film is located on the semiconductor substrate. The metal film includes a portion to have a Schottky junction with the semiconductor substrate. The metal film is made of an aluminum alloy in which an element is added to aluminum. The metal film includes a lower metal layer and an upper metal layer. The lower metal layer is located on the semiconductor substrate. The upper metal layer stacks on the lower metal layer. The lower metal layer has a thickness of 2.6 micrometers or less in a stacking direction of the lower metal layer and the upper metal layer.
Legal claims defining the scope of protection, as filed with the USPTO.
a semiconductor substrate; and a metal film located on the semiconductor substrate, the metal film including a portion having a Schottky junction with the semiconductor substrate, the metal film made of an aluminum alloy in which an element is added to aluminum, wherein a lower metal layer located on the semiconductor substrate; and an upper metal layer stacking on the lower metal layer, the metal film includes: the lower metal layer has a thickness of 2.6 micrometers or less in a stacking direction of the lower metal layer and the upper metal layer, the metal film has a thickness of 3 micrometers or more in the stacking direction, the metal film has a plurality of particles inside the lower metal layer and a plurality of particles inside the upper metal layer, the plurality of particles inside the lower metal layer are separated from the plurality of particles inside the upper metal layer, an average particle size of the plurality of particles inside the upper metal layer is smaller than an average particle size of the plurality of particles inside the lower metal layer, and the metal film further includes another portion having an ohmic junction with the semiconductor substrate, in addition to the portion having the Schottky junction with the semiconductor substrate. . A semiconductor device comprising:
Complete technical specification and implementation details from the patent document.
The present application is a continuation application of U.S. Utility application Ser. No. 18/065,916 filed on Dec. 14, 2022, which is a continuation application of International Patent Application No. PCT/JP2021/023793 filed on Jun. 23, 2021, which designated the U.S. and claims the benefit of priority from Japanese Patent Application No. 2020-110888 filed on Jun. 26, 2020. The entire disclosures of all of the above applications are incorporated herein by reference.
The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device.
A semiconductor device may have a metal film on a semiconductor substrate such as silicon, and the metal film may form a Schottky junction with the semiconductor substrate. The metal film may be made of an aluminum alloy in which an element such as silicon or copper is added to aluminum.
The present disclosure describes a semiconductor device having a semiconductor substrate and a metal film, and further describes a method of manufacturing the semiconductor device including formation of the semiconductor substrate and formation of the metal film.
In a semiconductor device having a metal film to form a Schottky junction with a semiconductor substrate such as silicon, if a nodule is formed inside the metal film, stress caused by the nodule may be applied to the portion of the metal film to have the Schottky junction. In a case where the stress is large, it is possible that a Schottky barrier changes, and it is possible that a leakage fault rate increases. For this reason, a semiconductor device having a prescribed portion to have the Schottky junction may be provided. In particular, in the semiconductor device described above, an interlayer insulation film is formed on the semiconductor substrate; and a contact hole for exposing the semiconductor substrate is formed at the interlayer insulation film. The semiconductor device is formed such that the metal film has a portion to have the Schottky junction with the semiconductor substrate through the contact hole. In this semiconductor device, since the nodule formed at the metal film is easily formed in the vicinity of an opening of the interlayer insulation film, the portion of the metal film to have the Schottky junction is located apart from the vicinity of the opening of the interlayer insulation film. The semiconductor device has a portion of the semiconductor substrate exposed from the interlayer insulation film. In this portion, the metal film has an ohmic junction with the semiconductor substrate in the vicinity of the opening. In the inner edge of the semiconductor substrate, the metal film has the Schottky junction with the semiconductor substrate.
In the semiconductor device described above, the Schottky junction is formed at a portion different from the portion where the nodule is easily formed. However, the nodule may also be formed at a position away from the vicinity of the opening. For example, in a case where the semiconductor substrate is enlarged in a planar direction, the influence of the nodule may not be neglected. Additionally, the leakage fault rate may also increase.
According to a first aspect of the present disclosure, a semiconductor substrate and a metal film. The metal film is located on the semiconductor substrate. The metal film includes a portion to have a Schottky junction with the semiconductor substrate. The metal film is made of an aluminum alloy in which an element is added to aluminum. The metal film includes a lower metal layer and an upper metal layer. The lower metal layer is located on the semiconductor substrate. The upper metal layer stacks on the lower metal layer. The lower metal layer has a thickness of 2.6 micrometers or less in a stacking direction of the lower metal layer and the upper metal layer.
Since the thickness of the lower metal layer is 2.6 micrometers or less, it is possible to suppress an increase in the leakage fault rate.
According to a second aspect of the present disclosure, a method of manufacturing a semiconductor device includes preparation of a semiconductor substrate and formation of a metal film on the semiconductor substrate. The metal film includes a lower metal layer and an upper metal layer. The metal film has a portion to have a Schottky junction with the semiconductor substrate, and the metal film is made of an aluminum alloy in which an element is added to aluminum. The formation of the metal film includes formation of the lower metal layer at the semiconductor substrate and formation of the upper metal layer on the lower metal layer. In the formation of the lower metal layer, the lower metal layer is formed to have a thickness of 2.6 micrometers or less in a stacking direction of the lower metal layer and the upper metal layer.
Since the lower metal layer is formed to have the thickness of 2.6 micrometers or less, it is possible to manufacture the semiconductor device that suppresses an increase in the leakage fault rate.
The following describes multiple embodiments with reference to the drawings. Hereinafter, in the respective embodiments, substantially the same configurations are denoted by identical symbols, and repetitive description will be omitted.
1 FIG. 10 1 2 1 2 24 10 10 1 25 10 10 2 b b A first embodiment will be described with reference to the drawings. As illustrated in, the semiconductor device includes a semiconductor substratewhich is shared by an insulated gate bipolar transistor (IGBT) regionand a freewheeling diode (FWD) region. The IGBT regionhas an IGBT element, and the FWD regionhas an FWD element. That is, the semiconductor device according to the present embodiment is a reverse conducting (RC) IGBT. In the semiconductor device according to the present embodiment, the portion above a collector layerlocated at a second surfaceof the semiconductor substrateis set as the IGBT region, and the portion above a cathode layerlocated at the second surfaceof the semiconductor substrateis set as the FWD region.
10 11 11 11 10 11 12 13 11 12 11 13 11 12 12 13 13 13 14 14 12 14 14 11 10 10 − − − − − a The semiconductor device has the semiconductor substrateincluded in an N-type drift layer. The N-type drift layermay also be simply referred to as a drift layerin the following. In the present embodiment, the semiconductor substrateis made of a silicon substrate. On the drift layer, a P-type electrical field relaxation regionand an N-type barrier regionare formed in order from the drift layer. The P-type electrical field relaxation regionhas lower impurity concentration than the drift layer. The N-type barrier regionhas higher impurity concentration than the drift layer. The P-type electrical field relaxation regionmay be simply referred to as an electrical field relaxation regionin the following, and the N-type barrier regionmay be simply referred to as a barrier regionin the following. On the barrier region, a P-type base layeris formed. The P-type base layerhas higher impurity concentration than the electrical field relaxation region. The P-type base layermay be simply referred to as a base layerin the following. The description “on the drift layer” refers to a first surfaceside of the semiconductor substrate.
15 10 14 13 12 10 11 14 13 12 15 15 1 2 15 1 2 a 1 FIG. Multiple trenchesare formed at the semiconductor substrateso as to penetrate through the base layer, the barrier region, and the electrical field relaxation regionfrom the first surfaceside to reach the drift layer. Accordingly, the base layer, the barrier regionand the electrical field relaxation regionare divided into several pieces by the trenches. In the present embodiment, the trenchesare respectively formed in the IGBT regionand the FWD region. In the present embodiment, the trenchesare formed in a striped shape with the direction intersecting the arrangement direction of the IGBT regionand the FWD region(that is, the depth direction on the paper surface in) as the longitudinal direction.
15 16 17 16 15 17 16 Each of the trenchesis filled with a gate insulation filmand a gate electrode. The gate insulation filmis formed so as to cover a wall surface of each of the trenches, and the gate electrodeis made of polysilicon or the like and formed on the gate insulation film. Accordingly, the trench gate structure is formed.
17 1 17 2 17 2 22 22 Although not shown, the gate electrodeformed in the IGBT regionis connected to, for example, a gate driver (not shown) through, for example, a gate pad for receiving an application of a predetermined voltage. The gate electrodeformed in the FWD regionis maintained at a predetermined potential. For example, the gate electrodeformed in the FWD regionis connected to an upper electrode, and is maintained at the same potential as the upper electrode.
18 19 20 14 18 11 14 18 14 15 18 15 15 15 + An emitter region, a contact region, and a pillar regionare formed at the base layer. The emitter regionis the N-type and has higher impurity concentration than the drift layer, and is formed at a surface layer portion of the base layer. The emitter regionis formed so as to terminate in the base layerand to be in contact with a side surface of each of the trenches. The emitter regionextends in a bar shape along the longitudinal direction of each of the trenchesin a region between adjacent two of the trenches, and is terminated inside a distal end of each of the trenches.
19 14 14 19 14 18 19 15 18 + The contact regionis a P-type and has higher impurity concentration than the base layer, and is formed at the surface layer portion of the base layer. The contact regionis formed to be terminated inside the base layerand sandwiched between two emitter regions. The contact regionextends in a bar shape along the longitudinal direction of each of the trenchesto be in contact with the emitter region.
20 13 20 19 14 13 20 13 The impurity concentration of the pillar regionis at a comparable level with respect to the barrier region. The pillar regionis formed to penetrate the contact regionand the base layerto reach the barrier region. The pillar regionis formed so as to be connected to the barrier region.
10 10 21 21 21 21 18 19 20 a a a On the first surfaceof the semiconductor substrate, an interlayer insulation filmmade of, for example, borophosphosilicate glass (BPSG) is formed. A contact holeis formed at the interlayer insulation film. The contact holeexposes the emitter region, the contact regionand the pillar region.
22 21 22 1 2 22 18 19 21 21 22 20 22 22 22 1 2 22 a The upper electrodeis formed on the interlayer insulation film. The upper electrodecorresponds to a metal film. In the IGBT regionand the FWD region, the upper electrodehas an ohmic junction with the emitter regionand the contact regionthrough the contact holeformed at the interlayer insulation film; and the upper electrodehas a Schottky junction with the pillar region. In other words, the upper electrodeaccording to the present embodiment has a structure having both of a Schottky-junction portion and an ohmic-contact portion. With the formation of the upper electrode, the upper electrodefunctions as an emitter electrode in the IGBT regionand functions as an anode electrode in the FWD region. A specific structure of the upper electrodewill be described hereinafter.
23 11 11 14 23 23 23 10 10 b An N-type field stop layerhaving carrier concentration higher than the drift layeris formed on a side of the drift layeropposite to the base layer. In the following, the N-type field stop layermay also be simply referred to as an FS layer. The FS layeris formed at a side closer to the second surfaceof the semiconductor substrate.
1 24 11 23 2 25 11 23 24 24 25 25 1 2 10 10 24 25 24 1 25 2 + + + + b In the IGBT region, a P-type collector layeris formed on the side opposite to the drift layeracross the FS layer. In the FWD region, an N-type cathode layeris formed on the side opposite to the drift layeracross the FS layer. In the following, the P-type collector layermay also be simply referred to as the collector layer, and the N-type cathode layermay also be simply referred to as the cathode layer. In the present embodiment, the IGBT regionand the FWD regionare distinguished from each other depending on whether a layer formed on the second surfaceof the semiconductor substrateis the collector layeror the cathode layer. In other words, in the semiconductor device according to the present embodiment, the portion on the collector layeris the IGBT region, and the portion on the cathode layeris the FWD region.
11 24 25 26 24 25 26 10 10 26 1 2 b At the side opposite to the drift layeracross the collector layerand the cathode layer, a lower electrodeis formed to be electrically connected to the collector layerand the cathode layer. In other words, the lower electrodeis formed at the second surfaceof the semiconductor substrate. The lower electrodefunctions as a collector electrode in the IGBT region, and functions as a cathode electrode in the FWD region.
1 14 18 24 2 11 23 25 The semiconductor device according to the present embodiment includes the IGBT element in the IGBT region. The IGBT element includes the base layeras a base of the IGBT element, the emitter regionas an emitter of the IGBT element, and the collector layeras a collector of the IGBT element. The semiconductor device according to the present embodiment also includes the FWD element in the FWD region. The FWD element with a PN junction includes a base layer as the anode, and further includes the drift layer, the FS layerand the cathode layeras the cathode.
+ − − + 10 24 25 23 11 12 13 14 18 19 20 The structure of the semiconductor device according to the present embodiment is described above. In the present embodiment, the N-type, the N-type, and the N-type correspond to a first conductive type, and the P-type, the P-type, and P-type correspond to a second conductive type. Further, in the present embodiment, the semiconductor substratehas a structure including the collector layer, the cathode layer, the FS layer, the drift layer, the electrical field relaxation region, the barrier region, the base layer, the emitter region, the contact region, and the pillar region.
22 22 22 22 22 The following describes the upper electrodein the present embodiment. The upper electrodeof the present embodiment is made of an aluminum alloy in which an element is added to aluminum, such as an aluminum-silicon (AlSi) alloy, an aluminum-copper (AlCu) alloy, an aluminum-silicon-copper (AlSiCu) alloy. In the present embodiment, the upper electrodeis formed by sputtering as will be described hereinafter. However, in order to inhibit the generation of an alloy spike, an added element is added to have limit solid solubility higher than or equal to limit solid solubility of the aluminum for the temperature at the time of sputtering. The upper electrodeaccording to the present embodiment is formed to have a thickness of 3 micrometers (μm) or more so as not to have a breakdown easily, when a probe needle or the like for inspecting the characteristics of the semiconductor device is in contact with the upper electrode.
2 FIG. 22 22 22 10 22 22 10 22 22 18 19 20 a b a a As illustrated in, the upper electrodeis formed by stacking a lower metal layerand an upper metal layerfrom the semiconductor substrate. In the upper electrode, the lower metal layerhas an ohmic junction or a Schottky junction with the semiconductor substrate. Specifically, in the upper electrode, the lower metal layerhas the ohmic junction with the emitter regionand the contact region, and has the Schottky junction with the pillar region.
22 22 22 22 22 22 22 22 22 22 22 22 c a b c a a c a b c c. 2 FIG. The upper electrodein the present embodiment includes an insulation filmarranged between the lower metal layerand the upper metal layer. The insulation filmis a natural oxide film formed by forming the lower metal layerthrough sputtering and exposing the lower metal layerto the atmosphere, and a thickness of the insulation filmis set to be extremely thin, at 10 nanometers or less. For this reason, the lower metal layerand the upper metal layerare electrically connected through a tunnel effect. For understanding the insulation film,illustrates an enlarged insulation film
22 22 22 22 22 22 22 22 22 22 a b a b a b a a b. The upper electrodeis in a state in which particles Ra included in the lower metal layerand particles Rb included in the upper metal layerare separated. In other words, the grain boundary of the particle Ra included in the lower metal layerand the grain boundary of the particle Rb included in the upper metal layerare not connected but are separated. The grain boundary of the particle Ra included in the lower metal layerand the grain boundary of the particle Rb included in the upper metal layerrespectively are terminated in the respective layers. Therefore, even though the nodule is generated in the lower metal layer, the nodule is terminated inside the lower metal layer, and does not protrude to the upper metal layer
22 22 22 The nodule precipitates inside the aluminum alloy included in the upper electrodeas described above. If the nodule is formed in a portion where the Schottky junction is formed, the Schottky barrier may fluctuate due to the stress caused by the nodule, and a leakage fault may occur. In this case, the nodule easily grow in the thickness direction of the upper electrode. In other words, the stress caused by the nodule easily depends on the length of the nodule in the thickness direction of the upper electrode.
22 22 22 22 22 22 a b a a b. In the upper electrodeaccording to the present embodiment, the nodule inside the lower metal layerdoes not protrude into the upper metal layeras described above. For this reason, the stress caused by the nodule depends on the thickness of the lower metal layer. The thickness described above is the length along the stacking direction of the lower metal layerand the upper metal layer
3 FIG. 3 FIG. 22 22 22 22 22 a a a a a The inventors in the present application obtained the result shown inby reviewing the relationship between the thickness of the lower metal layerand the leakage fault rate. As illustrated in, it is confirmed that the leakage fault rate begins to occur when the lower metal layeris 1.5 μm or more; and the leakage fault rate increases steeply when the lower metal layeris 2.6 μm or more. Therefore, in the present embodiment, the lower metal layerhas a thickness of 2.6 μm or less. The leakage fault rate can be sufficiently reduced by making the thickness of the lower metal layerto be 1.5 μm or less.
The structure of the semiconductor device according to the present embodiment has been described above. The following describes a basic operation of the above-mentioned semiconductor device.
22 26 14 11 17 22 26 First, in the semiconductor device, when a voltage higher than that of the upper electrodeis applied to the lower electrode, the PN junction formed between the base layerand the drift layeris brought into a reverse conduction state to form a depletion layer. When a low-level voltage (for example, 0 V) that is less than a threshold voltage Vth of the insulated gate structure is applied to the gate electrode, a current does not flow between the upper electrodeand the lower electrode.
17 1 22 26 1 14 15 17 18 11 24 11 11 In order to turn the IGBT element to the ON state, a high-level voltage, which is equal to or higher than the threshold voltage Vth of the insulated gate structure, is applied to the gate electrodeof the IGBT regionin a state where a voltage higher than that of the upper electrodeis applied to the lower electrode. As a result, in the IGBT region, an inversion layer is formed in a portion of the base layerwhich is in contact with each trenchin which the gate electrodeis disposed. Each IGBT element is turned to the ON-state by supplying electrons from the emitter regionto the drift layerthrough the inversion layer, thereby supplying holes from the collector layerto the drift layer, and decreasing the resistance value of the drift layerby the conductivity modulation.
22 26 26 22 2 22 20 22 26 25 11 12 13 20 13 22 When the IGBT element is turned to OFF-state and the FWD element is turned to the ON-state (that is, the FWD element is operated as a diode), the voltage to be applied to the upper electrodeand the lower electrodeis switched, and a voltage higher than that applied to the lower electrodeis applied to the upper electrode. Therefore, in the FWD region, the Schottky junction between the upper electrodeand the pillar regionis turned on. Subsequently, electrons flow toward the upper electrodefrom the lower electrodethrough the cathode layer, the drift layer, the electrical field relaxation region, the barrier regionand the pillar region, and the potential of the barrier regionis changed to a potential closer to the potential of the upper electrode.
2 14 13 22 22 22 13 22 22 26 13 14 In the FWD region, a potential difference is hardly generated at the PN junction formed at the boundary between the base layerand the barrier region. Therefore, even if the potential of the upper electrodeis increased thereafter, the PN junction is not turned on for a while. When the potential of the upper electrodeis further increased, the current flowing through the Schottky junction also increases. Therefore, the potential difference between the upper electrodeand the barrier regionincreases, and the potential difference generated at the PN junction also increases. When the potential of the upper electrodeis raised above a predetermined potential, the PN junction, that is, the FWD element is turned on. The electrons flow toward the upper electrodefrom the lower electrodethrough the barrier regionand the base layer.
22 11 In the semiconductor device according to the present embodiment, the timing of turning on the PN junction is delayed by firstly turning on the Schottky junction when the potential of the upper electroderises. Therefore, the flow of holes into the drift layeris suppressed. Thus, it is possible to reduce a recovery current and recovery loss when the FWD element is in a recovery operation.
14 13 13 22 20 22 20 1 11 In the semiconductor device according to the present embodiment, also in the IGBT region, a parasitic diode is formed by the PN junction between the base layerand the barrier region. The barrier regionof the IGBT element at the PN junction is connected to the upper electrodethrough the pillar region. Therefore, as described above, when the potential of the upper electroderises, the current firstly flows to the pillar region. Subsequently, when a forward voltage further rises, the PN junction included in the parasitic diode is turned on. Also in the IGBT region, the timing of turning on the PN junction is delayed, and the flow of the holes to the drift layeris suppressed. Thus, the recovery current is suppressed.
12 13 11 12 15 12 11 Further, in the semiconductor device of the present embodiment, the electrical field relaxation regionis formed between the barrier regionand the drift layer. Therefore, as compared with the case where the electrical field relaxation regionis not formed, it is difficult for the equipotential lines to enter between the trenchesdue to the PN junction formed between the electrical field relaxation regionand the drift layer. Thus, the breakdown voltage can be further enhanced.
22 The following describes a method of manufacturing the upper electrodein the semiconductor device.
10 14 18 19 20 21 10 10 21 21 a a Although not shown, the semiconductor substratefor forming, for example, the base layer, the emitter region, the contact regionand the pillar regionis prepared for a semiconductor manufacturing process. Subsequently, the interlayer insulation filmis formed on the first surfaceof the semiconductor substrate, and the contact holeis formed at the interlayer insulation film.
4 FIG.A 10 22 22 22 10 22 10 10 22 a a a As illustrated in, the semiconductor substrateis arranged in a sputtering apparatus, and the lower metal layeris formed by sputtering. At this time, the lower metal layeris formed by adding an element having the limit solid solubility higher than or equal to the limit solid solubility of the aluminum for the temperature at the time of sputtering so that alloy spikes are less likely to occur. Therefore, it is not necessary to form, for example, a barrier metal at a portion where the upper electrodehas an ohmic junction with the semiconductor substratebecause alloy spikes are less likely to occur. In other words, in the present embodiment, the upper electrodehaving a portion to have an ohmic junction with the semiconductor substrateand a portion to have a Schottky junction with the semiconductor substratecan be formed by the identical process without forming, for example, the barrier metal. Further, in this embodiment, the lower metal layeris formed to have a thickness of 2.6 μm or less as described above.
4 FIG.B 4 FIG.C 10 22 22 10 22 22 22 c a b a As illustrated in, the semiconductor substrateis removed from the sputtering apparatus and exposed to the atmosphere to form the insulation filmon the lower metal layer. As illustrated in, the semiconductor substrateis again arranged in the sputtering apparatus, and the upper metal layeris formed by conducting the sputtering as similar to the lower metal layer. Therefore, the upper electrodeaccording to the present embodiment is formed.
22 22 22 22 22 22 c a a a a At this time, since the insulation filmis formed at the surface of the lower metal layer, the grain boundary of the particle Ra included in the lower metal layerdoes not protrude into the upper metal layer. In other words, it is possible to suppress the enlargement of the nodule generated in the lower metal layerin the thickness direction of the upper electrode. Therefore, it is possible to manufacture the semiconductor device in which the leakage fault is less likely to occur.
22 22 22 22 22 22 22 22 10 b a a b a a a According to the present embodiment, the upper electrodeis formed by stacking the upper metal layeron the lower metal layer. The grain boundary in the lower metal layerand the grain boundary in the upper metal layerare not connected and are separated. The lower metal layerhas a thickness of 2.6 μm or less. Even though the nodule is formed in the portion of the lower metal layerhaving the Schottky junction, it is possible to suppress an increase in the leakage fault rate. In this situation, the leakage fault rate can be further suppressed by making the thickness of the lower metal layerto be 1.5 μm or less. In the present embodiment, an increase in the leakage fault rate is suppressed by preventing the nodule from becoming excessively large. Even though the semiconductor substrateis enlarged in the planar direction, it is possible to suppress an increase in the leakage fault rate. In addition, it is possible to enhance the degree of freedom in designing the semiconductor device.
22 22 10 22 22 22 a a a a a In the present embodiment, at the time of forming the lower metal layer, an element having the limit solid solubility equal to or higher than the limit solid solubility of the aluminum at the temperature of sputtering is added. Therefore, it is possible to suppress the generation of alloy spikes. Even though the barrier metal is not formed, the lower metal layercan have an ohmic junction with the semiconductor substrate. In other words, the lower metal layerhaving a portion to have an ohmic junction and a portion to have a Schottky junction can be formed by the identical process without forming the barrier metal. When the element having limit solid solubility higher than or equal to the limit solid solubility of the aluminum at the temperature of sputtering is added to form the lower metal layer, the nodule is easily generated. However, an increase in the leakage fault rate is suppressed by making the lower metal layerto have a thickness of 2.6 μm or less.
22 22 b a The following describes a second embodiment. The present embodiment is different from the first embodiment, such that the average particle size of the particles Rb included in the upper metal layeris smaller than the average particle size of the particles Ra included in the lower metal layerin the present embodiment. The other configurations are the same as those of the first embodiment, and therefore a description of the same configurations will be omitted below. The average particle size described in the present disclosure may also be referred to, for example, an average particle diameter or an average particle radius.
5 FIG. 22 22 22 b a. In the present embodiment, as illustrated in, in the upper electrode, the average particle size of the particles Rb included in the upper metal layeris smaller than the average particle size of the particles Ra included in the lower metal layer
22 The upper electrodeis manufactured as follows.
22 22 22 22 22 22 a b a b b a. 4 FIG.A 4 FIG.C When the lower metal layeris formed in the process illustrated in, the sputtering at a temperature of 400 degrees Celsius or higher is conducted. Subsequently, when the upper metal layeris formed in the process illustrated in, the sputtering at a lower temperature than the sputtering for forming the lower metal layeris conducted. For example, the sputtering at about 300 to 350 degrees Celsius is conducted when the upper metal layeris formed. When the metal layer is formed with the sputtering, since the average particle size becomes larger as the temperature rises, the average particle size of the particles Rb included in the upper metal layeris smaller than the average particle size of the particles Ra included in the lower metal layer
22 22 b a According to the present embodiment, the average particle size of the particles Rb included in the upper metal layeris smaller than the average particle size of the particles Ra included in the lower metal layerin the present embodiment. Therefore, as compared with the case in which the average particle size of the particles
22 22 22 22 b a b a Rb included in the upper metal layeris larger than or equal to the average particle size of the particles Ra included in the lower metal layer, the boundary step of the grain boundary becomes smaller at the surface of the upper metal layeron a side opposite from the lower metal layer. Therefore, it is possible to reduce the possibility of erroneously determining a grain boundary step as a fault or foreign matter when performing an appearance inspection.
22 22 22 c b a The following describes a third embodiment. The present embodiment is different from the first embodiment, such that the insulation filmis not arranged between the upper metal layerand the lower metal layer. The other configurations are the same as those of the first embodiment, and therefore a description of the same configurations will be omitted below.
6 FIG. 22 22 22 22 c a b. As illustrated in, in the present embodiment, in the upper electrode, the insulation filmis not arranged between the lower metal layerand the upper metal layer
22 The upper electrodeis manufactured as follows.
22 22 22 22 22 22 22 22 a a a a b a a b 4 FIG.A 4 FIG.C 4 FIG.B After the sputtering for forming the lower metal layeris conducted in the process illustrated in, inert gas such as argon is introduced into the sputtering apparatus to cool down the lower metal layerto completely stop the growth of the particles Ra included in the lower metal layer. Subsequently, the process illustrated inis conducted without conducting the process illustrated in. At this time, since the growth of the particles Ra included in the lower metal layeris completely stopped, the upper metal layeris formed by the particles Rb different from the particles Ra included in the lower metal layer. Therefore, the particles Ra included in the lower metal layerand particles Rb included in the upper metal layerare separated.
22 22 22 22 22 c a b a b Even though the insulation filmis not arranged between the lower metal layerand the upper metal layer, it is possible to attain the effects identical to the effects in the first embodiment, as long as the particles Ra included in the lower metal layerand the particles Rb included in the upper metal layerare separated.
Although the present disclosure has been described in accordance with the embodiments, it is understood that the present disclosure is not limited to such embodiments or structures. The present disclosure encompasses various modifications and variations within the scope of equivalents. In addition, while the various elements are shown in various combinations and configurations, which are exemplary, other combinations and configurations, including more, less or only a single element, are also within the spirit and scope of the present disclosure.
1 2 1 2 22 22 22 a b Each of the above embodiments describes that the semiconductor device includes the IGBT regionand the FWD region. However, if the semiconductor has a portion to be a Schottky junction, the semiconductor device may have only one of the IGBT regionand the FWD region. The upper electrodemay have only a portion to be the Schottky junction, or may not have a portion to be an ohmic junction. In each of the above embodiments, the lower metal layerand the upper metal layermay have different compositions.
22 22 b a The embodiments described above can also be combined with each other. For example, through the combination of the second embodiment and the third embodiment, the average particle size of the particles Rb included in the upper metal layeris smaller than the average particle size of the particles Ra included in the lower metal layer. The combination of two or more above-described embodiments may be further combined with another embodiment.
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