System and Method for Semiconductor Structure

This application is a divisional of U.S. Patent Application No. 18/314,885, filed on May 10, 2023, and entitled, “System and Method for Semiconductor Structure,” which application is hereby incorporated herein by reference in its entirety.

The present invention relates generally to a system and method for semiconductor processing, and, in particular embodiments, to a system and method for area selective deposition.

Dimension shrinkage is one of the driving forces in the development of integrated circuit processing. By reducing the size dimensions, cost-benefit and device performance boosts can be obtained. This scalability creates inevitable complexity in process flow, especially on patterning techniques. For example, as smaller circuits such as transistors are manufactured, the critical dimension (CD) or resolution of patterned features is becoming more challenging to produce, particularly in high volume. Self-aligned patterning may replace overlay-driven patterning so that cost effective scaling can continue even after the introduction of extreme ultraviolet (EUV) lithography. Patterning options that enable reduced variability, extend scaling, and enhance CD and process control are useful in a high-volume manufacturing environment; however, it is getting extremely difficult to produce scaled devices at reasonably low cost and high yield. Selective deposition, together with selective etch, can significantly reduce the cost associated with advanced patterning. Selective deposition of thin films such as gap fill, area selective deposition of dielectrics and metals on specific substrates, and selective hard masks are key steps in patterning in highly scaled technology nodes.

Area selective deposition (ASD) techniques may be advantageous for photoresist mask smoothing, but ASD techniques may present new challenges. Selectivity to different areas may frequently be material dependent, which can limit applicability of ASD techniques. A variety of material modification techniques exist for improved selectivity, such as atomic layer deposition (ALD) and atomic layer etching (ALE) style precursor adhesion and wettability alteration. However, concurrent or separately from any of these effects, improved deposition on tops of features may provide overall improvements to ASD techniques.

In accordance with an embodiment, a method for an area selective deposition process includes: forming a first masking layer over a substrate, the first masking layer including a first mask line and a second mask line, where a trench between the first mask line and the second mask line has a first width; in a plasma processing chamber, heating respective top surfaces of the first mask line and the second mask line with polarized light, where the first width is smaller than half a wavelength of the polarized light; and in the plasma processing chamber, forming a second masking layer over the first masking layer with an area selective deposition process, where the second masking layer is thinner over a sidewall of the first mask line than over a top surface of the first mask line.

In accordance with another embodiment, a method for manufacturing a semiconductor structure includes: placing a substrate into a plasma processing chamber, a patterned first masking layer being over a target layer of the substrate; bombarding the patterned first masking layer with linearly polarized light, where a polarization direction of the linearly polarized light is aligned with a pattern of trenches through the patterned first masking layer; performing a first area selective deposition of a second masking layer over the patterned first masking layer; patterning the target layer using the second masking layer and the patterned first masking layer as an etching mask; and forming a pattern between remaining portions of the target layer.

In accordance with yet another embodiment, a plasma processing system includes: a plasma processing chamber; a chuck configured to hold a substrate; and an ellipsometer, the ellipsometer configured to provide polarized light to the substrate in the plasma processing chamber, the ellipsometer including a laser generator, a polarizing filter between the laser generator and the plasma processing chamber, a detector, and an analyzer between the detector and the plasma processing chamber.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure, as claimed.

The making and using of various embodiments are discussed in detail below. It should be appreciated, however, that the various embodiments described herein are applicable in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use various embodiments, and should not be construed in a limited scope.

According to one or more embodiments of the present disclosure, this application relates to methods of area selective deposition (ASD) using polarized light to differentially heat features. Differential heating of top surfaces of features with light may improve reaction rates of an ASD precursor deposition process. Patterns with regularly spaced features (e.g., trenches or vias) may be differentially heated with linearly polarized light using an orientation and wavelength that reduce or prevent light from reaching respective bottoms of the features. Patterns with irregular or isolated features (e.g., curved waveguides) may have light preferentially delivered to tops of features using grazing incidence or circular polarization.

1 1 2 FIGS.A,B,A 2 FIG.B 3 4 4 5 6 6 7 7 7 8 8 9 9 10 FIGS.,A,B,,A,B,A,B,C,A,B,A,B,A 10 FIG.B 11 FIG. 12 FIG. Embodiments of the disclosure are described in the context of the accompanying drawings. Embodiments of plasma processing systems will be described using, and. Embodiments of a semiconductor manufacturing process will be described using, and. An embodiment of a method for an area selective deposition process will be described using. An embodiment of a method for manufacturing a semiconductor structure will be described using.

1 FIG.A 1 FIG.A 1 FIG.A 100 100 101 102 104 106 120 122 124 114 100 illustrates a diagram of an embodiment plasma processing systemthat operates using inductively coupled plasma (ICP), in accordance with some embodiments. Plasma processing systemincludes an RF source, a matching circuit, an antenna, a plasma processing chamber, a polarized laser system including a laser generator, a polarizing filter, and a beam expander, and, optionally, a dielectric plate, which may (or may not) be arranged as illustrated in. Further, plasma processing systemmay include additional components not depicted in.

104 101 102 101 101 104 106 101 In various embodiments, antennais coupled to an RF sourcethrough a matching circuit. RF sourceincludes an RF power supply, which may include a generator circuit. RF sourceprovides forward RF waves to antenna, which are radiated towards plasma processing chamber. Throughout the description, the RF sourcemay be alternatively referred to as a power supply or RF source.

101 102 102 104 101 104 101 104 RF sourceis coupled to matching circuitand matching circuitis coupled to antennavia power transmission lines, such as coaxial cables or the like. The RF sourcemay be employed to provide RF power to the antennaas a continuous wave (CW). In various embodiments, the RF sourcemay be employed to provide pulse-modulated RF power to the antenna.

102 101 104 101 104 106 101 102 102 106 104 101 106 Typically, a matching circuit (auto or manual) coupled to the radiating antenna is used to minimize losses (i.e., reflected power) in response to changes in the load condition. The matching circuit(also referred to as a matching network or an impedance matching network) is coupled between the RF sourceand the antenna. As forward power propagates from the RF sourceto the antenna, some reflected power may be reflected back due to impedance mismatch between the plasma processing chamberand the RF source. The matching circuitis used to reduce reflected power by transforming the impedance looking into the matching circuit(in other words, the impedance of the transmission lines, plasma process chamber, and antenna) to a same impedance as the RF sourceand any intermediate transmission lines. This increases the efficiency of supplying power to the plasma processing chamber.

106 106 106 115 106 115 106 Plasma processing chambermay be, e.g., a medium frequency (MF) or high frequency (HF) plasma chamber. The plasma processing chambermay be a vacuum chamber. In some embodiments, the plasma processing chamberis configured to operate plasmaat a first resonant frequency, wherein the first resonant frequency is in a range from about 1 MHz to about 27 MHz. For example, the plasma processing chambermay be configured to operate plasmaat 1 MHz or more, 13.56 MHz or more, 27 MHz or more, or the like. However, any suitable plasma processing chambermay be used and may generate plasma with any suitable method, such as DC plasma.

106 108 110 108 106 118 108 106 116 106 116 108 110 106 108 108 1 FIG.A In various embodiments, plasma processing chamberincludes a substrate holder(e.g., a chuck). As illustrated, substrate(e.g., a semiconductor wafer) is placed on substrate holderto be processed. Optionally, plasma processing chambermay include a bias power supplycoupled to substrate holder. The plasma processing chambermay also include one or more pump outletsto remove by-products from plasma processing chamberthrough selective control of gas flow rates within. In various embodiments, pump outletsare placed near (e.g., below/around the perimeter of) substrate holderand substrate. In various embodiments, plasma processing chambermay include additional substrate holders (not illustrated). In various embodiments, the placement of the substrate holdermay differ from that illustrated in. Thus, the quantity and position of the substrate holderare non-limiting.

104 106 104 104 104 104 In various embodiments, antennaradiates an electromagnetic field toward the plasma processing chamber. In an embodiment, antennaincludes arms connected to capacitive structures that generate the azimuthal symmetry. In various embodiments, the excitation frequency of the antennais in the radio frequency range (10-400 MHz), which is not limiting, and other frequency ranges can similarly be contemplated. For example, inventive aspects disclosed herein equally apply to applications in the microwave frequency range. Various examples of designs for antennasmay be found in U.S. Patent Application No. 17/649,823, which is incorporated by reference herein in its entirety. However, any suitable antennamay be used.

104 106 106 114 114 106 104 114 104 106 114 106 104 114 114 114 120 In various embodiments, antennais outside of plasma processing chamberand is separated from plasma processing chamberby the dielectric plate, which is typically made of a dielectric material. Dielectric plateseparates the low-pressure environment within plasma processing chamberfrom the external atmosphere. It should be appreciated that antennacan be placed directly adjacent to dielectric plate. In various embodiments, antennais separated from plasma processing chamberby air. In various embodiments, the properties of the dielectric plateare selected to minimize reflections of the RF wave from the plasma processing chamber. In other embodiments, antennais embedded within the dielectric plate. In various embodiments, dielectric plateis in the shape of a disk. The dielectric platemay be transparent or semitransparent to light, such as laser light produced by the laser generator.

114 106 104 The dielectric plateincludes a first outer surface and a second outer surface. The first outer surface faces the plasma processing chamber. The second outer surface faces the antenna. The second outer surface is above the first outer surface in a vertical direction.

104 101 106 110 104 101 104 114 106 106 112 106 110 In an embodiment, the antennacouples RF power from RF sourceto the plasma processing chamberto treat substrate. In particular, antennaradiates an electromagnetic wave in response to being fed the forward RF waves from RF source. The radiated electromagnetic wave penetrates from the atmospheric side (i.e., antennaside) of the dielectric plateinto plasma processing chamber. The radiated electromagnetic wave generates an electromagnetic field within the plasma processing chamber. The generated electromagnetic field ignites and sustains plasma in a plasma generating regionby transferring energy to free electrons within the plasma processing chamber. The generated plasma can be used for a plasma process to, for example, selectively etch or deposit material on substrate. The plasma process may include an etch process such as a Reactive Ion Etch (RIE) process, an Atomic Layer Etch (ALE) process or the like, a deposition process such as a Plasma-Enhanced Physical Vapor Deposition (PVD) process, a Plasma-Enhanced Chemical Vapor Deposition (CVD) process, an Atomic Layer Deposition (ALD) process, an Area Selective Deposition (ASD) process, or the like.

112 114 106 112 114 106 In various embodiments, the plasma generating regionis immediately below the nearest portion of the dielectric plateto the plasma processing chamber. In various embodiments, the upper most surface of the plasma generating regioncorresponds to the plane where the outer surface of the dielectric platefaces the plasma processing chamber.

1 FIG.A 104 106 104 106 112 104 106 In, antennais external to plasma processing chamber. In various embodiments, however, antennacan be placed internal to the plasma processing chamber. In such an embodiment, the plasma generating regionis immediately below the nearest portion of the antennato the plasma processing chamber.

100 110 110 120 122 124 120 120 110 2 2 The plasma processing systemincludes a polarized laser system for treating the substratein order to improve selectivity for an area selective deposition (ASD) process performed on the substrate. The polarized laser system includes a laser generator, a polarizing filter, and a beam expander. In various embodiments, the laser generatoris a pulsed laser with, e.g., a pulse energy delivered to a wafer in a range of 3 mJ/cm/pulse to 1000 3 mJ/cm/pulse and a wavelength in a range of 170 nm to 3000 nm. The laser generatormay be configured to produce laser pulses with a duration of 20 femtoseconds to 100 milliseconds. The wavelength of the laser generator may be smaller than widths of trenches on the substrate.

120 122 124 106 110 122 124 122 122 124 110 110 124 Laser light from the laser generatorpasses through a polarizing filterand through a beam expanderinto the plasma processing chamberto target the substrate. The laser light may be guided through the polarizing filterand the beam expanderby, e.g., an optical fiber or the like. In various embodiments, the polarizing filteris a linear filter to produce linearly polarized laser light. In other embodiments, the polarizing filteris a circular filter to produce circularly polarized light. The beam expanderwidens the polarized laser beam in order to target a large portion of the substrate, or multiple substrates. In some embodiments, the beam expandercomprises one or more lenses. However, any suitable beam expander or focusing lens may be used.

1 FIG.B 180 180 122 180 122 180 180 130 106 180 110 110 180 110 110 110 180 110 In some embodiments, as illustrated by, the beam expander is or includes a digital light projection system(also referred to as a digital projection system) as described in U.S. Patent No. 10,147,655, which is hereby included by reference herein in its entirety. Additionally, the digital light projection systemmay include mirrors with built-in polarizing gratings, so that the function of the polarizing filtermay also be performed by the digital light projection systemand a polarizing filterexternal to the digital light projection systemmay be omitted. As such, the digital light projection systemprojects polarized lightinto the plasma processing chamber. In some embodiments, the digital light projection systemilluminates specific spots on the substrateas controlled by a program of the digital light projection system. For example, if more material is being etched in a center portion of the substrate, the digital light projection systemmay illuminate only the center portion of the substrate, or may illuminate the center portion of the substratelonger than an edge portion of the substrate. However, the digital light projection systemmay illuminate any suitable portion of the substratefor any suitable length of time.

1 FIG.A 130 124 104 114 124 104 104 114 130 106 124 130 106 106 Referring again to, polarized lightfrom the beam expanderpasses through the antennaand the dielectric plate(if present). The beam expandermay be aimed through a gap in the antenna(e.g., a space between spiral arms of the antenna). The dielectric plate, if present, may be transparent to the polarized light. The plasma processing chambermay have one or more openings or transparent windows (also referred to as view ports) adjacent to the beam expanderto allow the polarized lightto enter the plasma processing chamber. One or more window(s) added to the body of the plasma processing chambermay be used to enable an ASD process if multiple light sources are in range of the window(s) or if the multiple light sources are swapped into and out of position (e.g., on a turret or a linear stage).

130 112 110 130 106 110 In some embodiments, the polarized lightpenetrates plasma in the plasma generating regionto reach the substrate. In other embodiments, pulses of the polarized lightare synchronized to be out of phase with the pulsed power of the plasma in order to allow for better transmission through the plasma processing chamberto the substrate.

130 110 110 130 130 130 130 5 6 FIGS.,A 2 2 The polarized lightmay differentially deposit thermal energy on top surfaces of features on the substraterather than on sidewalls or bottom surfaces of features (e.g., mask lines having trenches between them) on the substrate. In other words, the polarized lightenables preferential heating of, e.g., trench tops. This heating of top surfaces of features with the polarized lightmay improve reaction rates of an ASD precursor deposition process (see below,, and 6B). A wide process range is enabled, as the energy of the laser generator may be tuned over a range from less than 1 mJ/cm/pulse to an ablation threshold of 400-600 mJ/cm/pulse, depending on the type of material of the features, other plasma conditions, or the like. Additionally, adhesion on top surfaces may be altered by the polarized lightas a function of temperature to drive reaction rates or molecular decomposition on the top surfaces. As pulse heating from pulsed polarized lightmay dissipate rapidly, the preferential heating by polarized light bombardment may be useful for thin resists (e.g., EUV resists) and short features. The preferential heating by polarized light bombardment is not dependent on chemical or substrate material selectivity and may be used with any suitable ASD precursor or substrate material.

110 Preferentially delivering thermal energy to the tops of the features may allow for desirable adhesion of precursors and/or desorption of undesirable contaminants and reaction byproducts as well as tuning of reaction rate kinetics without causing undesirable ablation of material on the substrate. Improved selectivity of deposition enabled by the polarized light bombardment may improve on existing chemical selectivity of ASD processes, such as for high aspect ratio features. This may desirably increase reaction rates and lead to higher process throughput. Additionally, the improved ASD by polarized light bombardment can enable smoothing of mask features (e.g., reduction of line edge roughness (LER)) or expansion of masks (e.g., tuning of double patterning or correction of lithography) with better selectivity between mask and underlayer as well as selectivity between masks and underlayers that may have been previously not achievable with ASD processes. In some embodiments, improved masks formed with greater amounts of material deposited on top surfaces of mask features by the polarized light bombardment allow for new hard masks to be generated. This may be done by etching of an underlying hard mask layer using the improved masks as an etching mask. The improved ASD by polarized light bombardment may be used to improve a pattern in a photoresist after a patterning step, to recover a pattern of a mask partially through an etch process (or sequence of etch processes) as the mask is degrading, to regenerate a mask on a partially etched structure by preferentially depositing on top surfaces of lines, the like, or a combination thereof. For example, a single process could include three improved ASD by polarized light bombardment steps: a first step improving the pattern of a mask before an etch, a second step recovering a mask pattern partially through an etch, and a third step regenerating the mask after the original mask has been consumed.

130 130 130 In embodiments in which the polarized lightis linearly polarized, the linearly polarized light may have an orientation and wavelength that reduces or prevents light from reaching bottoms of regularly spaced features (e.g., trenches or vias). For example, laser wavelength may be chosen to be smaller than trench widths. The linear polarization of the polarized lightthereby allows thermal energy to be deposited on top surfaces of features (e.g., on tops of mask lines adjacent to trenches) while avoiding trench bottoms that are oriented 90 degrees out of phase with the direction of linear polarization. However, trenches that are oriented in phase with the direction of linear polarization may receive heating on respective bottoms surfaces of the trenches. Targeting of feature tops does not depend on depths of features (e.g., trenches) but on pitches between the features. As such, the polarized light bombardmentmay be used with features with high aspect ratio (e.g., deep trenches), low aspect ratio (e.g., shallow trenches), or a combination thereof (e.g., staircase style structures or etches).

2 FIG.A 2 FIG.A 2 FIG.A 150 100 101 102 132 134 106 120 122 126 100 illustrates a diagram of an embodiment plasma processing systemthat operates using capacitively coupled plasma (CCP), in accordance with some embodiments. Plasma processing systemincludes an RF source, a matching circuit, a first electrode, a second electrode, a plasma processing chamber, a polarized laser system including a laser generator, a polarizing filter, and a beam focuser, which may (or may not) be arranged as illustrated in. Further, plasma processing systemmay include additional components not depicted in.

132 106 108 101 102 134 106 108 134 134 132 134 112 1 FIG.A The first electrodeis located in the plasma processing chamberabove the substrate holderand is coupled to the RF source, e.g. through the matching circuit. The second electrodeis located in the plasma processing chamberbelow the substrate holder. In some embodiments, the second electrodeis coupled to ground. In other embodiments, the second electrodeis coupled to another RF source, e.g. through another matching circuit. An electric field is generated between the first electrodeand the second electrode, which act as opposite plates of a capacitor. The electric field ignites and couples power to a plasma in the plasma generating region. The generated plasma can be used for a plasma process such as, for example, an area selective deposition (ASD) process, or another plasma process as described above with respect to.

132 108 110 140 106 106 126 120 122 126 106 108 126 110 110 126 126 As the first electrodemay be located over the substrate holder(and over a mounted substrate), in some embodiments the polarized laser system is positioned to project polarized lightthrough a sidewall of the plasma processing chamberrather than through a top surface of the plasma processing chamber. The polarized light system includes a beam focuserthat is coupled to the laser generatorthrough the polarizing filterby, e.g., an optical fiber or the like. The beam focusermay be positioned at an opening or transparent window into the plasma processing chamberabove a top surface of the substrate holder. As such, the polarized light system may be included with any existing plasma chamber design that is compatible with an opening or transparent window in a suitable position. The beam focuserfocuses the polarized laser beam in order to target a large portion of the substrate, or multiple substrates. In some embodiments, the beam focusercomprises one or more lenses. However, any suitable beam focusermay be used.

2 FIG.B 2 FIG.A 1 1 FIGS.A-B 152 152 150 140 106 152 140 106 illustrates a diagram of an embodiment plasma processing systemthat includes an ellipsometer, in accordance with some embodiments. Although the plasma processing systemis illustrated similar to the plasma processing system(see above,) that operates using capacitively coupled plasma (CCP) with polarized lightprojected through a sidewall of the plasma processing chamber, the plasma processing systemmay also operate using inductively coupled plasma (ICP) and project polarized lightthrough a top surface of the plasma processing chamber(see above,).

122 110 120 122 160 162 160 106 140 110 142 160 162 160 142 140 110 120 160 110 120 160 110 140 142 40 70 120 160 1 FIG.A 2 FIG.A The polarized laser system comprises an ellipsometer in conjunction with a polarizing filter. The ellipsometer may be used to focus on a single spot of the substrate. The ellipsometer comprises a light source (e.g., a laser generator; see above,), a polarizing filter, and a detectorwith associated optics such as an analyzer(e.g., a second polarizing filter) and an optional compensator (e.g., a quarter wave plate) between the detectorand the plasma processing chamber. The polarized lighthits a single spot of the substrate, from which reflected polarized lightis received by the detectorthrough the analyzer. The detectormeasures the change in the polarization of the reflected polarized lightfrom the polarization of the polarized light, which may be used to, for example, provide feedback on the physical properties of the substrate. The vertical positions of the laser generatorand the detectorwith respect to the substratemay be different from their illustration in. For example, in some embodiments, the laser generatorand the detectorare above the substrateso that the incident angle of the polarized lightand the reflected angle of the reflected polarized lightare in a range ofº toº. However, any suitable vertical positions of the laser generatorand the detectormay be used.

1 1 2 2 FIGS.A,B,A andB 100 106 150 152 106 100 106 150 152 106 150 124 106 132 140 108 Althoughillustrate embodiments of the ICP plasma processing systemhaving a polarized light system providing polarized light through a top surface of the plasma processing chamberand the CCP plasma processing systemsandhaving a polarized light system providing polarized light through a sidewall of the plasma processing chamber, in other embodiments the ICP plasma processing systemhas a polarized light system providing polarized light through a sidewall of the plasma processing chamberand the CCP plasma processing systemsandhave a polarized light system providing polarized light through a top surface of the plasma processing chamber. For example, an embodiment of the CCP plasma processing systemmay have a beam expanderpositioned at a top surface of the plasma processing chambersuch that the first electrodedoes not block a path of the polarized lightto the substrate holder.

140 110 108 140 110 130 110 108 100 1 FIG.A Embodiments in which the polarized lightis linearly polarized may enable selectivity to the tops of features (e.g., trench tops) on the substrate. The substrate holdermay be rotated during bombardment with polarized lightto increase uniformity of heating across the substrate. Embodiments in which the polarized lightis circularly polarized may preferentially deliver light to tops of shallow, irregular, or isolated features (e.g., curved waveguides). In some embodiments, non-polarized light may be used at a grazing incidence to target the tops of features on the substrate. Rotating the substrate holderduring polarized light bombardment and using circularly polarized light or non-polarized light at a grazing incidence may also be used in embodiments of the ICP plasma processing system(see above,).

3 4 4 5 6 6 7 7 8 8 9 9 10 10 FIGS.,A,B,,A,B,A,B,A,B,A,B,A andB , illustrate various cross-sectional and top views of intermediate steps of an example semiconductor manufacturing process, in accordance with some embodiments. The example semiconductor manufacturing process demonstrates an area selective deposition (ASD) process over an EUV-patterned metal-based resist (MBR). The ASD process is preceded by a polarized light bombardment to increase selectivity to top surfaces of features. However, embodiments of polarized light bombardments may be used with any suitable ASD process (including processes with non-MBR photoresists that are not patterned with EUV), and all such combinations are within the scope of the disclosed embodiments.

3 FIG. 200 200 202 204 202 202 202 202 202 202 202 200 202 illustrates a cross-sectional view of a semiconductor structure, in accordance with some embodiments. The semiconductor structureincludes a substrateand a target layerover the substrate. In some embodiments, the substrate may be a silicon wafer, or a silicon-on-insulator (SOI) wafer. In certain embodiments, the substrate may comprise a silicon germanium wafer, silicon carbide wafer, gallium arsenide wafer, gallium nitride wafer, and other compound semiconductors. In other embodiments, the substrate comprises heterogeneous layers such as silicon germanium on silicon, gallium nitride on silicon, silicon carbon on silicon, as well layers of silicon on a silicon or SOI substrate. In various embodiments, the substrate is patterned or embedded in other components of the semiconductor device. In various embodiments, the substrate may be a part of a semiconductor device, and may have undergone a number of steps of processing following, for example, a conventional process. The substrate accordingly may comprise layers of semiconductors useful in various microelectronics. For example, the semiconductor structuremay comprise a substrate in which various device regions are formed.

204 206 208 206 202 208 206 206 208 208 206 206 208 206 208 8 8 FIGS.A-B 9 10 FIGS.A-B In some embodiments, the target layerincludes a dielectric layerand a hardmask layer. The dielectric layeris formed over the substrateand the hardmask layeris formed over the dielectric layer. The dielectric layeris the layer to be patterned using the hardmask layeras an etch mask, after the hardmask layerhas been subsequently patterned (see below,). After being patterned, a metallization pattern is formed in trenches through the dielectric layer(see below,). In some embodiments, the dielectric layeris a silicon-based dielectric material with a low dielectric constant (i.e., low-k value) such as organosilicate glass (SiCOH), dense SiCOH, porous SiCOH, and other porous dielectric materials. In some embodiments, the hardmask layercomprises titanium nitride, titanium, titanium oxide, tantalum, tungsten carbide, other tungsten based compounds, ruthenium based compounds, aluminum based compounds, amorphous silicon, silicon nitride, silicon carbide, or the like. However, any suitable materials may be used for the dielectric layerand the hardmask layer.

220 204 220 220 220 In some embodiments, an underlying layeris formed over the target layer. The underlying layermay be a bottom antireflective coating (BARC) that may double as a hardmask layer for etching a portion of a layer below the underlying layer. Examples of materials used for forming the underlying layerinclude spin-on glass (SOG), silicon-containing antireflective coating (SiARC), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), organic BARC, or a combination thereof.

220 230 A first mask material comprising a metal-based resist (MBR) is deposited on the underlying layer, the deposition forming an MBR layer. In some embodiments, the MBR comprises a metal oxide nanoparticle or a nanocluster, the metal comprising hafnium, zirconium, titanium, tin, zinc, indium, or aluminum. The MBR may also include an organometallic complex, where the metal may be antimony, tin, bismuth, tellurium, platinum, palladium, cobalt, iron, or chromium.

230 220 204 220 3 FIG. Generally, the resist layer (e.g., the MBR layer) and the antireflective coating-cum-hardmask (e.g., the underlying layer) are layers of a sacrificial lithography stack that may be patterned and used as an etch mask to pattern a layer below the lithography stack that is included in a device structure. Sometimes, the layer adjacent below the lithography stack may be referred to as a base layer. For example, the target layerdisposed adjacent below the underlying layerinmay be referred to as a base layer.

4 4 FIGS.A andB 3 FIG. 4 4 FIGS.A andB 4 FIG.A 4 FIG.B 200 230 232 232 220 236 232 1 illustrate respective cross-sectional and top views of the semiconductor structurefollowing from, in accordance with some embodiments. In, the MBR layeris patterned using, e.g., an extreme ultraviolet (EUV) lithography process to form a patterned MBR layer, referred to as a first masking layer. The first masking layerexposes a portion of the underlying layerat bottom surfaces of a pattern of trenchesbetween portions of the first masking layer(also referred to as mask lines), as illustrated in cross-sectional view inand in top view in. In some embodiments, trenches 236 have a first width Wthat is half a wavelength of the developing radiation (e.g., EUV light with a wavelength of 13.5 nm), such as in a range of 7 nm to 10 nm. In order to deposit thermal energy during the ASD process, the width W1 is desirably less than half of the light source used for the ASD process. As an example, if a 193 nm ArF laser was used to provide developing radiation, the width W1 would desirably be 96.5 nm or smaller.

5 FIG. 1 1 2 FIGS.A,B and 200 232 200 106 100 150 130 200 232 236 232 232 236 illustrates a cross-sectional view of the semiconductor structureduring a polarized light bombardment. After forming the first masking layer, the semiconductor structureis transferred to a plasma chamber (for example, the plasma processing chamberof an ICP plasma processing systemor a CCP plasma processing system; see above,). Polarized lightis used to bombard the semiconductor structure, thereby preferentially heating top surfaces of the first masking layerwhile not heating bottom surfaces of the trenches. As such, after heating the respective top surfaces of the first masking layerwith polarized light, a temperature of the respective top surfaces of the first masking layeris higher than a temperature of a bottom surface of the trenches.

130 236 130 140 232 232 232 130 130 236 1 1 1 2 FIGS.A,B and 6 6 FIGS.A andB In some embodiments, the polarized lightis linearly polarized with a wavelength that is larger than the first width Wof the trenches. However, any suitable linearly or circularly polarized lightormay be used, as described above with respect to. The differential deposition of thermal energy into top surfaces of the first masking layermay improve a subsequent area selective deposition process (see below,) by, e.g., increasing deposition on top surfaces of the first masking layerrelative to sidewalls of the first masking layer. In some embodiments where the polarized lightis linearly polarized, a polarization direction of the polarized lightis aligned with the pattern of trenches.

6 6 FIGS.A andB 5 FIG. 6 FIG.A 200 240 106 232 220 200 232 240 232 220 232 illustrate respective cross-sectional and top views of the semiconductor structurefollowing from, in accordance with some embodiments. A first plasma is used to deposit a second masking layerin the plasma processing chamber. The first plasma comprises a source gas that reacts chemically selectively with the first masking layerrelative to the underlying layer. The semiconductor structureis exposed to the first plasma to deposit a second mask material selectively on the first masking layer. By proper selection of process parameters of the plasma deposition process, the chemical selectivity of the reaction may be utilized to perform an area selective deposition (ASD) process to form a second masking layer. As illustrated in the cross-sectional view in, the second mask material deposits over the first masking layer(the patterned MBR layer), while a negligible thickness of the second mask material (not illustrated) is formed over a portion of the underlying layernot covered by the first masking layer.

240 4 2 2 In some embodiments, forming the second masking layermay include performing an optional in situ trim etch process that removes a portion of the deposited second mask material. In embodiments where the second mask material comprises a silicon-based material, the trim etch process may be a plasma etch using fluorocarbons, fluorine, chlorine, or hydrogen bromide as an etchant. In embodiments where the second mask material comprises an organic material, the etchant may comprise CO, CH, CO, O, or the like. One purpose for performing the trim etch process is to open a larger portion of the space between resist lines that may be covered by the second mask material along sidewalls of the lines.

6 FIG.A 5 FIG. 240 232 232 232 232 232 240 232 232 250 220 In the example embodiment illustrated in, the completed second masking layerhas a thinner layer of the second mask material along a sidewall of the first masking layercompared to a thickness of the second mask material over a substantially flat top surface of the first masking layer. The preferential deposition of a greater proportion of second mask material on top surfaces of the first masking layercompared to deposition of the second mask material on sidewalls of the first masking layermay be increased by the prior heating of the top surfaces of the first masking layerby polarized light, as described above with respect to. The second mask material and the processes used to form the second masking layermay be selected such that some of the roughness along the sidewall of the first masking layeris smoothed out. The combined first masking layerand the second masking layer forms an etch maskthat may be used in a subsequent etch process to pattern the underlying layer.

4 2 4 4 x 4-x In some embodiments, the ASD process is used to deposit an amorphous material comprising silicon as the second mask material. The first plasma used to deposit the silicon comprises silane (SiF) as the source gas and an inert gas (e.g., argon, nitrogen, or helium) as a diluent gas. In some embodiments using silane as the source gas, the first plasma may include additive gases such as H, SiCl, CH, CHF, or a mixture thereof.

2 4 x 4-x 2, 2 Additionally, the gaseous mixture used for the first plasma may be selected to deposit an organic polymer as the second mask material. The first plasma used to deposit the organic polymer comprises carbon monoxide (CO) as the source gas and an inert diluent gas (e.g., argon, nitrogen, or helium). In some embodiments using CO as the source gas, the first plasma may include additive gases such as H, CH, CHF, COO, or a mixture thereof.

7 7 FIGS.A andB 7 FIG.A 250 232 240 250 220 320 220 250 220 220 220 250 240 240 232 2 2 Next, in, after the etch maskcomprising the first masking layerand the second masking layerhas been formed, an etch process is performed to transfer the pattern of the etch maskto the underlying layer, thereby forming a patterned underlying layer. In some embodiments, the underlying layermay be etched in situ by a plasma etch process by generating a second plasma in the same plasma chamber where the first plasma was generated. In some other embodiments, the pattern transfer etch with the etch maskmay be performed after transferring the substrate to some other processing equipment. The second plasma comprises etchants that remove the material of the underlying layer. For example, if the underlying layercomprises spin-on glass (SOG), silicon-containing antireflective coating (SiARC), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), or silicon oxycarbonitride (SiOCN), the second plasma may be using a fluorine based or a chlorine based etch chemistry. If the underlying layercomprises an organic BARC then the second plasma may comprise a fluorocarbon, HBr, O, CO, CO, or the like. The plasma etching comprises exposing the substrate to the second plasma for a fixed etch duration or terminating the etch process based on an endpoint signal. In some embodiments, the plasma etching may be a substantially anisotropic etching process. As illustrated in, a portion of the etch maskmay be removed by the second plasma by the time the etch process is completed. In this example, a portion of the second masking layerhas been lost during etching. In some other example, the etching may remove the entire second masking layerand, in some instances, a portion of the first masking layer.

5 6 7 FIGS.andA-B 106 The method described with references toillustrate an example embodiment where the polarized light bombardment, the ASD process, and the pattern transfer etch used to form the patterned underlying layer are single step processes. In some other embodiments, a method may be used in which a cyclic deposition and etch process is performed in the plasma process chamberto pattern an underlying layer disposed adjacent below a patterned MBR layer.

7 FIG.C 232 320 240 320 200 320 204 200 240 illustrates an embodiment in which the first masking layerhas been consumed by the etch process and the dimensions of the patterned underlying layerhave been reduced by the etch process. An additional polarized light bombardment and ASD process may be performed to preferentially form additional portions of the second masking layerover the patterned underlying layer. This may regenerate the mask on a partially etched structure (e.g., the semiconductor structure) by preferentially depositing on, e.g., top surfaces and/or upper sidewall portions of lines (such as the lines of the patterned underlying layer). In other words, partially through an etch process to pattern the target layer, the semiconductor structureis bombarded with linearly polarized light again and another ASD process of the second masking layeris performed.

8 8 FIGS.A andB 10 10 FIGS.A-B 204 250 320 236 204 304 250 320 304 306 308 306 Next, in, the target layeris patterned in order to subsequently form a pattern (e.g., a metallization pattern; see below,). The etch mask(if still present) and the patterned underlying layerare used as an etching mask in an etching process (e.g., a wet or dry process) to extend the trenchesthrough the target layer. After the etching process, a patterned target layerremains under the etch mask(if present) and the patterned underlying layer. In some embodiments, the patterned target layercomprises a patterned dielectric layerand a patterned hardmask layeron the patterned dielectric layer.

9 9 FIGS.A andB 312 200 236 304 312 312 312 250 320 312 312 In, a materialis formed over the semiconductor structureto fill the trenchesbetween portions of the patterned target layer. In some embodiments, the materialis a conductive material used to form a metallization pattern. However, the materialmay comprise any suitable material, such as a dielectric material, a conductive material, or a combination thereof, and may be used to form any suitable feature, such as another mask for subsequent patterning processes. In some embodiments, prior to forming the material, the etch mask(if present) and the patterned underlying layermay be removed with a suitable process, e.g. a CMP. In embodiments where the materialis conductive, the materialmay be copper formed using electroplating. However, any suitable conductive material (e.g., tungsten, cobalt, ruthenium, the like, or a combination thereof) and deposition method (e.g., ALD, PVD, or the like) may be used.

10 10 FIGS.A andB 5 6 6 FIGS.andA-B 312 304 314 312 314 314 308 314 306 314 240 232 In, excess materialformed over a top surface of the patterned target layeris removed with a suitable process, e.g. a CMP, to form a pattern. In embodiments where the materialis a conductive material, the patternmay be, for example, a metallization pattern. However, the patternmay also be a mask for subsequent patterning processes. In some embodiments, the patterned hardmask layeris also removed, leaving the patternbetween remaining portions of the patterned dielectric layer. The shape of the patternmay be improved by controlling the ASD process with a polarized light bombardment in order to preferentially deposit more of the second masking layeron top surfaces of the first masking layerin earlier patterning steps (see above,).

11 FIG. 3 4 FIGS.,A 4 FIG.B 400 402 232 202 236 1 illustrates a process flow chart diagram of a methodfor an area selective deposition process, in accordance with some embodiments. In step, a first masking layercomprising a first mask line and a second mask line is formed over a substrate, as described above with respect to, and. A trenchbetween the first mask line and the second mask line has a first width W.

404 130 106 130 1 5 FIGS.A and 1 In step, respective top surfaces of the first mask line and the second mask line are heated with polarized lightin a plasma processing chamber, as described above with respect to. The first width Wis smaller than half a wavelength of the polarized light.

406 240 232 6 6 FIGS.A-B In step, a second masking layeris formed over the first masking layerwith an area selective deposition process, as described above with respect to. The second masking layer is thinner over a sidewall of the first mask line than over a top surface of the first mask line.

12 FIG. 1 5 FIGS.A and 3 4 FIGS.,A 500 502 110 106 232 204 110 4 illustrates a process flow chart diagram of a methodfor manufacturing a semiconductor structure, in accordance with some embodiments. In step, a substrateis placed into a plasma processing chamber, as described above with respect to. A patterned first masking layeris over a target layerof the substrate, as described above with respect to, andB.

504 232 130 236 232 1 5 FIGS.A and In step, the patterned first masking layeris bombarded with linearly polarized light (e.g., polarized light), as described above with respect to. A polarization direction of the linearly polarized light is aligned with a pattern of trenchesthrough the patterned first masking layer.

506 240 232 508 204 240 232 510 314 204 306 6 6 FIGS.A-B 7 8 FIGS.A-B 9 10 FIGS.A-B In step, an area selective deposition of a second masking layerover the patterned first masking layeris performed, as described above with respect to. In step, the target layeris patterned using the second masking layerand the patterned first masking layeras an etching mask, as described above with respect to. In step, a patternis formed between remaining portions of the target layer(e.g., the patterned dielectric layer), as described above with respect to.

Example embodiments of the invention are described below. Other embodiments can also be understood from the entirety of the specification as well as the claims filed herein.

Example 1. A method for an area selective deposition process, the method including: forming a first masking layer over a substrate, the first masking layer including a first mask line and a second mask line, where a trench between the first mask line and the second mask line has a first width; in a plasma processing chamber, heating respective top surfaces of the first mask line and the second mask line with polarized light, where the first width is smaller than half a wavelength of the polarized light; and in the plasma processing chamber, forming a second masking layer over the first masking layer with an area selective deposition process, where the second masking layer is thinner over a sidewall of the first mask line than over a top surface of the first mask line.

Example 2. The method of example 1, where the polarized light is linearly polarized.

Example 3. The method of example 1, where the polarized light is circularly polarized.

Example 4. The method of one of examples 1 to 3, where the polarized light enters the plasma processing chamber through a top surface of the plasma processing chamber.

Example 5. The method of one of examples 1 to 3, where the polarized light enters the plasma processing chamber through a sidewall of the plasma processing chamber.

Example 6. The method of one of examples 1 to 5, where the polarized light is projected into the plasma processing chamber by a digital light projection system.

Example 7. The method of one of examples 1 to 6, where a temperature of the respective top surfaces of the first mask line and the second mask line is higher than a temperature of a bottom surface of the trench after heating the respective top surfaces of the first mask line and the second mask line with polarized light.

Example 8. A method for manufacturing a semiconductor structure, the method including: placing a substrate into a plasma processing chamber, a patterned first masking layer being over a target layer of the substrate; bombarding the patterned first masking layer with linearly polarized light, where a polarization direction of the linearly polarized light is aligned with a pattern of trenches through the patterned first masking layer; performing a first area selective deposition of a second masking layer over the patterned first masking layer; patterning the target layer using the second masking layer and the patterned first masking layer as an etching mask; and forming a pattern between remaining portions of the target layer.

8 Example 9. The method of example, further including, partially through an etch process to pattern the target layer, bombarding the substrate with linearly polarized light and performing a second area selective deposition of the second masking layer.

Example 10. The method of one of examples 8 or 9, where the first area selective deposition forms a greater proportion of material over top surfaces of the patterned first masking layer than over sidewalls of the patterned first masking layer.

Example 11. The method of one of examples 8 to 10, where the plasma processing chamber is part of an inductively coupled plasma processing system.

Example 12. The method of one of examples 8 to 10, where the plasma processing chamber is part of a capacitively coupled plasma processing system.

Example 13. The method of one of examples 8 to 12, where the linearly polarized light is produced by a pulsed laser generator.

Example 14. A plasma processing system including: a plasma processing chamber; a chuck configured to hold a substrate; and an ellipsometer, the ellipsometer configured to provide polarized light to the substrate in the plasma processing chamber, the ellipsometer including a laser generator, a polarizing filter between the laser generator and the plasma processing chamber, a detector, and an analyzer between the detector and the plasma processing chamber.

Example 15. The plasma processing system of example 14, where the ellipsometer is configured to provide polarized light through a top surface of the plasma processing chamber.

Example 16. The plasma processing system of example 14, where the ellipsometer is configured to provide polarized light through a sidewall of the plasma processing chamber.

Example 17. The plasma processing system of one of examples 14 to 16, where the plasma processing chamber includes an antenna over the chuck, the antenna configured to inductively couple power to a plasma.

Example 18. The plasma processing system of one of examples 14 to 17, where the plasma processing chamber includes a first electrode over the chuck and a second electrode under the chuck, the first electrode and the second electrode being configured to capacitively couple power to a plasma.

Example 19. The plasma processing system of one of examples 14 to 18, where the laser generator is configured to produce laser pulses.

Example 20. The plasma processing system of one of examples 14 to 19, where the polarizing filter is a linear filter.

While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.