Hard Mask Trimming in Method for Manufacturing Semiconductor Device

This application is a continuation of U.S. patent application Ser. No. 17/856,376, filed on Jul. 1, 2022, all of which are hereby expressly incorporated by reference into the present application.

In a method for manufacturing a semiconductor device, a self-aligned multiple patterning process, such as a self-aligned double patterning (SADP) process, a self-aligned quadruple patterning (SAQP) process, or the like, is used to form smaller features without using extreme ultraviolet (EUV) lithography. A high dielectric constant (high-k) dielectric material, such as a metal oxide material, is used as a hard mask material in the self-aligned multiple patterning process to replace a photoresist material so as to confer better resistivity to a thermal process, a dry etching process, a wet etching process, or the like.

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

1 FIG. 2 FIG. 1 FIG. 10 10 10 101 102 101 103 101 102 101 102 104 102 103 101 101 102 103 102 103 102 103 104 104 104 102 103 104 105 105 104 102 103 2 2 3 2 The present disclosure is directed to a method for manufacturing a semiconductor device in which a patterned hard mask used for a self-aligned multiple patterning process (for example, but not limited to, a self-aligned double patterning (SADP) process, a self-aligned quadruple patterning (SAQP) process, or the like) is trimmed by a lateral etching process so as to control the dimensions of hard mask portions of the patterned hard mask.is a schematic view illustrating a short-loop structurebefore being trimmed by the lateral etching process, andis a schematic view illustrating the short-loop structureafter being trimmed by the lateral etching process. A short-loop structure is a structure which has a short turn-around time and can produce the desired test results quickly. Referring to the example illustrated in, the short-loop structureincludes a substrate; a plurality of strip portionsdisposed on the substrateand spaced apart from each other; a plurality of spacersdisposed on the substrateto separate the strip portionsfrom the substrate, spaced apart from each other, and laterally cover the strip portions, respectively; and a plurality of hard mask portionsdisposed on the strip portionsand the spacers, respectively. In some embodiment, the substrateincludes, for example, but not limited to, silicon, or the like. Other materials suitable for the substrateare within the contemplated scope of the present disclosure. In some embodiments, the strip portionsinclude a first dielectric material, and the spacersinclude a second dielectric material which has an etch selectivity different from that of the first dielectric material. In some embodiments, the strip portionsinclude silicon oxide (SiO), or the like, and the spacersinclude silicon nitride (SiN), silicon carbon nitride (SiCN), silicon carbon oxynitride (SiOCN), or the like. Other materials suitable for the strip portionsand the spacersare within the contemplated scope of the present disclosure. In some embodiments, the hard mask portionsinclude a high-k dielectric material, for example, but not limited to, hafnium-based (Hf-based) dielectric materials, zirconium-based (Zr-based) dielectric materials, aluminum-based (Al-based) dielectric materials, or the like, or combinations thereof. In some embodiments, the hard mask portionsmay include a metal oxide material, for example, but not limited to, hafnium oxide (HfO), aluminum oxide (AlO), zirconium oxide (ZrO), or the like, or combinations thereof. Other metal oxide materials suitable for the hard mask portionsare within the contemplated scope of the present disclosure. Each of the strip portionscooperates with a corresponding one of the spacersand a corresponding one of the hard mask portionsto constitute a fin feature. The fin featureincludes a fin portion and a corresponding one of the hard mask portionsdisposed on the fin portion. The fin portion includes one of the strip portionsand a corresponding one of the spacers.

104 1 1 104 104 1 1 104 105 2 2 105 102 2 2 102 105 105 105 In some embodiments, each of the hard mask portionshas a width (W) ranging from about 10 nm (nanometers) to about 20 nm. In some embodiments, the width (W) of each of the hard mask portionsranges from about 14 nm to about 18 nm. In some embodiments, each of the hard mask portionshas a height (H) ranging from about 20 nm to about 36 nm. In some embodiments, the height (H) of each of the hard mask portionsranges from about 26 nm to about 30 nm. In some embodiments, the fin featurehas a height (H) ranging from about 80 nm to about 92 nm. In some embodiments, the height (H) of the fin featureranges from about 84 nm to about 88 nm. In some embodiments, each of the strip portionshas a width (W) ranging from about 5 nm to about 9 nm. In some embodiments, the width (W) of each of the strip portionsranges from about 6 nm to about 8 nm. In some embodiments, a fin-to-fin critical dimension (D) of the fin features(i.e., a spacing distance between two adjacent ones of the fin features) ranges from about 20 nm to about 80 nm. In some embodiments, the fin-to-fin critical dimension (D) of the fin featuresranges from about 40 nm to about 60 nm.

2 FIG. 3 FIG. 10 104 104 105 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 104 Referring to the example illustrated in, which is a schematic view illustrating the short-loop structureafter the lateral etching process, lateral portions of each of the hard mask portionsare trimmed by the lateral etching process, and a top part of each of the hard mask portionsmay be etched away by the lateral etching process. In some embodiments, the lateral etching process is an anisotropic etching process, in which a lateral etching rate is larger than a vertical etching rate.is a schematic view illustrating a comparison of dimension of the fin featurebefore and after the lateral etching process. In some embodiments, a lateral etch amount of each of the hard mask portionsranges from about 2 nm to about 7 nm. In some embodiments, the lateral etch amount of each of the hard mask portionsranges from about 3 nm to about 6 nm. In some embodiments, the lateral etch amount of each of the hard mask portionsranges from about 4 nm to about 5 nm. The lateral etch amount is defined as a thickness of a lateral portion of each of the hard mask portionsetched away by the lateral etching process. In some embodiments, a top lost amount of each of the hard mask portionsranges from about 0 nm to about 6 nm. In some embodiments, the top lost amount of each of the hard mask portionsrange from about 0 nm to about 5 nm. In some embodiments, the top lost amount of each of the hard mask portionsranges from about 0 nm to about 4 nm. The top lost amount is defined as a thickness of a top part of each of the hard mask portionsetched away by the lateral etching process. It is desirable for the hard mask portionstrimmed by the lateral etching process to have a minimal top lost amount. In some embodiments, a sidewall roughness (LWR, i.e., line width roughness) of each of the hard mask portionsranges from about 0 nm to about 2 nm. In some embodiments, the sidewall roughness of each of the hard mask portionsranges from about 0 nm to about 1.5 nm. The line width roughness (LWR) generally refers to a roughness of a width of a line of material in a semiconductor device, for example, during a fabrication process. Evaluation of the line width roughness may be performed by analyzing top-down scanning electron microscope (SEM) images to derive a 3σ deviation from the mean roughness of each of the hard mask portions. In some embodiments, an etch stop ratio of the hard mask portionsranges from about 0% to about 5%. In some embodiments, the etch stop ratio of the hard mask portionsranges from about 0% to about 4%. In some embodiments, the etch stop ratio of the hard mask portionsranges from about 0% to about 3%. The etch stop ratio is defined as a ratio of a number of the hard mask portionswith an etch stop failure (i.e., having the lateral etch amount of less than 0.5 nm) to a total number of the hard mask portionstrimmed by the lateral etching process.

4 FIG. 2 3 3 2 2 3 4 2 5 2 4 2 2 3 3 2 2 4 2 5 2 6 2 3 2 2 2 2 3 2 4 2 3 3 2 2 3 4 2 5 2 4 2 2 3 3 2 2 4 2 5 2 6 2 3 2 2 2 2 3 2 4 3 3 2 104 In some embodiments, the lateral etching process may include a radical etching process and a chemical etching process.shows a schematic view illustrating a reaction mechanism of the lateral etching process conducted by the radical etching process and the chemical etching process. In some embodiments, an etchant gas for the radical etching process includes a hydrogen gas (H) and a fluoride gas. In some embodiments, the fluoride gas may include, for example, but not limited to, nitrogen fluoride (NF), methyl fluoride (CHF), difluoromethane (CHF), trifluoromethane (CHF), perfluoromethane (CF), ethyl fluoride (CHF), difluoroethane (CHF), trifluorocthane (CHF), tetrafluorocthane (CHF), pentafluoroethane (CHF), perfluoroethane (CF), vinyl fluoride (CHF), difluoroethylene (CHF), trifluoroethylene (CHF), tetrafluoroethylene (CF), or combinations thereof. In some embodiments, an etchant gas for the chemical etching process includes a chloride gas. In some embodiments, the chloride gas may include, for example, but not limited to, chlorine (Cl), hydrogen chloride (HCl), boron chloride (BCl), methyl chloride (CHCl), dichloromethane (CHCl), trichloromethane (CHCl), perchloromethane (CCl), ethyl chloride (CHCl), dichloroethane (CHCl), trichloroethane (CHCl), tetrachloroethane (CHCl), pentachloroethane (CHCl), perchloroethane (CCl), vinyl chloride (CHCl), dichloroethylene (CHCl), trichloroethylene (CHCl), tetrachloroethylene (CCl), or combinations thereof. The reaction mechanism of the lateral etching process conducted by the radical etching process and the chemical etching process is also illustrated below, in which the fluoride gas is exemplified by nitrogen fluoride (NF) and the chloride gas is exemplified by boron chloride (BCl). The hard mask portionsto be trimmed by the lateral etching process are exemplified by hard mask portions made of hafnium oxide (HfO).

4 FIG. 2 3 2 4 2 3 4(g) 3(g) As shown inand the reaction mechanism illustrated above, in the radical etching process, hafnium oxide (HfO) is subjected to fluorination with hydrogen fluoride (HF), which is produced by recombination of fluoride (F) radicals with hydrogen (H) radicals respectively formed from nitrogen fluoride (NF) and hydrogen (H), to form hafnium fluoride (HfF) and water vapor (HO). Hafnium fluoride is deposited on hafnium oxide, and the water vapor is evaporated. In the chemical etching process, hafnium fluoride formed from the fluorination is then subjected to chlorination with boron chloride (BCl) to form hafnium chloride (HfCl) and boron fluoride (BF), both of which can be removed, for example, but not limited to, under vacuum. The radical etching process and the chemical etching process may be performed alternately. That is, a plurality of cycles of alternating the radical etching process and the chemical etching process may be performed.

5 FIG. 5 FIG. 104 104 2 3 4 2 1 1 4 2 1 1 2 3 104 104 104 104 104 is a graph plot illustrating relationship of the sidewall roughness (i.e., LWR) of the hard mask portionsversus a ratio value of the fluoride gas to the hydrogen gas (i.e., fluoride/hydrogen) and a pressure of the chloride gas based on a substantially identical lateral etch amount of the hard mask portions(HK EA). Tests T, T, Tare conducted at a ratio value of the fluoride gas to the hydrogen gas (R) being less than that (R) for Test T, and Test Tis conducted at a pressure of the chloride gas (P) being greater than that (P) for Tests T, T, T. As shown by the graph plot illustrated in, the sidewall roughness (i.e., LWR) of the hard mask portionscan be reduced effectively by reducing the ratio value of the fluoride gas to the hydrogen gas used in the radical etching process and by increasing the pressure of the chloride gas used in the chemical etching process. In some embodiments, the sidewall roughness (i.e., LWR) of the hard mask portionscan be reduced from a value ranging from about 3.3 nm to about 3.5 nm to a value ranging from about 2.2 nm to about 1.6 nm by reducing the ratio value of the fluoride gas to the hydrogen gas from a ratio value ranging from about 7/40 to about 9/40 to a ratio value ranging from about 2/40 to about 1/40, based on a lateral etch amount ranging from about 4.2 nm to about 3.8 nm of the hard mask portions. In some embodiments, the sidewall roughness (i.e., LWR) of the hard mask portionscan be reduced by a value ranging from about 1.2 nm to about 1.4 nm by reducing the ratio value of the fluoride gas to the hydrogen gas by a value ranging from about 6/40 to about 8/40, based on a lateral etch amount ranging from about 4.2 nm to about 3.8 nm. In some embodiments, the sidewall roughness (i.e., LWR) of the hard mask portionscan be reduced by a value ranging from about 0.1 nm to about 0.3 nm by increasing the pressure of the chloride gas by a value ranging from about 7 Torr to about 9 Torr, based on a lateral etch amount ranging from about 4.2 nm to about 3.8 nm.

6 FIG. 104 104 104 104 104 104 104 104 104 104 104 104 Referring to, which is a schematic view illustrating the lateral etching process conducted by the radical etching process (i.e., the fluorination) and the chemical etching process (i.e., the chlorination), a plurality of cycles of alternating the radical etching process and the chemical etching process described above are conducted in a chamber. The lateral etching process is an etching process similar to an atomic layer etching process. In some embodiments, the radical etching process and the chemical etching process are conducted at a temperature ranging from about 200° C. to about 500° C. If the radical etching process and the chemical etching process are conducted at a temperature greater than 500° C., the etching rate of the hard mask portionsmay be too fast and the etch selectivity may be worsened. If the radical etching process and the chemical etching process are conducted at a temperature less than 200° C., the etching rate of the hard mask portionsmay be too slow. In some embodiments, the radical etching process is conducted at a power ranging from about 250 W to about 500 W. If the radical etching process is conducted at a power greater than 500 W, the etching rate of the hard mask portionsmay be too fast and the etch selectivity may be worsened. If the radical etching process is conducted at a power less than 250 W, the etching rate of the hard mask portionsmay be too slow. In some embodiments, the radical etching process is conducted at a pressure ranging from about 2000 mTorr to about 5000 mTorr. If the radical etching process is conducted at a pressure greater than 5000 mTorr, the etching rate of the hard mask portionsmay be too fast and the etch selectivity may be worsened. If the radical etching process is conducted at a pressure less than 2000 mTorr, the etching rate of the hard mask portionsmay be too slow. In some embodiments, the chemical etching process is conducted at a pressure ranging from about 2000 mTorr to about 24000 mTorr. If the chemical etching process is conducted at a pressure greater than 24000 mTorr, the etching rate of the hard mask portionsmay be too fast and the etch selectivity may be worsened. If the chemical etching process is conducted at a pressure less than 2000 mTorr, the etching rate of the hard mask portionsmay be too slow. In some embodiments, the radical etching process is conducted at a flow rate of the fluoride gas ranging from about 15 sccm to about 200 sccm and a flow rate of the hydrogen gas ranging from about 1000 sccm to about 2400 sccm. If the radical etching process is conducted at a flow rate of the fluoride gas being greater than 200 sccm and/or a flow rate of the hydrogen gas being greater than 2400 sccm, the etching rate of the hard mask portionsmay be too fast and the etch selectivity may be worsened. If the radical etching process is conducted at a flow rate of the fluoride gas being less than 15 sccm and/or a flow rate of the hydrogen gas being less than 1000 sccm, the etching rate of the hard mask portionsmay be too slow. In some embodiments, the chemical etching process is conducted at a flow rate of the chloride gas ranging from about 200 sccm to about 500 sccm. If the chemical etching process is conducted at a flow rate of the chloride gas being greater than 500 sccm, the etching rate of the hard mask portionsmay be too fast and the etch selectivity may be worsened. If the chemical etching process is conducted at a flow rate of the chloride gas being less than 200 sccm, the etching rate of the hard mask portionsmay be too slow. In some embodiments, an inert diluent gas may be used in the radical etching process and the chemical etching process. In some embodiments, the inert diluent gas may include, for example, but not limited to, argon (Ar), helium (He), or a combination thereof. Other suitable materials are within the contemplated scope of the present disclosure. In some embodiments, a flow rate of the inert diluent gas ranges from about 500 sccm to about 2000 sccm.

7 FIG. 2 3 3 2 2 3 4 2 5 2 4 2 2 3 3 2 2 4 2 5 2 6 2 3 2 2 2 2 3 2 4 2 3 2 104 In some embodiments, the lateral etching process may include a radical or plasma etching process and a cleaning process.shows a schematic view illustrating a reaction mechanism of the lateral etching process conducted by the radical etching process and the cleaning process. The radical etching process is similar to the plasma etching process except that in the radical etching process, plasmas (which include ions and radicals) are subjected to a filtering process using an ion shield to filter the ions out of the plasmas such that only the radicals are introduced into a chamber for the etching process. In some embodiments, an etchant gas for the radical or plasma etching process includes a chloride gas. In some embodiments, the chloride gas may include, for example, but not limited to, chlorine (Cl), hydrogen chloride (HCl), boron chloride (BCl), methyl chloride (CHCl), dichloromethane (CHCl), trichloromethane (CHCl), perchloromethane (CCl), ethyl chloride (CHCl), dichloroethane (CHCl), trichloroethane (CHCl), tetrachloroethane (CHCl), pentachloroethane (CHCl), perchloroethane (CCl), vinyl chloride (CHCl), dichloroethylene (CHCl), trichloroethylene (CHCl), tetrachloroethylene (CCl), or combinations thereof. In some embodiments, a cleaning gas for the cleaning process includes oxygen gas (O). The reaction mechanism of the lateral etching process conducted by the radical etching process and the cleaning process is also illustrated below. The chloride gas for the radical etching process is exemplified by boron chloride (BCl), and the hard mask portionsto be trimmed by the lateral etching process is exemplified by hard mask portions made of hafnium oxide (HfO).

7 FIG. 3 2 4 x x 3 x 104 As shown inand the reaction mechanism illustrated above, in the radical etching process, BClgas is dissociated into BCl* radicals and Cl* radicals. Hafnium oxide (HfO) is reacted with Cl* radicals to form hafnium chloride (HfCl) gas, which may be removed, for example, but not limited to, under vacuum. BCl* radicals are combined with each other to form BClpolymer that is deposited on hafnium oxide. In the cleaning process using the oxygen gas, BClpolymer is reacted with O* radicals to form BOCl gas and (BOCl)gas, which can be removed, for example, but not limited to, under vacuum, so as to clean BClpolymer from surfaces of the hard mask portions. The radical etching process and the cleaning process may be performed alternately. That is, a plurality of cycles of alternating the radical etching process and the cleaning process may be performed.

8 FIG. 104 104 104 104 104 104 104 104 104 104 104 104 104 104 x Referring to, which is a schematic view illustrating the lateral etching process conducted by the radical or plasma etching process and the cleaning process, a plurality of cycles of alternating the radical or plasma etching process and the cleaning process as described above are conducted in a chamber. In some embodiments, the plasma or radical etching process and the cleaning process are conducted at a temperature ranging from about 50° C. to about 130° C. If the plasma or radical etching process and the cleaning process are conducted at a temperature greater than 130° C., the etching rate of the hard mask portionsmay be too fast and the etch selectivity may be worsened. If the plasma or radical etching process and the cleaning process are conducted at a temperature less than 50° C., the etching rate of the hard mask portionsmay be too slow. In some embodiments, the radical etching process is conducted at a power ranging from about 250 W to about 750 W. If the radical etching process is conducted at a power greater than 750 W, the etching rate of the hard mask portionsmay be too fast and the etch selectivity may be worsened. If the radical etching process is conducted at a power less than 250 W, the etching rate of the hard mask portionsmay be too slow. In some embodiments, the plasma etching process and the cleaning process are conducted at a power ranging from about 250 W to about 1000 W. If the plasma etching process and the cleaning process are conducted at a power greater than 1000 W, the etching rate of the hard mask portionsmay be too fast and the etch selectivity may be worsened. If the plasma etching process and cleaning process are conducted at a power less than 250 W, the etching rate of the hard mask portionsmay be too slow. In some embodiments, the radical etching process is conducted at a pressure ranging from about 2 mTorr to about 15 mTorr. If the radical etching process is conducted at a pressure greater than 15 mTorr, the etching rate of the hard mask portionsmay be too fast and the etch selectivity may be worsened. If the radical etching process is conducted at a pressure less than 2 mTorr, the etching rate of the hard mask portionsmay be too slow. In some embodiments, the plasma etching process and the cleaning process are conducted at a pressure ranging from about 1 mTorr to about 10 mTorr. If the plasma etching process and the cleaning process are conducted at a pressure greater than 10 mTorr, the etching rate of the hard mask portionsmay be too fast and the etch selectivity may be worsened. If the plasma etching process and cleaning process are conducted at a pressure less than 1 mTorr, the etching rate of the hard mask portionsmay be too slow. In some embodiments, the radical etching process is conducted at flow rate of the chloride gas ranging from about 100 sccm to about 400 sccm. If the radical etching process is conducted at a flow rate of the chloride gas being greater than 400 sccm, the etching rate of the hard mask portionsmay be too fast and the etch selectivity may be worsened. If the radical etching process is conducted at a flow rate of the chloride gas being less than 100 sccm, the etching rate of the hard mask portionsmay be too slow. In some embodiments, the plasma etching process is conducted at flow rate of the chloride gas ranging from about 50 sccm to about 200 sccm. If the plasma etching process is conducted at a flow rate of the chloride gas being greater than 200 sccm, the etching rate of the hard mask portionsmay be too fast and the etch selectivity may be worsened. If the plasma etching process is conducted at a flow rate of the chloride gas being less than 50 sccm, the etching rate of the hard mask portionsmay be too slow. In some embodiments, the cleaning process is conducted at flow rate of the oxygen gas ranging from about 25 sccm to about 100 sccm. If the cleaning process is conducted at a flow rate of the oxygen gas being less than 25 sccm, etching byproducts (for example, but not limited to, BClpolymer) would not be removed effectively. In some embodiments, an inert diluent gas may be used in the plasma etching process and the cleaning process. In some embodiments, the inert diluent gas may include, for example, but not limited to, argon (Ar). Other suitable materials are within the contemplated scope of the present disclosure. In some embodiments, a flow rate of the inert diluent gas ranges from about 10 sccm to about 200 sccm.

9 12 FIGS.to 2 FIG. 9 FIG. 10 11 FIGS.and 9 FIG. 11 FIG. 12 FIG. 9 FIG. 11 FIG. 12 FIG. 11 FIG. 10 104 10 104 10 104 10 10 10 10 104 10 10 10 10 each illustrates a fragmentary view of the short-loop structureshown inin which the hard mask portionsare laterally trimmed by the lateral etching process conducted by the radical etching process (i.e., the fluorination) and the chemical etching process (i.e., the chlorination). In the short-loop structurehaving the configuration shown in, the hard mask portionsobtained after the lateral etching process have a relatively large sidewall roughness which is greater than an upper limit of the aforesaid range of the sidewall roughness, and a relatively large top lost amount which is greater than an upper limit of the aforesaid range of the top lost amount, because the radical etching process (i.e., the fluorination) is conducted at a relatively large flow rate of the fluoride gas. In the short-loop structureshaving the configurations respectively shown in, the hard mask portionsobtained after the lateral etching process have a relatively small sidewall roughness, which is slightly greater than the upper limit of the aforesaid range of the sidewall roughness or is within the aforesaid range of the sidewall roughness, and a relatively small top lost amount, which is within the aforesaid range of the top lost amount, because the radical etching process (i.e., the fluorination) is conducted at a flow rate of the fluoride gas being less than that used to obtain the short-loop structurehaving the configuration shown in. However, an etch stop (i.e., an un-etched sidewall) may be found in the short-loop structures, as shown in the short-loop structureshaving the configuration shown in. In the short-loop structurehaving the configuration shown in, the hard mask portionsobtained after the lateral etching process have a relatively small sidewall roughness, which is within the aforesaid range of the sidewall roughness, and a relatively small top lost amount, which is within the aforesaid range of the top lost amount, because the radical etching process (i.e., the fluorination) is conducted at a flow rate of the fluoride gas being less than that used to obtain the short-loop structurehaving the configuration shown in. In addition, the etch stop found in short-loop structurehaving the configuration shown inis not found in the short-loop structurehaving the configuration shown in, because the chemical etching process (i.e., the chlorination) is conducted at a temperature higher than that of the chemical etching process to form the short-loop structurehaving the configuration shown in.

13 16 FIGS.to 2 FIG. 13 FIG. 14 FIG. 15 16 FIGS.and 15 FIG. 16 FIG. 15 FIG. 16 FIG. 15 FIG. 10 104 10 104 10 104 10 104 104 10 x x each illustrates a fragmentary view of the short-loop structureshown inin which the hard mask portionsare laterally trimmed by the lateral etching process conducted by the radical or plasma etching process with or without the cleaning process. In the short-loop structurehaving the configuration shown in, the hard mask portionsobtained after the lateral etching process conducted by the radical etching process have a top lost amount substantially the same as the lateral etch amount. In the short-loop structurehaving the configuration shown in, the hard mask portionsobtained after the lateral etching process conducted by the plasma etching process are formed with dense byproduct (for example, but not limited to, BClpolymer) disposed thereon, because the lateral etching process is conducted merely by the plasma etching process without the cleaning process (i.e., without using oxygen gas to remove the byproduct). In the short-loop structureshaving the configurations shown in, the hard mask portionsobtained after the lateral etching process conducted by the plasma etching process followed by the cleaning process using oxygen gas, the byproduct (for example, but not limited to, BClpolymer) can be effectively removed. In addition, a comparison of the configuration shown inand that shown inshows that when the plasma etching process is conducted for a relatively long time period, sidewall residues remaining on the hard mask portionsof the configuration shown incan be removed effectively. The sidewall residues are not found in the configuration shown inbecause the plasma etching process is conducted for a relatively long time period, compared to plasma etching process conducted for obtaining the short-loop structureshaving the configuration shown in. In some embodiments, the plasma etching process may be conducted for a time period ranging from about 40 seconds to about 60 seconds.

17 FIG. 18 20 FIGS.to 17 FIG. 200 300 200 300 illustrates a methodfor manufacturing a semiconductor device in accordance with some embodiments in which hard mask portions are laterally trimmed.are schematic views of a semiconductor deviceat some intermediate stages of the manufacturing method as depicted inin accordance with some embodiments. Additional steps can be provided before, after or during the method, and some of the steps described herein may be replaced by other steps or be eliminated. Similarly, further additional features may be present in the semiconductor device, and/or features present may be replaced or eliminated in additional embodiments.

17 FIG. 18 19 FIGS.and 200 201 300 310 320 310 330 310 320 330 340 330 350 340 320 330 351 350 Referring toand the examples illustrated in, the methodbegins at step, where hard mask portions are laterally trimmed. A semiconductor deviceincludes a substrate, a plurality of a nanosheet stacksdisposed on the substrateand spaced apart from each other, a plurality of sacrificial segmentsdisposed on the substratesuch that each of the nanosheet stacksis laterally covered by two corresponding ones of the sacrificial segments, a plurality of dielectric elementseach disposed between two corresponding ones of the sacrificial segmentsand configured as a fin portion, and a plurality of hard mask portionsrespectively disposed on the dielectric elementsso as to permit the nanosheet stacksand the sacrificial segmentsto expose through openingsdefined by the hard mask portions.

310 310 310 310 310 310 In some embodiments, the substratemay be, for example, but not limited to, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a bulk semiconductor substrate, or the like. The substratemay have multiple layers. The substratemay include, for example, elemental semiconductor materials, such as crystalline silicon, diamond, or germanium; compound semiconductor materials, such as silicon carbide, gallium arsenic, indium arsenide, gallium phosphide, indium arsenide, indium phosphide, or indium antimonide; alloy semiconductor materials, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, aluminum gallium arsenide, or gallium indium phosphide; or combinations thereof. The substratemay be intrinsic or doped with a dopant or different dopants. Other materials suitable for the substrateare within the contemplated scope of the present disclosure. In some embodiments, the substrateis a bulk silicon substrate.

320 321 322 321 321 322 321 322 In some embodiments, each of the nanosheet stacksincludes a plurality of first nanosheetsand a plurality of second nanosheetsalternating with the first nanosheets. The first nanosheetsinclude a first semiconductor material, and the second nanosheetsinclude a second semiconductor material having an etch selectivity different from that of the first semiconductor material. In some embodiments, the first semiconductor material is silicon, and the second semiconductor material is silicon germanium (SiGe). Other semiconductor materials suitable for the first nanosheetsand the second nanosheetsare within the contemplated scope of the present disclosure.

330 330 In some embodiments, the sacrificial segmentsincludes a third semiconductor material. In some embodiments, the third semiconductor material is the same as the second semiconductor material. In some embodiments, the sacrificial segmentsinclude, for example, but not limited to, silicon germanium, or the like.

340 341 342 341 330 341 342 342 341 342 Each of the dielectric elementsincludes a first dielectric portionand a second dielectric portiondisposed to separate the first dielectric portionfrom corresponding ones of the sacrificial segments. In some embodiments, the first dielectric portionmay include an oxide material, for example, but not limited to, silicon oxide or the like, and the second dielectric portionmay include a low dielectric constant (low-k) dielectric material. In some embodiments, the second dielectric portionmay include a silicon-based dielectric material, for example, but not limited to, silicon oxide, silicon nitride, silicon oxycarbide, or the like. In some embodiments, the first dielectric portionand the second dielectric portionare made of different dielectric materials.

350 350 In some embodiments, the hard mask portionsinclude a high-k dielectric material, for example, but not limited to, hafnium-based (Hf-based) dielectric materials, zirconium-based (Zr-based) dielectric materials, aluminum-based (Al-based) dielectric materials, or the like, or combinations thereof. In some embodiments, the hard mask portionsmay include metal oxide, for example, but not limited to, hafnium oxide, aluminum oxide, zirconium oxide, or the like, or combinations thereof.

350 350 350 350 340 350 321 350 322 350 340 350 321 350 322 18 FIG. 19 FIG. The hard mask portionsis laterally trimmed by the lateral etching process described above so as to control the dimension thereof. The lateral etching process is indicated by arrows shown in. When the lateral portions of the hard mask portionsare trimmed by lateral etching process, top parts of the hard mask portionsmay be etched away by the lateral etching process. The lateral portions and top parts removed by the lateral etching process are indicated by dotted lines shown in. In some embodiments, the lateral etching process are conducted by the radical etching process (the fluorination) and the chemical etching process (the chlorination) described above. The etch selectivity of the hard mask portionsrelative to the dielectric elementsmay range from about 100 to about 200, the etch selectivity of the hard mask portionsrelative to the first nanosheetsmay range from about 100 to about 200, and the etch selectivity of the hard mask portionsrelative to the second nanosheetsmay range from about 100 to about 200. In some embodiments, the lateral etching process are conducted by the radical or plasma etching process and the cleaning process described above. The etch selectivity of the hard mask portionsrelative to the dielectric elementsmay range from about 100 to about 200, the etch selectivity of the hard mask portionsrelative to the first nanosheetsmay range from about 2 to about 10, and the etch selectivity of the hard mask portionsrelative to the second nanosheetsmay range from about 2 to about 10.

17 FIG. 19 20 FIGS.and 200 202 322 330 360 360 321 321 300 Referring toand the examples illustrated in, the methodproceeds to step, where second nanosheets and sacrificial segments are removed. The second nanosheetsand the sacrificial segmentsare removed by an etching process, for example, but not limited to, a dry etching process or a wet etching process, to form cavitiesfor forming gate structures (not shown) in the cavitiesso that the gate structures surrounds the first nanosheets. The first nanosheetsremaining after the etching process serve as channel portions of the semiconductor device.

In a method for manufacturing a semiconductor device of the present disclosure, a patterned hard mask used for a self-aligned multiple patterning process (for example, but not limited to, a self-aligned double patterning (SADP) process, a self-aligned quadruple patterning (SAQP) process, or the like) is trimmed by a lateral etching process so as to control the dimensions of hard mask portions of the patterned hard mask. In some embodiments, the lateral etching process may be conducted by a radical etching process and a chemical etching process. A plurality of cycles of alternating the radical etching process and the chemical etching process may be performed. In some embodiments, the lateral etching process may be conducted by a radical or plasma etching process and a cleaning process. A plurality of cycles of alternating the radical or plasma etching process and the cleaning process may be performed. The lateral etching process to trim the hard mask portions of the patterned hard mask of the present disclosure can be applied in a front-end-of-line (FEOL) process, a middle-end-of-line (MEOL) process, a back-end-of-line (BEOL) process, or combinations thereof.

In accordance with some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes: forming a patterned hard mask on a patterned structure disposed on a substrate, such that a hard mask portion of the patterned hard mask is disposed on a fin portion of the patterned structure; and laterally trimming the hard mask portion by a lateral etching process which includes a radical etching process and a chemical etching process.

In accordance with some embodiments of the present disclosure, the radical etching process is conducted using an etching gas including a fluoride gas and a hydrogen gas.

In accordance with some embodiments of the present disclosure, the chemical etching process is conducted using an etching gas including a chloride gas.

In accordance with some embodiments of the present disclosure, the radical etching process and the chemical etching process are conducted at a temperature ranging from about 200° C. to about 500° C.

In accordance with some embodiments of the present disclosure, the radical etching process is conducted at a power ranging from about 250 W to about 500 W.

In accordance with some embodiments of the present disclosure, the radical etching process is conducted at a pressure ranging from about 2000 mTorr to about 5000 mTorr.

In accordance with some embodiments of the present disclosure, the chemical etching process is conducted at a pressure ranging from about 2000 mTorr to about 24000 mTorr.

In accordance with some embodiments of the present disclosure, the radical etching process is conducted at a flow rate of the fluoride gas ranging from about 15 sccm to about 200 sccm and a flow rate of the hydrogen gas ranging from about 1000 sccm to about 2400 sccm.

In accordance with some embodiments of the present disclosure, the chemical etching process is conducted at a flow rate of the chloride gas ranging from about 200 sccm to about 500 sccm.

In accordance with some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes: forming a patterned hard mask on a patterned structure disposed on a substrate, such that a hard mask portion of the patterned hard mask is disposed on a fin portion of the patterned structure; laterally trimming the hard mask portion by a lateral etching process which includes a radical etching process, a plasma etching process, or a combination thereof, and a cleaning process.

In accordance with some embodiments of the present disclosure, the radical etching process, the plasma etching process, or the combination thereof is conducted using an etching gas including a chloride gas.

In accordance with some embodiments of the present disclosure, the cleaning process is conducted using an oxygen gas.

In accordance with some embodiments of the present disclosure, the radical etching process, the plasma etching process, or the combination thereof is conducted at a temperature ranging from about 50° C. to about 130° C.

In accordance with some embodiments of the present disclosure, the plasma etching process and the cleaning process are conducted at a power ranging from about 250 W to about 1000 W.

In accordance with some embodiments of the present disclosure, the plasma etching process and the cleaning process are conducted at a pressure ranging from about 1 mTorr to about 10 mTorr.

In accordance with some embodiments of the present disclosure, the plasma etching process is conducted at flow rate of the chloride gas ranging from about 50 sccm to about 200 sccm.

In accordance with some embodiments of the present disclosure, the cleaning process is conducted at flow rate of the oxygen gas ranging from about 25 sccm to about 100 sccm.

In accordance with some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes: forming a patterned hard mask on a patterned structure disposed on a substrate, such that a hard mask portion of the patterned hard mask is disposed on a fin portion of the patterned structure; and laterally trimming the hard mask portion by a lateral etching process, such that the hard mask portion trimmed by the lateral etching process has a lateral etch amount ranging from about 2 nm to about 7 nm.

In accordance with some embodiments of the present disclosure, the hard mask portion trimmed by the lateral etching process has a top lost amount ranging from about 0 nm to about 5 nm.

In accordance with some embodiments of the present disclosure, the hard mask portion trimmed by the lateral etching process has a sidewall roughness ranging from about 0 nm to about 2 nm.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes or structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.