Semiconductor Device and Method of Manufacturing Thereof

Present semiconductor devices and methods for manufacturing semiconductor devices are inadequate, for example resulting in manufacturing processes that are too time-consuming and/or too costly, resulting in semiconductor packages with unreliable connections and/or interconnection structures having suboptimal dimensions, etc. Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such approaches with the present disclosure as set forth in the remainder of the present application with reference to the drawings.

Various aspects of this disclosure provide a semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising a stacked die structure and a method of manufacturing thereof.

The following discussion presents various aspects of the present disclosure by providing examples thereof. Such examples are non-limiting, and thus the scope of various aspects of the present disclosure should not necessarily be limited by any particular characteristics of the provided examples. In the following discussion, the phrases “for example,” “e.g.,” and “exemplary” are non-limiting and are generally synonymous with “by way of example and not limitation,” “for example and not limitation,”and the like.

As utilized herein, “and/or” means any one or more of the items in the list joined by “and/or”. As an example, “x and/or y” means any element of the three-element set {(x), (y), (x, y)}. In other words, “x and/or y” means “one or both of x and y.” As another example, “x, y, and/or z” means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, “x, y and/or z” means “one or more of x, y, and z.”

The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting of the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “includes,” “comprising,” “including,” “has,” “have,” “having,” and the like when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, for example, a first element, a first component or a first section discussed below could be termed a second element, a second component or a second section without departing from the teachings of the present disclosure. Similarly, various spatial terms, such as “upper,” “above,” “lower,” “below,” “side,” “lateral,” “horizontal,” “vertical,” and the like, may be used in distinguishing one element from another element in a relative manner. It should be understood, however, that components may be oriented in different manners, for example a semiconductor device may be turned sideways so that its “top” surface is facing horizontally and its “side” surface is facing vertically, without departing from the teachings of the present disclosure.

It will also be understood that terms coupled, connected, attached, and the like include both direct and indirect (e.g., with an intervening element) coupling, connecting, attaching, etc., unless explicitly indicated otherwise. For example, if element A is coupled to element B, element A may be indirectly coupled to element B through an intermediate signal distribution structure, element A may be directly coupled to element B (e.g., adhered directly to, soldered directly to, attached by direct metal-to-metal bond, etc.), etc.

In the drawings, the dimensions of structures, layers, regions, etc. (e.g., absolute and/or relative dimensions) may be exaggerated for clarity. While such dimensions are generally indicative of an example implementation, they are not limiting. For example, if structure A is illustrated as being larger than region B, this is generally indicative of an example implementation, but structure A is generally not required to be larger than structure B, unless otherwise indicated. Additionally, in the drawings, like reference numerals may refer to like elements throughout the discussion.

Along with a current trend toward smaller and thinner electronic products, it is generally desirable for semiconductor devices employed in such electronic products to have increased functionality and a reduced size. Such goals have resulted in the development of a variety of semiconductor packaging technologies. Examples of such packaging technologies include, PoP (Package-on-Package) configurations in which a semiconductor package is stacked on another package, a PiP (Package-in-Package) configurations in which a semiconductor package is mounted in another package, etc. Such packaging technologies, however, are generally associated with increased package (or device) thickness and relatively complex manufacturing processes, for example involving increased cycle time, increased cost, increased opportunity for defects, etc.

Various aspects of the present disclosure provide a semiconductor device, which may also be referred to herein as a semiconductor package, having a reduced overall thickness and that may facilitate stacking of semiconductor dies, and a fabricating method thereof.

Various aspects of the present disclosure provide a semiconductor device that includes: a first substrate, a first metal pillar on a first side of the first substrate; a first semiconductor die coupled to the first side of the first substrate; a second metal pillar on the first metal pillar; a second semiconductor die coupled to the first semiconductor die; a second substrate on the second metal pillar and on the second semiconductor die; and encapsulating material between the first substrate and the second substrate and encapsulating at least a side of each of the first metal pillar, the first semiconductor die, the second metal pillar and the second semiconductor die.

In various example implementations, the encapsulating material may, for example, include: a first encapsulating material that has a same height as the first metal pillar from the first substrate; and a second encapsulating material that has a same height as the second metal pillar from the second substrate. The first encapsulating material and the second encapsulating material may be formed of a same material. The first encapsulating material and the second encapsulating material may be formed of different materials. The first encapsulating material may, for example, have a greater height than that of the first semiconductor die from the first substrate and may encapsulate the first side of the first semiconductor die.

In various example implementations, the semiconductor device may, for example, include an adhesion member that couples the first and second semiconductor dies to each other. In an example implementation, the encapsulating material may include: a first encapsulating material that has a same height as the first metal pillar from the first substrate; and a second encapsulating material that has a same height as the second metal pillar from the second substrate and surrounds the adhesion member. The adhesion member may, for example, have a same height as the second encapsulating material from the second substrate.

In various example implementations, an active side of the first semiconductor die may be electrically coupled to an active side of the second semiconductor die through at least the first substrate, the first metal pillar, the second metal pillar, and the second substrate.

In various example implementations, the first metal pillar and the second metal pillar may be displaced from each other in a direction perpendicular to a stacking direction in which the first metal pillar and the second metal pillar are stacked; and the semiconductor device comprises a pillar redistribution structure electrically connecting the first metal pillar and the second metal pillar. The encapsulating material may, for example include: a first encapsulating material that has a same height as the first metal pillar from the first substrate; and a second encapsulating material between the first encapsulating material and the second substrate, wherein the pillar redistribution structure is over the first encapsulating material and at least a portion of the pillar redistribution structure is embedded in the second encapsulating material.

In various example implementations, the second semiconductor die may be displaced from the first semiconductor die in a direction perpendicular to a stacking direction in which the first semiconductor die and the second semiconductor die are stacked. Also, in various example implementations, there might be no intervening layers between the first and second metal pillars.

Various aspects of the present disclosure also provide a semiconductor device that includes: a first substrate; a first metal pillar plated on a first side of the first substrate; a first semiconductor die comprising: a first side facing away from the substrate; and a second side facing the substrate, and comprising pads that are connected to the first side of the substrate with conductive bumps; a second metal pillar plated on the first metal pillar; a second semiconductor die comprising: a first side facing away from the first semiconductor die and comprising pads; and a second side coupled to the first side of the first semiconductor die; a second substrate comprising: a first side facing away from the second semiconductor die; and a second side facing the first semiconductor die and comprising a conductive layer connected to the die pads of the second semiconductor die; and encapsulating material between the first substrate and the second substrate and encapsulating at least lateral sides of the first metal pillar, the first semiconductor die, the second metal pillar and the second semiconductor die.

In various example implementations, the encapsulating material may include: a first encapsulating material that has a same height as the first metal pillar from the first substrate; and a second encapsulating material that extends entirely between the first encapsulating material and the second substrate.

In various example implementations, the semiconductor device may comprise an adhesion member that couples the first and second semiconductor dies to each other. The encapsulating material may, for example, include: a first encapsulating material; and a second encapsulating material that has a same height as the adhesion member from the second substrate.

In various example implementations, the second metal pillar may be plated directly on the first metal pillar. In various example implementations, the semiconductor device may comprise a pillar redistribution structure through which the first metal pillar and the second metal pillar are electrically connected.

Various aspects of the present disclosure provide a method of manufacturing a semiconductor device, where the fabricating method includes: providing a first substrate; forming a first metal pillar on a first side of the first substrate; coupling a first semiconductor die to the first side of the first substrate; forming a second metal pillar on the first metal pillar; coupling a second semiconductor die to the first semiconductor die; forming a second substrate on the second metal pillar and on the second semiconductor die; and forming an encapsulating material between the first substrate and the second substrate that encapsulates at least a side of each of the first metal pillar, the first semiconductor die, the second metal pillar and the second semiconductor die.

Various aspects of the present disclosure will now be described in detail with reference to the accompanying drawings such that they may be readily practiced by those skilled in the art.

1 FIG. 2 2 FIGS.A-J 1 FIG. 1 FIG. 2 2 FIGS.A-J 100 100 shows a flow diagram of an example methodof manufacturing a semiconductor device, in accordance with various aspects of the present disclosure.show cross-sectional views of an example semiconductor device during manufacturing in accordance with the example methodof. The following discussion will generally refer toandtogether.

1 FIG. 1 FIG. 2 2 FIGS.A-J 100 1 2 3 4 5 6 7 8 9 10 11 12 100 Referring to, the example methodof manufacturing a semiconductor device may comprise: (S) forming a first substrate, (S) forming a first metal pillar, (S) attaching a first semiconductor die, (S) forming a first encapsulating material, (S) performing a first thinning, (S) forming a second metal pillar, (S) attaching a second semiconductor die, (S) forming a second encapsulating material, (S) performing a second thinning, (S) forming a second substrate, (S) attaching interconnection structures, and (S) singulating. Various blocks (or steps, stages, processes, etc.) of the example methodillustratedwill be now be described with reference to.

1 FIG. 2 FIG.A 200 100 1 105 110 105 105 105 105 105 a Referring toand the example structureof, the example methodmay, at block S, comprise forming (or providing, receiving, etc.) a carrierand forming a first substrateon the carrier. The carriermay comprise any of a variety of characteristics, non-limiting examples of which are provided herein. The carriermay, for example, comprise a carrier for a single semiconductor device (or package) or may, for example, comprise a wafer or panel on which any number of semiconductor devices (or packages) may be formed. The carriermay, for example, comprise a semiconductor wafer or panel. The carriermay also, for example, comprise a glass wafer or panel, a metal wafer or panel, a ceramic wafer or panel, a plastic wafer or panel, etc.

105 110 110 1 105 110 1 110 110 In an example scenario, the carriermay be received with the first substratealready formed thereon. In such a scenario, the first substrateneed not be formed at block S. In another example scenario, the carriermay be received without the first substrate(or a portion thereof) formed thereon, and block Smay comprising forming the first substrate(or a remaining portion) thereon. Note that the first substratemay also be referred to herein as an interposer.

1 110 110 112 111 113 105 Block Smay, for example, comprise forming the first substratehaving any number of dielectric layers and conductive layers (e.g., signal distribution layers, pad layers, conductive vias, underbump metallization, etc.). In an example implementation, a first substratecomprising a signal distribution layer, a dielectric layer, and a pad (or via) layermay be formed on the carrier.

112 112 110 130 120 The signal distribution layer, which may also be referred to herein as a redistribution layer, a distribution layer, a conductive layer, a trace layer, etc., may comprise any of a variety of materials (e.g., copper, aluminum, nickel, iron, silver, gold, titanium, chromium, tungsten, palladium, combinations thereof, alloys thereof, equivalents thereof, etc.), but the scope of the present disclosure is not limited thereto. The signal distribution layer(or first substrate) may, for example, provide electrical signal pathways between terminals of the first semiconductor dieand respective first metal pillars.

1 112 1 112 112 105 Block Smay comprise forming the signal distribution layerin any of a variety of manners, non-limiting examples of which are presented herein. For example, block Smay comprise forming the signal distribution layerutilizing any one or more of a variety of processes (e.g., electrolytic plating, electroless plating, chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), sputtering or physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, printing, screen printing, lithography, etc.), but the scope of the present disclosure is not limited thereto. The signal distribution layermay, for example, be formed directly on the carrier, on an intervening dielectric layer, etc.

112 1 112 1 105 2 FIG.A In various example scenarios, for example in which the signal distribution layeris electroplated, block Smay comprise forming one or more seed layers prior to electroplating the signal distribution layer. For example, though not shown in, block Smay comprise forming one or more seed layers on the top surface of the carrier. Such seed layer(s) may comprise any of a variety of materials. For example, the seed layer(s) may comprise copper. Also for example, the seed layer(s) may comprise one or more layers of any of a variety of metals (e.g., silver, gold, aluminum, tungsten, titanium, nickel, molybdenum, etc.). The seed layer(s) may be formed utilizing any of a variety of techniques (e.g., sputtering or other physical vapor deposition (PVD) technique, chemical vapor deposition (CVD), electroless plating, electrolytic plating, etc.). The seed layer(s) may, for example, be utilized during a subsequent electroplating process.

105 105 110 110 105 110 Note that in various example implementations, the carriermay be provided (or formed) having an oxide and/or nitride layer (or other dielectric material) thereon, in which case blockmay comprise removing such layer prior to forming the substrate, forming the substrateon such layer, forming another layer on the carrierprior to forming the substrate, etc.

111 3 4 2 The dielectric layermay comprise one or more layers of any of a variety of dielectric materials, for example inorganic dielectric materials (e.g., SiN, SiO, SiON, SiN, oxides, nitrides, combinations thereof, equivalents thereof, etc.) and/or organic dielectric materials (e.g., a polymer, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), a molding material, a phenolic resin, an epoxy, silicone, acrylate polymer, combinations thereof, equivalents thereof, etc.), but the scope of the present disclosure is not limited thereto.

1 111 Block Smay comprise forming the dielectric layerutilizing any one or more of a variety of processes (e.g., spin coating, spray coating, printing, sintering, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), sheet lamination, evaporating, etc.), but the scope of the present disclosure is not limited thereto.

1 111 112 1 1 111 Block Smay, for example, also comprise patterning the dielectric layer, for example forming apertures therein that expose various portions of various conductive layers discussed herein (e.g., the signal distribution layer, other signal distribution layers, conductive layers, pad layers, etc.). For example, block Smay comprise ablating apertures (e.g., utilizing laser ablation, utilizing mechanical ablation, utilizing etching, etc.). Also for example, block Smay comprise originally forming the dielectric layer(e.g., depositing, etc.) having the desired apertures.

113 The pad (or via) layer, which may also be referred to herein as a pad, a via, a trace, a land, a bond pad layer, a conductive layer, a trace layer, etc., may comprise any of a variety of materials (e.g., copper, aluminum, nickel, iron, silver, gold, titanium, chromium, tungsten, palladium, combinations thereof, alloys thereof, equivalents thereof, etc.), but the scope of the present disclosure is not limited thereto.

1 113 1 113 1 113 112 111 111 Block Smay comprise forming the pad (or via) layerin any of a variety of manners, non-limiting examples of which are presented herein. For example, block Smay comprise forming the pad layerutilizing any one or more of a variety of processes (e.g., electrolytic plating, electroless plating, chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), sputtering or physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, printing, screen printing, lithography, etc.), but the scope of the present disclosure is not limited thereto. Block Smay, for example, comprise forming the pad layeron portions of the signal distribution layerexposed by apertures in the dielectric layer, on portions of the dielectric layer, etc.

112 1 113 113 1 112 111 2 FIG.A As with the signal distribution layeror any conductive layer discussed herein, block Smay comprise forming one or more seed layers as part of the processing of forming the pad (or via) layer(e.g., prior to electroplating the pad layer, etc.). For example, though not shown in, block Smay comprise forming one or more seed layers on the top surface of the signal distribution layer, on a top surface and/or aperture surfaces of the dielectric layer, etc.

1 110 Note that although an illustrative set of conductive layers and dielectric layers is shown in the drawings, block Smay comprise forming the first substrateto have any number of such conductive and/or dielectric layers.

105 112 111 113 As discussed herein, the carriermay comprise a silicon (or other semiconductor) wafer. In such case, the signal distribution layer, the dielectric layer, and the pad (or via) layermay be formed in a semiconductor wafer fabrication process (e.g., at a wafer fab facility, etc.). Also for example, any or all of such layers may be formed in a packaging process (e.g., at a semiconductor device packaging facility, etc.) that may, for example, receive a semiconductor wafer as an input to the packaging process.

100 105 105 105 105 105 105 105 At any of a variety of stages of the example method, at least a portion of the carrier(and in some example implementations, all of the carrier) may be removed. Such removing may be performed in any of a variety of manners (e.g., by mechanically grinding a backside of the carrieror a portion thereof, by chemically etching a backside of the carrieror a portion thereof, by performing chemical/mechanical planarization (CMP), etc.). In other example implementations, the carrieror a portion thereof may be removed by peeling, pulling, shearing, etc. Accordingly, the scope of the present disclosure should not be limited by any particular manner of removing all or a portion of the carrier. Note that although the carrieris generally illustrated as a thin layer in the drawings, the carriermay be relatively thick (e.g., providing structural support during various stages of the packaging process) until it is thinned and/or removed.

1 105 110 In general, block Smay comprise forming (or providing or receiving) a carrierand/or forming a first substratethereon. Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular carrier or substrate or by characteristics of any particular manner of forming such a carrier or substrate.

1 FIG. 2 FIG.B 200 100 2 120 110 113 112 b Referring toand the example structureof, the example methodmay, at block S, comprise forming a first metal (or conductive) pillar, or a plurality thereof. The first metal pillarmay, for example, be formed on the first substrate(e.g., on a pad layerthereof, on a signal distribution layerthereof, etc.).

2 120 113 112 110 In an example implementation, block Smay comprise forming the first metal pillarto extend vertically from the pad layer(or the redistribution layer) of the first substrate. Such forming may be performed in any of a variety of manners, non-limiting examples of which are provided herein.

2 120 113 1 111 111 In an example implementation, Block Smay, for example, comprise forming a first metal pillaron a respective interconnection pad of the pad layer(e.g., as formed or received at block S) or on another conductive layer portion. As discussed herein, the respective interconnection pad may, for example, comprise any of a variety of conductive materials (e.g., copper, aluminum, silver, gold, nickel, alloys thereof, etc.). The respective interconnection pad may, for example, be exposed through an aperture in the dielectric layeror another dielectric layer. The dielectric layermay, for example, cover side surfaces of the respective interconnection pad and/or an outer perimeter of the top surface of the respective interconnection pad.

110 120 110 110 a a a. In an example implementation, an under-bump metallization (UBM) structuremay be formed, on which the first metal pillarmay then be formed. The UBM structuremay also be referred to herein as a pillar seed layer

2 1 110 111 112 111 a In an example implementation, Block S(or block S) may comprise forming a UBM seed layer of the UBM structureover the dielectric layerand/or over the portion of the respective interconnection pad of the pad layerthat is exposed through an aperture in the dielectric layer. The UBM seed layer may, for example, comprise any of a variety of conductive materials (e.g., copper, gold, silver, metal, etc.). The UBM seed layer may be formed in any of a variety of manners (e.g., sputtering, electroless plating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, etc.).

2 110 120 120 2 2 a Block Smay, for example, comprise forming a mask (or template) over the UBM seed layer to define a region (or volume) in which one or more UBM layers of the UBM structureand/or the first metal pillar(or other interconnection structure) is to be formed. For example, the mask may comprise a photoresist (PR) material or other material, which may be patterned to cover regions other than the region on which the UBM layer(s) and/or first metal pillarare to be formed. Block Smay then, for example, comprise forming one or more UBM layers on the UBM seed layer exposed through the mask. The UBM layer may comprise any of a variety of materials (e.g., titanium, chromium, aluminum, titanium/tungsten, titanium/nickel, copper, alloys thereof, etc.). Block Smay comprise forming the UBM layer on the UBM seed layer in any of a variety of manners (e.g., electroplating, sputtering, electroless plating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, etc.).

2 120 110 120 120 120 120 120 2 100 120 2 120 a Block Smay then, for example, comprise forming the first metal pillar(or post or other interconnection structure) on the UBM structure(or pillar seed layer). The first metal pillarmay comprise any of a variety of characteristics. For example, the first metal pillarmay be cylinder-shaped, elliptical cylinder-shaped, rectangular post-shaped, etc. The first metal pillarmay, for example, comprise a flat upper end, a concave upper end, or a convex upper end. The first metal pillarmay, for example, comprise any of the materials discussed herein with regard to the conductive layers. In an example implementation, the first metal pillarmay comprise copper (e.g., pure copper, copper with some impurities, etc.), a copper alloy, etc.). In an example implementation, block S(or another block of the example method) may also comprise forming a solder cap (or dome) on the first metal pillar. Block Smay comprise forming the first metal pillarin any of a variety of manners (e.g., electroplating, electroless plating, chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), sputtering or physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, printing, screen printing, lithography, etc.), but the scope of the present disclosure is not limited thereto.

120 2 2 120 120 110 a. After forming the first metal pillar, block Smay comprise stripping or removing the mask (e.g., chemical stripping, ashing, etc.), if a mask is utilized. Additionally, block Smay comprise removing at least a portion of the UBM seed layer (e.g., at least the portion that is not covered by the first metal pillar(e.g., by chemically etching, etc.)). Note that during the etching of the UBM seed layer, a lateral edge portion of at least the UBM seed layer under the UBM layer may, for example, be etched. Such etching may, for example, result in an undercut beneath the first metal pillarand the UBM layer of the UBM structure

1 FIG. 2 FIG.C 2 FIG.C 200 100 3 130 110 130 131 130 110 131 110 131 130 112 132 3 130 110 c Referring toand the example structureof, the example methodmay, at block S, comprise attaching a first semiconductor dieto a top side (or portion) of the first substrate. The first semiconductor diemay, for example, be oriented in a manner in which an active side(e.g., on which semiconductor is generally formed) of the first semiconductor diefaces the first substrateand an inactive side opposite the active sidefaces away from the first substrate. Note that the active sidemay also be referred to as a conductive side (e.g., comprising die bond pads electrically connected to semiconductor circuitry of the die) and the inactive side may also be referred to as a non-conductive side (or non-patterned side). For example, as illustrated in, the lower side of the first semiconductor diemay be attached to interconnection pads of the pad layerwith conductive bumps(e.g., C4 bumps, microbumps, metal pillars, conductive balls, etc.). Block Smay comprise attaching the first semiconductor dieto the top side of the first substratein any of a variety of manners (e.g., mass reflow, thermocompression bonding, direct metal-to-metal intermetallic bonding, laser soldering, conductive epoxy bonding, etc.).

130 110 130 110 The first semiconductor diemay, for example, be centered on the substrate, but may also be laterally offset. For example, a plurality of the first semiconductor diemay be attached to the substrateto be included in a same packaged semiconductor device.

130 110 120 120 120 130 120 100 Note that the first semiconductor die, for example when attached to the substrate, may be taller than the first metal pillar, shorter than the first metal pillar, or generally the same height as the first metal pillar. As discussed herein, the tops of the semiconductor dieand/or of the first metal pillar(s)may be planarized at any of a variety of stages of the method.

130 160 130 The first semiconductor die(as with the second semiconductor diediscussed herein) may comprise any of a variety of circuit characteristics. For example, the first semiconductor diemay comprise electrical circuits, such as central processing units (CPUs), digital signal processors (DSPs), network processors, power management units, audio processors, RF circuits, wireless baseband system on chip (SoC) processors, sensors, application specific integrated circuits (ASICs), volatile and/or non-volatile memory, etc.

1 FIG. 2 FIG.D 200 100 4 140 4 140 d Referring toand the example structureof, the example methodmay, at block S, comprise forming a first encapsulating material. Block Smay comprise forming the first encapsulating material(or encapsulant) in any of a variety of manners, non-limiting examples of which are provided herein.

140 140 111 The first encapsulating materialmay comprise any of a variety of encapsulating or molding materials (e.g., resin, polymer, polymer composite material, polymer with filler, epoxy resin, epoxy resin with filler, epoxy acrylate with filler, silicone resin, combinations thereof, equivalents thereof, etc.). The first encapsulating materialmay also, for example, comprise any of the dielectric materials discussed herein (e.g., with regard to the dielectric layer, etc.).

4 140 4 140 111 Block Smay comprise forming the first encapsulating materialin any of a variety of manners (e.g., compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, paste printing, film assisted molding, etc.). Also for example, block Smay comprise forming the first encapsulating materialutilizing any of a variety of techniques that may be utilized to form a dielectric layer, examples of which are provided herein (e.g., with regard to forming the dielectric layer, etc.).

2 FIG.D 2 FIG.D 140 110 110 140 130 120 140 130 120 140 130 140 110 130 As shown in, the first encapsulating materialmay cover a top side of the substrate(e.g. any dielectric and/or conductive layer that is exposed at the top side of the substrate). The first encapsulating materialmay also cover, in-whole or in-part, the lateral sides of the first semiconductor die(or plurality thereof) and/or the lateral sides of the first metal pillar(or plurality thereof). The first encapsulating materialmay be formed to also cover the top sides of the first semiconductor dieand/or of the first metal pillar. Thoughand other drawings herein show the first encapsulating materialonly covering the top side of the first substrate, it should be understood that the first encapsulating materialmay also be formed to cover lateral sides of the first substrate(e.g., following separation of the first substratefrom a wafer or panel or other set of substrates).

140 130 140 130 Note that the first encapsulating materialmay also underfill the first semiconductor die, and/or an underfill separate from the first encapsulating materialmay be applied during and/or after the attaching of the first semiconductor die. For example, such underfill may comprise any of a variety of types of material, for example, an epoxy, a thermoplastic material, a thermally curable material, polyimide, polyurethane, a polymeric material, filled epoxy, a filled thermoplastic material, a filled thermally curable material, filled polyimide, filled polyurethane, a filled polymeric material, a fluxing underfill, and equivalents thereof, but not limited thereto. Such underfilling may be performed utilizing a capillary underfill process, utilizing a pre-applied underfill, etc.

1 FIG. 2 FIG.E 2 FIG.E 200 100 5 4 5 140 5 130 120 5 140 130 120 130 120 140 130 140 140 130 e Referring toand the example structureof, the example methodmay, at block S, comprise thinning the assembly as encapsulated at block S(e.g., performing a first thinning operation, etc.). For example, block Smay comprise thinning (e.g., mechanically grinding, chemically etching, shaving or shearing, peeling, any combination thereof, etc.) a top side of the first encapsulating materialto a desired thickness. Block Smay, for example, comprise thinning (e.g., mechanically grinding, chemically etching, shaving, peeling, any combination thereof, etc.) the first semiconductor die(or plurality thereof) and/or the first metal pillar(or plurality thereof). In the example implementation shown in, block Scomprises performing the thinning in a manner that results in coplanar top surfaces of the first encapsulating material, the first semiconductor die(s), and/or the first metal pillar(s). Thus, at least respective top surfaces (and/or at least an upper portion of lateral side surfaces) of the first semiconductor die(s)and the first metal pillar(s), are exposed from (or at) the top surface of the first encapsulating material. Note that while the example implementation shows the top side of the first semiconductor dieexposed from the first encapsulating material, such exposure is not required. For example, in various implementations, a thin layer of the first encapsulating materialcovering the top side of the first semiconductor diemay remain.

1 5 In various example implementations, blocks S-S(and/or the resulting structure) may share any or all characteristics with generally analogous blocks (and/or the resulting structures) shown in U.S. patent application Ser. No. 14/823,689, filed on Aug. 11, 2016, and titled “Semiconductor Package and Fabricating Method Thereof,” the entirety of which is hereby incorporated herein by reference in its entirety for all purposes.

1 FIG. 2 FIG.F 200 100 6 150 120 150 120 f Referring toand the example structureof, the example methodmay, at block S, comprise forming a second metal pillar (or a plurality thereof). The second metal pillarmay, for example be formed on the first metal pillar(e.g., directly on, indirectly on with one or more intervening layers, etc.). Also for example, each of a plurality of second metal pillarsmay be formed on a respective one of a plurality of the first metal pillars.

6 150 120 6 150 120 2 6 150 120 In an example implementation, block Smay comprise forming the second metal pillarto extend vertically from the first metal pillar. Such forming may be performed in any of a variety of manners, non-limiting examples of which are provided herein. For example, block Smay comprise forming the second metal pillarin the same manner in which the first metal pillarwas formed at block S. Also for example, Block Smay comprise forming the second metal pillarin a different manner than that in which the first metal pillarwas formed.

6 150 120 120 120 140 140 120 120 In an example implementation, Block Smay, for example, comprise forming a second metal pillaron (e.g., directly on or indirectly on) a respective first metal pillar. As discussed herein, the first metal pillarmay, for example, comprise any of a variety of conductive materials (e.g., copper, aluminum, silver, gold, nickel, alloys thereof, etc.). The first metal pillar(e.g., a top surface thereof, a top portion of a lateral surface thereof, etc.) may, for example, be exposed at a top surface of the first encapsulating material. The first encapsulating materialmay, for example, cover a lower portion or all of a lateral side surface of the first metal pillarand/or may cover an outer perimeter of the top surface of the first metal pillar.

6 150 120 150 120 150 120 In an example implementation, block Smay comprise forming the second metal pillardirectly on the top surface of the first metal pillar. Note that the lateral and/or vertical dimensions (and/or shape) of the second metal pillarmay match the lateral and/or vertical dimensions (and/or shape) of the respective first metal pillar, but this need not be the case. For example, the second metal pillarmay comprise smaller or larger lateral and/or vertical dimensions that the first metal pillar.

120 150 6 110 2 a In another example implementation, an under-bump metallization (UBM) structure (or interface layer structure) may be formed on the first metal pillar, and the second metal pillarmay then be formed on the UBM structure. If formed, block Smay comprise forming such a UBM structure (or interface layer structure) in a same manner as that discussed herein with regard to the UBM structure(or pillar seed layer) that may be formed at block S, for example utilizing the same or similar masking process, metal forming process, masking and/or metal removing process, etc.

150 150 150 150 120 150 6 100 150 6 150 The second metal pillarmay comprise any of a variety of characteristics. For example, the second metal pillarmay be cylinder-shaped, elliptical cylinder-shaped, rectangular post-shaped, etc. The second metal pillarmay, for example, comprise a flat upper (and/or lower) end, a concave upper (and/or lower) end, or a convex upper (and/or lower) end. The second metal pillarmay, for example, comprise any of the materials discussed herein with regard to the conductive layers, with regard to the first metal pillar, etc. In an example implementation, the second metal pillarmay comprise copper (e.g., pure copper, copper with some impurities, etc.), a copper alloy, etc.). In an example implementation, block S(or another block of the example method) may also comprise forming a solder cap (or dome) or layer of another metal on the second metal pillar. Block Smay comprise forming the second metal pillarin any of a variety of manners (e.g., electroplating, electroless plating, chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), sputtering or physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, printing, screen printing, lithography, etc.), but the scope of the present disclosure is not limited thereto.

150 150 120 150 120 150 120 150 120 As discussed herein, the second metal pillar(or a plurality thereof) may be exactly aligned with a respective first metal pillar, but such alignment may also be misaligned (e.g., by design or due to manufacturing tolerances). Thus, there may be a surface discontinuity between the second metal pillarand the first metal pillar(e.g., a step, a sharp curve, etc.). Note that, as discussed herein, the second metal pillarmay be laterally displaced from the first metal pillarso that there is no direct vertical overlap between the second metal pillarand the first metal pillar(e.g., forming a signal distribution structure to electrically connect the second metal pillarand the first metal pillar).

150 6 150 6 150 7 As discussed herein, the second metal pillarmay be formed having any of a variety of height (or vertical) dimensions. For example, block Smay comprise forming the second pillarto have a height that is taller than a desired final height (e.g., to compensate for manufacturing tolerances, etc.). Also for example, block Smay comprise forming the second metal pillarto have a height that is as high or higher than an expected height of a second semiconductor die (e.g., as mounted at block S, etc.).

1 FIG. 2 FIG.G 200 100 7 160 130 7 3 g Referring toand the example structureof, the example methodmay, at block S, comprise attaching a second semiconductor die(or a plurality thereof) to a top side (or portion) of the first semiconductor die. Block Smay, for example, share any or all characteristics with block S.

160 161 130 130 130 130 130 160 160 130 160 130 160 130 130 160 In an example implementation, the second semiconductor diemay, for example, be oriented in a manner in which an active sideof the semiconductor diefaces away from the first semiconductor die, and inactive side of the semiconductor diefaces toward the first semiconductor die. For example, the respective inactive sides of the first and second semiconductor diesandmay face each other. The second semiconductor diemay, for example, be centered over the first semiconductor die. The second semiconductor diemay, for example, have a size that is equal to, less than, or greater than the size of the first semiconductor die. Note that, as discussed herein, the second semiconductor diemay be laterally displaced relative to the first semiconductor die. Also note that there may be one or more of the first semiconductor dies(of a same or different type) and one or more of the second semiconductor dies(of a same or different type).

160 130 160 160 130 160 130 The second semiconductor die(as with the first semiconductor diediscussed herein) may comprise any of a variety of circuit characteristics. For example, the second semiconductor diemay comprise electrical circuits, such as central processing units (CPUs), digital signal processors (DSPs), network processors, power management units, audio processors, RF circuits, wireless baseband system on chip (SoC) processors, sensors, application specific integrated circuits (ASICs), volatile and/or non-volatile memory, etc. In an example implementation, the second semiconductor diemay perform a same function as the first semiconductor die(e.g., both performing memory functionality, both performing processing functionality, etc.). In another example implementation, the second semiconductor diemay perform a different function than the first semiconductor die. Such different respective functions may, however, be complementary (e.g., one performing a processing function, one performing a memory function, another die performing a communication function, another die performing a sensor function, etc.).

2 FIG.G 2 FIG.G 160 130 160 160 160 160 160 130 160 140 140 140 140 160 130 160 160 160 a a a a a a a For example, as illustrated in, the lower side of the second semiconductor diemay be attached to the upper side of the first semiconductor diewith an adhesion member. The adhesion membermay, for example comprise a layer of adhesive paste, a layer of liquid adhesive, a preformed double-sided adhesive tape or sheet (e.g., a die-attach tape), etc. The adhesion membermay, for example, partially or completely cover the bottom side of the second semiconductor die. The adhesion membermay also, for example, partially or completely cover the top side of the first semiconductor die. For example, though not shown in, the adhesion membermay cover at least a portion of a top side of the first encapsulating material, for example a portion of the top side of the first encapsulating materialthat is around the periphery of the first semiconductor dieand immediately adjacent to the first semiconductor die. The adhesion membermay, for example, comprise a dielectric material that inhibits electrical connectivity between the first semiconductor dieand the second semiconductor die. The adhesion membermay, however, be thermally conductive. Note that the adhesion membermay, in various example implementations, be electrically conductive.

160 130 150 150 150 160 162 161 150 162 150 162 160 9 161 160 162 160 150 100 Note that the second semiconductor die, for example when attached to the first semiconductor die, may be taller than the second metal pillar, shorter than the second metal pillar, or generally the same height as the second metal pillar. In an example implementation, the second semiconductor diemay comprise conductive bumps(or pads, pillars, balls, other interconnection structures, etc.) on the active sidethat extend in an upward direction. In such an implementation, the height of the second metal pillarmay be at least as high as a lower end of such conductive bumps. In such a configuration, the second metal pillarand the conductive bumpsof the second semiconductor diemay be planarized (e.g., at block S, etc.) without damaging active circuitry on the active sideof the second semiconductor die. The tops of the conductive bumps, the second semiconductor dieand/or the second metal pillar(s)may be planarized at any of a variety of stages of the method.

1 FIG. 7 Note that although not explicitly shown in, a testing operation may be performed on the assembly before the second semiconductor die is attached at block S.

1 FIG. 2 FIG.H 200 100 8 170 8 170 8 4 h Referring toand the example structureof, the example methodmay, at block S, comprise forming a second encapsulating material. Block Smay comprise forming the second encapsulating material(or encapsulant) in any of a variety of manners, non-limiting examples of which are provided herein. Block Smay, for example, share any or all characteristics with Block Sdiscussed herein.

170 170 111 170 140 170 140 The second encapsulating materialmay comprise any of a variety of encapsulating or molding materials (e.g., resin, polymer, polymer composite material, polymer with filler, epoxy resin, epoxy resin with filler, epoxy acrylate with filler, silicone resin, combinations thereof, equivalents thereof, etc.). The second encapsulating materialmay also, for example, comprise any of the dielectric materials discussed herein (e.g., with regard to the dielectric layer, etc.). The encapsulating materialmay, for example, comprise a same material as the first encapsulating material. Note however, in an example implementation, the second encapsulating materialmay be a different material than the first encapsulating material, for example a material having different physical properties (e.g., different coefficient of thermal expansion (CTE), elasticity modulus, shrinkage factor, etc.). Such an implementation may, for example, be utilized to reduce or eliminate warping of the semiconductor package by tuning (or balancing) warpage forces (e.g., due to different respective coefficients of thermal expansion of the various components of the semiconductor device, different etc.).

8 170 8 170 111 Block Smay comprise forming the second encapsulating materialin any of a variety of manners (e.g., compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, paste printing, film assisted molding, etc.). Also for example, block Smay comprise forming the second encapsulating materialutilizing any of a variety of techniques that may be utilized to form a dielectric layer, examples of which are provided herein (e.g., with regard to forming the dielectric layer, etc.).

2 FIG.H 2 FIG.H 170 140 170 160 150 170 160 170 160 150 170 162 161 160 162 140 4 170 a As shown in, the second encapsulating materialmay cover a top side of the first encapsulating material. The second encapsulating materialmay also cover, in-whole or in-part, the lateral sides of the second semiconductor dieand/or the lateral sides of the second metal pillar(s). The second encapsulating materialmay additionally cover lateral and/or upper sides of the adhesion member. The second encapsulating materialmay be formed to also cover the top sides of the second semiconductor die(e.g., any or all of a dielectric layer on a top side thereof, a conductive layer on a top side thereof, conductive bumps on a top side thereof, etc.) and/or of the second metal pillar(s). As shown in, the second encapsulating materialmay cover lateral sides of the conductive bumpson the active sideof the second semiconductor die, while the upper ends of the conductive bumpsmay be exposed. As with the first encapsulating materialformed at block S, the second encapsulating materialmay be formed at a wafer or panel level for a plurality of semiconductor packages simultaneously, or may be formed at an individual package level.

160 130 140 160 170 160 160 130 140 a Note that in an example implementation in which there is space between the second semiconductor die, and the first semiconductor dieor first encapsulating material(e.g., when the adhesion memberdoes not entirely fill such space, etc.), the second encapsulating materialmay also underfill the second semiconductor diebetween the second semiconductor die, and the first semiconductor dieand/or first encapsulating material.

1 2 FIGS.andH 100 9 8 9 170 150 160 162 161 160 9 5 Still referring to, the example methodmay, at block S, comprise thinning the assembly as encapsulated at block S(e.g., performing a second thinning operation, etc.). For example, block Smay comprise thinning (e.g., mechanical grinding, chemically etching, shaving or shearing, peeling, any combination thereof, etc.) a top side of the second encapsulating material, the second metal pillarand/or a top side of the second semiconductor die(e.g., conductive bumpson the active sideof the second semiconductor die) to a desired thickness. Block Smay, for example, share any or all characteristics with Block S.

2 FIG.H 9 170 160 162 161 150 162 160 150 170 In the example implementation shown in, block Scomprises performing the thinning in a manner that results in coplanar top surfaces of the second encapsulating material, the second semiconductor die(e.g., conductive bumpsor other interconnection structures on an active sidethereof, etc.), and/or the second metal pillar(s). Thus, at least respective top surfaces (and/or at least an upper portion of lateral side surfaces) of conductive bumpson a top side of the second semiconductor dieand the second metal pillar(s)are exposed from (or at) the top surface of the second encapsulating material.

150 9 150 2 FIG.H As discussed herein, the second metal pillarmay, in some implementations, be formed with an interface layer on a top end thereof (e.g., a solder layer, a UBM layer, an interface metallization, etc.). In the example implementation shown in, block Smay also comprise exposing and/or planarizing such interface layer at the top end of the second metal pillar.

170 170 170 9 As discussed herein, the second encapsulating materialmay be originally formed having any of a variety of thicknesses. In an example implementation in which the second encapsulating materialis formed at its desired thickness and in which the top side conductors are exposed from the second encapsulating materialas desired (e.g., utilizing film-assisted molding, spin coating, etc.), the thinning at block Smight be skipped.

1 FIG. 2 FIG.I 200 100 10 180 10 180 170 150 160 i Referring toand the example structureof, the example methodmay, at block S, comprise forming a second substrate. Block Smay, for example, comprise forming the second substrateon top of the second encapsulating material, the second metal pillar, and/or the second semiconductor die.

10 180 10 1 10 Block Smay comprise forming the second substrate, which may also be referred to herein as an interposer, in any of a variety of manners, non-limiting examples of which are provided herein. For example, block Smay share any or all characteristics with block S. Block Smay, for example, share any or all characteristics with generally analogous blocks (and/or the resulting structures) shown in U.S. patent application Ser. No. 14/823,689, filed on Aug. 11, 2016, and titled “Semiconductor Package and Fabricating Method Thereof,” the entirety of which is hereby incorporated herein by reference in its entirety for all purposes.

10 180 180 182 181 183 180 110 Block Smay, for example, comprise forming the second substratehaving any number of dielectric layers and conductive layers (e.g., signal distribution layers, pad layers, conductive vias, underbump metallization, land layers, etc.). In an example implementation, a second substratecomprising a signal distribution layer, a dielectric layer, and a pad (or via) layermay be formed. Note that while the second substratemay be generally different from the first substrate, any or all characteristics may be the same, may be vertically and/or horizontally symmetrical, etc.

183 The pad (or via) layer, which may also be referred to herein as a pad, a via, a trace, a land, a bond pad layer, a conductive layer, a trace layer, etc., may comprise any of a variety of materials (e.g., copper, aluminum, nickel, iron, silver, gold, titanium, chromium, tungsten, palladium, combinations thereof, alloys thereof, equivalents thereof, etc.), but the scope of the present disclosure is not limited thereto.

10 183 10 183 10 183 150 162 Block Smay comprise forming the pad (or via) layerlayer in any of a variety of manners, non-limiting examples of which are presented herein. For example, block Smay comprise forming the pad (or via) layerutilizing any one or more of a variety of processes (e.g., electrolytic plating, electroless plating, chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), sputtering or physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, printing, screen printing, lithography, etc.), but the scope of the present disclosure is not limited thereto. Block Smay, for example, comprise forming the pad layeron a top side of the second metal pillar, on top sides of the conductive bumps, etc.

10 183 183 10 150 162 170 2 FIG.I As with any of the conductive layers discussed herein, block Smay comprise forming one or more seed layers as part of the processing of forming the pad (or via) layer(e.g., prior to electroplating the pad layer, etc.). For example, though not shown in, block Smay comprise forming one or more seed layers on the top surface of the second metal pillar, conductive bumps, second encapsulating material, etc.

183 170 160 150 Note that in various example implementation, prior to forming the pad (or via) layer, one or more dielectric layers may be formed over the top surface of the second encapsulating material, second semiconductor die, and/or second metal pillar(s).

181 3 4 2 The dielectric layermay comprise one or more layers of any of a variety of dielectric materials, for example inorganic dielectric materials (e.g., SiN, SiO, SiON, SiN, oxides, nitrides, combinations thereof, equivalents thereof, etc.) and/or organic dielectric materials (e.g., a polymer, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), a molding material, a phenolic resin, an epoxy, silicone, acrylate polymer, combinations thereof, equivalents thereof, etc.), but the scope of the present disclosure is not limited thereto.

10 181 Block Smay comprise forming the dielectric layerutilizing any one or more of a variety of processes (e.g., spin coating, spray coating, printing, sintering, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), sheet lamination, evaporating, etc.), but the scope of the present disclosure is not limited thereto.

10 181 183 10 10 181 Block Smay, for example, also comprise patterning the dielectric layer, for example forming apertures therein that expose various portions of various conductive layers discussed herein (e.g., pad layers, signal distribution layers, etc.). For example, block Smay comprise ablating apertures (e.g., utilizing laser ablation, utilizing mechanical ablation, utilizing etching, etc.). Also for example, block Smay comprise originally forming the dielectric layer(e.g., depositing, etc.) having the desired apertures.

182 182 180 160 120 184 The signal distribution layer, which may also be referred to herein as a redistribution layer, a distribution layer, a conductive layer, a trace layer, etc., may comprise any of a variety of materials (e.g., copper, aluminum, nickel, iron, silver, gold, titanium, chromium, tungsten, palladium, combinations thereof, alloys thereof, equivalents thereof, etc.), but the scope of the present disclosure is not limited thereto. The signal distribution layer(or second substrate) may, for example, provide electrical signal pathways between terminals of the second semiconductor dieand/or respective second metal pillarsand/or respective lands.

10 182 10 182 Block Smay comprise forming the signal distribution layerlayer in any of a variety of manners, non-limiting examples of which are presented herein. For example, block Smay comprise forming the signal distribution layerutilizing any one or more of a variety of processes (e.g., electroplating, electroless plating, chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), sputtering or physical vapor deposition (PVD), atomic layer deposition (ALD), plasma vapor deposition, printing, screen printing, lithography, etc.), but the scope of the present disclosure is not limited thereto.

182 10 182 10 170 160 150 2 FIG.I In various example scenarios, for example in which the signal distribution layeris electroplated, block Smay comprise forming one or more seed layers prior to electroplating the signal distribution layer. For example, though not shown in, block Smay comprise forming one or more seed layers on the top surface of the second encapsulating material, second semiconductor die, and/or second metal pillar. Such seed layer(s) may comprise any of a variety of materials. For example, the seed layer(s) may comprise copper. Also for example, the seed layer(s) may comprise one or more layers of any of a variety of metals (e.g., silver, gold, aluminum, tungsten, titanium, nickel, molybdenum, etc.). The seed layers may be formed utilizing any of a variety of techniques (e.g., sputtering or other physical vapor deposition (PVD) technique, chemical vapor deposition (CVD), electroless plating, electrolytic plating, etc.). The seed layer(s) may, for example, be utilized during a subsequent electroplating process.

10 180 10 185 184 185 184 184 2 FIG.I Block Smay comprise forming any number of conductive and dielectric layers of the second substrate. In the example implementation shown in, block Scomprises forming a second dielectric layerand a land layer. The second dielectric layerand/or the forming thereof may share any or all characteristics with other dielectric layers and/or the forming thereof discussed herein. The land layerand/or the forming thereof may share any or all characteristics with other conductive layers and/or the forming thereof discussed herein. Note that the land layermay, for example, also be referred to as a conductive layer, a pad, a land, a signal distribution structure, etc.

184 10 184 11 184 180 185 For example, in an example implementation, the land layermay comprise under bump metallization, as discussed herein. For example, block Smay comprise forming the land layerto have one or more metallization layers conducive to the attachment of interconnection structures (e.g., conductive balls, conductive pillars or posts, etc.), for example as attached at block S. The land layermay, for example, be exposed at the top surface of the second substrate(e.g., second dielectric layer, etc.).

182 10 184 184 10 182 181 2 FIG.I As with the signal distribution layer, or any conductive layer discussed herein, block Smay comprise forming one or more seed layers as part of the processing of forming the land layer(e.g., prior to electroplating the land layer, etc.). For example, though not shown in, block Smay comprise forming one or more seed layers on the top surface of the signal distribution layer, on a top surface and/or aperture surfaces of the dielectric layer, etc.

10 180 Note that although an illustrative set of conductive layers and dielectric layers is shown in the drawings, block Smay comprise forming the second substrateto have any number of such conductive and/or dielectric layers.

110 110 180 As discussed herein, first substrate(or interposer), or a portion thereof, may be formed in a semiconductor wafer fabrication process (e.g., at a wafer fab facility, etc.). Also for example, any or all of the layers of the first substratemay be performed in a packaging process that may, for example, receive a semiconductor wafer as an input to the packaging process. In an example implementation, the layers (e.g., conductive layers, dielectric layers, etc.) of the second substratemay be performed in a packaging process. Thus, in various example implementations, one or more substrate portions may be formed in a semiconductor wafer fabrication process and one or more substrate portions may be formed in a semiconductor device packaging process.

10 180 In general, block Smay comprise forming a second substrate(or interposer). Accordingly, the scope of the present disclosure should not be limited by characteristics of any particular carrier or substrate or by characteristics of any particular manner of forming such a carrier or substrate.

1 FIG. 2 FIG.I 200 100 11 190 180 i Referring toand the example structureof, the example methodmay, at block S, comprise forming conductive interconnection structureson the second substrate.

190 190 190 37 95 The conductive interconnection structuresmay comprise any of a variety of characteristics. For example, an interconnection structuremay comprise a conductive ball or bump (e.g., a solder ball or bump, wafer bump, a solid core or copper core solder ball, etc.). For example, in an example implementation including a solder ball or bump, such balls or bumps may comprise tin, silver, lead, Sn—Pb, Sn—Pb, Sn—Pb, Sn—Pb—Ag, Sn—Pb—Bi, Sn—Cu, Sn—Ag, Sn—Au, Sn—Bi, Sn—Ag—Cu, Sn—Ag—Bi, Sn—Zn, Sn—Zn—Bi, combinations thereof, equivalents thereof, etc., but the scope of this disclosures is not limited thereto. A conductive interconnection structuremay also comprise a conductive pillar or post, a wire, a land, etc., which may for example comprise any of the conductive materials (e.g., metals, conductive adhesives, etc.) discussed herein.

190 190 The conductive interconnection structuresmay be configured in any or a variety of configurations. For example, the conductive interconnection structuresmay be configured in a ball grid array configuration, a land grid array configuration, etc.

11 190 11 190 11 184 Block Smay comprise forming (or attaching) such interconnection structuresin any of a variety of manners, non-limiting examples of which are provided herein. For example, block Smay comprise forming (or attaching) such interconnection structuresby ball-dropping, bumping, metal-plating, pasting and reflowing, etc. For example, block Smay comprise dropping a conductive ball on the land layer(or pad), reflowing, and cooling.

11 191 184 180 191 190 191 190 190 190 191 190 Step Smay also, for example, comprise forming (or attaching) components(e.g., passive components, active components, etc.) on the land layerof the second substrate. In an example implementation, the componentsmay have a smaller height than the conductive interconnection structures. For example, the componentsmay have a smaller height than a solder ball conductive interconnection structure, a smaller height than a solid core (e.g., a copper core, etc.) of a solder ball conductive interconnection structure, etc. In such an implementation, the conductive interconnection structuresmay provide a standoff to maintain space for the componentswhen the conductive interconnection structuresare attached to another substrate or component.

1 FIG. 2 FIG.I 200 100 12 i Referring toand the example structureof, the example methodmay, at block S, comprise singulating a semiconductor device package from a plurality of connected packages.

100 110 140 170 180 As mentioned here, any or all of the blocks of the example methodmay be performed at a wafer or panel level, for example forming a plurality of semiconductor packages at the same time. The wafer or panel may then, for example, be singulated into individual packages. Such singulating may, for example, be performed by any one or more of mechanical cutting (e.g., sawing, cutting, abrading, snapping, etc.), energy cutting (e.g., laser cutting, plasma cutting, etc.), chemical cutting (e.g., etching, dissolving, etc.), etc. In an example implementation, such singulating may form coplanar lateral side surfaces of the package. For example, one or more of the lateral side surfaces of the first substrate, first encapsulating material, second encapsulating material, and/or second substratemay be coplanar on one or more lateral sides of the singulated semiconductor package.

200 100 200 200 2 FIG.J 1 FIG. The example semiconductor device packageshown inmay result from the example methodof, as discussed herein. Note that other method steps may be performed on the example package, for example adding or removing components, etc., without departed from the scope of this disclosure. Note that the example semiconductor device(or any device discussed herein) may be referred to as a semiconductor package, an electronic device, an electronic package, a device, a package, etc.

5 140 130 140 120 130 140 7 160 140 130 130 130 160 300 a 3 FIG. As discussed herein, in an example implementation, block Smay be skipped or may be performed to a degree that leaves the first encapsulating materialhaving a higher height than the first semiconductor die. For example, the top surface of the first encapsulating materialand the top surface(s) of the first metal pillar(s)may be coplanar, while the top surface of the first semiconductor dieremains covered by the first encapsulating material. In such an example implementation, block Smay comprise attaching the second semiconductor dieto the top surface of the first encapsulating material(e.g., directly above and centered on the first semiconductor die, partially directly above and partially not directly above the first semiconductor die, completely laterally offset from the first semiconductor die, etc.) utilizing the adhesion member.shows an example semiconductor devicethat may result from such a process.

3 FIG. 2 2 4 5 FIGS.A-J,, and 300 300 More specifically,shows a cross-sectional view of an example semiconductor device, in accordance with various aspects of the present disclosure. It should be understood that the example devicemay share any or all characteristics with the other examples devices discussed herein, for example, with the other example devices shown in.

3 FIG. 300 240 130 120 130 120 140 160 140 160 a As shown in, in the example semiconductor device, a top portion of the first encapsulating materialcovers the top side of the first semiconductor die. The first metal pillarsare taller than the first semiconductor die. The top ends of the first metal pillarsand the top side of the first encapsulating materialmay, for example, be coplanar. The adhesion unitcontacts the top side of the first encapsulating materialand contacts the lower side of the second semiconductor die.

240 130 120 120 120 130 240 130 240 130 240 130 During processing, the first encapsulating materialmay, for example, prevent foreign materials from being formed on the first semiconductor die. For example, if grinding is performed to expose the first metal pillarafter forming the first metal pillar, there is a possibility that particles of a metal from grinding the first metal pillar(e.g., copper particles, etc.) may be scattered toward the first semiconductor die. However, since the first encapsulating materialencapsulates the top side (or portion) of the first semiconductor die, the first encapsulating materialprevents the metal particles from directly contacting and/or from being mounted on the first semiconductor die. Thus, the encapsulating materialmay prevent damage from being caused to the first semiconductor die.

4 5 100 8 8 4 8 100 8 140 170 120 130 150 160 400 1 FIG. 4 FIG. In another example implementation, blocks Sand/or Sof the example methodmay be skipped. For example, block Smay comprise performing a first encapsulating step instead of a second encapsulating step. For example, block Smay combine the first encapsulating at block Sand the second encapsulating at block Sin the example methodof. In such an example implementation, block Smay comprise forming a single integral encapsulating material that covers the various elements of the semiconductor device as discussed herein with regard to both the first encapsulating materialand the second encapsulating material. For example, the single integral encapsulating material may encapsulate the first metal pillar(s), the first semiconductor die, the second metal pillar, and the second semiconductor die.shows an example semiconductor devicethat may result from such a process.

4 FIG. 2 2 3 5 FIGS.A-J,, and 400 400 More specifically,shows a cross-sectional view of an example semiconductor device, in accordance with various aspects of the present disclosure. It should be understood that the example devicemay share any or all characteristics with the other examples devices discussed herein, for example, with the other example devices shown in.

4 FIG. 370 140 170 370 140 As shown in, the single unitary and continuous encapsulating materialreplaces the first encapsulating materialand the second encapsulating materialof various other implementations. For example, the encapsulating materialmay share any or all characteristics with the first encapsulating materialand second encapsulating material discussed herein, albeit as a single unitary continuous encapsulating material.

8 100 4 370 120 130 150 160 110 8 370 140 170 100 In an example implementation, for example at block Sof the example method(e.g., skipping block S, etc.), the encapsulantmay be formed after the first metal pillar, the first semiconductor die, the second metal pillarand the second semiconductor dieon the top side of the first substrateare all formed. Block Smay, for example comprise forming the encapsulantby simultaneously forming the first encapsulantand the second encapsulantof the semiconductor device.

370 400 In such an implementation, the encapsulantmay be formed in a simplified manner, thus reducing the number of process steps and time for manufacturing the semiconductor device.

120 150 500 5 FIG. In yet another example implementation, as discussed herein, the first metal pillarsand the second metal pillarsmay be laterally offset from each other, and may, for example, be electrically coupled to each other by a signal distribution structure. Additionally, any number of semiconductor dies (or other electrical components) may be utilized.shows an example semiconductor devicethat may result from such a process.

5 FIG. 2 2 3 4 FIGS.A-J,, and 500 500 More specifically,shows a cross-sectional view of an example semiconductor device, in accordance with various aspects of the present disclosure. It should be understood that the example devicemay share any or all characteristics with the other examples devices discussed herein, for example, with the other example devices shown in.

450 5 6 100 5 450 140 120 130 450 a a a 1 FIG. For example, a signal distribution structuremay be formed, for example between blocks Sand Sof the example methodof. For example, after block S, the signal distribution structuremay be formed on (or over) the first encapsulating material, the first metal pillar(s), and/or the first semiconductor die. The signal distribution structuremay also be referred to as a pillar redistribution layer, a redistribution layer, a pillar redistribution structure, a trace, etc.

450 110 180 450 110 1 180 10 450 120 450 120 450 150 6 a a a a a The signal distribution structuremay share any or all characteristics with the first substrateand/or the second substratediscussed herein. The signal distribution structuremay, for example, be formed in a manner that shares any or all characteristics with the forming of the first substrateat block Sand/or with the forming of the second substrateat block S. The signal distribution structuremay, for example, be formed to be connected to the first metal pillar(s). The signal distribution structuremay, for example, comprise a conductive layer that laterally redistributes electrical signals to and/or from the first metal pillar(s). The signal distribution structuremay, for example, comprise a pad layer (or other conductive layer, UBM layer, etc.) on which the second metal pillar(s)may then be formed at block S.

450 120 130 140 170 450 450 170 a a a Note that the signal distribution structuremay be formed on top of the first metal pillar, the first semiconductor die, and the first encapsulating material. In an example implementation, the second encapsulating materialmay be formed to cover the signal distribution structure. For example, top and/or lateral side portion of the signal distribution structuremay be covered by the second encapsulating material.

500 160 Additionally, as discussed herein, a plurality of semiconductor dies may be utilized on each level of the semiconductor device (or package) instead of the single semiconductor dies, which are presented as single dies herein for illustrative clarity. As an example, the semiconductor devicecomprises a plurality of semiconductor dies in place of the second semiconductor dieof other implementations.

460 460 465 465 460 465 160 a a a a a 1 2 2 FIGS.andA-H In particular, a second semiconductor diemay, for example, be attached to the first semiconductor die with an adhesion member, and a third semiconductor diemay, for example, be attached to the first semiconductor die with an adhesion member. The adhesion membersandmay, for example, share any or all characteristics with the example adhesion memberdiscussed herein with regard to.

460 461 180 465 466 180 180 The second semiconductor diemay, for example, comprise an active sidehaving conductive bumps that are attached to the second substrate, and the third semiconductor diemay, for example, comprise an active sidehaving conductive bumps that are attached to the second substrate. Such conductive bumps and/or their connection to the second substratemay, for example, share any or all characteristics with other conductive bumps and/or their connections as discussed herein.

460 465 460 460 130 140 130 140 460 165 130 170 130 Note that, as discussed herein, the second semiconductor dieand third semiconductor diemay be laterally offset (partially or wholly) from the first semiconductor die. For example, the second semiconductor dieis attached to a top side of the first semiconductor dieand to a top side of the first encapsulating material, overhanging at least one lateral side of the first semiconductor die. Thus, the first encapsulating materialis vertically directly under a portion of the second semiconductor die. Also for example, the third semiconductor dieis positioned laterally inward from a lateral side of the first semiconductor die, and thus a portion of the second encapsulating materialis directly over a portion of the first semiconductor die.

In summary, various aspects of this disclosure provide a semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising a stacked die structure and a method of manufacturing thereof. While the foregoing has been described with reference to certain aspects and examples, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the disclosure. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure without departing from its scope. Therefore, it is intended that the disclosure not be limited to the particular example(s) disclosed, but that the disclosure will include all examples falling within the scope of the appended claims.