Hybrid Inverse Lithography Technology Optimization

The present application claims the benefit of and priority to U.S. Provisional Application No. 63/716,834, filed Nov. 6, 2024, the entire disclosure of which is hereby incorporated herein by reference.

Improving semiconductor processes and systems, and increasing yield from semiconductor processes and systems, may include modeling of many, if not all, processing steps associated with these semiconductor processes and systems. One such semiconductor process is lithography. Non-limiting examples of lithography processing steps include exposure, resist development, and mask-writing. Existing approaches may be subject to noise, optical diffraction, diffusion, and other lithography-related issues. This can create issues during fabrication of semiconductor devices, including those having large mask designs for advanced technology nodes.

Inverse lithography technology (ILT) optimizations may be crucial for achieving viable semiconductor yield in advanced technology nodes. Lithography processes for these advanced technology nodes may have increasingly smaller process windows and/or increasingly problematic optical proximity effects. Conventional ILT optimizations can generate mask designs that are robust and manufacturable. Such optimizations may inversely optimize lithographic printing simulations by, for example, back propagating gradients of simulated loss with respect to a mask design (e.g., a perturbed mask design). Conventional ILT optimizations may be efficient for smaller mask designs. However, computational costs and/or inefficient scaling are challenges associated with using ILT models for advanced technology nodes.

Requirements of a full simulation of mask designs for each step makes conventional ILT optimizations inefficient for scaling to larger mask designs. For instance, a complete conventional ILT optimization of mask designs for a large circuit layout (e.g., a full chip) may take several days, or even weeks, to perform using a significant amount of computer processing resources. Thus, such approaches are impractical for full chips due to weeks-long runtimes and the need for many accelerators to scale in parallel.

Aspects of the technology disclosed herein include a hybrid approach to ILT optimization that leverages machine learning (ML) ILT models to improve the accuracy of ILT optimizations and/or increase acceleration to convergence of ILT optimizations. ML ILT models can be implemented, for example, using an image translation architecture (e.g., a U-Net or other neural network architecture). By way of example, a ML ILT model can be implemented using a convolutional neural network (CNN), a computer vision-oriented neural network, or a set of vision transformers. Mask designs output by trained ML ILT models, which can be output in just milliseconds, can be used to initialize subsequent ILT optimizations. Technical benefits of the disclosed technology include providing reduced (e.g., significantly reduced) computational requirements (e.g., computational resources, runtimes) relative to conventional ILT optimizations alone.

Typical ILT optimizations are initialized with target mask designs, which are considerably far from mask designs ultimately generated by the ILT optimizations. In contrast, the disclosed technology uses ML ILT models to, in effect, replace initial iterations (e.g., the initial tens or hundreds of iterations) that would otherwise need to be performed. That is, the ML ILT models are trained to predict mask designs similar to mask designs that the ILT optimizations would have generated after those “replaced” iterations. Mask designs output by ML ILT models are also referred to herein as “predicted ILT mask designs”. Trained ML ILT models can output predicted ILT mask designs in a mere fraction of the time that it would take to perform those “replaced” iterations with accuracy. Initialization of ILT optimizations with predicted ILT mask designs reduces how many subsequent iterations of the ILT optimizations are performed. Even with the reduced quantity of iterations, the generated mask designs satisfy accuracy criteria. For example, how many iterations of the ILT optimizations are performed can be reduced by a factor of three. This is a significant technical benefit for the computing technology, as it reduces not only the amount of time required to generate a target design, but also reduces the amount of processing power and/or processing resources that would be required.

The disclosed technology can include training ML ILT models using target mask designs and corresponding mask designs generated by ILT optimizations based on those target mask designs. Mask designs output by trained ML ILT models are accurately predictive of masks designs generated by ILT optimizations. However, in some instances, mask designs output by trained ML ILT models may not satisfy accuracy requirements across an entire layout. For example, the quality of mask designs output by a trained ML ILT model cannot exceed the quality of those mask designs from ILT optimizations on which the ML ILT model is trained. At best, ML ILT models, by themselves, can output mask designs having the same quality as those mask designs from ILT optimizations on which the ML ILT models are trained. Moreover, if a target mask design includes a feature or shape that a ML ILT model did not encounter in training of that ML ILT model, the predicted ILT mask design output by that ML ILT model may include unexpected and/or unmanufacturable features.

Aspects of the technology disclosed herein include generating training data sets using mask designs from standard cell libraries for given technology nodes. The training data set includes target mask designs and corresponding mask designs generated by ILT optimizations based on those target mask designs. The training data set can be expanded via augmentations (e.g., one or more of rotations, crops, flips, etc.) of mask designs from standard cell libraries. This expansion of the training data set can increase the coverage of ML ILT models, for example, in terms of feature types and/or shapes, which can improve generalization of predictions by the ML ILT models to various shapes and/or geometries. The training data set can include target mask designs having varying levels of density, which can reduce tendency of trained ML ILT models to overfit on a particular subset of possible mask designs. Aspects of the technology disclosed herein include generating training data sets via an automated workflow to generate target mask designs by randomly routing random nets.

Training data sets can include mask designs generated by predetermined quantities of iterations of ILT optimizations (e.g., on the order of 1500 iterations, at least 100 iterations, no more than 2000 iterations, etc.). After training (e.g., for a few hundred or thousand epochs), ML ILT models can learn translations from target mask designs to predicted ILT mask designs, with capability to generalize to unseen patterns.

According to one aspect of the technology, a method includes obtaining, by one or more processors, a target mask design for a semiconductor device to be fabricated; determining, by one or more processors based on a machine learning inverse lithography technology (ML ILT) model, a predicted ILT mask design corresponding to the target mask design; performing, by one or more processors, an ILT optimization using the predicted ILT mask design as an initialization point; and generating, by one or more processors based on completion of the ILT optimization, a mask design in order to fabricate the semiconductor device.

In an example, the method may include determining, by one or more processors, a mask pattern based on the mask design by simulating one or more lithographic processes.

Alternatively or additionally to the above, the method may include training, by one or more processors, the ML ILT model using a set of target mask designs and a set of mask designs based on the ILT optimization. The set of target mask designs may include one or more mask designs from a standard cell library. The set of target mask designs may include one or more augmented mask designs based on a standard cell library. Training the ML ILT model may include determining, by one or more processors based on the ML ILT model, another predicted ILT mask design corresponding to a given target mask design of the set of target mask designs; and determining, by one or more processors, a level of difference between the other predicted ILT mask design and a given mask design of the set of mask designs corresponding to the given target mask design. Here, the method may include determining, by one or more processors, whether the level of difference exceeds a threshold level of difference. Here, the method may include, responsive to determining that the level of difference does not exceed the threshold level of difference, determining, by one or more processors, that the ML ILT model is fully trained.

Alternatively or additionally to the above, the semiconductor device may be a component of an integrated circuit (IC) device.

Alternatively or additionally to the above, the semiconductor device may be a component of at least one of a microelectromechanical systems (MEMS) device, a photonic device or a display device.

According to another aspect of the technology, a system is provided that comprises memory configured to store at least one of a machine learning inverse lithography technology (ML ILT) model and a target mask design for a semiconductor device to be fabricated, and one or more processors operatively coupled to the memory. The one or more processors are configured to: determine, based on the ML ILT model, a predicted ILT mask design corresponding to the target mask design; perform an ILT optimization using the predicted ILT mask design as an initialization point; and generate, based on completion of the ILT optimization, a mask design in order to fabricate the semiconductor device.

In an example, the one or more processors may be further configured to simulate one or more lithographic processes using the mask design; and determine a mask pattern based on the simulation of the one or more lithographic processes.

Alternatively or additionally to the above, the memory may be further configured to store a set of target mask designs and a set of mask designs based on the ILT optimization. The one or more processors may be further configured to train the ML ILT model using the set of target mask designs and the set of mask designs. The set of target mask designs may include one or more mask designs from a standard cell library. The set of target mask designs may include one or more augmented mask designs based on a standard cell library. The one or more processors may be configured to: train the ML ILT model by being configured to determine, based on the ML ILT model, another predicted ILT mask design corresponding to a given target mask design of the set of target mask designs; and determine a level of difference between the other predicted ILT mask design and a given mask design of the set of mask designs corresponding to the given target mask design. Here, the one or more processors may be further configured to determine whether the level of difference exceeds a threshold level of difference. Here, the one or more processors may be further configured to, responsive to a determination that the level of difference does not exceed the threshold level of difference, determine that the ML ILT model is fully trained.

Alternatively or additionally to the above, the semiconductor device may be a component of an integrated circuit (IC) device.

Alternatively or additionally to the above, the semiconductor device may be a component of at least one of a microelectromechanical systems (MEMS) device, a photonic device or a display device.

1 FIG. 100 102 104 illustrates an exemplary integrated circuit design flowfor use with aspects of the technology, including generating a circuit design and/or fabricating an integrated circuit that incorporates determining potential manufacturing defects in a mask pattern. As shown, the design flow may include preparing a system specification at block, such as to identify system-level requirements for the integrated circuit. The system specification is intended to capture the overall goal of the desired integrated circuit. This may include determining the device's cost, performance, general architecture, how off-chip communication will be conducted, etc. The process flow may also include performing architectural design at block. At this stage, the design's architecture and its layout are determined by design engineers. This can include integration of memory management, analog and/or mixed-signal components, on-device and external communication, any power constraints, choice of process technology and/or layer stacks, etc.

106 108 The process flow continues with performing functional design and logic design at block, and performing circuit design at block. Functional design may include refinement of the design's specification to achieve the functional behavior of the desired system. Logic design involves adding the design's structure to a behavioral representation of the desired design. Here, considerations include logic minimization, performance enhancement, as well as testability. This stage may consider problems associated with test vector generation, error detection and correction, and the like. By way of example, the functional design and logic design may include generating a behavioral model description (e.g., using HDL) and floor-planning. During circuit design, logic blocks are replaced by corresponding electronic circuits, which may include devices such as resistors, capacitors, and/or transistors. At this stage, circuit simulation may be performed in order to verify timing behavior and other constraints of the system. A Spice tool or other program may be used for circuit simulation.

110 112 Once the circuit design is complete, physical design may be performed at block(e.g., component and wiring placement and routing), followed by physical verification and sign-off at block(e.g., to obtain GDSII information with shapes to form the masks used to create the layers for fabricating the integrated circuit). During physical design, the actual layout of the integrated circuit is performed. Here, all of the components are placed and interconnected using metal interconnections. During this stage, the system may perform optimization of curvilinear interconnects, alternatively or additionally to any other layout operations. A circuit design that is able to pass testing of a circuit simulator in the circuit design stage may be found to be faulty after it has been packaged, e.g., due to geometric design rule issues. Thus, physical design rules are followed to ensure correctness during chip fabrication. Errors may include short or open circuits, open channels, or other issues may result when physical design rules are not followed. During physical verification and sign-off, the system performs any verification steps that are required before chip manufacturing. This can include design rule checking and correction, timing simulation, electromagnetic simulation, etc.

114 116 118 114 118 Layout post-processing occurs at block, then fabrication at block, and the packaging and testing at block. At block, the layout post-processing may include geometry processing before actual manufacturing, e.g., any dummy fill insertion, correction for optical proximity, mask optimization, etc. Fabrication comprises semiconductor manufacturing, which includes stages such as lithography patterning (masking), baking or annealing, etching, etc. Then the raw die of the chip is inserted into a package and I/O pins are connected to the package at block. Testing of the chip also occurs at this stage.

108 120 122 124 126 122 As shown, in the circuit design phase of block, the process may involve technology-independent synthesis at block. This step involves transferring the circuit definitions, such as register-transfer-level (RTL) descriptions, into generic data structures such as And-inverter graph (AIG), and optimizing the circuit in terms of nodes and levels. At block, technology mapping is performed based on information from a standard cell library. This step involves maps the generic optimized AIG descriptions into real, manufacturable standard cells included in the standard cell library. From this, technology-dependent synthesis is then performed at block. This step further optimizes the circuit defined in the gate-level netlist in terms of power, performance and area, using standard-cell-based definitions from block.

2 FIG. 2 FIG. 2 FIG. 200 202 204 206 208 210 200 212 202 204 206 One example of a system for performing circuit design and fabrication is shown in. In particular,is a functional diagram, of an example systemthat includes a plurality of computing devices,,and a storage systemconnected via a network. Systemmay also include a fabrication facilitythat is configured to produce integrated circuits designed according to the processes described herein. As shown in, each of computing devices,andmay include one or more processors, memory, data and instructions.

2 FIG. By way of example, the one or more processors may be any conventional processors, such as commercially available central processing units (CPUs), graphical processing units (GPUs) or tensor processing unites (TPUs). Alternatively, the one or more processors may include a dedicated device such as an ASIC or other hardware-based processor. As shown in, the memory for each computing device stores information accessible by the one or more processors, including instructions and data that may be executed or otherwise used by the processor(s). The memory may be of any type capable of storing information accessible by the processor, including a computing device or computer-readable medium, or other medium that stores data that may be read with the aid of an electronic device, such as a hard-drive, memory card, ROM, RAM, DVD or other optical disks, as well as other write-capable and read-only memories. Systems and methods may include different combinations of the foregoing, whereby different portions of the instructions and data are stored on different types of media.

Moreover, reference to “one or more processors” herein includes situations where a set of processors may be configured to perform one or more operations. Any combination of such a set of processors may perform individual operations or a group of operations. This may include two or more CPUs, GPUs or TPUs (or other hardware-based processors) or any combination thereof. It may also include situations where the processors have multiple processing cores. Therefore, reference to “one or more processors” does not require that all processors (or cores) in the set must each perform all of the operations. Rather, unless expressly stated, any one of the one or more processors (or cores) may perform different operations when a set of operations is indicated, and different processors (or cores) may perform specific operations, either sequentially or in parallel.

The instructions may be any set of instructions to be executed directly (such as machine code) or indirectly (such as scripts) by the processor. For example, the instructions may be stored as computing device code on the computing device-readable medium. In that regard, the terms “instructions” and “programs” may be used interchangeably herein. The instructions may be stored in object code format for direct processing by the processor, or in any other computing device language including scripts or collections of independent source code modules that are interpreted on demand or compiled in advance.

The data may be retrieved, stored or modified by processor in accordance with the instructions. For instance, although the claimed subject matter is not limited by any particular data structure, the data may be stored in computing device registers, in a relational database as a table having a plurality of different fields and records, XML documents or flat files, HDL information, GDSII information, etc. The data may also be formatted in any computing device-readable format.

200 212 The computing devices may include all of the components normally used in connection with a computing device such as the processor and memory described above as well as a user interface having one or more user inputs (e.g., one or more of a button, mouse, keyboard, touch screen, gesture input and/or microphone), various electronic displays (e.g., a monitor having a screen or any other electrical device that is operable to display information), and speakers. The computing devices may also include a communication system having one or more wired or wireless connections to facilitate communication with other computing devices of systemand/or the fabrication facility.

210 210 The various computing devices may communicate directly or indirectly via one or more networks, such as network. The networkand any intervening nodes may include various configurations and protocols including short range communication protocols such as Bluetooth™, Bluetooth LE™, the Internet, World Wide Web, intranets, virtual private networks, wide area networks, local networks, private networks using communication protocols proprietary to one or more companies, Ethernet, WiFi and HTTP, and various combinations of the foregoing. Such communication may be facilitated by any device capable of transmitting data to and from other computing devices, such as modems and wireless interfaces.

202 202 204 206 212 210 204 206 212 In one example, computing devicemay include one or more server computing devices having a plurality of computing devices, e.g., a load balanced server farm or cloud computing architecture, which exchange information with different nodes of a network for the purpose of receiving, processing, and transmitting the data to and from other computing devices. For instance, computing devicemay include one or more server computing devices that are capable of communicating with computing devices,and the fabrication facilityvia the network. In some examples, client computing devicemay be an engineering workstation used by a developer to perform circuit design and/or other processes for integrated circuit design and fabrication. Client computing devicemay also be used by a developer, for instance to prepare system requirements for the integrated circuit or manage the manufacturing process with the fabrication facility.

208 202 204 206 208 208 210 2 FIG. Storage systemcan be of any type of computerized storage capable of storing information accessible by the server computing devices,and/or, such as a hard-drive, memory card, ROM, RAM, DVD, CD-ROM, flash drive and/or tape drive. In addition, storage systemmay include a distributed storage system where data is stored on a plurality of different storage devices which may be physically located at the same or different geographic locations. Storage systemmay be connected to the computing devices via the networkas shown in, and/or may be directly connected to or incorporated into any of the computing devices.

208 208 Storage systemmay store various types of information. For instance, the storage systemmay store training data sets for ML ILT models, one or more trained ML ILT models, models of lithography processing steps, and/or other processes as well as instructions for selected conventional ILT optimizations and other processes described herein.

3 FIGS.A-F 3 FIGS.A-J 300 302 302 illustrate examples of target mask designs and mask designs generated by selected ILT optimizations based on those target mask designs that can be used in training ML ILT models in accordance with aspects of the technology. As used herein, “target mask design” refers to an intended mask pattern to be fabricated. A mask design other a target mask design, such as one generated by ILT optimizations, may be different than the target mask design but provides the intended mask pattern. A goal of training a ML ILT model is to have that ML ILT model predict, for a given target mask design, the mask design that a selected ILT optimization process would generate for that target mask design with at least a particular level of accuracy. By way of example, if the target mask designis input to a trained ML ILT model, then, ideally, the trained ML ILT model will output the mask design, or, less ideally, a mask design similar to the mask designwith at least a particular level of accuracy. This applies to all pairs of a target mask design and corresponding mask design generated by ILT optimization illustrated by.

3 FIG.A 3 FIG.B 3 FIG.C 3 FIG.D 3 FIG.E 3 FIG.F 3 FIG.G 3 FIG.H 3 FIG.I 3 FIG.J 302 300 306 304 310 308 314 312 318 314 322 320 326 324 330 328 334 332 338 336 342 340 346 344 350 348 354 352 358 356 362 360 366 364 370 368 374 372 illustrates mask designgenerated by ILT optimization of target mask design, and mask designgenerated by ILT optimization of target mask design.illustrates mask designgenerated by ILT optimization of target mask design, and mask designgenerated by ILT optimization of target mask design.illustrates mask designgenerated by ILT optimization of target mask design, and mask designgenerated by ILT optimization of target mask design.illustrates mask designgenerated by ILT optimization of target mask design, and mask designgenerated by ILT optimization of target mask design.illustrates mask designgenerated by ILT optimization of target mask design, and mask designgenerated by ILT optimization of target mask design.illustrates mask designgenerated by ILT optimization of target mask design, and mask designgenerated by ILT optimization of target mask design.illustrates mask designgenerated by ILT optimization of target mask design, and mask designgenerated by ILT optimization of target mask design.illustrates mask designgenerated by ILT optimization of target mask design, and mask designgenerated by ILT optimization of target mask design.illustrates mask designgenerated by ILT optimization of target mask design, and mask designgenerated by ILT optimization of target mask design.illustrates mask designgenerated by ILT optimization of target mask design.

4 FIGS.A-C 4 FIGS.A-C 403 300 302 403 403 302 illustrate examples of predicted ILT mask designs in accordance with aspects of the technology. By way of example, predicted ILT mask designis output by a ML ILT model when the target mask designis input to that ML ILT model outputs. As demonstrated by comparing the mask designgenerated by a selected ILT optimization to the predicted ILT mask design, the predicted ILT mask designis very similar to the mask design. The same is true for each pair of mask designs generated by an ILT optimization and predicted ILT mask design illustrated by. A ML ILT model can be trained until a predicted ILT mask design output by that ML ILT model for a given target mask design has at least a threshold level of accuracy relative to a mask design generated by an ILT optimization for that target mask design.

4 FIG.A 4 FIG.A 300 302 300 403 304 306 304 405 illustrates, for the target mask design, the mask designgenerated by an ILT optimization of the target mask designand the predicted ILT mask design.illustrates, for the target mask design, the mask designgenerated by an ILT optimization of the target mask designand predicted ILT mask design.

4 FIG.B 4 FIG.B 308 310 308 407 312 314 312 409 illustrates, for the target mask design, the mask designgenerated by an ILT optimization of the target mask designand predicted ILT mask design.illustrates, for the target mask design, the mask designgenerated by an ILT optimization of the target mask designand the predicted ILT mask design.

4 FIG.C 4 FIG.C 316 318 316 411 320 322 320 413 illustrates, for the target mask design, the mask designgenerated by an ILT optimization of the target mask designand predicted ILT mask design.illustrates, for the target mask design, the mask designgenerated by an ILT optimization of the target mask designand predicted ILT mask design.

5 FIGS.A-B illustrate examples of comparisons of simulated mask patterns based on mask designs to target mask designs in accordance with aspects of the technology. These mask patterns are results from simulating one or more lithography processes (e.g., mask writing) using a mask design.

5 FIG.A 500 510 500 520 500 510 520 By way of example,illustrates target mask design(not optimized), mask designgenerated by an ILT optimization of the target mask design, and predicted ILT mask designoutput by a trained ML ILT model based on the target mask design. The mask designis generated by the ILT optimization after a runtime of approximately thirty minutes. In contrast, the predicted ILT mask designis output by the ML ILT model after a runtime of a few milliseconds.

502 500 512 510 522 520 Mask patternis a result of simulating lithography processes using the target mask design. Mask patternis a result of simulating lithography processes using the mask design. Mask patternis a result of simulating lithography processes using the predicted ILT mask design.

502 512 500 522 500 510 520 522 500 512 512 522 502 Unlike the mask pattern, the mask pattern, resulting from the ILT optimization, includes sharp features (e.g., sharp corners) as in the target design. The mask patternalso includes sharp features as in the target design. Although, there are differences between the mask designgenerated by an ILT optimization and the predicted ILT mask design, the mask patternclosely resembles the target mask designand the mask pattern. Additionally, like the mask pattern, the mask patterndoes not include the defects (e.g., bridging defects) of the mask pattern.

5 FIG.A 504 502 500 514 512 500 524 522 500 522 500 512 522 512 502 522 502 500 illustrates a comparisonof the mask patternto the target mask design, a comparisonof the mask patternto the target mask design, and a comparisonof the mask patternto the target mask design. Although the mask patternincludes more differences relative to the target mask designthan the mask pattern, the mask patternstill closely resembles the mask patternwithout the defects of the mask pattern. Moreover, the mask patternhas fewer differences than the mask patternbased on the unoptimized target mask design.

5 FIG.B 530 540 530 550 530 540 550 By way of example,illustrates target mask design(not optimized), mask designgenerated by an ILT optimization of the target mask design, and predicted ILT mask designoutput by a trained ML ILT model based on the target mask design. The mask designis generated by the ILT optimization after a runtime of approximately thirty minutes. In contrast, the predicted ILT mask designis output by the ML ILT model after a runtime of a few milliseconds.

532 530 542 540 552 550 Mask patternis a result of simulating lithography processes using the target mask design. Mask patternis a result of simulating lithography processes using the mask design. Mask patternis a result of simulating lithography processes using the predicted ILT mask design.

540 550 552 530 542 542 552 532 Although there are differences between the mask designgenerated by an ILT optimization and the predicted ILT mask design, the mask patternclosely resembles the target mask design, and the mask pattern. Additionally, like the mask pattern, the mask patterndoes not include the defects of the mask pattern.

5 FIG.B 534 532 530 544 542 530 554 552 530 532 530 542 552 542 552 532 530 illustrates a comparisonof the mask patternto the target mask design, a comparisonof the mask patternto the target mask design, and a comparisonof the mask patternto the target mask design. Although the mask patternincludes more differences relative to the target mask designthan the mask pattern, the mask patternstill closely resembles the mask pattern. Moreover, the mask patternhas significantly fewer differences than the mask patternbased on the unoptimized target mask design.

6 FIGS.A-B illustrate examples of simulated mask patterns based on mask designs in accordance with aspects of the technology. These mask patterns are results from simulating one or more lithography processes (e.g., mask writing) using a mask design.

6 FIG.A 600 610 600 620 600 602 600 612 610 622 620 610 620 622 600 612 By way of example,illustrates target mask design(not optimized), mask designgenerated by an ILT optimization of the target mask design, and predicted ILT mask designoutput by a trained ML ILT model based on the target mask design. Mask patternis a result of simulating lithography processes using the target mask design. Mask patternis a result of simulating lithography processes using the mask design. Mask patternis a result of simulating lithography processes using the predicted ILT mask design. Although there are differences between the mask designgenerated by an ILT optimization and the predicted ILT mask design, the mask patternclosely resembles the target mask designand the mask pattern.

6 FIG.B 630 640 630 650 630 632 630 642 640 652 650 640 650 652 630 642 By way of example,illustrates target mask design(not optimized), mask designgenerated by an ILT optimization of the target mask design, and predicted ILT mask designoutput by a trained ML ILT model based on the target mask design. Mask patternis a result of simulating lithography processes using the target mask design. Mask patternis a result of simulating lithography processes using the mask design. Mask patternis a result of simulating lithography processes using the predicted ILT mask design. Although there are differences between the mask designgenerated by a selected ILT optimization and the predicted ILT mask design, the mask patternclosely resembles the target mask designand the mask pattern.

7 FIGS.A-B illustrate examples of simulated mask patterns based on augmented mask designs in accordance with aspects of the technology. These mask patterns are results from simulating one or more lithography processes using a mask design.

7 FIG.A 700 710 700 720 700 700 By way of example,illustrates augmented target mask design(not optimized), mask designgenerated by a selected ILT optimization of the target mask design, and predicted ILT mask designoutput by a ML ILT model based on the target mask design. The target mask designis augmented, relative to a corresponding mask design from a standard cell library, in that the corresponding mask design from the standard cell library is rotated and cropped in this example.

702 700 712 710 722 720 710 720 722 700 712 Mask patternis a result of simulating lithography processes using the target mask design. Mask patternis a result of simulating lithography processes using the mask design. Mask patternis a result of simulating lithography processes using the predicted ILT mask design. Although there are differences between the mask designgenerated by a selected ILT optimization and the predicted ILT mask design, the mask patternclosely resembles the target mask designand the mask pattern.

7 FIG.B 730 740 730 750 730 730 By way of example,illustrates target mask design(not optimized), mask designgenerated by a selected ILT optimization of the target mask design, and predicted ILT mask designoutput by a ML ILT model based on the target mask design. The target mask designis augmented, relative to a corresponding mask design from a standard cell library, in that the corresponding mask design from the standard cell library is rotated and cropped.

732 730 742 740 752 750 740 750 752 742 Mask patternis a result of simulating lithography processes using the target mask design. Mask patternis a result of simulating lithography processes using the mask design. Mask patternis a result of simulating lithography processes using the predicted ILT mask design. Although there are differences between the mask designgenerated by an ILT optimization and the predicted ILT mask design, the mask patternclosely resembles the mask pattern.

8 FIGS.A-L 8 FIG.A 8 FIG.A 800 802 800 806 800 illustrate examples of comparisons of optimizations using a hybrid ILT optimization approach in accordance with aspects of the technology to selected ILT optimizations.illustrates a target mask designand a predicted ILT mask designoutput by a ML ILT model based on the target mask design.illustrates a mask designgenerated by a selected ILT optimization of the target mask design.

8 FIG.A 808 808 802 806 800 illustrates a mask designgenerated by a hybrid ILT optimization approach disclosed herein. The mask designis the result of a selected ILT optimization initialized with the predicted ILT mask design. In contrast, the mask designis the result of a selected ILT optimization initialized with the target mask design.

8 FIG.B 804 800 803 800 805 802 804 illustrates a graphrepresenting loss relative to the target mask designachieved by an optimization as more iterations of that optimization are performed. The linecorresponds to the selected ILT optimization initialized with the target mask design. The linecorresponds to the hybrid ILT optimization approach, which includes the selected ILT optimization initialized with the predicted ILT mask design. The graphshows that the hybrid ILT optimization approach provides a sustained advantage over only utilizing the selected ILT optimization. That is, the hybrid ILT optimization approach provides lesser loss values than the selected ILT optimization, even as more iterations are performed.

804 800 802 Moreover, the graphshows that the hybrid ILT optimization approach achieves a given loss value significantly quicker than the selected ILT optimization by itself. By way of example, the selected ILT optimization achieves a loss value of approximately 2,000 after approximately 60 iterations of the selected ILT optimization initialized with the target mask design(see the dashed lines). In contrast, the hybrid ILT optimization approach achieves a loss value of approximately 2,000 after only approximately 20 iterations of the selected ILT optimization initialized with the predicted ILT mask design. Thus, the hybrid ILT optimization approach provides the same loss value but in about a third of the time.

802 800 800 800 800 The hybrid ILT optimization approach provides this advantage because using the predicted ILT mask designto initialize the selected ILT optimization, instead of the target mask design, starts the selected ILT optimization with a mask design that, in effect, has the benefit of some optimization, by virtue of the ML ILT model, already been performed on the target mask design, but without actually performing the selected ILT optimization on the target mask design. Thus, the prediction of an ILT mask design by the ML ILT model effectively replaces iterations of the selected ILT optimization that would be performed if the selected ILT optimization were initialized with the target mask design. As described herein, the ML ILT model effectively replaces these iterations of the selected ILT optimization in a fraction of the time it would take to perform these iterations (e.g., milliseconds) with greatly reduced computational costs.

8 FIG.C 8 FIG.C 8 FIG.C 810 812 810 816 810 818 818 812 816 810 illustrates a target mask designand a predicted ILT mask designoutput by a ML ILT model based on the target mask design.illustrates a mask designgenerated by a selected ILT optimization of the target mask design.illustrates a mask designgenerated by a hybrid ILT optimization approach disclosed herein. The mask designis the result of a selected ILT optimization initialized with the predicted ILT mask design. In contrast, the mask designis the result of a selected ILT optimization initialized with the target mask design.

8 FIG.D 814 813 810 815 812 814 illustrates a graphrepresenting loss achieved by an optimization as more iterations of that optimization are performed. The linecorresponds to the selected ILT optimization initialized with the target mask design. The linecorresponds to the hybrid ILT optimization approach, which includes the selected ILT optimization initialized with the predicted ILT mask design. The graphshows that the hybrid ILT optimization approach provides a sustained advantage over the selected ILT optimization by itself. That is, the hybrid ILT optimization approach provides lesser loss values than the selected ILT optimization, even as more iterations are performed.

804 800 812 Moreover, the graphshows that the hybrid ILT optimization approach achieves a given loss value significantly quicker than the selected ILT optimization. By way of example, the selected ILT optimization achieves a loss value of approximately 200 after approximately 60 iterations of the selected ILT optimization initialized with the target mask design(see the dashed lines). In contrast, the hybrid ILT optimization approach achieves a loss value of approximately 200 after only approximately 20 iterations of the selected ILT optimization initialized with the predicted ILT mask design. Thus, the hybrid ILT optimization approach provides the same loss value but in about a third of the time.

812 810 810 810 800 The hybrid ILT optimization approach provides this advantage because using the predicted ILT mask designto initialize the selected ILT optimization, instead of the target mask design, starts the selected ILT optimization with a mask design that, in effect, has the benefit of some optimization, by virtue of the ML ILT model, already been performed on the target mask design, but without actually performing the selected ILT optimization on the target mask design. Thus, the prediction of an ILT mask design by the ML ILT model effectively replaces many iterations of the selected ILT optimization that would be performed if the selected ILT optimization were initialized with the target mask design.

8 FIG.E 8 FIG.E 8 FIG.E 820 822 820 826 820 828 828 822 826 820 illustrates a target mask designand a predicted ILT mask designoutput by a ML ILT model based on the target mask design.illustrates a mask designgenerated by a selected ILT optimization of the target mask design.illustrates a mask designgenerated by a hybrid ILT optimization approach disclosed herein. The mask designis the result of a selected ILT optimization initialized with the predicted ILT mask design. In contrast, the mask designis the result of a selected ILT optimization initialized with the target mask design.

8 FIG.F 824 823 820 825 822 824 illustrates a graphrepresenting loss achieved by an optimization as more iterations of that optimization are performed. The linecorresponds to the selected ILT optimization initialized with the target mask design. The linecorresponds to the hybrid ILT optimization approach, which includes the selected ILT optimization initialized with the predicted ILT mask design. The graphshows that the hybrid ILT optimization approach provides a sustained advantage over the selected ILT optimization. That is, the hybrid ILT optimization approach provides lesser loss values than the selected ILT optimization, even as more iterations are performed.

824 820 822 Moreover, the graphshows that the hybrid ILT optimization approach achieves a given loss value significantly quicker than the selected ILT optimization. By way of example, the selected ILT optimization achieves a loss value of approximately 200 after approximately 40 iterations of the selected ILT optimization initialized with the target mask design(see the dashed lines). In contrast, the hybrid ILT optimization approach achieves a loss value of approximately 200 after only approximately 10 iterations of the selected ILT optimization initialized with the predicted ILT mask design. Thus, the hybrid ILT optimization approach provides the same loss value but in about a quarter of the time.

822 820 820 820 820 The hybrid ILT optimization approach provides this advantage because using the predicted ILT mask designto initialize the selected ILT optimization, instead of the target mask design, starts the selected ILT optimization with a mask design that, in effect, has the benefit of some optimization, by virtue of the ML ILT model, already been performed on the target mask design, but without actually performing the selected ILT optimization on the target mask design. Thus, the prediction of an ILT mask design by the ML ILT model effectively replaces iterations of the selected ILT optimization that would be performed if the selected ILT optimization were initialized with the target mask design.

8 FIG.G 8 FIG.G 8 FIG.G 830 832 830 836 830 838 838 832 836 830 illustrates a target mask designand a predicted ILT mask designoutput by a ML ILT model based on the target mask design.illustrates a mask designgenerated by a selected ILT optimization of the target mask design.illustrates a mask designgenerated by a hybrid ILT optimization approach disclosed herein. The mask designis the result of a selected ILT optimization initialized with the predicted ILT mask design. In contrast, the mask designis the result of a selected ILT optimization initialized with the target mask design.

8 FIG.H 834 833 830 835 832 834 illustrates a graphrepresenting loss achieved by an optimization as more iterations of that optimization are performed. The linecorresponds to the selected ILT optimization initialized with the target mask design. The linecorresponds to the hybrid ILT optimization approach, which includes the selected ILT optimization initialized with the predicted ILT mask design. The graphshows that the hybrid ILT optimization approach provides a sustained advantage over the selected ILT optimization. That is, the hybrid ILT optimization approach provides lesser loss values than the selected ILT optimization, even as more iterations are performed.

834 830 832 Moreover, the graphshows that the hybrid ILT optimization approach achieves a given loss value significantly quicker than the selected ILT optimization. By way of example, the selected ILT optimization achieves a loss value of approximately 200 after approximately 60 iterations of the selected ILT optimization initialized with the target mask design(see the dashed lines). In contrast, the hybrid ILT optimization approach achieves a loss value of approximately 200 after only approximately 25 iterations of the selected ILT optimization initialized with the predicted ILT mask design. Thus, the hybrid ILT optimization approach provides the same loss value but in about 40% of the time.

832 830 830 830 830 The hybrid ILT optimization approach provides this advantage because using the predicted ILT mask designto initialize the selected ILT optimization, instead of the target mask design, starts the selected ILT optimization with a mask design that, in effect, has the benefit of some optimization, by virtue of the ML ILT model, already been performed on the target mask design, but without actually performing the selected ILT optimization on the target mask design. Thus, the prediction of an ILT mask design by the ML ILT model effectively replaces iterations of the selected ILT optimization that would be performed if the selected ILT optimization were initialized with the target mask design.

8 FIG.I 8 FIG.I 8 FIG.I 840 842 840 846 840 848 848 842 846 840 illustrates a target mask designand a predicted ILT mask designoutput by a ML ILT model based on the target mask design.illustrates a mask designgenerated by a selected ILT optimization of the target mask design.illustrates a mask designgenerated by a hybrid ILT optimization approach disclosed herein. The mask designis the result of a selected ILT optimization initialized with the predicted ILT mask design. In contrast, the mask designis the result of a selected ILT optimization initialized with the target mask design.

8 FIG.J 804 843 840 845 842 844 illustrates a graphrepresenting loss achieved by an optimization as more iterations of that optimization are performed. The linecorresponds to the selected ILT optimization initialized with the target mask design. The linecorresponds to the hybrid ILT optimization approach, which includes the selected ILT optimization initialized with the predicted ILT mask design. The graphshows that the hybrid ILT optimization approach provides a sustained advantage over the selected ILT optimization. That is, the hybrid ILT optimization approach provides lesser loss values than the selected ILT optimization, even as more iterations are performed.

844 840 842 Moreover, the graphshows that the hybrid ILT optimization approach achieves a given loss value significantly quicker than the selected ILT optimization. By way of example, the selected ILT optimization achieves a loss value of approximately 300 after approximately 80 iterations of the selected ILT optimization initialized with the target mask design(see the dashed lines). In contrast, the hybrid ILT optimization approach achieves a loss value of approximately 300 after only approximately 20 iterations of the selected ILT optimization initialized with the predicted ILT mask design. Thus, the hybrid ILT optimization approach provides the same loss value but in about a quarter of the time.

842 840 840 840 840 The hybrid ILT optimization approach provides this advantage because using the predicted ILT mask designto initialize the selected ILT optimization, instead of the target mask design, starts the selected ILT optimization with a mask design that, in effect, has the benefit of some optimization, by virtue of the ML ILT model, already been performed on the target mask design, but without actually performing the selected ILT optimization on the target mask design. Thus, the prediction of an ILT mask design by the ML ILT model effectively replaces iterations of the selected ILT optimization that would be performed if the selected ILT optimization were initialized with the target mask design.

8 FIG.K 8 FIG.K 8 FIG.K 850 852 850 856 850 858 858 852 856 850 illustrates a target mask designand a predicted ILT mask designoutput by a trained ML ILT model based on the target mask design.illustrates a mask designgenerated by a selected ILT optimization of the target mask design.illustrates a mask designgenerated by a hybrid ILT optimization approach disclosed herein. The mask designis the result of a selected ILT optimization initialized with the predicted ILT mask design. In contrast, the mask designis the result of a selected ILT optimization initialized with the target mask design.

8 FIG.L 854 853 850 855 852 854 illustrates a graphrepresenting loss achieved by an optimization as more iterations of that optimization are performed. The linecorresponds to the selected ILT optimization initialized with the target mask design. The linecorresponds to the hybrid ILT optimization approach, which includes the selected ILT optimization initialized with the predicted ILT mask design. The graphshows that the hybrid ILT optimization approach provides a sustained advantage over the selected ILT optimization. That is, the hybrid ILT optimization approach provides lesser loss values than the selected ILT optimization, even as more iterations are performed.

854 850 852 Moreover, the graphshows that the hybrid ILT optimization approach achieves a given loss value significantly quicker than the selected ILT optimization. By way of example, the selected ILT optimization achieves a loss value of approximately 300 after approximately 180 iterations of the selected ILT optimization initialized with the target mask design(see the dashed lines). In contrast, the hybrid ILT optimization approach achieves a loss value of approximately 300 after only approximately 40 iterations of the selected ILT optimization initialized with the predicted ILT mask design. Thus, the hybrid ILT optimization approach provides the same loss value but in about one fifth of the time.

852 850 850 850 850 The hybrid ILT optimization approach provides this advantage because using the predicted ILT mask designto initialize the selected ILT optimization, instead of the target mask design, starts the selected ILT optimization with a mask design that, in effect, has the benefit of some optimization, by virtue of the ML ILT model, already been performed on the target mask design, but without actually performing the selected ILT optimization on the target mask design. Thus, the prediction of an ILT mask design by the ML ILT model effectively replaces iterations of the selected ILT optimization that would be performed if the selected ILT optimization were initialized with the target mask design.

9 FIG. 900 900 902 904 900 906 900 908 900 illustrates an example methodin accordance with the above discussion. The methodincludes, at block, obtaining, by one or more processors, a target mask design for a semiconductor device to be fabricated. At block, the methodincludes determining, by the one or more processors based on a machine learning inverse lithography technology (ML ILT) model, a predicted ILT mask design corresponding to the target mask design. At block, the methodincludes performing, by one or more processors, an ILT optimization using the predicted ILT mask design as an initialization point. At block, the methodincludes generating, by one or more processors based on completion of the ILT optimization, a mask design in order to fabricate the semiconductor device.

Although the technology herein has been described with reference to particular embodiments and configurations, it is to be understood that these embodiments and configurations are merely illustrative of the principles and applications of the present technology. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and configurations, and that other arrangements may be devised without departing from the spirit and scope of the present technology as defined by the appended claims.