Fabrication Method of High Electron Mobility Transistor Structure

This application is a division of U.S. application Ser. No. 18/098,079, filed on Jan. 17, 2023. The content of the application is incorporated herein by reference.

The present disclosure relates generally to a fabrication method of semiconductor devices, and more particularly to a fabrication method of a high electron mobility transistor (HEMT) structure integrating an enhancement-mode HEMT and a depletion-mode HEMT.

In the applications of AC/DC power converters and drivers, junction field-effect transistors (JFETs) or depletion-mode field-effect transistors (D-mode FETs) are usually used to provide start-up function. However, the conventional JFETs require a well region to pinch-off the voltage, and the well region is most likely varied by the fabrication process, which easily leads to a shift in the pinch-off voltage. In addition, a gate structure of the conventional D-mode FETs such as depletion mode metal-insulator-semiconductor field effect transistors (D-mode MISFETs) requires forming a gate recess. However, the etching depth of the gate recess is not easy to be precisely controlled, which leads to instability of the threshold voltage (Vt) of the D-mode MISFETs. In addition, interface traps are usually produced between the gate dielectric layer and the semiconductor layer of the D-mode MISFETs, thereby reducing the reliability of the D-mode MISFETs.

In view of this, the present disclosure provides a high electron mobility transistor (HEMT) structure and a fabrication method thereof. The HEMT structure integrates an enhancement-mode (E-mode) HEMT and a depletion-mode (D-mode) HEMT, and the fabrication method thereof does not require additional process steps. A layout of a compound semiconductor cap layer of the HEMT structure is used to achieve the effect of lateral depletion, so that the HEMT structures of the present disclosure provide a start-up function. Moreover, through adjusting the width of a gap between segments of the compound semiconductor cap layer, the threshold voltage (Vt) of the D-mode HEMT is precisely controlled, so that the HEMT structures of the present disclosure have stable and precise electrical characteristics.

According to one embodiment of the present disclosure, a high electron mobility transistor structure is provided and includes a substrate, a compound semiconductor channel layer, a compound semiconductor barrier layer, a compound semiconductor cap layer, a gate electrode, a source electrode and a drain electrode. The compound semiconductor channel layer is disposed on the substrate. The compound semiconductor barrier layer is disposed on the compound semiconductor channel layer. The compound semiconductor cap layer is disposed on the compound semiconductor barrier layer. Moreover, the compound semiconductor cap layer includes a first segment and a second segment arranged along a first direction, and there is a first gap between the first segment and the second segment. The gate electrode is disposed on the compound semiconductor cap layer. The source electrode and the drain electrode are disposed on the compound semiconductor barrier layer, arranged along a second direction, and respectively located on two opposite sides of the compound semiconductor cap layer.

According to one embodiment of the present disclosure, a fabrication method of a high electron mobility transistor structure is provided and includes the following steps. A compound semiconductor channel layer is formed on a substrate. A compound semiconductor barrier layer is formed on the compound semiconductor channel layer. A compound semiconductor cap layer is formed on the compound semiconductor barrier layer. The compound semiconductor cap layer includes a first segment and a second segment arranged along a first direction, and there is a first gap between the first segment and the second segment. A gate electrode is formed on the compound semiconductor cap layer. In addition, a source electrode and a drain electrode are formed on the compound semiconductor barrier layer. The source electrode and the drain electrode are arranged along a second direction, and respectively located on two opposite sides of the compound semiconductor cap layer.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “under,” “lower,” “over,” “above,” “on,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” and/or “beneath” other elements or features would then be oriented “above” and/or “over” the other elements or features. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

It is understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer and/or section from another region, layer and/or section. Terms such as “first,” “second,” and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer and/or section discussed below could be termed a second element, component, region, layer and/or section without departing from the teachings of the embodiments.

As disclosed herein, the term “about” or “substantial” generally means within 20%, 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. Unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages disclosed herein should be understood as modified in all instances by the term “about” or “substantial”. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired.

Furthermore, as disclosed herein, the terms “coupled to” and “electrically connected to” include any directly and indirectly electrical connecting means. Therefore, if it is described in this document that a first component is coupled or electrically connected to a second component, it means that the first component may be directly connected to the second component, or may be indirectly connected to the second component through other components or other connecting means.

In the present disclosure, a “compound semiconductor” refers to a group III-V compound semiconductor that includes at least one group III element and at least one group V element, where group III element may be boron (B), aluminum (Al), gallium (Ga) or indium (In), and group V element may be nitrogen (N), phosphorous (P), arsenic (As), or antimony (Sb). Furthermore, the group III-V semiconductor may refer to, but not limited to, gallium nitride (GaN), indium phosphide (InP), aluminum arsenide (AlAs), gallium arsenide (GaAs), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), gallium indium phosphide (GaInP), AlGaAs, InAlAs, InGaAs, or the like, or the combination thereof. Besides, based on different requirements, group III-V compound semiconductor may contain dopants to become semiconductor with specific conductivity type, such as n-type or p-type.

Although the disclosure is described with respect to specific embodiments, the principles of the disclosure, as defined by the claims appended herein, can obviously be applied beyond the specifically described embodiments of the disclosure described herein. Moreover, in the description of the present disclosure, certain details have been left out in order to not obscure the inventive aspects of the disclosure. The details left out are within the knowledge of a person having ordinary skill in the art.

The present disclosure is directed to a high electron mobility transistor (HEMT) structure integrating an enhancement-mode (E-mode) HEMT and a depletion-mode (D-mode) HEMT and a fabrication method thereof. Through the layout of a compound semiconductor cap layer, the HEMT structure does not require additional process steps to achieve the effect of lateral depletion. Accordingly, the HEMT structures of the present disclosure provide a start-up function. Moreover, the threshold voltage (Vt) of the D-mode HEMT is precisely controlled by adjusting the width of a gap between segments of the compound semiconductor cap layer. When compared with the conventional depletion-mode metal-insulator-semiconductor field-effect transistors (D-mode MISFETs), the threshold voltage (Vt) of the D-mode HEMT of the HEMT structures of the present disclosure is stably and accurately controlled, so that the pinch-off voltage of the HEMT structures of the present disclosure is precisely controlled while providing a start-up function. Moreover, the interface trap between the gate dielectric layer and the semiconductor layer of the conventional D-mode MISFETs is overcome by the present disclosure, thereby improving the reliability of the HEMT structures.

1 FIG. 100 101 101 101 101 101 101 is a schematic top view of a HEMT structure according to an embodiment of the present disclosure. The HEMT structureincludes a substrate. In some embodiments, the material of the substratemay include ceramics, silicon carbide (SiC), aluminum nitride (AlN), sapphire or silicon. When the substrateis made of a material with high hardness, high thermal conductivity and low electrical conductivity, such as a ceramic substrate, it is more suitable for high-voltage semiconductor devices. The aforementioned high hardness, high thermal conductivity and low electrical conductivity of the substrateare compared with a single-crystal silicon substrate, and the high-voltage semiconductor devices refer to semiconductor devices with an operating voltage higher than 50V. In some embodiments, the substratemay be a semiconductor-on-insulator (SOI) substrate. In some other embodiments, the substratemay be provided by a composite substrate (or referred to as a QST substrate) composed of a core substrate wrapped around by a composite material layer. The core substrate includes ceramics, silicon carbide, aluminum nitride, sapphire or silicon. The composite material layer includes an insulating material layer and a semiconductor material layer. The insulating material layer may be single or multiple layers of silicon oxide, silicon nitride or silicon oxynitride. The semiconductor material layer may be silicon or polysilicon. In addition, during the fabrication of the HEMT structures, the composite material layer located on the backside of the core substrate may be removed by a thinning process, such as a grinding or etching process, so that the backside of the core substrate is exposed.

1 FIG. 1 FIG. 100 105 101 107 105 107 107 1 107 2 107 3 107 100 107 108 1 107 1 107 2 108 2 107 2 107 3 105 108 1 108 2 108 1 108 2 1 2 1 2 100 100 Still referring to, from a top view, the HEMT structureincludes a compound semiconductor barrier layer(hereinafter referred to as a barrier layer) disposed on the substrate, and a compound semiconductor cap layer(hereinafter referred to as a cap layer) disposed on the barrier layer. In some embodiments of the present disclosure, the cap layerincludes a plurality of segments, such as a first segment-, a second segment-, a third segment-, etc. Although five segments are shown in, more or fewer segments may be provided for the cap layerbased on various requirements of the HEMT structure. These segments of the cap layerare arranged along a first direction (for example, the X-axis direction), and these segments are separated from each other with respective gaps. For example, there is a first gap-between the first segment-and the second segment-. A second gap-is between the second segment-and the third segment-, and so on. In some embodiments, a partial surface of the barrier layeris exposed through the first gap-, the second gap-and other gaps. According to the embodiments of the present disclosure, the widths of the first gap-, the second gap-and other gaps in the first direction (for example, the X-axis direction), such as a first gap width S, a second gap width S, and other gap widths may be in a range from about 0.01 micrometers (μm) to about 1 μm. Moreover, the first gap width S, the second gap width Sand other gap widths may be the same as or different from each other based on the electrical requirements of the HEMT structure. The gap widths within this range make the HEMT structureachieve the required effect of lateral depletion.

107 1 107 2 107 3 1 2 3 1 2 100 100 100 100 In addition, according to some embodiments of the present disclosure, the range of the widths of the first segment-, the second segment-, the third segment-and other segments in the first direction (for example, the X-axis direction), such as a first segment width W, a second segment width W, a third segment width Wand other segment widths are determined by the range of the first gap width S, the second gap width Sand other gap widths. When the gap width is smaller, the ratio of the segment width to the gap width may be smaller. When each gap width is less than 1 μm, the effect of required lateral depletion achieved by the HEMT structureis better, and the device of the HEMT structureis turned off. In some embodiments, each gap width is, for example, from about 0.01 μm to about 0.5 μm, and the ratio of each segment width to each gap width is about 5 to 200, so that the HEMT structureachieves the effect of lateral depletion to quickly turn off the device thereof. In one embodiment, when the gap width is about 0.4 μm, the ratio of the segment width to the gap width is about 5 to turn off the device, and the segment width is about 2.0 μm. In another embodiment, when the gap width is about 0.5 μm, the ratio of the segment width to the gap width is about 179 to turn off the device, and the segment width is about 89.5 μm. In addition, when each gap width is smaller and each segment width is larger, the ratio of the segment width to the gap width is larger. In these conditions, the HEMT structureachieves the effect of lateral depletion faster and the device is turned off faster, so that the required threshold voltage (Vt) is smaller. Moreover, the magnitude of the threshold voltage (Vt) may also be adjusted according to the requirements of applications, as long as the device is turn-off.

1 2 3 1 2 3 100 100 100 1 1 1 2 1 1 2 2 1 2 3 2 In some embodiments, the first segment width W, the second segment width W, the third segment width W, and other segment widths may be in a range from about 1 μm to about 500 μm, which is based on the respective gap widths, for example, each gap width may be in a range from about 0.01 μm to about 5 μm. In addition, the first segment width W, the second segment width W, the third segment width Wand other segment widths may be the same as or different from each other based on the electrical requirements of the HEMT structures. Moreover, the effect of required lateral depletion for the HEMT structureis achieved by adjusting the segment width based on the gap width. Furthermore, in the embodiments of the present disclosure, each segment width and each gap width may be adjusted according to various electrical requirements (such as the pinch-off voltage, the threshold voltage, the drain current, etc.) of the HEMT structure, so that the HEMT structurehas more flexibility of products. In some embodiments, in the first direction (for example, the X-axis direction), the first gap width Sis about 0.01 μm to about 0.5 μm, and the ratio of the first segment width Wto the first gap width Smay be in a range from 5 to 200. In some embodiments, the second segment width Wmay be less than or equal to the first segment width W, and the first gap width Sand the second gap width Smay be respectively in a range from about 0.01 μm to about 0.5 μm. The ratio of the second segment width Wto the first gap width Sor the second gap width Smay be in a range from 5 to 200. In addition, the ratio of the third segment width Wto the second gap width Smay be in a range from 5 to 200.

1 FIG. 100 109 107 109 107 1 108 1 107 2 108 2 107 3 107 109 109 107 1 107 2 107 3 107 100 111 113 105 111 113 107 109 111 113 Still referring to, the HEMT structurefurther includes a gate electrodedisposed on the cap layer. In some embodiments, the gate electrodemay continuously cover the first segment-, the first gap-, the second segment-, the second gap-, the third segment-, other segments, and other gaps of the cap layer. In other embodiments, the gate electrodemay include a plurality of portions separated from each other along the first direction (for example, the X-axis direction). These portions of the gate electrodeare disposed directly above and respectively correspond to the first segment-, the second segment-, the third segment-, and other segments of the cap layer. In addition, the HEMT structureincludes a source electrodeand a drain electrodedisposed on the barrier layer. The source electrodeand the drain electrodeare arranged along a second direction (for example, the Y-axis direction), and are respectively located on two opposite sides of the cap layer, and are respectively located on two opposite sides of the gate electrode. The long axes of the source electrodeand the drain electrodeare respectively extended along the first direction (for example, the X-axis direction) to be a continuous electrode pattern.

2 FIG. 1 FIG. 2 FIG. 100 102 104 106 101 102 104 106 102 104 106 102 104 106 100 103 106 105 103 105 103 107 103 105 107 100 100 is a schematic cross-sectional view of a HEMT structure along the line B-B′ inaccording to an embodiment of the present disclosure. As shown in, in some embodiments, the HEMT structurefurther includes a nucleation layer, a buffer layerand a high resistance layer(or referred to as an electrical isolation layer) stacked on the substratein order from bottom to top. The materials of the nucleation layer, the buffer layerand the high resistance layerinclude compound semiconductors. In some embodiments, the nucleation layeris, for example, an aluminum nitride (AlN) layer. The buffer layermay be a superlattice (SL) structure, for example, including a plurality of alternately stacked aluminum gallium nitride (AlGaN) layers and aluminum nitride (AlN) layers. The high resistance layeris, for example, a carbon-doped gallium nitride (C-GaN) layer. The aforementioned materials of the nucleation layer, the buffer layerand the high resistance layerare for example, but not limited thereto. In addition, the HEMT structureincludes a compound semiconductor channel layer(hereinafter referred to as a channel layer) disposed between the high resistance layerand the barrier layer. In some embodiments, the channel layeris such as an undoped compound semiconductor layer, for example, an undoped gallium nitride (u-GaN) layer. The barrier layeris a compound semiconductor layer with an energy gap larger than that of the channel layer, for example, an aluminum gallium nitride (AlGaN) layer. The cap layeris such as a p-type compound semiconductor layer, for example, a p-type gallium nitride (p-GaN) layer. The aforementioned materials of the channel layer, the barrier layerand the cap layerare for example, but not limited thereto. The compositions and structural arrangements of the compound semiconductor layers of the HEMT structureare determined according to the requirements of various semiconductor devices using the HEMT structure.

2 FIG. 109 107 111 113 105 109 113 109 111 109 103 105 111 113 103 105 103 105 103 105 109 111 113 109 107 111 113 103 105 As shown in, the gate electrodeis disposed on the cap layer. The source electrodeand the drain electrodeare disposed on the barrier layer, and respectively located on two opposite sides of the gate electrode. The distance between the drain electrodeand gate electrodemay be greater than the distance between source electrodeand gate electrode. The channel layerand the barrier layerare extended along the second direction (for example, the Y-axis direction) between the source electrodeand the drain electrode. Since there is a discontinuous energy gap between the channel layerand the barrier layer, by stacking the channel layerand the barrier layerwith each other, electrons will be gathered at the heterojunction between the channel layerand the barrier layerdue to the piezoelectric effect, thereby producing a thin layer with high electron mobility, i.e., a two-dimensional electron gas region 2 DEG. In addition, the materials of the gate electrode, the source electrodeand the drain electrodemay include conductive materials such as metals, alloys, metal nitrides or semiconductor materials. In some embodiments, the metal may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), other suitable metals, or a combination thereof. The gate electrodemay produce a Schottky contact with the cap layer. The source electrodeand the drain electrodemay produce an ohmic contact with the underlying semiconductor layer such as the channel layerand the barrier layer.

109 107 111 113 109 107 111 113 111 113 2 FIG. For an E-mode (or referred to as normally-off) HEMT, when no voltage is applied to the gate electrode, the region covered by the cap layerdoes not form a two-dimensional electron gas (as shown in) and is regarded as a 2 DEG cut-off region, so that there is no conduction between the source electrodeand the drain electrode. When a positive voltage is applied to the gate electrode, the region covered by the cap layerwill form a two-dimensional electron gas, so that a continuous two-dimensional electron gas region is generated between the source electrodeand the drain electrodeto make conduction between the source electrodeand the drain electrode.

109 107 111 113 111 113 109 107 111 113 In addition, for a D-mode (or referred to as normally-on) HEMT, when no voltage or only a weak positive voltage is applied to the gate electrode, the region not covered by the cap layerstill forms a two-dimensional electron gas, so that the region between the source electrodeand the drain electrodewill generate a continuous two-dimensional electron gas region to make conduction between the source electrodeand the drain electrode. When a negative voltage is applied to the gate electrode, the two-dimensional electron gas in the region not covered by the cap layerwill be cut-off, which is regarded as a 2 DEG cut-off region, so that there is no conduction between the source electrodeand the drain electrode.

3 FIG. 1 FIG. 3 FIG. 100 100 107 107 1 107 2 100 107 108 1 109 103 105 100 103 105 100 109 109 1 109 2 109 107 1 107 2 107 108 1 109 is a schematic cross-sectional view of a HEMT structure along the line A-A′ inaccording to an embodiment of the present disclosure. As shown in, the HEMT structureincludes an enhancement-mode (E-mode) regionE corresponding to each segment of the cap layer, such as the first segment-and the second segment-, and a depletion-mode (D-mode) regionD corresponding to the gap between the segments of the cap layer, for example, the first gap-. According to the embodiments of the present disclosure, when no voltage is applied to the gate electrode, a two-dimensional electron gas region 2 DEG is generated at the heterojunction between the channel layerand the barrier layerin the D-mode regionD, and no 2 DEG region is generated at the heterojunction between the channel layerand the barrier layerin the E-mode the regionE. In addition, in this embodiment, the gate electrodeincludes a plurality of portions separated from each other, such as a first portion-and a second portion-. Theses portions of the gate electrodeare disposed directly above and respectively correspond to the first segment-and the second segment-of the cap layer. In addition, the first gap-is not filled up with the gate electrode.

1 FIG. 3 FIG. 100 109 113 113 108 1 111 100 Please refer toand, according to the embodiments of the present disclosure, during the operation of the HEMT structure, when no voltage or only a weak positive voltage is applied to the gate electrode, and a positive voltage is applied to the drain electrode, the current flows from the drain electrode, passes through the two-dimensional electron gas region 2 DEG below the first gap-, and then flows to the source electrode, so that the HEMT structureis in an on-state.

109 108 1 108 1 113 113 111 108 1 100 In contrast, when a sufficient negative voltage is applied to the gate electrode, it will generate an electric field to the two-dimensional electron gas region 2 DEG below the first gap-, so that the two-dimensional electron gas region 2 DEG below the first gap-is disappeared due to the influence of the electric field. Therefore, even if a positive voltage is applied to the drain electrode, the current still cannot flow from the drain electrodeto the source electrodethrough the region below the first gap-, so that the HEMT structureis in an off-state.

100 107 100 100 103 107 1 107 2 107 103 108 1 107 100 Therefore, according to the HEMT structuresof the embodiments of the present disclosure, by using the layout of the cap layerin the E-mode regionE and the D-mode regionD, the regions of the channel layerdirectly below the first segment-and the second segment-of the cap layerconstitute the channel region of an E-mode HEMT, and the other region of the channel layerdirectly below the first gap-of the cap layerconstitutes the channel region of a D-mode HEMT or a junction field effect transistor (JFET), so that the HEMT structuresof the present disclosure achieve the effect of lateral depletion to provide a start-up function in the applications of AC/DC power converters and drivers.

4 FIG. 1 FIG. 3 FIG. 3 FIG. 4 FIG. 5 FIG. 4 FIG. 4 FIG. 1 FIG. 4 FIG. 100 101 107 107 1 107 1 107 2 2 107 1 1 107 1 107 2 2 107 1 1 107 1 107 2 2 107 1 1 107 1 107 2 107 1 108 1 108 1 107 1 107 2 109 108 1 107 1 109 113 113 111 103 108 1 107 1 100 109 109 1 109 2 109 107 1 107 2 107 108 1 109 109 107 1 107 2 107 3 107 107 2 107 3 107 1 100 is a schematic cross-sectional view of a portion of a HEMT structure along the line A-A′ inaccording to another embodiment of the present disclosure, which shows another structure of the region C in. According to the embodiments of the present disclosure, the structure of the region C shown in,andmay be regarded as a repeating unit of the HEMT structure. The repeating unit is arranged repeatedly along the first direction (for example, the X-axis direction) on the substrateto construct the HEMT structure. Referring to, in this embodiment, the cap layermay further include a first connecting portion-Cdisposed between the first segment-and the second segment-. The thickness Tof the first connecting portion-Cis smaller than the respective thicknesses Tof the first segment-and the second segment-. In some embodiments, the thickness Tof the first connecting portion-Cis between about 10 nanometers (nm) and about 100 nm, and the respective thicknesses Tof the first segment-and the second segment-are between about 50 nm and about 150 nm. According to some embodiments of the present disclosure, since the thickness Tof the first connection portion-Cis about 5% to 70% of the respective thicknesses Tof the first segment-and the second segment-, the first connecting portion-Cdoes not make the two-dimensional electron gas region 2 DEG directly below the first gap-to be completely cut-off. Since the first gap-still has enough space between the first segment-and the second segment-, when a sufficient negative voltage is applied to the gate electrode, the two-dimensional electron gas region 2 DEG directly below the first gap-and the first connecting portion-Cwill still be affected by the electric field from the gate electrodeto be disappeared. Therefore, even if a positive voltage is applied to the drain electrode, the current cannot flow from the drain electrodeto the source electrodethrough the channel layerbelow the first gap-and the first connecting portion-C. Accordingly, the HEMT structureis still in an off-state, and has a start-up function similar to that provided by D-mode HEMT or junction field effect transistor (JFET). In addition, as shown in, in this embodiment, the gate electrodeincludes a plurality of portions separated from each other, such as the first portion-and the second portion-. Theses portions of the gate electroderespectively correspond to and are disposed directly above the first segment-and the second segment-of the cap layer. In addition, the first gap-is not filled up with the gate electrode, i.e., the gate electrodedoes not cover the first connecting portion-C. Moreover, referring toand, a second connecting portion (not shown) may also be disposed between the second segment-and the third segment-of the cap layer. The thickness of the second connecting portion is smaller than the respective thicknesses of the second segment-and the third segment-. In some embodiments, the thicknesses of the first connecting portion-Cand the second connecting portion may be the same as or different from each other according to the electrical requirements of the HEMT structure.

5 FIG. 1 FIG. 3 FIG. 105 108 1 109 107 1 107 105 107 2 107 109 108 1 109 108 1 is a schematic cross-sectional view of a portion of a HEMT structure along the line A-A′ inaccording to further another embodiment of the present disclosure, which shows another structure of the region C in. In this embodiment, a partial surface of the barrier layeris exposed through the first gap-, and the gate electrodecontinuously covers the first segment-of the cap layer, the aforementioned partial surface of the barrier layer, and the second segment-of the cap layer. In one embodiment, the gate electrodemay fill up the first gap-and have a flat top surface. In another embodiment, the gate electrodemay be conformally formed on the sidewalls and the bottom surface of the first gap-, and have a top surface with a concave-convex profile.

6 FIG. 6 FIG. 6 FIG. 6 FIG. 200 200 200 200 107 107 200 200 is graphs showing the drain current versus the gate voltage of HEMT structures according to some embodiments of the present disclosure. The vertical axis is the drain current Id with a unit of ampere (A), and the horizontal axis is the gate voltage Vg with a unit of volts (V). The drain current of the graphB is the drain current of the graphA represented in an exponential form, so that the change of the drain current Id of each curved line in the graphB within the range from 0 A to 0.2 A is easier observed than that in the graphA. The curved lines ofrespectively represent the characteristics of the drain current corresponding to the gate voltage of the HEMT structures of some embodiments, where the respective cap layersthereof have different sizes in the gap width S and the segment width W. The units of the gap width S and the segment width W of the cap layerin these embodiments are micrometers (μm). The gap width S and the segment width W of the embodiments inare respectively S=0.8/W=89.2, S=0.5/W=89.5, S=0.8/W=2, S=0.5/W=2, and S=0.4/W=2. As shown in the graphsA andB of, it is known that the cap layers of the HEMT structures with a larger segment width W (for example, W=89.2, W=89.5) make the drain current be cut-off quickly while less negative voltage is applied to the gate electrode. The cap layers of the HEMT structures with a smaller gap width S (for example, S=0.4, S=0.5) make the cut-off drain current be reduced to a lower value while the same negative voltage is applied to the gate electrode. Therefore, according to the embodiments of the present disclosure, the HEMT structures may have different electrical characteristics by adjusting the gap width and the segment width of the cap layer, thereby improving the flexibility of the HEMT structures in application to different electronic products.

7 FIG. 8 FIG. 1 FIG. 7 FIG. 2 FIG. 102 104 106 103 105 110 101 110 107 101 120 110 120 120 1 107 108 1 andare schematic cross-sectional views of some stages of a fabrication method of a HEMT structure along the line A-A′ inaccording to an embodiment of the present disclosure. As shown in, firstly, a nucleation layer, a buffer layer, a high resistance layer, a channel layer, a barrier layerand a compound semiconductor material layerare sequentially stacked on a substrate. The compound semiconductor material layeris used to form a cap layerin the subsequent process. The materials of the aforementioned layers are all compound semiconductors and the compositions thereof may refer to the aforementioned description of. The aforementioned layers may be formed in sequence on the substratefrom bottom to top by using different epitaxial growth processes. Next, a patterned photoresistis formed on the compound semiconductor material layer. The patterned photoresisthas an opening-corresponding to a predetermined region of a gap of the cap layer, such as a first gap-.

7 FIG. 101 120 1 120 110 120 107 107 1 107 2 108 1 Still referring to, at step S, an etching process is used to make an etchant pass through the opening-of the patterned photoresistto completely remove a portion of the compound semiconductor material layernot covered by the patterned photoresist, thereby forming each segment and each gap of the cap layer, such as a first segment-, a second segment-, and a first gap-.

8 FIG. 1 FIG. 103 108 1 107 107 1 107 1 107 1 107 2 105 109 107 109 107 1 107 1 107 2 108 1 107 109 111 113 105 100 Next, referring to, at step S, an epitaxial growth process is used to epitaxially grow a compound semiconductor material in the first gap-, thereby forming each connecting portion of the cap layer, for example, a first connecting portion-C. The thickness of the first connecting portion-Cis smaller than the respective thicknesses of the first segment-and the second segment-. Afterwards, at step S, a gate electrodeis formed on the cap layerby deposition, photolithography and etching processes. In this embodiment, the gate electrodecontinuously covers the first segment-, the first connecting portion-Cand the second segment-, and fills up the first gap-of the cap layer, so that the gate electrodehas a flat top surface. Then, referring to, the source electrodeand the drain electrodeare formed on the barrier layerto complete the HEMT structure.

9 FIG. 1 FIG. 7 FIG. 2 FIG. 7 FIG. 9 FIG. 1 FIG. 102 104 106 103 105 110 101 110 107 101 121 110 110 121 112 112 107 is a schematic cross-sectional view of an intermediate stage of a fabrication method of a HEMT structure along the line A-A′ inaccording to another embodiment of the present disclosure. Firstly, referring to, a nucleation layer, a buffer layer, a high resistance layer, a channel layer, a barrier layer, and a compound semiconductor material layerare sequentially stacked on a substrate. The compound semiconductor material layeris used to form a cap layerin the subsequent process. The materials of the aforementioned layers are compound semiconductors and the compositions thereof may refer to the aforementioned description of. The aforementioned layers may be formed in sequence on the substratefrom bottom to top by using different epitaxial growth processes. Next, referring toand, a first patterned photoresistis formed on the compound semiconductor material layer. Then, an etching process is used to remove a portion of the compound semiconductor material layernot covered by the first patterned photoresist, thereby forming a patterned compound semiconductor material block. The pattern of the patterned compound semiconductor material blockcorresponds to the outline of each segment of the cap layershown inconnected with each other by each connecting portion.

9 FIG. 1 FIG. 8 FIG. 201 121 130 112 130 130 1 107 108 1 130 1 130 112 130 1 107 107 1 130 109 107 111 113 105 100 Still referring to, at step S, firstly, the first patterned photoresistis removed, and then a second patterned photoresistis formed on the patterned compound semiconductor material block. The second patterned photoresisthas an opening-corresponding to a predetermined region of a gap of the cap layer, such as a first gap-. Then, an etching process is used to make an etchant pass through the opening-of the second patterned photoresistto remove an upper portion of the patterned compound semiconductor material blockexposed through the opening-, thereby forming a connecting portion of the cap layer, for example, a first connecting portion-C. Afterwards, the second patterned photoresistis removed. Then, referring toand, the gate electrodeis formed on the cap layer, and the source electrodeand the drain electrodeare formed on the barrier layerto complete the HEMT structure.

The HEMT structures of the embodiments of the present disclosure integrate the E-mode HEMT and the D-mode HEMT by using the layout of the compound semiconductor cap layer without additional process steps, thereby achieving the effect of lateral depletion. Therefore, the HEMT structures of the present disclosure have the start-up function the same as that provided by junction field effect transistors or D-mode field effect transistors. In addition, according to the HEMT structures of the present disclosure, the threshold voltage (Vt) of the D-mode HEMT is stably and precisely controlled by adjusting the gap width between the segments of the compound semiconductor cap layer. Compared with the conventional D-mode MISFETs, the HEMT structures of the present disclosure do not need to form a gate recess and a gate dielectric layer, thereby precisely controlling the threshold voltage (Vt) of the devices and avoiding the interface traps between the gate dielectric layer and the semiconductor layer of the conventional D-mode MISFETs. Therefore, the electrical performances and the reliability of the semiconductor devices using the HEMT structures of the present disclosure are improved. In addition, the fabricating processes of the HEMT structures of the present disclosure are compatible with the existing HEMT fabricating processes, thereby reducing the manufacturing cost thereof. Moreover, the HEMT structures of the present disclosure may be fabricated together with other HEMTs on the same wafer at the same time.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

The foregoing outlines the features of several embodiments, enabling those skilled in the art to fully appreciate the aspects of the present disclosure. Those skilled in the art should recognize that the present disclosure provides a foundation for designing or modifying other processes and structures to achieve substantially the same functions and/or substantially the same results as those of the embodiments introduced herein. Furthermore, such equivalent arrangements do not deviate from the spirit and scope of the present disclosure, and various changes, substitutions, and alterations may be made without so departing.