Resistive Random Access Memory (rram) Structure and Mult-Step Memory Opreration with All Word Lines Activated

The present disclosure relates to memory structures and, more particularly, to embodiments of a memory structure (e.g., a resistive random access memory (RRAM) structure and a method of operating the memory structure.

RRAM structures include an array of RRAM cells (also referred to herein as bit cells) arranged in columns and rows. Each bit cell can be, for example, a one-transistor one-resistor (1T1R) memory cell. Bit cells in each column can be connected between a source line (SL) and a bit line (BL) for the column. Bit cells in each row can be connected to a word line (WL) for the row. Specifically, each bit cell in a given column and a given row can include: a programmable resistor with a first terminal connected to the SL for the column and a second terminal opposite the first terminal; and an access transistor (e.g. a N-type field effect transistor) including a first source/drain region connected to the second terminal of the programmable resistor, a second source/drain region connected to the BL for the column, and a gate connected to the WL for the row.

Write operations in an RRAM structure can include a forming operation, a programming operation (also referred to herein as a set operation), and an erasing operation (also referred to herein as a reset operation). During a forming operation, the resistance state of the programmable resistor of a selected bit cell is switched from an initial very high resistance state (iHRS), as seen immediately after manufacturing, to an operational resistance state that is lower than the iHRS (e.g., to an operational high resistance state (HRS) or to an operational resistance state (LRS)). The HRS can be used to store, for example, a logic “0” and the LRS can be used to store, for example, a logic “1.” During a programming operation, the resistance state of the programmable resistor in a selected bit cell is switched from the HRS to the LRS (i.e., to store a logic “1”). During an erasing operation, the resistance state of the programmable resistor in a selected bit cell is switched from the LRS to the HRS (i.e., to store a logic “0”).

Typically, the forming operation is directed to a selected bit cell and includes concurrently applying a high positive voltage (e.g., +2.5V) to the WL connected to the selected bit cell, applying an even higher positive voltage (e.g., +4.0V) to the SL connected to the selected bit cell, and discharging the BL connected to the selected bit cell to ground. To accommodate these biasing conditions without placing the selected bit cell under undue stress, the access transistor of each bit cell is typically a high voltage transistor. Additionally, to avoid undue device stress in unselected bit cells, all other WLs, SLs and BLs in the RRAM structure also be connected to ground.

Disclosed herein are embodiments of a memory structure (e.g., a resistive random access memory (RRAM) structure). The structure can include an array of bit cells (e.g., RRAM cells) arranged in columns and rows. The structure can further include word lines (WLs) connected to the rows and a WL decode block including WL drivers connected to the WLs. The structure can further include a voltage generation block including a first charge pump connected to the WL decode block. The first charge pump can output a WL voltage (VWL) (e.g., a relatively low VWL) to the WL decode block and, during a memory operation, the WL drivers can concurrently apply the same VWL to all the WLs. The memory operation can, for example, be a multi-step forming operation directed to a selected column.

Also disclosed herein are embodiments of a method of operating a memory structure (e.g., an RRAM structure). The structure can include an array of bit cells (e.g., RRAM cells) arranged in columns and rows. The structure can further include word lines (WLs) connected to the rows and a WL decode block including WL drivers connected to the WLs. The structure can further include a voltage generation block including a first charge pump connected to the WL decode block. The method can include performing a memory operation (e.g., a multi-step forming operation directed to a selected column) in the memory structure. The memory operation can include outputting, by the first charge pump to the WL decode block, a WL voltage (VWL) to the WL decode block and concurrently applying, by the WL drivers, that same VWL to all the WLs.

It should be noted that all aspects, examples, and features of disclosed embodiments mentioned in the summary above can be combined in any technically possible way. That is, two or more aspects of any of the disclosed embodiments, including those described in this summary section, may be combined to form implementations not specifically described herein. The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features, objects and advantages will be apparent from the description and drawings, and from the claims.

As mentioned above, write operations in an RRAM structure can include a forming operation, a programming operation (also referred to herein as a set operation), and an erasing operation (also referred to herein as a reset operation). During a forming operation, the resistance state of the programmable resistor of a selected bit cell is switched from an initial very high resistance state (iHRS), as seen immediately after manufacturing, to an operational resistance state that is lower than the iHRS (e.g., to an operational high resistance state (HRS) or to an operational resistance state (LRS)). The HRS can be used to store, for example, a logic “0” and the LRS can be used to store, for example, a logic “1.” During a programming operation, the resistance state of the programmable resistor in a selected bit cell is switched from the HRS to the LRS (i.e., to store a logic “1”). During an erasing operation, the resistance state of the programmable resistor in a selected bit cell is switched from the LRS to the HRS (i.e., to store a logic “0”).

Typically, the forming operation is directed to a selected bit cell and includes concurrently applying a high positive voltage (e.g., +2.5V) to the WL connected to the selected bit cell, applying an even higher positive voltage (e.g., +4.0V) to the SL connected to the selected bit cell, and discharging the BL connected to the selected bit cell to ground. To accommodate these biasing conditions without placing the selected bit cell under undue stress, the access transistor of each bit cell is typically a high voltage transistor. Additionally, to avoid undue device stress in unselected bit cells, all other WLs, SLs, and BLs in the RRAM structure can also be connected to ground.

In view of the foregoing, disclosed herein are embodiments of a memory structure and, particularly, a resistive random access memory (RRAM) structure (hereinafter referred to as the structure) and a method of operating the structure including a multi-step forming operation during which the same relatively low word line voltage (VWL) is applied to all word lines (WLs) (i.e., during which all WLs are concurrently activated with the same relatively low VWL). The structure can include an array of RRAM cells (hereinafter referred to as bit cells) arranged in columns and rows. It can further include word lines (WLs) connected to the rows of bit cells, respectively, and source line (SL)-bit line (BL) pairs connected to the columns of bit cells, respectively. The structure can further be configured to perform a memory operation (e.g., a novel multi-step forming operation) during which all WLs for all rows are activated with the same relatively low positive word line voltage (VWL) (e.g., VWL=0.4V). In such a memory operation, all BLs and all SLs (except for a SL connected to bit cells in a selected column) can be connected to ground, while the SL connected to the bit cells in the selected column can receive a source line voltage (VSL) that starts at a relatively high positive voltage level (e.g., VSL=4.0V) during a first step of the memory operation and that decreases with each successive step. As a result of this multi-step forming process, the resistance states of the programmable resistors in the bit cells of the selected column concurrently and progressively (with the performance of each step) change from an initial resistance state to an operational resistance state that is lower than the initial resistance state (e.g., from an initial high resistance state (iHRS) to an operational high resistance state (HRS)). Throughout this memory operation, current on the BL of the selected column can be monitored (e.g., sensed by a self-termination circuit (STC)) and, when a threshold current level is reached (indicating that the current step in the multi-step forming operation has been completed), a feedback circuit causes the next step in the multi-step memory operation to be initiated. The steps can continue until the last step (e.g., performed using the lowest VSL) is completed and the desired operational resistance state (e.g., HRS) is reached. By configuring the structure with additional circuitry to enable such a multi-step forming operation, power, performance, and area (PPA) may be significantly improved over conventional structures. For example, power consumption may be reduced because the VWL is low (e.g., 0.4V) and, particularly, significantly less than the 2.5V VWL required for the forming operation in a conventional structure. Additionally, area consumption may be reduced because relatively small, low voltage transistors (e.g., 0.8V transistors) may be included in the bit cells with minimal, if any, risk of safe operating area (SOA) violations. Finally, performance may be improved because bit line current is limited during the multi-step forming operation and, thus, electromigration (EM) and IR drop violations may be avoided.

1 FIG. 100 Specifically,is a schematic diagram illustrating a disclosed embodiment of a memory structure and, particularly, a resistive random access memory (RRAM) structure (hereinafter referred to as structure) configured to facilitate performance of a multi-state forming operation during which the same relatively low word line voltage (VWL) is concurrently applied to all word lines (WLs).

100 110 101 181 181 182 182 183 183 100 110 512 101 0 y 0 y 0 x Structurecan include: an arrayof RRAM cells (hereinafter referred to as bit cells) arranged in columns (C0-Cy) and rows (R0-Rx); bit lines (BLs)-for the columns (C0-Cy), respectively; source lines (SLs)-for the columns (C0-Cy), respectively; and word lines (WLs)-for the rows (R0-Rx), respectively. In one example, structurearraycould include 4864 columns (i.e., C 0-C4863) androws (i.e., R0-R511) of bit cells.

100 190 190 181 181 182 182 183 183 150 150 120 130 140 150 190 150 170 181 181 170 0 y 0 y 0 x 0 y Structurecan further include a controllerand, in communication with controller, peripheral circuitry connected to BLs-, SLs-and WLs-to facilitate the performance of both write operations (including forming, programming, and erasing operations) and read operations. For example, this peripheral circuitry can include components for establishing specific biasing conditions on WLs, SLs, and BLs in the array during forming, programming, erasing, or read operations. Specifically, the peripheral circuitry can include, but is not limited to, a voltage generation blockand various decode blocks connected to the voltage generation block. Decode blocks can include, for example, a WL decode blockconnected to the WLs, a SL decode blockconnected to the SLs, and a BL decode blockconnected to the BLs. Voltage generation blockcan be configured to generate and output different voltages required for establishing specific biasing conditions during the memory operations. These decode blocks can be configured to receive control signals (e.g., address signals from controller) and to decode those signals. These decode blocks can further be configured to receive bias voltages from voltage generation blockand, based on the decoded address signals, cause drivers contained therein to selectively apply appropriate bias voltages to the WLs, SLs, or BLs (as applicable). The peripheral circuitry can also include a sense circuit, which is connected to BLs-and which includes one or more sense amplifiers. Sense circuitcan be configured to determine a stored data value in a selected bit cell during a read operation by sensing a change in an electrical parameter (e.g., voltage or current) on a BL, which is connected to the selected bit cell.

Peripheral circuitry, as described above, facilitates the performance of both write operations (e.g., forming, programming, and erasing operations) and read operations in RRAM structures is generally known in the art. Thus, details of this peripheral circuitry have been omitted from this specification, except for those specific details associated with the multi-step forming operation mentioned above and discussed in greater detail below.

1 FIG. 101 102 103 101 102 103 101 103 More specifically, as illustrated in, each bit cellcan include a programmable resistorand an access transistor(e.g., an N-type field effect transistor (NFET)). Within each bit cellin a given column, programmable resistorand access transistor(e.g., NFET) can be electrically connected in series between the SL and BL for that column. Additionally, within each bit cellin a given row, the gate of access transistorcan be electrically connected to the WL for that row.

2 2 FIGS.A-D 1 FIG. 2 2 FIGS.A-D 101 103 102 110 102 101 are cross-section diagrams illustrating, in greater detail, an example of a bit cell(including an access transistorand a programmable resistor) that can be incorporated into the arrayof.further illustrate different programming states of programmable resistorin bit cell, respectively.

2 2 FIGS.A-D 103 103 231 232 233 231 232 201 198 103 235 233 101 100 103 103 As illustrated in, access transistorcan be a field effect transistor (FET), such as an NFET. Specifically, access transistorcan include a first N-type source/drain, a second N-type source/drain region, and a channel region(e.g., a P-channel region or intrinsic channel region) between the two source/drain regions-. Optionally, the source/drain regions and channel region therebetween can be within an upper portion of a semiconductor layer or semiconductor substrate, which has, for example, P-conductivity and which is electrically connected to ground. Access transistorcan further include a gateadjacent to channel region. Various different NFET configurations are known in the art, any of which could be incorporated into a bit cell. Thus, a more detailed description of the NFET has been omitted from the specification in order to allow the reader to focus on the salient aspects of the disclosed embodiments. It should, however, be noted that because of the unique configuration of the peripheral circuitry in structure, which allows for the forming operation to be performed in multiple steps using a relatively low VWL (e.g., VWL≤0.4V), access transistorcan be a low voltage device, which is relatively small in size. For example, access transistorcould be a low threshold voltage NFET (LVTNFET) with a relatively low maximum voltage rating (e.g., a 0.8V LVTNFET), a channel length of 160 nanometers (nm), and a channel width of 40 nm.

102 221 222 221 101 222 232 103 231 103 102 103 235 103 102 212 221 212 214 222 214 213 212 214 Programmable resistorcan be a memristor or other similar type of programmable resistor having two-terminals (i.e., a first terminaland a second terminal). First terminalcan be electrically connected to the SL for the column containing the bit cell. Second terminalcan be electrically connected to source/drain regionof access transistor. Source/drain regionof access transistorcan be electrically connected to the BL for the column containing the bit cell. Thus, programmable resistorand access transistorare electrically connected in series between the SL and the BL for the same column. Additionally, gateof access transistorcan be connected to the WL for the row containing the bit cell. In some embodiments, programmable resistorcan be a back end of the line (BEOL) multi-layer structure and, particularly, a BEOL metal-insulator-metal (MIM) structure. The MIM structure can include a first metal layer(at first terminal). First metal layercan include one or more layers of metal or metal alloy materials (e.g., titanium, titanium nitride and/or any other suitable metal or metal alloy material). The MIM structure can further include a second metal layer(at second terminal). The second metal layercan include one or more layers of metal or metal alloy materials (e.g., titanium, titanium nitride and/or any other suitable metal or metal alloy material). The MIM structure can further include an insulator layer(also referred to as a switching layer) stacked between the two metal layersandand including one or more layers of isolation material (e.g., hafnium oxide and/or any other suitable insulator material).

2 FIG.A 2 FIG.B 102 221 222 102 102 221 222 213 215 213 212 214 102 101 101 100 101 As illustrated in, the post-manufacture resistance state of programmable resistorcan be an initial high resistance state (iHRS). iHRS can, for example, be approximately 100 megaohms (MΩ) or higher. During a forming operation (as discussed in greater detail below), specific bias voltages on terminalsandcan be employed to switch programmable resistorto an operational state that is lower than iHRS. Programmable resistorcan have, for example, two operational states including an operational high resistance state (HRS) (e.g., of approximately 50 kilohms (kΩ)) for storing a first logic value (e.g., a logic “0”) and an operational low resistance state (LRS) (e.g., of approximately 5 kΩ) for storing a second logic value (e.g., a logic “1”). For purposes of illustration, the forming operation described herein is employed to change the resistance state from iHRS to HRS to store the first logic value. Thus, as illustrated in, during the forming operation specific bias voltages on terminalsandcan be employed to initiate metal ion migration through insulator layer. Such metal ion migration can result in the formation of conductive filament(s)that extend at least partially through insulator layerbetween metal layersand, thereby reducing the resistance state of the programmable resistorfrom iHRS to HRS to store the first logic value (e.g., logic “0”). As mentioned above, in a conventional RRAM structure, this forming operation is achieved by applying a high positive voltage (e.g., 2.5V) to the WL of a row containing a selected bit cell, applying an even higher positive voltage (e.g., 4.0V) to the SL of a column containing the selected bit cell, and connecting all other WLs, all other SLs and all BLs to ground. However, as discussed in greater detail below, peripheral circuitry in structurecan be uniquely configured to allow for a novel multi-step forming operation during which: (a) all WLs for all rows concurrently receive the same low VWL (e.g., VWL≤0.4V); (b) the SL connected to a selected column receives a VSL that from a drops from a relatively high VSL (e.g., VSL=4.0V) with each successive step (e.g., down to VSL=1.3V or 1.0V); and (c) all other SLs and all BLs are connected to ground. As a result, the forming operation is concurrently performed with respect to all bit cellsin the selected column.

2 FIG.C 221 222 213 102 101 215 213 212 214 212 214 101 101 As illustrated in, during a programming operation (also referred to herein as a setting operation), specific bias voltages on the terminalsandcan be employed to cause further metal ion migration through insulator layerin the programmable resistorof a selected bit cell. This additional metal ion migration can increase the numbers and/or lengths of conductive filament(s)extending through insulator layerbetween and contacting metal layersand(e.g., so that metal layersandare electrically connected), as illustrated, in order to store the second logic value (e.g., logic “1”). In the disclosed embodiments, this programming operation can be achieved using any known techniques employed in conventional RRAM structures. For example, programming could be achieved by applying a high positive word line voltage (VWL) (e.g., VWL=2.5V) to the WL of a row containing a selected bit celland applying a similarly high positive source line voltage (VSL) (e.g., VSL=2.5V) to the SL of a column containing the selected bit cell, and further connecting all other WLs, all other SLs, and all BLs to ground.

2 FIG.D 221 222 213 215 213 212 214 102 101 212 214 101 As illustrated in, during an erasing operation (also referred to herein as a resetting operation), specific bias voltages on the terminalsandcan be employed to change the direction of metal ion migration through insulator layerin order to break-up of conductive filament(s)extending through insulator layerbetween metal layersandin the programmable resistorof a selected bit cell(e.g., so that metal layersandare no longer electrically connected), as illustrated, to again store the first logic value (e.g., logic “0”). In the disclosed embodiments, this erasing operation can be achieved using any known techniques employed in conventional RRAM structures. For example, erasing could be achieved by applying a high positive word line voltage (VWL) (e.g., VWL=3.8V) to the WL, applying a high positive bit line voltage (VBL) (e.g., VBL=3.0V) to the BL of a column containing the selected bit cell, and connecting all other WLs, all other BLs and all SLs to ground.

101 102 101 101 101 170 103 170 In addition to these write operations (i.e., forming, programming, and erasing), each a bit cellcan be individually and selectively subjected to a read operation. During a read operation, specific biasing conditions can be applied to determine the stored logic value in programmable resistorof a selected bit cell. In the disclosed embodiments, this read operation can be achieved using any known techniques employed in conventional RRAM structures. For example, reading could be achieved by applying a read voltage (referred to herein as VREAD) (e.g., VREAD=150 mV) to the BL of a column containing a selected bit cell, applying a VWL at a positive supply voltage (VDD) level (e.g., VDD=1.8V) to a WL of a row containing the selected bit cell, and connecting all other BLs, all other WLs, and all SLs to ground. Concurrently, during this read operation, sense circuitcan sense a change in an electrical parameter on the BL connected to the selected bit cell when access transistorturns on in response to VWL. Based on the sensed electrical parameter, sense circuitcan output a data output value indicative of the logic value “1” or “0” stored in the selected bit cell.

1 FIG. 150 151 152 151 169 190 160 152 168 160 152 152 Referring again to, to facilitate performance of the novel multi-step forming operation, voltage generation blockcan include a first charge pump(also referred to herein as a low voltage charge pump) and a second charge pump(also referred to herein as a high voltage charge pump). First charge pumpcan generate and output (i.e., can be configured to generate and output, can be adapted to generate and output, etc.) at least one relatively low VWL (e.g., VWL=0.4V) during a multi-step forming operation in response to a particular VWL trim code(e.g., received from controlleror, alternatively, received from a feedback circuit, as discussed in greater detail below). Second charge pumpcan generate and output (i.e., can be configured to generate and output, can be adapted to generate and output, etc.) VSL at different voltage levels during different steps, respectively, of the multi-step forming operation in response to different VSL trim codes(e.g., received from feedback circuit, as discussed in greater detail below). The different voltage levels of VSL at the different steps can decrease with each successive step in the multi-step forming operation. Specifically, at the first step in the multi-step forming operation, second charge pumpcan output VSL at a relatively high voltage level and the voltage level can drop with each successive step thereafter. For example, in a six-step forming operation, VSL can be output from second charge pumpas follows: Step 1—4.0V; Step 2—3.0V, Step 3—2.0V; Step 4—1.5V; Step 5—1.3V; and Step 6—1.0V. It should be noted that this example is provided for illustration purposes and the number of steps and/or the different VSL voltage levels are not intended to be limiting.

150 100 151 152 Various different charge pump circuits capable of selectively outputting a bias voltage at any one of multiple different voltage levels in response to different trim codes are known in the art. Any of these now known charge pump circuits (or any suitable later developed charge pump circuits) that are capable of generating a relatively low VWL (e.g., VWL=0.4V or 0.375V) and capable of generating a VSL at various different voltage levels (e.g., from a relatively high voltage level, such as 4.0V, down to some predetermined minimum voltage level, such as 1.3V or 1.0V) could be incorporated into voltage generation blockof structureas first charge pumpand second charge pump, respectively.

151 120 120 122 122 183 183 120 151 122 122 183 183 0 x 0 x 0 x 0 x In any case, first charge pumpcan be connected to WL decode block. WL decode blockcan include WL drivers-, which are electrically connected to WLs-, respectively. And, during the multi-step forming operation, WL decode blockcan receive VWL from first charge pumpand can cause (i.e., can be configured to cause, can be adapted to cause, etc.) WL drivers-to concurrently apply LV_VWL to all WLs-.

152 130 130 131 182 182 132 132 182 182 131 130 152 131 0 y 0 y 0 y Second charge pumpcan be connected to SL decode block. SL decode blockcan include a SL multiplexer(SL MUX) connected to SLs-and multiple SL drivers-, which are selectively connectable to SLs-through SL MUX. And, during the multi-step forming operation, SL decode blockcan receive VSL from second charge pumpand can cause (i.e., can be configured to cause, can be adapted to cause, etc.) SL MUXto: (a) connect the SL for a selected column to a corresponding SL driver so that VSL (which as mentioned above decreases with each successive step) is applied to that SL; and (b) connect all other SLs to ground.

140 141 181 181 140 141 140 181 181 141 140 143 143 140 141 0 y 0 y 0 y BL decode blockcan further include a BL multiplexer(BL MUX) connected to BLs-. And, during the multi-step forming operation, BL decode blockcan cause (i.e., can be configured to cause, can be adapted to cause, etc.) BL MUXto connect all BLs to ground. BL decode blockcan further include at least one self-termination circuit (STC) connectable to BLs-through BL MUX. For purposes of illustration, BL decode blockis shown as having multiple STCs-(one for each BL). And, during the multi-step forming operation, BL decode blockcan cause (i.e., can be configured to cause, can be adapted to cause, etc.) BL MUXto connect an STC (which is enabled) to a BL for a selected column.

143 143 145 145 0 y 0 y Each STC-can be configured to selectively monitor and, particularly, to selectively sense a bit line current (IBL) on a BL of a selected column, when enabled during a forming operation, and to output a digital output signal (Dout)-with a first logic value (e.g., logic “0”) when the IBL is below a threshold bit line current level (IBLmax) and with a second logic value (e.g., a logic “1”) when IBL is at or above IBLmax.

3 FIG. 3 FIG. 143 140 100 143 143 143 320 320 310 301 301 320 143 330 320 399 330 145 399 330 145 399 110 103 103 110 320 330 301 is one example of an STCthat could be incorporated into BL decode blockof structure. As illustrated, this STCcan be connected to receive an enable signal (EN) and an inverted enable signal (ENB) for the forming operation. When EN is high and ENB is low, the specific STCwill switch to an on-state (i.e., will be enabled). STCcan include a current mirror-controlled first inverter(i.e., a first invertercontrolled by a current mirror) with an input terminal connected to STC input node(which is connected to receive an IBL from the BL of a selected column) and with an output terminal. When IBL on STC input nodereaches IBLmax, the output at the output terminal of first inverterwill switch from a high voltage level to a low voltage level. STCcan further include a second inverterwith an input terminal connected to the output terminal of first inverterand with an output terminal connected to an STC output node. When the voltage level on the input terminal of second inverteris high, a digital output signal (Dout)at STC output nodewill be at logic “0.” When the voltage level on the input terminal of second invertergoes low, Douton STC output nodewill switch to a logic “1.” It should be noted that the IBLmax can be, for example, set at a predetermined maximum bit cell current level (IBCmax) multiplied by the total number of bit cells in each column (i.e., multiplied by the total number of rows in array). This bit cell current level can be, for example, predetermined so as to avoid placing the access transistorin any given bit cell within the selected column under undue stress (e.g., to ensure that the drain voltage (Vd) on access transistordoes not rise above some Vdmax) during the multi-step forming operation. For example, in some embodiments, Vdmax could be 1.24V with IBCmax being 1 μA. Therefore, if arrayincludes 512 rows, IBLmax would be 1 μA*512 or 512 μA. Those skilled in the art will recognize that in a STC structure as shown in, the bias voltage (VB) can be selectively adjusted to ensure that first inverterand thereby second inverterswitch states when the IBLmax is reached at STC input node.

100 160 140 150 160 145 145 143 143 168 152 150 160 162 162 160 150 168 152 152 160 161 143 143 162 161 169 0 y 0 y 0 y Structurecan further include a feedback circuitconnected to BL decode blockand to voltage generation block. During the multi-step memory operation, feedback circuitcan receive a Dout-from a corresponding STC-and can change (i.e., can be configured to change, adapted to change, etc.) the VSL trim codesupplied to second charge pumpin voltage generation blockwhen that Dout switches from logic “0” to logic “1.” For example, feedback circuitcan include a counter(also referred to herein as a state machine). Countercan decrement (i.e., can be configured to decrement, adapted to decrement, etc.) a binary number, each time the Dout switches from logic “0” to logic “1” indicating completion of a current step in the multi-step forming operation and triggering initiation of the next step multi-step forming operation. This binary number can be output from feedback circuitto voltage generation blockas VSL trim code. Decrementing the binary number (i.e., the VSL trim code) at the completion of each step, causes second charge pumpto drop the voltage level of VSL for the next step in the multi-step forming operation (as discussed above with regard to second charge pump). Optionally, feedback circuitcan further include a delay element, which is connected between the input to the feedback circuit (and thereby any STC-) and counter. Delay element(e.g., a buffer) can delay Dout for some period of time (e.g., approximately 10 ns) to prevent premature switching of VSL trim codebefore IBL is steady at or above IBLmax.

100 102 101 103 101 In the above-described structure, this novel multi-step forming operation concurrently and progressively (with the performance of each step) changes resistance states of programmable resistorsof all bit cellsin a selected column from a post-manufacture initial high resistance state (iHRS) (e.g., of ˜100 MΩ or higher) to, for example, an operational high resistance state (HRS) (e.g., of ˜50 kΩ) for storing a first logic value (e.g., a logic “0”). Furthermore, by employing this multi-step forming operation, power, performance, and area (PPA) may be significantly improved over conventional structures. For example, power consumption may be reduced because the VWL is low (e.g., 0.4V). Additionally, area consumption may be reduced because relatively small, low voltage access transistors(e.g., 0.8V transistors) may be included in bit cellswithout risking safe operating area (SOA) violations. Finally, performance may be improved because IBL is limited to IBLmax during the multi-step forming operation and, thus, electromigration (EM) and IR drop violations may be avoided.

4 FIG. 100 is a timing diagram illustrating examples of changes in various electrical parameters in structureduring the above-described multi-step forming operation when an STC is enabled (EN) and VWL is concurrently applied to all WLs. As illustrated, in first step (S1), when VSL is at the highest voltage level (e.g., 4.0V) and Dout from the STC is low, drain voltage (Vd) from each bit cell in the selected column, IBC and IBL will all begin to rise and resistance of the programmable transistor in each bit cell (RBC) in the selected column will begin to fall. When IBL reaches IBLmax, Dout will go high, thereby indicating the completion of S1 and initiating second step (S2) by causing VSL to drop (e.g., down to 3.0V). As illustrated, once VSL drops to 3.0V at the beginning of S2, Dout will go low and Vd, IBC, and IBL will also drop to some degree. Then, during S2, IBC, IBL, and Vd will begin to rise again and RBC will continue to fall. When IBL again reaches IBLmax, Dout will go high, thereby indicating the completion of S2 and initiating the third step (S3) by causing VSL to drop (e.g., down 2.0V) and so forth until the last trim bit code for the last VSL is output signaling the last step in the multi-step forming operation.

160 151 169 120 122 122 183 183 190 169 0 x 0 x It should be noted that, in further embodiments, feedback circuitcould include an additional counter (not shown). This additional counter could, for example, decrement a binary number output to first charge pumpas VWL trim codeat the last step (or last few steps) in order to decrease the voltage level of VWL output to WL decode blockand concurrently applied by WL drivers-to WLs-during the last step(s). By further reducing VWL (e.g., from 0.4V to 0.35) RBC may be adjusted with finer granularity. In other alternative embodiments, a multi-step forming operation could be performed as described above with the same VWL being used for each step. However, controllercould change the VWL trim codeand cause a second forming operation to be performed with respect to the selected column using VWL at an even lower voltage level (e.g., reduced from 0.4V to 0.35) if the desired resistance state (e.g., HRS) is not verified after the multi-step forming operation. See the verification process discussed in greater detail below with regard to the method embodiments.

5 FIG. 1 FIG. 100 is a flow diagram illustrating embodiments of a method of operating structureofand, particularly, embodiments of a method of performing a multi-step forming operation therein.

5 FIG. 1 FIG. 190 101 110 100 502 502 169 151 151 120 168 152 152 130 502 132 182 131 143 181 141 502 132 122 122 132 182 122 122 183 183 502 143 0 0 0 0 0 0 x 0 0 0 x 0 x 0 Referring toin combination with, the method can include initiating (e.g., in response to control signals from controller) a multi-step forming operation for all bit cellsin a selected column in arrayof structure(see process). For purposes of illustration, the method is described below with C0 being the selected column. Initiating the multi-step forming operation at processcan include providing a VWL trim codeto first charge pumpso as to cause first charge pumpto generate and output VWL at a relatively low voltage level (e.g., VWL=0.4V) to WL decode blockand further providing a step 1 (S1) VSL trim codeto second charge pumpto cause second charge pumpto generate and output VSL at a relatively high voltage level (e.g., VWL=4.0V) to SL decode block. Initiating the multi-step forming operation at processcan further include selectively connecting SL driverfor selected column C0 to SLof selected column C0 via SL MUXand further selectively connecting STCfor selected column C0 to BLof selected column C0 via BL MUX. Initiating the multi-step forming operation at processcan further include enabling SL driverand further enabling all WL drivers-such that the S1 VSL is applied to by SL driverto SLand so that VWL is concurrently applied by all WL drivers-to all WLs-, respectively. Additionally, initiating the multi-step forming operation at processcan further include enabling STCfor selected column C0.

181 143 504 143 181 181 160 0 0 0 0 0 Following initiation of the multi-step forming operation, the method can include continuous monitoring (e.g., sensing) IBL on BL(e.g., through STC) (see process). The method can also include outputting (by STC) a digital output signal (Dout) with a first logic value (e.g., a logic “0”) when IBL on BLis below a threshold bit line current level (IBLmax) and with a second logic value (e.g., a logic “1”) when IBL on BLis at or above IBLmax. Dout can be output to a feedback circuit.

160 506 160 169 152 160 169 152 510 160 162 169 162 152 160 161 162 161 162 169 508 The method can further include: monitoring, by feedback circuit, the state of the received Dout (see process); maintaining, by feedback circuit, a VSL trim codesupplied to second charge pumpwhen Dout is at logic “0” and changing, by feedback circuit, the VSL trim codesupplied to second charge pumpwhen Dout switches from the logic “0” to logic “1” (see process). For example, in some embodiments, feedback circuitcan include a counterand, this process of changing the VSL trim codecan include decrementing, by counter, a binary number (which is output from feedback circuit as the VSL trim code) each time Dout switches from logic “0” to logic “1” indicating completion of a current step and triggering initiation of the next step in the multi-step forming operation (i.e., causing second charge pumpto output VSL at the next lower voltage level for step 2 (S2)). It should be noted that as discussed above, feedback circuitcan optionally include a delay element(e.g., a buffer) downstream of counter(e.g., so as to be connected between the STC and counter). In this case, the method can also include delaying, by delay element, Dout for some period of time (e.g., approximately 10 ns) before receipt by counterto prevent premature switching of VSL trim codebefore IBL is steady at or above IBLmax (see process).

169 510 504 510 512 101 514 151 152 132 143 122 122 502 514 102 101 0 0 0 x Once the VSL trim codehas changed at process, processes-can be repeated until the last step using the lowest voltage level for VSL has been completed (see process). Then, the multi-step forming operation for bit cellsin selected column C0 will end (see process). For example, first and second charge pumps-, SL driver, STC, and WL drivers-will all be disabled. As discussed above, the multi-step forming operation (i.e., processes-) can be performed to concurrently and progressively (with the performance of each step) change resistance states of programmable resistorsof all bit cellsin the selected column from a post-manufacture initial high resistance state (iHRS) (e.g., of ˜100 MΩ or higher) to an operational resistance state that is lower than iHRS (e.g., to an operational high resistance state (HRS) of, for example, ˜50 kΩ for storing a first logic value of, for example, a logic “0.”

In the method embodiments as described above, VWL is at the same relatively low voltage level (e.g., 0.4V) for all steps of the forming operation. However, in alternative method embodiments, the voltage level of VWL during the last step or last few steps of the forming operation could also be decreased (e.g., from 0.4V to 0.35V). By stepping down VWL during this multi-step forming operation, RBC may be adjusted with even finer granularity.

101 516 518 Optionally, the method can further include verifying whether the bit cellsin the selected column reached the desired resistance state (e.g., HRS to store a logic “0”) (see process). This verification process can include, for example, a reading operation (as described above) to determine the stored value in one bit cell in the selected column or multiple reading operations to determine stored values in some or all of the bit cells in the selected column. If the bit cell(s) in the selected column are determined to be storing the correct logic value (e.g., a logic “0”), then the forming operation for that selected column can be considered verified. However, if the bit cell(s) in the selected column are determined to be storing an incorrect logic value (e.g., a logic “1”), then the forming operation for that selected column can be considered unverified. In this case, further RBC adjusting may be required. For example, the last step of the multi-step forming operation using the same VWL (e.g., 0.4V) could be repeated or optionally one or more additional steps could be performed using an even lower VWL (e.g., 0.35V) (see process).

520 Once the multi-step forming process is completed in a selected column and, optionally, verified, another column can be selected and the processes described above can be repeated for the next selected column (see process).

It should be understood that in the method and structures described above, a semiconductor material refers to a material whose conducting properties can be altered by doping with an impurity. Examples of semiconductor materials include, for example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, silicon germanium carbide, silicon carbide, etc.) and III-V compound semiconductors (i.e., compounds obtained by combining group III elements, such as aluminum (Al), gallium (Ga), or indium (In), with group V elements, such as nitrogen (N), phosphorous (P), arsenic (As) or antimony (Sb)) (e.g., GaN, InP, GaAs, or GaP). A pure semiconductor material and, more particularly, a semiconductor material that is not doped with an impurity for the purposes of increasing conductivity (i.e., an undoped semiconductor material) is referred to in the art as an intrinsic semiconductor. A semiconductor material that is doped with an impurity for the purposes of increasing conductivity (i.e., a doped semiconductor material) is referred to in the art as an extrinsic semiconductor and will be more conductive than an intrinsic semiconductor made of the same base material. That is, extrinsic silicon will be more conductive than intrinsic silicon; extrinsic silicon germanium will be more conductive than intrinsic silicon germanium; and so on. Furthermore, it should be understood that different impurities (i.e., different dopants) can be used to achieve different conductivity types (e.g., P-type conductivity and N-type conductivity) and that the dopants may vary depending upon the different semiconductor materials used. For example, a silicon-based semiconductor material (e.g., silicon, silicon germanium, etc.) is typically doped with a Group III dopant, such as boron (B) or indium (In), to achieve P-type conductivity, whereas a silicon-based semiconductor material is typically doped with a Group V dopant, such as arsenic (As), phosphorous (P) or antimony (Sb), to achieve N-type conductivity. A gallium nitride (GaN)-based semiconductor material is typically doped with magnesium (Mg) to achieve P-type conductivity and with silicon (Si) or oxygen to achieve N-type conductivity. Those skilled in the art will also recognize that different conductivity levels will depend upon the relative concentration levels of the dopant(s) in a given semiconductor region.

It should be understood that the terminology used herein is for the purpose of describing the disclosed structures and methods and is not intended to be limiting. For example, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Additionally, as used herein, the terms “comprises,” “comprising,” “includes,” and/or “including” specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Furthermore, as used herein, terms such as “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” “upper,” “lower,” “under,” “below,” “underlying,” “over,” “overlying,” “parallel,” “perpendicular,” etc., are intended to describe relative locations as they are oriented and illustrated in the drawings (unless otherwise indicated) and terms such as “touching,” “in direct contact,” “abutting,” “directly adjacent to,” “immediately adjacent to,” etc., are intended to indicate that at least one element physically contacts another element (without other elements separating the described elements). The term “laterally” is used herein to describe the relative locations of elements and, more particularly, to indicate that an element is positioned to the side of another element as opposed to above or below the other element, as those elements are oriented and illustrated in the drawings. For example, an element that is positioned laterally adjacent to another element will be beside the other element, an element that is positioned laterally immediately adjacent to another element will be directly beside the other element, and an element that laterally surrounds another element will be adjacent to and border the outer sidewalls of the other element. The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed.

The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

The descriptions of the various disclosed embodiments have been presented for purposes of illustration but are not intended to be exhaustive or limiting. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosed embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.