Fully Molded Bridge Interposer and Method of Making the Same

This is a continuation-in-part of U.S. Utility patent application Ser. No. 19/291,459, entitled “Fully Molded Bridge Interposer and Method of Making the Same,” which was filed on Aug. 5, 2025, which application is a continuation of U.S. Utility patent application Ser. No. 18/085,397, entitled “Fully Molded Bridge Interposer and Method of Making the Same,” which was filed on Dec. 20, 2022, which application is a continuation of U.S. Utility patent application Ser. No. 17/581,704, entitled “Fully Molded Bridge Interposer and Method of Making the Same,” which was filed on Jan. 21, 2022, which application claims the benefit, including the filing date, of U.S. Provisional Patent No. 63/141,945, entitled “Fully Molded Bridge Interposer and Method of Making the Same,” which was filed on Jan. 26, 2021, the disclosures of which are hereby incorporated herein by this reference.

This disclosure relates to a fully molded bridge interposer and methods of making the same.

Semiconductor devices are commonly found in modern electronic products. Semiconductor devices vary in the number and density of electrical components. Discrete semiconductor devices generally contain one type of electrical component, for example, light emitting diode (LED), small signal transistor, resistor, capacitor, inductor, and power metal oxide semiconductor field effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include microcontrollers, microprocessors, memories, analog to digital or digital to analog converters, power management and charged-coupled devices (CCDs), as well as microelectromechanical systems (MEMs) devices including digital micro-mirror devices (DMDs).

Semiconductor devices perform a wide range of functions such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electronic devices, storing information, and creating visual projections for displays. Semiconductor devices are found in many fields of entertainment, communications, power conversion, networks, computers, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.

Semiconductor devices exploit the electrical properties of semiconductor materials. The atomic structure of semiconductor material allows its electrical conductivity to be manipulated by the application of an electric field or base current or through the process of doping. Doping introduces impurities into the semiconductor material to manipulate and control the conductivity of the semiconductor device.

A semiconductor device contains active and passive electrical structures. Active structures, including bipolar, complementary metal oxide semiconductors, and field effect transistors, control the flow of electrical current. By varying levels of doping and application of an electric field or base current, the transistor either promotes or restricts the flow of electrical current. Passive structures, including resistors, capacitors, and inductors, create a relationship between voltage and current necessary to perform a variety of electrical functions. The passive and active structures are electrically connected to form circuits, which enable the semiconductor device to perform high-speed calculations and other useful functions.

Semiconductor devices are generally manufactured using two complex manufacturing processes, that is, front-end manufacturing, and back-end manufacturing, each involving potentially hundreds of steps. Front-end manufacturing involves the formation of a plurality of semiconductor die on the surface of a semiconductor wafer. Each semiconductor die is typically identical and contains circuits formed by electrically connecting active and passive components. Back-end manufacturing involves singulating individual semiconductor die from the finished wafer and packaging the die to provide structural support and environmental isolation. More recently, back-end manufacturing has been expanded to included emerging technology that allows multiple semiconductor die to be interconnected within a single package or device unit, thereby expanding the conventional definition of back-end technology. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly can refer to both a single semiconductor device and multiple semiconductor devices.

One goal of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance, can be produced more efficiently, have a smaller form factor, and may be less cumbersome when integrated within wearable electronics, portable handheld communication devices, such as phones, and in other applications. In other words, smaller semiconductor devices may have a smaller footprint, a reduced height, or both, which is desirable for smaller end products. A smaller semiconductor die size can be achieved by improvements in the front-end process resulting in semiconductor die with smaller, higher density active and passive components. Back-end processes may result in semiconductor device packages with a smaller footprint by improvements in electrical interconnection and packaging materials.

In some aspects, the disclosure concerns a semiconductor assembly, including: a bridge component including conductive studs disposed over a frontside, a backside opposite the conductive studs, and no vias formed through the bridge component, wherein the bridge component includes one or more interconnect layers disposed over the frontside and an outermost interconnect layer is coupled to the conductive studs; conductive vertical interconnects formed as copper posts disposed in a periphery of the semiconductor assembly; an encapsulant disposed on five sides of the bridge component, on sides of the conductive studs, and on sides of the copper posts that leave ends of the conductive studs and opposing first and second ends of the copper posts coplanar with top and bottom surfaces of the encapsulant, wherein the encapsulant is not disposed over the backside of the bridge component; a frontside build-up interconnect structure over the conductive studs of the bridge component and coupled to first ends of the copper posts opposite the second ends of the copper posts, the frontside build-up interconnect structure including first pads at a first pitch within a footprint of the bridge component of less than or equal to 80 μm and second pads at a second pitch outside a footprint of the bridge component of greater than or equal to the first pitch.

In some aspects, the disclosure concerns a semiconductor assembly, wherein the bridge component includes one or more of an active device and a passive device.

In some aspects, the disclosure concerns a semiconductor assembly, wherein the bridge component further includes one or more planarization layers disposed between two or more interconnect layers.

In some aspects, the disclosure concerns a semiconductor assembly, wherein the bridge component includes up to and including 8 build-up interconnect structures and one or more planarization layers disposed between the build-up interconnect structures.

In some aspects, the disclosure concerns a semiconductor assembly, further including a misalignment of the bridge component with respect to an assembly edge is greater than a misalignment of an under bump metallization (UBM) with respect to the assembly edge.

In some aspects, the disclosure concerns a semiconductor assembly, further including a backside build-up interconnect structure formed over a backside of the bridge component and coupled to first ends of the copper posts.

In some aspects, the disclosure concerns a semiconductor assembly, wherein: the semiconductor assembly further includes a total thickness less than or equal to 150 μm; and the semiconductor assembly is disposed over, and is coupled to, a package substrate, a printed circuit board (PCB), a multilayer ceramic capacitors (MLCC), or a passive device.

In some aspects, the disclosure concerns a semiconductor assembly, including: a bridge component formed without vias extending through the bridge component, and including conductive studs, wherein the bridge component includes one or more interconnect layers disposed over a frontside of the bridge component and an outermost interconnect layer is coupled to the conductive studs; conductive vertical interconnects disposed in a periphery of the semiconductor assembly; an encapsulant disposed on five sides of the bridge component, on sides of the conductive studs, and on sides of the conductive vertical interconnects that leave ends of the conductive studs and opposing first and second ends of the conductive vertical interconnects coplanar with top and bottom surfaces of the encapsulant; a frontside build-up interconnect structure over the conductive studs of the bridge component and coupled to first ends of the conductive vertical interconnects opposite the second ends of the conductive vertical interconnects, the frontside build-up interconnect structure including first pads at a first pitch within a footprint of the bridge component and second pads at a second pitch outside a footprint of the bridge component.

In some aspects, the disclosure concerns a semiconductor assembly, wherein the bridge component includes one or more of an active device and a passive device.

In some aspects, the disclosure concerns a semiconductor assembly, wherein the bridge component further includes one or more planarization layers disposed between two or more interconnect layers.

In some aspects, the disclosure concerns a semiconductor assembly, wherein the bridge component includes up to and including eight interconnect layers and one or more planarization layers disposed between the interconnect layers.

In some aspects, the disclosure concerns a semiconductor assembly, further including a misalignment of the bridge component with respect to an assembly edge is greater than a misalignment of an under bump metallization (UBM) with respect to the assembly edge.

In some aspects, the disclosure concerns a semiconductor assembly, further including: a first component including a system on chip (SOC) integrated circuit, memory controller or high bandwidth memory (HBM) controller, voltage regulator, a serializer/deserializer (SERDES), or active semiconductor die, the first component including high density interconnects coupled with the first pads, and low density interconnects coupled with the second pads; and a second component including a SOC integrated circuit, memory controller or HBM controller, voltage regulator, a SERDES, or active semiconductor die, the second component including, high density interconnects coupled with the first pads, and low density interconnects coupled with the second pads.

In some aspects, the disclosure concerns a semiconductor assembly, wherein the first pitch within a footprint of the bridge component is less than or equal to 80 μm and the second pitch outside a footprint of the bridge component is greater than or equal to the first pitch.

In some aspects, the disclosure concerns a semiconductor assembly, wherein: the semiconductor assembly further includes a total thickness less than or equal to 150 μm; and the semiconductor assembly is disposed over, and is coupled to, a package substrate, a printed circuit board (PCB), a multilayer ceramic capacitors (MLCC), or a passive device.

In some aspects, the disclosure concerns a method of making a semiconductor assembly, including: providing a temporary carrier; disposing conductive vertical interconnects in a periphery of a bridge component site; disposing a bridge component over the carrier and within the bridge component site, wherein the bridge component includes one or more interconnect layers disposed over a frontside and an outermost interconnect layer includes a plurality of conductive studs and the bridge component does not include vias through the bridge component; forming an encapsulant disposed on five sides of the bridge component, on sides of the conductive studs, and on sides of the conductive vertical interconnects that leave ends of the conductive studs and first ends of the conductive vertical interconnects exposed from the encapsulant, wherein the bridge component, conductive vertical interconnects, and encapsulant together form a molded bridge interposer; and forming a frontside build-up interconnect structure over the conductive studs of the bridge component and coupled to first ends of the conductive vertical interconnects opposite second ends of the conductive vertical interconnects, the frontside build-up interconnect structure including first pads at a first pitch within a footprint of the bridge component and second pads at a second pitch outside a footprint of the bridge component.

In some aspects, the disclosure concerns a method, further including: removing at least a portion of the carrier; and removing a portion of the encapsulant from over the conductive vertical interconnects and the conductive studs.

In some aspects, the disclosure concerns a method, wherein: a pitch of the conductive studs includes a pitch of greater than or equal to 80 μm; and the first pitch is less than or equal to the second pitch.

In some aspects, the disclosure concerns a method, further including forming a backside build-up interconnect structure formed over the temporary carrier before disposing the bridge component over the temporary carrier and over the backside build-up interconnect structure.

In some aspects, the disclosure concerns a method, wherein the bridge component includes an active device or a passive component.

In some aspects, the disclosure concerns a method, further including: coupling a first component including a system on chip (SOC) integrated circuit, memory controller or high bandwidth memory (HBM) controller, voltage regulator, a serializer/deserializer (SERDES), or active semiconductor die to the molded bridge interposer, the first component including interconnects coupled with a first portion of the first pads, and lower density interconnects coupled with a first portion of the second pads; and coupling a second component including a SOC integrated circuit, memory controller or HBM controller, voltage regulator, a SERDES, or active semiconductor die, the second component including interconnects coupled with a second portion of the first pads, and lower density interconnects coupled with a second portion of the second pads.

In some aspects, the disclosure concerns a method, further including a misalignment of the bridge component with respect to an assembly edge is greater than a misalignment of an under bump metallization (UBM) with respect to the assembly edge.

In some aspects, the disclosure concerns a method, further including forming the frontside build-up interconnect structure using unit specific patterning.

In some aspects, the disclosure concerns a method, wherein the bridge component further includes one or more planarization layers disposed between two or more interconnect layers.

In some aspects, the disclosure concerns a method, wherein the bridge component includes up to and including 8 interconnect layers and one or more planarization layers disposed between the interconnect layers.

The foregoing and other aspects, features, and advantages will be apparent to those of ordinary skill in the art from the specification, drawings, and the claims.

This disclosure relates to fully molded semiconductor structures, devices, and packages, and more particularly to a fully molded bridge interposer. In some instances, the fully molded semiconductor structures may comprise routing for semiconductor devices comprising different pitches, such as high density and ultra-high density as described more fully herein.

The fully molded semiconductor structures or bridge interposer (and method for making and using the same) may comprise, or provide: (i) a simplified supply chain, (ii) when compared with a conventional interposer-removing a need for an expensive large silicon die with through silicon vias (TSVs), which can be very large die that are very expensive (at least in part) because of TSV technology, (iii) when compared with Intel's Embedded Multi-die Interconnect Bridge (EMIB) technology, providing the advantage of no need for specialized substate technology—a enabling or facilitating the use of a low-cost substrate, (iv) improved electrical performance from using plated Cu Post vs TSVs, (v) have available ultra-high density connections (of or about a 10 μm area array bond pad pitch) where bridge die are embedded, high density (of or about a 20 μm area array bond pad pitch) elsewhere, and (vi) high density connections between bridge die and other devices or packages.

At least some of the above advantages are available at least in part by using unit specific patterning (such as patterning, custom lithography) and build up interconnect structures such as a frontside build-up interconnect structure, which is also known under the trademark “Adaptive Patterning”) with respect the bridge die. Unit specific patterning: (i) allows to use high-speed chip attach for bridge die and AP will ensure alignment for high density interconnects between M-Series interposer and attached devices, (ii) aligns via to Cu Studs allowing largest contact vias with smallest studs (fine pitch), (iii) with respect to an interposer makes the molded bridge interposer including a frontside build-up interconnect structure much cheaper that a giant interposer die, (iv) with respect to EMIB, vias can be large compared to stud size and capture pad size, lithography defined vias (not laser drilled), (v) allows connections between devices inside the molded bridge interposer with unit specific patterning or routing to compensate for die shift (including bridge die shift) between embedded devices, which may include memory controllers, voltage regulators, SERDES, etc., and (vi) make embedding active devices more useful.

This disclosure, its aspects and implementations, are not limited to the specific package types, material types, or other system component examples, or methods disclosed herein. Many additional components, manufacturing and assembly procedures known in the art consistent with semiconductor manufacture and packaging are contemplated for use with particular implementations from this disclosure. Accordingly, for example, although particular implementations are disclosed, such implementations and implementing components may comprise any components, models, types, materials, versions, quantities, and/or the like as is known in the art for such systems and implementing components, consistent with the intended operation.

The word “exemplary,” “example” or various forms thereof are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “exemplary” or as an “example” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Furthermore, examples are provided solely for purposes of clarity and understanding and are not meant to limit or restrict the disclosed subject matter or relevant portions of this disclosure in any manner. It is to be appreciated that a myriad of additional or alternate examples of varying scope could have been presented, but have been omitted for purposes of brevity.

Where the following examples, embodiments and implementations reference examples, it should be understood by those of ordinary skill in the art that other manufacturing devices and examples could be intermixed or substituted with those provided. In places where the description above refers to particular embodiments, it should be readily apparent that a number of modifications may be made without departing from the spirit thereof and that these embodiments and implementations may be applied to other technologies as well. Accordingly, the disclosed subject matter is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the disclosure and the knowledge of one of ordinary skill in the art.

Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, resistors, and transformers, create a relationship between voltage and current necessary to perform electrical circuit functions.

Passive and active components are formed over the surface of the semiconductor wafer by a series of process steps including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process modifies the electrical conductivity of semiconductor material in active devices, transforming the semiconductor material into an insulator, conductor, or dynamically changing the semiconductor material conductivity in response to an electric field or base current. Transistors contain regions of varying types and degrees of doping arranged as necessary to enable the transistor to promote or restrict the flow of electrical current upon the application of the electric field or base current.

Active and passive components are formed by layers of materials with different electrical properties. The layers can be formed by a variety of deposition techniques determined in part by the type of material being deposited. For example, thin film deposition can involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes. Each layer is generally patterned to form portions of active components, passive components, or electrical connections between components.

The layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned. A pattern is transferred from a photomask to the photoresist using light. In one embodiment, the portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. In another embodiment, the portion of the photoresist pattern not subjected to light, the negative photoresist, is removed using a solvent, exposing portions of the underlying layer to be patterned. The remainder of the photoresist is removed, such as by a stripping process, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.

Patterning is the basic operation by which portions of the photoresist material are partially removed, so as to provide a pattern or electroplating template for the subsequent formation of structures, such as patterning redistribution layers (RDLs), under bump mentalization (UBM), copper posts, vertical interconnects, or other desirable structures. Portions of the semiconductor wafer can be removed using photolithography, photomasking, masking, oxide or metal removal, photography and stenciling, and microlithography. Photolithography includes forming a pattern in reticles or a photomask and transferring the pattern into the surface layers of the semiconductor wafer. Photolithography forms the horizontal dimensions of active and passive components on the surface of the semiconductor wafer in a two-step process. First, the pattern on the reticle, masks, or direct write imaging design file are transferred into a layer of photoresist. Photoresist is a light-sensitive material that undergoes changes in structure and properties when exposed to light. The process of changing the structure and properties of the photoresist occurs as either negative-acting photoresist or positive-acting photoresist. Second, the photoresist layer is transferred into the wafer surface. The transfer occurs when etching removes or electroplating adds the portion of the top layers of semiconductor wafer not covered by the photoresist. The chemistry of photoresists is such that the photoresist remains substantially intact and resists removal by chemical etching solutions while the portion of the top layers of the semiconductor wafer not covered by the photoresist is removed by etching or a layer is added by electroplating. The process of forming, exposing, and removing the photoresist, as well as the process of removing or adding a portion of the semiconductor wafer can be modified according to the particular resist used and the desired results. Negative or positive tones resist can be designed for solvent or base develop solutions.

In negative-acting photoresists, photoresist is exposed to light and is changed from a soluble condition to an insoluble condition in a process known as polymerization. In polymerization, unpolymerized material is exposed to a light or energy source and polymers form a cross-linked material that is etch-resistant. In most negative resists, the polymers are polyisopremes. Removing the soluble portions (i.e. the portions not exposed to light) with chemical solvents or base developers leaves a hole in the resist layer that corresponds to the opaque pattern on the reticle. A mask whose pattern exists in the opaque regions is called a clear-field mask.

In positive-acting photoresists, photoresist is exposed to light and is changed from relatively nonsoluble condition to much more soluble condition in a process known as photosolubilization. In photosolubilization, the relatively insoluble resist is exposed to the proper light energy and is converted to a more soluble state. The photosolubilized part of the resist can be removed by a solvent or a base in the development process. The basic positive photoresist polymer is the phenol-formaldehyde polymer, also called the phenol-formaldehyde novolak resin. Removing the soluble portions (i.e. the portions exposed to light) with chemical solvents or base developers leaves a hole in the resist layer that corresponds to the transparent pattern on the reticle. A mask whose pattern exists in the transparent regions is called a dark-field mask.

After removal of the top portion of the semiconductor wafer not covered by the photoresist, the remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.

Depositing a thin film of material over an existing pattern can exaggerate the underlying pattern and create a non-uniformly flat surface. A uniformly flat surface can be beneficial or required to produce smaller and more densely packed active and passive components. Planarization can be used to remove material from the surface of the wafer and produce a uniformly flat surface. Planarization involves polishing the surface of the wafer with a polishing pad. An abrasive material and corrosive chemical are added to the surface of the wafer during polishing. Alternatively, mechanical abrasion without the use of corrosive chemicals is used for planarization. In some embodiments, purely mechanical abrasion is achieved by using a belt grinding machine, a standard wafer back grinder, or other similar machine. The combined mechanical action of the abrasive and corrosive action of the chemical removes any irregular topography, resulting in a uniformly flat surface.

Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and then packaging the semiconductor die for structural support and environmental isolation. To singulate the semiconductor die, the wafer can be cut along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool, laser silicon lattice disruption process or saw blade. After singulation, the individual semiconductor die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with solder bumps, stud bumps, conductive paste, redistribution layers, or wirebonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.

Back-end manufacturing as disclosed herein also does more than merely packaging an embedded device or the semiconductor die for structural support and environmental isolation. The packaging described herein further provides non-monolithic electrical interconnection of die for increased functionality & performance. Previously, nearly all advanced semiconductor die were monolithic systems on chips (SoCs) where all electrical interconnect occurred on the silicon wafer during front-end processing. Now, however, work that was traditionally the domain of front-end domain work may be handled or moved to the back-end manufacturing, allowing many semiconductor die (chiplets) to be connected with packaging technology to form a chiplet-based SoC (which is non monolithic) and provides a composite package with greater functionality. The chiplet approach may also decrease waste from defects, increase production efficiency, reliability, and performance.

The electrical system can be a stand-alone system that uses the semiconductor device to perform one or more electrical functions. Alternatively, the electrical system can be a subcomponent of a larger system. For example, the electrical system can be part of a portable hand-held electronic device, such as smart phone, a wearable electronic device, or other video or electronic communication device. Additionally, the electrical system may comprise a graphics component, network interface component, or other signal processing component that can be inserted into a computer or electronics device and may assist with such functions as mobile computing, artificial intelligence, and autonomous functions such as autonomous driving. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and weight reduction can be beneficial or essential for the products to be accepted by the market. The distance between semiconductor devices must be decreased to achieve higher density.

By combining one or more semiconductor devices, structures, or packages with fan-out technology, manufacturers can incorporate multiple components or elements into more highly compact and integrated electronic devices and systems. Because the semiconductor devices include sophisticated functionality, electronic devices can be manufactured less expensively and as part of a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.

1 1 FIGS.A-F 1 FIG.A 10 12 14 15 16 16 18 17 18 20 22 20 20 show prior art relative to connecting multiple semiconductor die or semiconductor packages together, that may be used for high intensity or high demand computing, such as computing utilizing or dealing with graphics cards.illustrates an existing packaging technology or structurecomprising a graphics processing unit (GPU) coupled to an HBM controller diewith bumps or microbumpsand through a silicon interposercomprising silicon vias formed in and extending therethrough. The silicon interposermay then be disposed over and coupled to a package substrate, with conductive or solder interconnects, bumps, or balls. The package substratemay then be disposed over and coupled to a graphics card, a multilayer ceramic capacitors (MLCC), a PCBor a passive device with conductive or solder interconnects, bumps, or balls. The graphics cardmay comprise a multi-layer PCB, and the conductive bumpsmay be used for: display connections, electrical current, as well as for peripheral component interconnect express (PCIe) interconnections or high-speed serial computer expansion bus connections.

1 FIG.B 11 14 16 20 11 14 12 16 16 illustrates a representation of a cross-section structurethat could be seen by a scanning electron microscope (SEM) of an HBMstacked on—and coupled to—a silicon interposer, which may further be coupled to a substrate, PCB, or graphics card. The structureintegrates HBM memories(which may comprise DRAM die and Logic Die connected with via-middle TSV and micro-bumps) and the GPUstacked onto the silicon interposer, wherein the silicon interposercomprises via-middle through silicon vias (TSVs).

1 1 FIGS.C-F 30 32 illustrates an existing technology of Intel's Embedded Multi-die Interconnect Bridge (EMIB), that was developed to provide a cost-effective approach to in-package high density interconnect of heterogeneous chips or semiconductor die.

1 FIG.C 1 FIG.D 1 FIG.E 1 FIG.F 30 34 36 30 38 40 42 30 44 42 44 30 46 42 30 44 30 44 48 32 44 42 30 50 30 52 48 32 32 48 54 56 40 46 44 32 32 36 30 a b a b illustrates the EMIBembedded in a cavityof an organic substrate, the EMIBcomprises conductive pads or contact padscoupled together with a conductive redistribution layer (RDL).illustrates resinformed over the EMIB, and viasformed in, or extending through, the resinwith the viasfurther coupled with the EMIB. RDLsmay be formed over the resinand over the EMIBand coupled with the viasfor lateral connection that extend from the EMIBand viasto mounting sitesfor heterogeneous chips.illustrates additional viasand layers of resinformed over the EMIBwith contact pads for microbumpsformed over the EMIBand contact pads for ordinary bumpsformed at semiconductor die mounting sites.illustrates a first semiconductor dieon the left and a second semiconductor dieon the right, each mounted over respective semiconductor die siteswith microbumpsand ordinary bumpsand RDLs,and viasfor routing of signals and interconnections for the semiconductor die,being routed through the organic substrateand through the EMIB.

2 2 FIGS.A-C 2 FIG.A 2 2 FIGS.B andC 2 FIG.A 2 FIG.C 60 62 60 62 64 62 62 64 60 60 60 66 illustrate a chiplet, including a grouping of multiple components, such as semiconductor die, semiconductor chips, semiconductor devices and other similar components interconnected and molded together.illustrates a chiplet(without encapsulant) comprising a central, larger, component, such as a semiconductor die, semiconductor chip, semiconductor device, and other similar components with multiple, additional, smaller components, such as multiple semiconductor die, semiconductor chips, semiconductor devices and other similar components disposed around and grouped together with component, such as in a fan-out arrangement. Chip type or function of the various components,within the chipletmay comprise a central processing unit (CPU), a modem, a graphics processing unit (GPU), chips, semiconductor die, or processors specialized for running artificial intelligence (AI) algorithms, chips, semiconductor die or processors specialized for input/output (I/O), Serializer/Deserializer (SERDES) devices, and various other memory devices such as chips or semiconductor die specialized for Cache or storing data, and chips specialized for high bandwidth memory (HBM) or high-speed computer memory.illustrate the same or similar chipletshown inovermolded with encapsulant material, mold compound or a similar material, and in a fan-out arrangement. In, the overmolded chipletis coupled to, or disposed over (or on) a substrate or package substrate, which may be further coupled to, or mounted on, a motherboard, a printed circuit board (PCB), a multilayer ceramic capacitors (MLCC), an interposer, a passive device, or another semiconductor device or package. The method and device described herein may be advantageously used for applications in which the device is mounted to a substrate and may also be used for instances in which it is not mounted to a substrate, like for applications within a handheld mobile electronic device, such as a smartphone or other wearable technology.

3 3 FIGS.A-C 3 FIG.A 110 114 110 112 114 110 116 116 110 114 show various views of a waferand the formation and separation of individual componentstherefrom.illustrates a plan view of the wafer, such as a semiconductor wafer, native wafer and other, similar structures, comprising a base substrate material, such as, without limitation, silicon, germanium, gallium arsenide, indium phosphide, silicon carbide and similar materials, for structural support. A plurality of components, including semiconductor die, embedded devices, bridge die, silicon components with or without TSVs, and other similar components, can be formed on waferseparated by a non-active, inter-die wafer area or saw streetas described above. The saw streetcan provide cutting areas to singulate the waferinto the individual components.

114 118 121 114 120 118 14 120 18 114 114 120 114 114 114 114 120 121 114 114 114 114 300 256 114 300 120 114 114 114 Each componentmay comprise a backside or back surfaceand a front surface. In some embodiments, componentsmay comprise an active surfaceopposite the backside. Each componentmay comprise one or more active devices, passive devices, or both active devices and passive devices. In some instances, both the active layerand the backside or back surfaceof the componentmay be active. In some instances, the componentmay be formed without active and passive devices, and be used for transmission or routing, such as by comprising TSVs for vertical interconnect. The active surfaceof the componentmay contain one or more analog or digital circuits, diodes, or transistors implemented as active devices, passive devices, conductive layers, and dielectric layers formed within or on the componentand electrically interconnected according to the electrical design and function of the semiconductor die, and may comprise a processor or logic device. For example, the componentmay comprise circuits that may include one or more transistors, a FET, a JFET, a MOSFET, a BJT, an IGBT, a SIT, diodes, a Schottky transistor diode, and other circuit elements formed within active surfaceof the chip substrate and close to the front surfaceto implement analog circuits or digital circuits, such as one or more of a DSP, ASIC, memory, or other circuits. Circuits may include RF circuits, LED, LCOS, CIS, transistor, optoelectronic, MEMS and the like. The componentmay also contain IPDs such as inductors, capacitors, and resistors, RF signal processing, digital or analog power line control, clocking, and other functions. The componentmay be formed on a native wafer in a wafer level process as one of many packages being formed simultaneously on a carrier. In other instances, the componentmay be formed as part of a reconstituted wafer, and may comprise multiple components molded together. The componentmay also be another suitable embedded device, which is subsequently formed within a fully-molded bridge interposer, and surrounded (partially or entirely) by encapsulant. The componentwithin the fully molded bridge interposermay be an active die or a bridge die or chip formed without an active surfacewith only electrical routing, and with copper studs of the bridge dieelectrically connected or coupled with wiring, routing, or RDLs. The componentmay also be only a dummy substrate with no electrical function, but rather act as structural element and may or may not include copper studs. In some embodiments, the componentmay not include, and may be formed without, conductive studs.

3 FIG.B 3 FIG.A 3 FIG.B 110 3 3 126 121 120 122 126 126 114 126 126 120 122 126 122 126 122 126 122 2 3 4 2 5 2 3 illustrates a cross sectional sideview of the wafer, as shown taken along the section lineB-B in.also illustrates an optional insulating layer, such as a dielectric layer, a passivation layer, and similar structures, conformally applied over the front surface, over active surfaceand over conductive layer. Insulating layercan include one or more layers that are applied using PVD, CVD, screen printing, spin coating, spray coating, sintering, thermal oxidation, or other suitable process. Insulating layercan contain, without limitation, one or more layers of silicon dioxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), tantalum pentoxide (TaO), aluminum oxide (AlO), polymer, polyimide, benzocyclobutene (BCB), polybenzoxazoles (PBO), or other material having similar insulating and structural properties. Alternatively, semiconductor dieare packaged without the use of any PBO layers, and insulating layercan be formed of a different material or omitted entirely. In another embodiment, insulating layerincludes a passivation layer formed over the active surfacewithout being disposed over conductive layer. When insulating layeris present and formed over conductive layer, openings are formed completely through insulating layerto expose at least a portion of conductive layerfor subsequent mechanical and electrical interconnection. Alternatively, when insulating layeris omitted, conductive layeris exposed for subsequent electrical interconnection without the formation of openings.

3 FIG.B 128 122 128 128 128 128 128 128 122 128 122 128 128 114 122 114 110 128 122 128 121 128 also illustrates conductive bumps, including conductive interconnects, bumps, studs, and electrical interconnect structures that can be formed of copper or other suitable conductive material, in shapes of columns, pillars, posts, thick RDLs, which are disposed over, and coupled or connected to, conductive layer. When formed as posts, the conductive bumpswill have a height greater than a thickness, whereas when the conductive bumpsare formed as a pillar, the conductive bumpsmay have a tin cap. When the conductive bumpsare formed as a stud, the conductive bumpsmay be wider than it is tall. Conductive bumpscan be formed directly on conductive layerusing patterning and metal deposition processes such as printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition process. Conductive bumpscan be one or more layers of Al, Cu, Sn, Ni, Au, Ag, palladium (Pd), or other suitable electrically conductive material and can include one or more layers. In some instances, one or more UBM layers of Al, Cu, Sn, Ni, Au, Ag, Pd, or other suitable electrically conductive material can optionally be disposed between conductive layerand conductive bumps. In some embodiments, conductive bumpscan be formed by depositing a photoresist layer over the componentand conductive layerwhile the componentsare part of the wafer. A portion of the photoresist layer can be exposed and removed by an etching development process, and the conductive bumpscan be formed as copper pillars in the removed portion of the photoresist and over conductive layerusing a selective plating process. The photoresist layer can be removed leaving conductive bumpsthat provide for subsequent mechanical and electrical interconnection and a standoff with respect to front surface. Conductive bumpscan include a height H1 in a range of 5-100 micrometers (μm) or a height in a range of 20-50 μm, or a height of about 25 μm.

3 FIG.B 110 129 110 110 also illustrates the wafercan undergo an optional grinding operation with a grinderto planarize the surface and reduce a thickness of the wafer. A chemical etch can also be used to remove and planarize a portion of the wafer.

3 FIG.C 130 110 118 114 130 illustrates attaching a die attach film (DAF)to the waferthat can be disposed over, and in direct contact with, the backsidesof the components. The DAFcan comprise epoxy, thermal epoxy, epoxy resin, B-stage epoxy laminating film, ultraviolet (UV) B-stage film adhesive layer, UV B-stage film adhesive layer including acrylic polymer, thermo-setting adhesive film layer, a suitable wafer backside coating, epoxy resin with organic filler, silica filler, or polymer filler, acrylate based adhesive, epoxy-acrylate adhesive, a polyimide (PI) based adhesive, or other adhesive material.

3 FIG.C 4 4 FIGS.A-J 110 116 132 110 114 128 128 128 114 t also illustrates wafercan be singulated through gaps or saw streetsusing laser grooving, a saw blade or laser cutting tool, or both to singulate the waferinto individual componentswith conductive bumps, comprising topsof conductive bumps. The componentscan then be used as part of a subsequently formed component package as discussed in greater detail below with respect to.

3 3 FIGS.A-C 3 3 FIGS.D-F 3 FIG.C 3 3 FIGS.D-F 3 FIG.D 3 FIG.D 110 117 110 117 117 110 117 117 110 152 126 122 152 126 152 174 154 172 121 117 152 a a v Similar to,show embodiments of a waferand the formation of components, such as semiconductor die, embedded devices, bridge die, silicon bridge components with or without TSVs, and other similar components. The wafermay be separated into individual components,as shown and described with respect to. The waferand individual components,ofmay comprise additional layers disposed thereon in subsequent processes performed after, or as part of, wafer fabrication.depicts where wafercomprises a first conductive layer, such as an interconnect layer, an RDL layer, an outermost interconnect layer, and similar structures, formed over insulating layerand coupled or connected to, conductive layerby viasdisposed in openings formed in insulating layer. First conductive layermay be formed in a similar, or same, manner as shown and described for first electrically conductive layer, and formed of similar, or the same, electrically conductive materials and layers.further depicts where a first insulating layer, such as a passivation layer, a dielectric layer, and similar layers as shown and described for first insulating layer, may be disposed over frontsideof the componentand over first conductive layer.

3 FIG.E 3 FIG.D 4 FIG.A 3 3 FIGS.B andC 156 152 156 154 156 154 174 178 182 158 154 156 154 150 117 156 128 128 156 156 v v , continuing from, shows where a second conductive layer, such as an interconnect layer, an RDL layer, an outermost conductive layer, an outermost RDL layer and similar structures, may be formed in a similar, or same, manner as shown and described for first conductive layerand may be formed of similar, or the same, electrically conductive materials and layers. Second conductive layermay be disposed over first insulating layerand may comprise viasdisposed in openings formed in first insulating layer, as shown and described for conductive layers,, and viasof. A second insulating layer, such as a passivation layer, a dielectric layer, and similar layers which may be similar to or the same as first insulating layer, may be disposed over the second conductive layerand first insulating layerto form build-up interconnectof component. In some embodiments, up to and including eight layers, comprising combinations of conductive layers and insulating layers may be formed. In some embodiments, the second conductive layermay comprise an outermost RDL and may have conductive bumpscoupled thereto, the conductive bumpsmay be the same as, or similar to as shown and described previously forfor interconnection to additional components, build-up structures, or peripheral devices. In additional embodiments, the second conductive layermay comprise interconnect pads or thick RDLs, formed over the second conductive layerfor interconnection to additional components, build-up structures, or peripheral devices. A person of ordinary skill in the art (a “POSA”) would understand that additional conductive layers and dielectric layers may be formed, although not depicted.

3 FIG.F 3 FIG.E 4 FIG.A 4 FIG.F 150 160 158 164 164 158 160 256 160 162 162 156 166 174 178 182 160 264 160 160 v v a shows an embodiment of the build-up interconnect structureof, further comprising a planarization layerdisposed between second insulating layerand third insulating layer, where the third insulating layermay be the same as, or similar to, second insulating layerand may comprise an outermost insulating layer. The planarization layermay be formed of an encapsulant or mold compound similar to, or the same as, encapsulant or mold compoundas earlier described. Openings may be formed in planarization layer, and viasas part of third conductive layer, may be disposed therein for connection to second conductive layerand fourth conductive layer, similar to as shown and described for conductive layers,, and viasof. The planarization layercan undergo an optional grinding or planarization operation with grinder(similar to as shown and described for the molded panel of) to form a planarized top surfaceof planarization layerand reduce surface roughness for deposition of additional fine pitch RDL and dielectric layers.

160 160 160 154 158 164 152 156 162 150 160 154 158 162 152 156 166 166 164 160 162 166 128 128 a v 3 FIG.E 3 3 3 FIGS.B,C andD In some embodiments, the planarized top surfacecomprises a roughness less than 500 nanometers (nm) over a characteristic measurement distance. The characteristic measurement distance is defined by the ISO 4288 standard, an entirety of which is hereby incorporated by reference. The characteristic measurement distance may also be a distance great enough to characterize the roughness, such as to a generally accepted level of certainty, and in some instances could be a distance of three times the distance of the roughness. While conventional encapsulant grinding might be done with less flatness, greater accuracy and precision can be obtained by using integrated sensors such as laser, acoustic, or other non-contact methods to control the grinding, resulting in better flatness and reduced roughness. The planarization layermay comprise a molded direct contact interconnect structure (also known under the trademark “MDx”™). Molded direct contact interconnect build-up structures (and a methods for making and using the same) are discussed in U.S. Pat. Nos. 11,973,051, 12,062,550, and 12,170,261, the entire disclosures of which are incorporated herein by this reference. Use of one or more planarization layers, interleaved between dielectric layers,,and additional, and conductive layers,,and additional, as part of build-up interconnect structure, provides the benefit of reducing deformations, including dips, waves, or undulations present in conventional, known build-up interconnect structures, which follow contours from lower layers, including dielectric layers and conductive layers which make manufacturing more difficult and often increase manufacturing cost. A POSA would understand that additional planarization layersmay be interleaved with dielectric layers,,and conductive layers,, such as eight conductive layers each separated by dielectric layers, with one or more planarization layers disposed therebetween. Similar to as shown in, a fourth conductive layer, such as an interconnect layer, an RDL layer, an outermost conductive layer, an outermost RDL layer and similar structures, may comprise fourth level conductive viasdisposed in openings formed in third insulating layer, and may be formed over the planarization layersand coupled to third electrically conductive layer. In some embodiments, the fourth conductive layermay comprise an outermost RDL and may have conductive bumpscoupled thereto, the conductive bumpsmay be the same as, or similar to as shown and described previously forfor interconnection to additional components, build-up structures, or peripheral devices.

4 5 FIGS.A-C 4 FIG.A 300 300 140 300 140 140 , illustrate a structure, method, process flow for forming the fully molded bridge interposer, such as a component interposer, component device, semiconductor device, semiconductor assembly, and other, similar structures, where the interposermay comprise one or more components and peripheral posts.illustrates providing a carrier, such as a temporary carrier, substrate or similar support structure, on which subsequent processing of the fully-molded bridge interposercan occur, as described in greater detail herein. Carriermay be a temporary or sacrificial carrier or substrate, and may also be a reusable carrier or substrate. The carriermay be of any desirable or suitable size, including a circular shape comprising a range of diameters, for example from 300 mm to 600 mm and greater.

140 140 140 140 140 140 140 140 The carriercan comprise one or more base materials formed in one or more layers, which may comprise base materials such as metal, silicon, polymer, polymer composite, ceramic, perforated ceramic, glass, glass epoxy, stainless steel, mold compound, mold compound with filler, or other suitable low-cost, rigid material or bulk semiconductor material for structural support. When a UV release is used with the carrier, the carriermay comprise one or more transparent or translucent materials, such as glass. When a thermal release is used with a carrier, the carriermay comprise opaque materials. The carriercan be circular, square, rectangular, or other suitable or desirable shape and can include any desirable size, such as a size equal to, similar to, or slightly larger or smaller than a reconstituted wafer or panel that is subsequently formed on or over the carrier. In some instances, a diameter, length, or width of the temporary carriercan be equal to, or about, 200 millimeters (mm), 300 mm, 600 mm or more.

140 142 140 300 143 143 142 143 114 114 114 The carriercan comprise a plurality of component mounting sites or component attach areasspaced or disposed across a surface of the carrier, according to a design and configuration of the final fully-molded bridge interposer, to provide a peripheral area or space. The peripheral areacan partially or completely surround the die attach areasto provide space for subsequent vertical, through package interconnections, and an area for fan-out routing or build-up interconnect structures. For example, the peripheral areacan surround, or be offset from, one side of the component, or more than one side of the component, such as 2, 3, 4, or more sides of the component.

140 144 140 144 When a temporary carrieris used, an optional release layer, interface layer or double-sided tapecan be formed over carrieras a temporary adhesive bonding film or etch-stop layer. The release layermay be a film or laminate, and may also be applied by spin coating or other suitable process. The temporary carrier can be subsequently removed by strip etching, chemical etching, mechanical peel-off, CMP, plasma etching, thermal, light releasing process, mechanical grinding, thermal bake, laser scanning, UV light, or wet stripping.

4 FIG.A 170 140 252 128 300 170 300 170 172 140 172 172 174 172 296 2 3 4 2 5 2 3 v further illustrates forming a build-up interconnect structureover the carrierto electrically connect, and provide routing between, conductive interconnects, the conductive bumps, and in some embodiments to provide routing between other devices mounted on, or coupled with, the fully-molded bridge interposer. While the build-up interconnect structureis shown comprising three conductive layers and three insulating layers, a POSA will appreciate that fewer layers or more layers can be used depending on the configuration and design of the fully-molded bridge interposer. The build-up interconnect structurecan comprise a first insulating layer, such as a passivation layer, a dielectric layer, and layers made of similar materials, formed or disposed over the carrier. The first insulating layercan comprise one or more layers of SiO, SiN, SiON, TaO, AlO, polymer, polyimide, BCB, PBO, or other material having similar insulating and structural properties. The insulating layercan be formed using PVD, CVD, printing, spin coating, spray coating, sintering or thermal oxidation. Openings which may be filled by first level conductive viascan be formed through the insulating layerfor subsequent interconnection with bumps, such as lower bumps, balls, a ball grid array (BGA), solder bumps, or interconnect structures.

174 140 172 172 174 252 296 252 174 174 174 v v A first conductive layercan be formed over the carrierand over the first insulating layeras a first RDL layer to extend through openings in the first insulating layer, to electrically connect with first level conductive vias, and to electrically connect with the conductive interconnects, and bumps. Conductive interconnectsmay comprise structures such as conductive posts, copper posts, conductive pillars and other, similar structures. Conductive layercan be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material formed using a patterning and metal deposition process such as sputtering, electrolytic plating, and electroless plating, or other suitable process. First level conductive viasmay comprise similar materials formed in a similar manner as that of conductive layer.

174 170 282 172 170 114 128 252 296 In some instances, the conductive layerwithin the build-up interconnect structurecan be formed as UBMs which are the same as, or similar to, UBMs as shown and subsequently described for third conductive layer, that are formed over the first insulating layerto electrically connect with the other conductive layers and conductive vias within the build-up interconnect structure, as well as electrically connect to the component, the conductive bumps, the conductive interconnects, and bumps.

176 172 140 174 172 176 178 174 v A second insulating layer, which can be similar or identical to the first insulating layer, can be disposed or formed over the carrier, the first conductive layer, and the first insulating layer. An opening can be formed through the second insulating layer, and second level conductive viasformed therein to electrically connect with the first conductive layer.

178 174 140 172 174 178 178 174 174 178 252 114 v v v A second conductive layer, when desirable and when present, may be similar or identical to the first conductive layer, and can be formed as a second RDL layer such as over substrate, over the first insulating layer, over the first conductive layer, over the second level conductive vias, and within an opening of the second insulating layer, to electrically connect with the first conductive layer, the first level and second level conductive vias,, conductive interconnects, and the component.

180 172 178 176 180 182 178 v A third insulating or passivation layer, when desirable and when present, may be similar or identical to the first insulating layer, can be disposed or formed over the second conductive layerand the second insulating layer. An opening can also be formed in or through the third insulating layerand third level conductive viasformed therein to electrically connect with the second conductive layer.

182 178 182 180 176 178 178 176 178 252 114 v v A third conductive layer, when desirable and when present, may be similar or identical to the second conductive layer, can be formed as a third RDL layer—and comprising vias or third level conductive viasdisposed over and (or) through the third insulating layer, and further disposed over the second insulating layer, over the second conductive layer, over the second level conductive viaor within an opening of the second insulating layer, to electrically connect with the second conductive layer, conductive interconnects, and the component.

4 FIG.B 190 170 190 190 190 190 further illustrates forming a seed layerover the build-up interconnect structure. The seed layercan be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Titanium (Ti), Tungsten (W) or other suitable electrically conductive material. In some instances, the seed layerwill be, or may include, Ti/Cu, Ti/W/Cu, W/Cu or a coupling agent/Cu. The formation, placement, or deposition of the seed layercan be with PVD, CVD, electrolytic plating, electroless plating, or other suitable process. The seed layercan be deposited by sputtering, electroless plating, or by depositing laminated foil, such as Cu foil, combined with electroless plating.

4 FIG.C 248 190 170 140 248 248 250 248 248 250 248 143 140 250 248 249 248 251 248 249 248 250 250 248 250 248 illustrates forming or depositing a resist layer or photosensitive layerover and directly contacting seed layer, over build-up interconnect structure, and over the temporary carrier. After formation of the resist layerover the temporary carrier, the resist layercan then be exposed and developed to form openingsin the resist layer. In some instances, more than one photoresist layermay be used. Openingsmay be formed in the photoresist, and can be positioned over, or within a footprint of, the peripheral areaof the carrier. The openingscan extend completely through the resist layer, such as from a first surface or bottom surfaceof the resist layerto second surface or top surfaceof the resist layeropposite the first surface. An after development inspection (ADI) of the developed resist layerand the openingscan be performed to detect the condition or quality of the openings. After the ADI of resist layerand openings, a descum operation can be performed on the developed resist layer.

4 FIG.D 252 250 248 252 300 252 252 252 190 252 shows the formation of a plurality of conductive interconnects, such as conductive posts, copper posts, conductive pillars and other, similar structures that were formed within the openingsin resist layer. In some embodiments, the conductive interconnectsmay be formed in a periphery of the semiconductor assembly. The conductive interconnectscan be formed as columns, pillars, posts, bumps, or studs that are formed of copper or other suitable conductive material. Conductive interconnectscan be formed using patterning and metal deposition processes such as printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition process. When conductive interconnectsare formed by plating, the seed layercan be used as part of the plating process. Conductive interconnectscan be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Pd, solder, or other suitable electrically conductive material and can include one or more layers.

252 248 252 143 142 300 252 252 After formation of the conductive interconnects, the resist layercan be removed, such as by a stripping process, leaving conductive interconnectsin the peripheral areaaround the semiconductor die mounting sitesto provide for subsequent vertical or three dimensional (3D) electrical interconnection for the fully-molded bridge interposer. Conductive interconnectscan include a height H2 in a range of 80-300 μm or a height in a range of 100-150 μm, or a height thereabout. In other instances, conductive vertical interconnectsmay include a height in a range of 10-600 μm, 60-100 μm, 70-90 μm, or about, 80 μm. As used herein, “thereabout,” “about,” or “substantially” means a percent difference in a range of 0-5%, 1-10%, 1-20%, 1-30%, or 1-40% of the number or range indicated.

248 142 140 170 114 114 121 120 114 140 114 121 120 140 114 114 140 130 130 114 170 140 After removal of the resist layer, the component mounting siteson or over the temporary carrier, the build-up interconnect structure, or both, can be exposed and ready to receive the component. The orientation of componentcan be either face up with front surface(or active surfacein the instance where componentcomprises a semiconductor die) oriented away from the temporary carrierto which the componentare mounted, or alternatively can be mounted face down with the front surface(or active surface) oriented toward the temporary carrierto which the componentare mounted. After mounting the componentto the temporary carrierin a face up orientation, the DAFcan undergo a curing process to cure the DAFand to lock the componentin place to the build-up interconnect structureand over the temporary carrier.

4 FIG.E 4 FIG.D 4 FIG.E 4 FIG.E 140 252 4 252 143 142 114 142 114 142 114 114 252 114 114 114 114 252 114 a a b a b. 1 2 shows a top or plan view of a portion of the temporary carrierand the conductive interconnectstaken along the section lineE from.shows that the conductive interconnectscan be formed within, and extend intermittently across, the peripheral areaand surround the component mounting sites(and the component) without being formed within the component mounting sites. Additionally,shows that after the componentis mounted at the mounting site, a first sideof componentis offset by an offset Ofrom the conductive postsadjacent the first side. A second sideof component(which is opposite the first side) is offset by an offset Ofrom the conductive interconnectsadjacent the first side

4 FIG.F 4 4 FIGS.D andE 4 FIG.F 4 FIG.G 114 140 256 114 114 256 114 256 114 121 120 114 114 256 114 256 128 252 252 258 258 170 170 270 170 270 270 140 170 a , continuing from, illustrates that after mounting the componentsto the carrier, an encapsulant, such as a mold compound, a polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, PBO, polyimide, polymer with or without proper filler, and similar materials, can be deposited around the componentsusing a paste printing, compression molding, transfer molding, liquid encapsulant molding, lamination, vacuum lamination, spin coating, or other suitable applicator. Componentcan be embedded in encapsulant, which can be non-conductive and environmentally protect the componentfrom external elements and contaminants. The encapsulantcan be formed as a single encapsulant in a single step adjacent to and directly contacting all lateral sides of the component (such as four lateral sides of the component), as well as be formed over the front surface(and over active surfacewhere componentcomprises an active semiconductor device) of the componentsuch that encapsulantis disposed on five sides of the component. The same single encapsulantcan also be formed around and directly contact the sides of the conductive bumpsand the sidesof conductive interconnectsin a single step to form at least part of a molded bridge interposer panel or molded panel. The molded bridge interposer panel or molded panelmay comprise one build-up interconnect structure, as shown in, or may comprise two opposing build-up interconnect structures,, as illustrated in. While a method is shown of forming build-up interconnect structurefirst, followed by building build-up interconnect structure, the order may be reversed. In some instances, the encapsulation and frontside build-up interconnect structuremay be built first, followed by removal of the temporary carrier, and further followed by the formation of the backside build-up interconnect structure.

258 256 262 256 253 252 262 256 253 252 253 252 256 258 257 256 253 The molded panelcan optionally undergo a curing process or post mold cure (PMC) to cure the encapsulant. In some instances, a top surface, such as a front surface and first surface of the encapsulantcan be substantially coplanar with first endsof the conductive interconnects. Alternatively, the top surfaceof the encapsulantcan be over, offset, or vertically separated from the first endsof the conductive interconnects, such that the first endsof the conductive interconnectsare exposed with respect to the encapsulantafter the reconstituted waferundergoes a grinding operation, or through a recessin the encapsulantto expose the first ends.

258 264 268 258 258 262 256 268 258 262 256 253 252 128 128 256 258 253 252 256 143 114 270 t The molded panelcan also undergo an optional grinding operation with grinderto planarize the top surface, front surface, or first surfaceof the molded paneland to reduce a thickness of the molded panel. The optional grinding operation also serves to planarize the top surfaceof the encapsulant. The top surfaceof the molded panelafter grinding or planarization can comprise one or more of the top surfaceof the encapsulant, the first endsof the conductive interconnects, and planarized topsof conductive bumps. A chemical etch can also be used to remove and planarize the encapsulantand the molded panel. Thus, the first endsof conductive interconnectscan be exposed by grinding or planarization with respect to encapsulantin the peripheral areato provide for electrical connection between componentand a subsequently formed redistribution layer or build-up interconnect structure.

258 256 258 258 The reconstituted wafercan also undergo a panel trim or trimming to remove excess encapsulantthat has remained in undesirable locations as a result of a molding process, such as eliminating a flange present for a mold chase. The molded panelcan include a footprint or form factor of any shape and size including a circular, rectangular, or square shape, the reconstituted wafercomprising a diameter, length, or width of, or about, 200 millimeter (mm), 300 mm, or any other desirable size.

4 FIG.F 114 258 259 258 114 258 also shows that actual positions of the componentwithin the molded panelmay be measured with an inspection device or optical inspection device. As such, subsequent processing of the fully molded panelas shown and described with respect to subsequent FIGs. can be performed with respect to the actual positions of the componentwithin the molded panel.

170 270 258 252 128 300 270 300 270 272 258 272 272 274 272 252 128 114 252 274 270 114 114 4 FIG.A 4 FIG.G 4 FIG.F 2 3 4 2 5 2 3 v Similar to or the same as shown and described for build-up interconnect structureof,, shows forming a build-up interconnect structure—such as a second, a frontside, or active side build-up interconnect structure—over the molded panelto electrically connect, and provide routing between, conductive interconnectsand the conductive bumps, and in some embodiments to provide routing between other devices mounted on, or coupled with, the fully-molded bridge interposer. While the build-up interconnect structureis shown comprising three conductive layers and three insulating layers, a person of ordinary skill in the art will appreciate that fewer layers or more layers can be used depending on the configuration and design of the fully-molded bridge interposer. The build-up interconnect structurecan comprise a first insulating layer, such as a passivation layer, a dielectric layer, and layers made of similar materials formed or disposed over the molded panel. The first insulating layercan comprise one or more layers of SiO, SiN, SiON, TaO, AlO, polymer, polyimide, BCB, PBO, or other material having similar insulating and structural properties. The first insulating layercan be formed using PVD, CVD, printing, spin coating, spray coating, sintering or thermal oxidation. Openings, which may be filled by first level conductive viascan be formed through the insulating layerover the conductive interconnectsand the conductive bumpsto connect with the componentand the conductive interconnects. In some embodiments, first conductive layerof build-up interconnect structuremay comprise first pads at a first pitch P1 (as shown in) within a footprint of the component(e.g. 80 μm or less), and second pads at a second pitch P2 outside a footprint of the component(e.g. 80 μm or more).

274 258 272 272 274 128 252 274 274 274 v v A first conductive layercan be formed over the molded paneland over the first insulating layeras a first RDL layer to extend through openings in the first insulating layer, to electrically connect with the first level conductive vias, and to electrically connect with the conductive bumpsand the conductive interconnects. As used herein, the term RDL includes distribution, redistribution, or movement, of signal through the conductive material in a vertical direction, horizontal direction, or both. As such, an RDL may, but need not have, a horizontal component. Conductive layercan be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material formed using a patterning and metal deposition process such as sputtering, electrolytic plating, and electroless plating, or other suitable process. First level conductive viasmay comprise similar materials formed in a similar manner as that of conductive layer.

274 272 270 274 274 128 128 128 128 114 300 114 300 274 128 128 114 114 252 114 114 114 114 114 114 252 114 114 128 274 274 270 114 258 114 270 128 274 274 252 114 114 300 114 300 128 274 252 114 v c c v c a a a b a b b c v c v c v 2 2 2 2 4 FIG.G 1 2 1 2 1 2 1 2 When the first conductive layeris formed, it may be formed at least partially within, or as part of, a corresponding first via layer formed within the first insulating layerof the frontside build-up interconnect structure. The first conductive layermay comprise viasaligned to centersof the copper studs. The alignment with the centersof studs or conductive bumpsmay be measured with an r(or R-squared) value for a lot (or statistically significant number) of componentsor devices. The R-squared value (also known as the coefficient of correlation) is a statistical measure of how closely data is fitted to a regression line, which in this case is based on the lot of componentsor devices. Stated another way, an R-squared value is the proportion of the variation in the dependent variable that is predictable from the independent variable. The alignment of first level conductive viaswith the centersof studs or conductive bumps(as shown in) may have an rvalue greater than or equal to 0.5, 0.6, 0.7, 0.8, or in a range greater than or equal to 0.5-0.8 relative to a difference between an offset Obetween a first sideof the componentand a copper postadjacent the first sideof the componentand a second offset Obetween a second sideof the componentopposite the first sideof the componentsand a corresponding copper postadjacent the second sideof the component. As such, the rvalue of greater than about 0.5 (or 50%), 0.6 (or 60%), 0.7 (or 70%), 0.8 (or (0%), or more between the centersand the centers of the viasof the conductive layerwhen compared with the difference in the offsets between Oand Oprovides a structural way of identifying that the processing of the build-up interconnect structurewas performed with respect to the actual positions of the componentwithin the molded panel, thereby allowing for finer pitch connections with the high density and ultra-high density interconnection with the componentand the build-up interconnect structure. Stated another way, the differences, offsets, or misalignments between the centersand the centers of the viasof the conductive layeris less than (or more closely aligned), than the differences, offsets, or misalignments between the differences in offsets Oand Obetween the copper postsof the componentfor the lot of componentsor devices. Stated yet another way, for a lot of componentsor devices, the differences, offsets, or misalignments between the centersand the centers of the viasis not statistically correlated (or has an rvalue less than 0.5) to the alignment of the die to the copper postson each side of the component(measured by looking at the offsets Oand O).

276 272 258 274 272 276 278 274 v A second insulating layer, which can be similar or identical to the first insulating layer, can be disposed or formed over the molded panel, the first conductive layer, and the first insulating layer. An opening can be formed through the second insulating layer, and second level conductive viasformed therein to electrically connect with the first conductive layer.

278 274 258 272 274 278 272 274 274 278 252 114 v v v A second conductive layer, when desirable and when present, may be similar or identical to the first conductive layer, and can be formed as a second RDL layer over molded panel, over the first insulating layer, over the first conductive layer, over the second level conductive vias, and within an opening of the second insulating layer, to electrically connect with the first conductive layer, the first level and second level conductive vias,, conductive interconnects, and the components.

280 272 278 276 280 282 278 v A third insulating layer, when desirable and when present, may be similar or identical to the first insulating layer, can be disposed or formed over the second conductive layerand the second insulating layer. An opening can also be formed in or through the third insulating layerand third level conductive viasformed therein to electrically connect with the second conductive layer.

282 278 282 280 276 278 278 280 282 278 252 114 v v A third conductive layer, when desirable and when present, may be similar or identical to the second conductive layer, can be formed as a third RDL layer, and comprising vias or third level conductive viasdisposed over and (or) through the third insulating layer, and be further disposed over the second insulating layer, over the second conductive layer, over the second level conductive via, and within an opening of the third insulating layer. The third conductive layercan electrically connect with the second conductive layer, and be coupled with the conductive interconnectsand the components.

282 270 280 270 114 128 252 282 174 290 290 290 In some instances, the third (or final) conductive layerwithin the build-up interconnect structurecan be formed as UBMs that are formed over the third insulating layerto electrically connect with the other conductive layers and conductive vias within the build-up interconnect structure, as well as electrically connect to the component, the conductive bumps, and the conductive interconnects. The UBMs as part of third conductive layer(and UBMs as part of first conductive layer), like all of the layers, plating layers, or conductive layers formed by a plating process as presented herein, can be a multiple metal stack comprising one or more of an adhesion layer, barrier layer, seed layer, or wetting layer. The adhesion layer can comprise titanium (Ti), or titanium nitride (TiN), titanium tungsten (TiW), Al, or chromium (Cr). The barrier layer can be formed over the adhesion layer and can be made of Ni, NiV, platinum (Pt), palladium (Pd), TiW, or chromium copper (CrCu). In some instances, the barrier layer can be a sputtered layer of TiW or Ti and can serve as both the adhesion layer and the barrier layer. In either event, the barrier layer can inhibit unwanted diffusion of material, like Cu. The seed layer can be Cu, Ni, NiV, Au, Al, or other suitable material. For example, the seed layer can be a sputtered layer of Cu comprising a thickness of about 2000 angstroms (e.g., 2000 plus or minus 0-600 angstroms). The seed layer can be formed over the barrier layer and can act as an intermediate conductive layer below subsequently formed upper bumps, balls, or interconnect structures. In some instances, the wetting layer can comprise a layer of Cu with a thickness in a range of about 5-11 μm or 7-9 μm. Upper bumps, such as when formed of SnAg solder, can consume some of the Cu UBM during reflow and forms an intermetallic compound at the interface between the solder bumpand the Cu of the wetting layer. However, the Cu of the wetting layer can be made thick enough to prevent full consumption of the Cu pad by the solder during high temperature aging.

282 282 282 270 UBMsmay be formed as a POP UBM pad, UBM structure, or land pad, such as for stacked POP structure, an additional electronic component. In some instances, the UBMscan comprise Ni, Pd and Au. UBMscan provide a low resistive interconnect to build-up interconnect structureas well as a barrier to solder diffusion and seed layer for solder wettability.

290 282 290 282 282 290 290 282 290 282 290 252 The upper bumpscan be formed on or coupled to the UBMs. The bumpscan be formed by depositing an electrically conductive bump material over the UBMsusing an evaporation, electrolytic plating, electroless plating, ball drop, or screen-printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, bismuth (Bi), Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material can be bonded to the UBMsusing a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps. In some applications, bumpsare reflowed a second time to improve electrical contact to UBMs. The bumpscan also be compression bonded or thermocompression bonded to the UBMs. Bumpsrepresent one type of interconnect structure that can be formed over the conductive interconnects, and other desirable structures, such as conductive paste, stud bump, micro bump, or other electrical interconnects may also be used as desired.

4 FIG.H 258 170 270 294 300 300 illustrates singulation of the molded paneland build-up interconnect structures,with saw blade or laser cutting toolto form individual fully-molded bridge interposers. The final interposer structuremay be thinner than previous packages, comprising an overall height or thickness of, or on the order of, or about, 50-250, 100-200, or less than or about 150 μm. Stacks of multiple layers can be correspondingly thicker, and increase in multiples of the above ranges, resulting in an overall thickness in a range of 200-1,000 μm. As part of the reduced height of the structure, the final structure may be made without an interposer, comprising the build-up interconnect layers and conductive interconnects providing the function of a conventional interposer.

140 140 144 144 140 140 258 258 140 253 254 252 290 128 170 270 253 254 252 The carrierin any of the embodiments disclosed herein, can be removed, e.g., by grinding the carrier, by exposing UV release tapeto UV radiation separate the UV tapefrom the glass substrate, by thermal release, or other suitable method. After removal of the carrier, the molded panelcan also undergo an etching process, such as a wet etch, to clean the surface of the molded panelexposed by removal of the temporary carrier, such as any exposed first or second ends,of conductive interconnect, for subsequent connection of bumps, balls or interconnect structureand tops of conductive bumpsafter planarizing, as part of build-up interconnect structures,. The exposed first and (or) second ends,of the conductive interconnectscan also undergo a coating or pad finishing process, such as by an Organic Solderability Preservative (OSP) coating, solder printing, electroless plating, or other suitable process, to form a PoP UBM pad, UBM structures, land pads, BGA pads, or other suitable structures, as desired.

296 170 270 253 254 252 296 170 270 254 252 170 270 253 254 252 296 296 252 296 252 296 252 5 FIG.C Bumps, such as lower bumps, balls, or interconnect structures, can be formed on or coupled through either or both of build-up interconnect structures,, to either or both of the exposed first and second ends,of the conductive interconnects, as shown, for example, in. The bumpscan be formed by depositing an electrically conductive bump material over pads on build-up interconnect structures,, coupled to the exposed second endsof the conductive interconnectsusing an evaporation, electrolytic plating, electroless plating, ball drop, or screen-printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material can be bonded to the pads on build-up interconnect structures,coupled to either or both of exposed first and second ends,of the conductive interconnectsusing a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps. In some applications, bumpsare reflowed a second time to improve electrical contact to conductive interconnects. The bumpscan also be compression bonded or thermocompression bonded to the conductive interconnects. Bumpsrepresent one type of interconnect structure that can be formed over the conductive interconnects, and other desirable structures, such as conductive paste, stud bump, micro bump, or other electrical interconnects may also be used as desired.

4 FIG.H 4 FIG.I 3 FIG.E 258 170 270 294 302 302 117 Similar to as shown and described for,illustrates singulation of a molded paneland build-up interconnect structures,with saw blade or laser cutting toolto form individual, fully-molded bridge interposers, such as a component interposer, component device, semiconductor device, semiconductor assembly, and other, similar structures. The fully-molded bridge interposercomprises one or more componentsas shown in, such as a semiconductor die, embedded devices, a bridge die, and other, similar components, having conductive layers and insulating layers disposed thereon.

4 FIG.I 4 FIG.J 3 FIG.F 258 170 270 294 304 304 117 a Similar to as shown and described for,illustrates singulation of a molded paneland build-up interconnect structures,with saw blade or laser cutting toolto form individual, fully-molded bridge interposers, such as a component interposer, component device, semiconductor device, semiconductor assembly, and other, similar structures. The fully-molded bridge interposercomprises one or more componentsas shown in, such as a semiconductor die, embedded devices, a bridge die, and other, similar components, having one or more conductive layers and insulating layers disposed thereon, and having one or more planarization layers interleaved between the conductive layers and insulating layers.

117 117 a The use of components,provides for increased interconnection density through the use of additional dielectric layers and conductive layers. Finer or smaller pitch and reduced manufacturing defects may be achieved through incorporation of one or more planarization layers interleaved between the dielectric and conductive layers.

5 FIG.A 2 2 FIGS.A-C 2 FIG.A 1 FIGS.A 5 5 FIGS.A-E 300 310 312 314 320 60 62 64 300 illustrates a high-level perspective view of a fully molded bridge interposerdisposed (or sandwiched) between: (i) a chiplet arrangementof semiconductor devices (e.g., a System On Chip (SOC)and High Bandwidth Memory (HBM) devices), and (ii) a substrate or package substrate, similar to what was shown in. In the past, a chipletor arrangement of semiconductor devices,similar to what was shown inmay have been coupled together with silicon interposers comprising TSVS, or EMIBs, as shown and described above with respect to-IF. However,show the new technology of a fully molded bridge interposerto replace the existing technology of a silicon interposer or EMIB.

5 FIG.B 5 FIG.A 5 FIG.B 4 FIG.H 5 FIG.B 5 FIG.B 5 FIG.B 5 300 300 252 114 256 252 256 262 256 266 256 262 300 300 310 312 314 320 shows a cross-sectional profile view taken along the section-line or box labeled “B” in.shows a cross-sectional profile view of the fully-molded bridge interposer, similar to the view shown in. Moreover, the view offurther includes the features of the fully-molded bridge interposershown more closely to scale.shows the peripheral conductive interconnect structuresdisposed around, and laterally offset from, the componentand within the encapsulant material. The peripheral conductive interconnect structurescan extend completely through the encapsulantin a vertical direction from, or adjacent, the top surfaceof the encapsulantto, or adjacent, the bottom surfaceof the encapsulantopposite top surfaceto provide vertical electrical interconnection through the fully-molded bridge interposer, which can facilitate stacking of packages in PoP arrangements.further shows a fully molded bridge interposerdisposed between a chiplet arrangementof at least two semiconductor devices (such as a SOCand a HBM) and a package substrate.

5 FIG.C 5 FIG.B 5 FIG.C 300 5 114 128 252 256 170 270 262 266 256 114 128 252 300 170 174 174 296 114 128 252 310 312 314 310 312 v shows a close-up sectional profile view of a portion of the fully molded bridge interposerofshown within the section-line or box designatedC.shows the component, conductive or copper bumps or interconnects, and conductive or copper posts, included within the encapsulant. Electrical build-up interconnect structures,comprising RDLs are formed above and below opposing surfaces,of the encapsulantas well as above and below the componentand conductive or copper studs, and conductive or copper posts. In some embodiments of the molded bridge interposer, build-up interconnect structuremay comprise first conductive layer, comprising first level conductive viascoupled to bumps. The component, conductive or copper studs, and conductive or copper posts, are electrically coupled to, or interconnected with, the chiplet arrangement, which may include a SOC, HBMs, and any other number of desired semiconductor devices within the chipletor SOC.

300 310 290 300 320 296 290 296 300 Attachment options for the molded bridge interposer, to chiplet arrangementinclude upper bumps, balls, or interconnect structures. Attachment options for the molded bridge interposerto the substrateinclude lower bumps, such as balls, or interconnect structures. Bumpsandmay each include: 1) solder bumps, 2) plated copper plus a solder post, and 3) direct copper to copper bonding. Additional design options for the fully molded bridge interposerinclude: 1) underfill, and 2) over mold, as desired or as applicable.

5 FIG.C 114 115 252 also shows exemplary layers labeled with dimensions that are about, or approximately, the dimensions indicated. The componentmay comprise a height or thickness (with or without ta die attach material) of about 100 μm and the conductive postsmay comprise a height of about 125 μm. As used herein “about” and “approximately” mean within a percent difference of less than or equal to 40%, 30%, 20%, 10%, 5%, 3%, 2%, or 1%.

5 5 FIGS.D andE 5 FIG.B 5 FIG.D 5 FIG.E 302 304 5 5 117 117 160 a show close-up sectional profile views of a portion of the fully molded bridge interposers,ofshown within the section-line or box designatedD,E.depicts a detail view of componentcomprising additional conductive layers and insulating layers disposed thereon.illustrates a detail view of componentcomprising planarization layersinterleaved with additional RDL and conductive layers.

300 302 304 300 2 2 2 2 The fully-molded bridge interposers,,provide cost advantages for high density integration, which includes integrations comprising 2 μm line and space pitch, and 20 μm area array bond pad pitch. Advantages include: (i) cost reduction greater than or equal to 80% for extending die size with respect to growing monolithic silicon (e.g., $0.01 per mmversus $0.06 per mm), and (ii) cost reduction greater than or equal to 50% compared to laminate embedded bridges (e.g., $0.01 per mmvs. $0.03 per mm. For ultra-high density integration with the fully molded bridge interposer, an enabled 20 μm area array bond pad pitch allows for increased or improved input/output (IO) on advanced node silicon without a die size penalty so that the integrated circuit (IC) device IO count is no longer constrained by a number of bond pads which will fit in minimum possible device size. As such, as much as an 80% reduction in die size is possible when total size has been based bond pad area requirements when using existing technology.

While this disclosure includes a number of embodiments in different forms, the drawings and written descriptions present detail of particular embodiments with the understanding that the present disclosure is to be considered as an exemplification of the principles of the disclosed methods and systems, and is not intended to limit the broad aspect of the disclosed concepts to the embodiments illustrated. Additionally, it should be understood by those of ordinary skill in the art that other manufacturing devices and examples could be intermixed or substituted with those provided. In places where the description above refers to particular embodiments, it should be readily apparent that a number of modifications may be made without departing from the spirit thereof and that these embodiments and implementations may be applied to other technologies as well. Accordingly, the disclosed subject matter is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the disclosure and the knowledge of one of ordinary skill in the art.