Method of Detecting Opening of Semiconductor Device Including Detection Structure and Semiconductor Device

This application is a continuation-in-part application of U.S. patent application Ser. No. 18/415,195, filed on Jan. 17, 2024, which claims priority to Korean Patent Application No. 10-2023-0098160, filed on Jul. 27, 2023, in the Korean Intellectual Property Office. This application also claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2025-0074873, filed on Jun. 9, 2025, in the Korean Intellectual Property Office. The disclosures of each of the aforementioned applications are incorporated by reference herein in their entireties.

The present disclosure relates generally to semiconductor integrated circuits, and more particularly, to a method of detecting an opening of a semiconductor device including a detection structure and a semiconductor device that performs the method.

Integrated circuits may be manufactured by forming repeated patterns in a wafer of semiconductor material. The wafer may be cut and/or diced into a plurality of semiconductor dies, and the respective semiconductor die may be packaged into a semiconductor chip. However, manufacturing defects, such as, but not limited to, openings, may occur in the semiconductor die during the cutting and/or packaging processes. In order to potentially increase a manufacturing yield of the semiconductor dies (e.g., decrease yield of defective products), the semiconductors may be inspected to detect and/or locate the openings precisely.

One or more example embodiments of the present disclosure may provide a method of detecting an opening of a semiconductor device including a detecting structure, capable of determining a location of the opening accurately.

Further, one or more example embodiments of the present disclosure may provide a semiconductor device capable of performing a method of detecting an opening.

According to an aspect of the present disclosure, a method of detecting an opening of a semiconductor device includes developing a first capacitance during a first time interval based on coupling a detection circuit with an end of a detection structure, and determining, based on a physical amount of a signal output from the end of the detection structure, a location of the opening in the detection structure. The detection structure is formed in a semiconductor die of the semiconductor device in an annular shape. The first capacitance corresponds to a sum of an intrinsic capacitance of the detection circuit and a second capacitance of the detection structure. The signal being detected by the detection circuit.

According to an aspect of the present disclosure, a semiconductor device includes a semiconductor die including a central region and an external region at least partially surrounding the central region, a detection structure formed in the semiconductor die in an annular shape to at least partially surround the central region, and a detection circuit coupled with the detection structure via a switch at a first node. The detection structure is configured to develop a first capacitance during a first time interval based on coupling with an end of the detection structure, and determine, based on a physical amount of a signal output from the end of the detection structure, a location of an opening in the detection structure. The first capacitance corresponds to a sum of an intrinsic capacitance of the detection circuit and a second capacitance of the detection structure.

According to an aspect of the present disclosure, a semiconductor device includes a first semiconductor die including a first central region and a first external region at least partially surrounding the first central region, a second semiconductor die including a second central region and a second external region at least partially surrounding the second central region, a memory cell structure formed in the first central region of the first semiconductor die, a peripheral circuit formed in the second central region of the second semiconductor die along a first direction and a second direction, a first detection structure formed in the second central region of the second semiconductor die to at least partially surround a first sub circuit region and a second sub circuit region which are spaced apart from each other in the second direction in the peripheral circuit, and a detection circuit coupled with an end of the first detection structure via a switch at a first node. The first semiconductor die is at least partially stacked in a vertical direction on the second semiconductor die. The detection circuit includes a charging transistor coupled between a power supply voltage and the first node, a discharging transistor coupled between the first node and a ground voltage, and a comparator including a first input terminal coupled to the first node, a second input terminal coupled to a reference voltage and an output terminal. The charging transistor is configured to precharge the first detection structure during a second time interval based on a precharge signal. The discharging transistor is configured to discharge a precharged voltage in the first detection structure based on a discharge signal. A voltage at the first node decreases from a first time point at which the discharging transistor is turned-on. The comparator is configured to output an output signal that transits at a second time point at which the voltage at the first node reaches the reference voltage. The detection circuit is configured to determine a location of an opening in the first detection structure based on a duration of a time interval from the first time point to the second time point.

In some embodiments, the measuring circuit may develop capacitance corresponding to a sum of an intrinsic capacitance of the detection circuit and a second capacitance of the detection structure during a first time interval based on connecting to an end of a detection structure and may determine, based on a physical amount of a signal output from the end of the detection structure, a location of the opening in the detection structure. The physical amount may be a voltage or a period of a clock signal. Therefore, a chip size overhead may be prevented because the location of the opening is detected by using one monitoring metal line.

Additional aspects may be set forth in part in the description which follows and, in part, may be apparent from the description, and/or may be learned by practice of the presented embodiments.

The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of embodiments of the present disclosure defined by the claims and their equivalents. Various specific details are included to assist in understanding, but these details are considered to be exemplary only. Therefore, those of ordinary skill in the art may recognize that various changes and modifications of the embodiments described herein may be made without departing from the scope and spirit of the disclosure. In addition, descriptions of well-known functions and structures are omitted for clarity and conciseness.

With regard to the description of the drawings, similar reference numerals may be used to refer to similar or related elements. It is to be understood that a singular form of a noun corresponding to an item may include one or more of the things, unless the relevant context clearly indicates otherwise. As used herein, each of such phrases as “A or B,” “at least one of A and B,” “at least one of A or B,” “A, B, or C,” “at least one of A, B, and C,” and “at least one of A, B, or C,” may include any one of, or all possible combinations of the items enumerated together in a corresponding one of the phrases. As used herein, such terms as “1st” and “2nd,” or “first” and “second” may be used to simply distinguish a corresponding component from another, and does not limit the components in other aspect (e.g., importance or order). It is to be understood that if an element (e.g., a first element) is referred to, with or without the term “operatively” or “communicatively”, as “coupled with,” “coupled to,” “connected with,” or “connected to” another element (e.g., a second element), it means that the element may be coupled with the other element directly (e.g., wired), wirelessly, or via a third element.

It is to be understood that when an element or layer is referred to as being “over,” “above,” “on,” “below,” “under,” “beneath,” “connected to” or “coupled to” another element or layer, it may be directly over, above, on, below, under, beneath, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly over,” “directly above,” “directly on,” “directly below,” “directly under,” “directly beneath,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

Reference throughout the present disclosure to “one embodiment,” “an embodiment,” “an example embodiment,” or similar language may indicate that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present solution. Thus, the phrases “in one embodiment”, “in an embodiment,” “in an example embodiment,” and similar language throughout this disclosure may, but do not necessarily, all refer to the same embodiment.

It is to be understood that the specific order or hierarchy of blocks in the processes/flowcharts disclosed are an illustration of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of blocks in the processes/flowcharts may be rearranged. Further, some blocks may be combined or omitted. The accompanying claims present elements of the various blocks in a sample order, and are not meant to be limited to the specific order or hierarchy presented.

The embodiments herein may be described and illustrated in terms of blocks, as shown in the drawings, which carry out a described function or functions. These blocks, which may be referred to herein as units or modules or the like, or by names such as device, logic, circuit, controller, counter, comparator, generator, converter, or the like, may be physically implemented by analog and/or digital circuits including one or more of a logic gate, an integrated circuit, a microprocessor, a microcontroller, a memory circuit, a passive electronic component, an active electronic component, an optical component, and the like.

As used herein, each of the terms “SiO”, “SiON”, and “SiN”, and the like may refer to a material made of elements included in each of the terms and is not a chemical formula representing a stoichiometric relationship.

Hereinafter, various embodiments of the present disclosure are described with reference to the accompanying drawings.

1 FIG.A is a top view illustrating a layout of a semiconductor device, according to example embodiments.

1 FIG.A 1000 Referring to, a semiconductor devicemay include at least one semiconductor die. The semiconductor die may include a central region CTREG and an external region EREG at least partially surrounding the central region CTREG.

1000 1000 1000 Various semiconductor integrated circuits may be formed in the central region CTREG depending on a kind and/or type of the semiconductor device. For example, the semiconductor devicemay be and/or may include a nonvolatile memory device and a memory integrated circuit may be formed in the central region CTREG of the semiconductor die. However, the present disclosure is not limited in this regard, and the semiconductor devicemay be and/or may include other kinds and/or types of devices and/or integrated circuits without departing from the scope of the present disclosure.

A detection structure DS, which may have an annular shape, according to example embodiments, may be configured to detect an opening and/or may be formed in the external region EREG.

The detection structure DS may include a first conduction segment passing through a left-bottom corner region CLB of the external region EREG, a second conduction segment passing through a left-upper corner region CLU of the external region EREG, a third conduction segment passing through a right-upper corner region CRU of the external region EREG and a fourth conduction segment passing through a right-bottom corner region CRB of the external region EREG. However, the present disclosure is not limited in this regard, and the detection structure DS may include less conduction segments (e.g., less than four (4)) and/or more conduction segments (e.g., more than four (4)). Alternatively or additionally, the conduction segments of the detection structure DS may be configured in a different configuration and/or arrangement. For example, the first to fourth conduction segments may pass through same and/or different regions of the external region EREG.

920 971 910 920 920 1 2 1 2 910 A detection circuitmay be connected to an end of the detection structure DS via a connection componentand a switch. The detection circuitmay develop a first capacitance during a first time interval based on connecting to an end of the detection structure DS and may determine, based on a physical amount of a signal output from the end of the detection structure DS, a location of the opening in the detection structure DS. The first capacitance may correspond to a sum of an intrinsic capacitance of the detection circuitand a second capacitance of the detection structure DS. The detection structure DS may include a first end ETand a second end ETand the end of the detection structure DS may be one of the first end ETand the second end ET. The switchmay be provided in the external region EREG.

920 920 920 The detection structure DS may be referred to as a monitoring metal line, and may be formed with a metal line and may operate as a capacitor. When a precharge voltage is applied to the detection structure DS, a capacitance (e.g., a second capacitance) of the detection structure DS may increase. When the detection structure DS is coupled to a ground voltage via the detection circuit, the voltage precharged in the detection structure DS and the capacitance of the detection structure DS may be decreased (e.g., may be discharged). A capacitance of the detection circuitmay be referred to an intrinsic capacitance. When an opening occurs in the detection structure DS, the capacitance of the detection circuitdue to the precharged voltage may vary, and a time interval for discharging the precharged voltage in the detection structure DS may vary.

In example embodiments, the physical amount may be a voltage. When the opening occurs in the detection structure DS, a time interval for discharging the precharged voltage in the detection structure DS may vary based on a location of the opening.

In example embodiments, the signal may be a clock signal and the physical amount may be a period of the clock signal.

When an opening occurs in the detection structure DS, the period of the clock signal may vary depending on a location at which the opening occurs (e.g., a location of the opening) and the number of periods of the clock signal may vary depending on the location of the opening because the period of the clock signal varies.

Hereinafter, example embodiments may be described using an orthogonal set of an X direction, a Y direction and a Z direction for convenience of illustration and description. The X direction, the Y direction and the Z direction may be used to indicate three perpendicular directions along the three directions, and may not be limited to particular directions. The X direction may correspond to a first horizontal direction and/or a row direction, the Y direction may correspond to a second horizontal direction and/or a column direction, and the Z direction may correspond to a vertical direction. If exceptional descriptions are not mentioned, the Z direction may indicate a vertical direction perpendicular to conduction layers.

As used herein, “upper”, “bottom”, “left” and “right” may not be used to represent particular fixed positions but to represent relative positions. Accordingly, example embodiments may include structures of bilateral symmetry, structures of top and bottom symmetry, rotated structures and the like with respect to the detection structure disclosed herein.

1 FIG.B is a top view illustrating a layout of a semiconductor device, according to example embodiments.

1 FIG.B 1000 a Referring to, a semiconductor devicemay include at least one semiconductor die. The semiconductor die may include a central region CTREG and an external region EREG at least partially surrounding the central region CTREG.

1 A detection structure DS, which may have an annular shape, according to example embodiments, may be configured to detect an opening and/or may be formed in an edge portion of the central region CTREG.

1 1 FIG.A The detection structure DSmay have a configuration similar to a configuration of the detection structure DS in.

1 The detection structure DSmay include a first conduction segment passing through a left-bottom corner region of the central region CTREG, a second conduction segment passing through a left-upper corner region of the central region CTREG, a third conduction segment passing through a right-upper corner region CRU of the central region CTREG and a fourth conduction segment passing through a right-bottom corner region of the central region CTREG.

920 1 971 910 920 1 1 920 1 1 2 1 2 910 1 1 2 1 1 2 A detection circuitmay be connected to an end of the detection structure DSvia a connection componentand a switch. The detection circuitmay develop a first capacitance during a first time interval based on connecting to an end of the detection structure DSand may determine, based on a physical amount of a signal output from the end of the detection structure DS, a location of the opening in the detection structure DS. The first capacitance may correspond to a sum of an intrinsic capacitance of the detection circuitand a second capacitance of the detection structure DS. The detection structure DS may include a first end ETand a second end ETand the end of the detection structure DS may be one of the first end ETand the second end ET. The switchmay be provided in the external region EREG or in the central region CTREG. The detection structure DSmay include a first end ETand a second end ETand the end of the detection structure DSmay be one of the end ETand the second end ET.

1 FIG.A 1 FIG.B 1 Therefore, the detection structure DS ofand/or the detection structure DSof, according to example embodiments, may have an annular shape and/or may be formed adjacent to an edge portion of the central region CTREG in the semiconductor die.

2 FIG. 1 FIG.A is a top view illustrating the detection structure in, according to example embodiments.

2 FIG. 910 In, the switchis illustrated for convenience of description.

2 FIG. 11 12 13 14 Referring to, the detection structure DS may include a first conduction segment CSG, a second conduction segment CSG, a third conduction segment CSGand a fourth conduction segment CSG.

11 1 910 12 11 13 12 14 13 2 910 The first conduction segment CSGmay include the first end ETthat may be connected to the switchand may pass through the left-bottom corner region CLB of the external region EREG. The second conduction segment VSGmay be connected to the first conduction segment CSGat a first connection node AN and may pass through the left-upper corner region CLU of the external region EREG. The third conduction segment CSGmay be connected to the second conduction segment CSGat a second connection node BN and may pass through the right-upper corner region CRU of the external region EREG. The fourth conduction segment CSGmay be connected to the third conduction segment CSGat a third connection node CN, and may pass through the right-bottom corner region CRB of the external region EREG, and may include the second end ETthat may be connected to the switch.

3 FIG. is a flow chart illustrating a method of detecting an opening of a semiconductor device including a detection structure according to example embodiments.

1 1 2 3 FIGS.A,B,, and 920 910 920 110 130 Referring to, the detection circuitmay be connected to an end of the detection structure DS via the switchand a first capacitance corresponding to a sum of an intrinsic capacitance of the detection circuitand a second capacitance of the detection structure DS may be developed during a first time interval (operation S). Based on a physical amount of a signal output from the end of the detection structure DS, a location of the opening in the detection structure DS may be determined (operation S). As discussed above, the physical amount may be a voltage of a period of a clock signal.

4 FIG.A 2 FIG. illustrates an example of resistance and parasitic capacitance in the detection structure in, according to example embodiments.

4 FIG.A Referring to, it may be assumed that an opening does not occur in the detection structure DS.

4 FIG.A 1 11 1 11 2 12 2 12 As shown in, the detection structure DS may be modeled as having a resistance Rin the first conduction segment CSGand a parasitic capacitance CPbetween the first conduction segment CSGand a ground voltage VSS. The detection structure DS may be further modeled as having a resistance Rin the second conduction segment CSGand a parasitic capacitance CPbetween the second conduction segment CSGand the ground voltage VSS.

3 13 3 13 4 14 4 14 The detection structure DS may be further modeled as having a resistance Rin the third conduction segment CSGand a parasitic capacitance CPbetween the third conduction segment CSGand the ground voltage VSS. The detection structure DS may be further modeled as having a resistance Rin the fourth conduction segment CSGand a parasitic capacitance CPbetween the fourth conduction segment CSGand the ground voltage VSS.

4 FIG.B 2 FIG. illustrates an example of parasitic capacitance in the detection structure in, according to example embodiments.

4 FIG.B 1 2 3 4 Referring to, it may be assumed that an opening (e.g., first opening OP, second opening OP, third opening OP, fourth opening OP) occurs in the detection structure DS.

4 FIG.B 1 11 1 11 1 11 1 11 As shown in, when the first opening OPoccurs in the first conduction segment CSG, the detection structure DS may be modeled as having a parasitic capacitance CPin the first conduction segment CSG, and the parasitic capacitance CPmay be coupled between the first conduction segment CSGand the ground voltage VSS. The first opening OPmay represent one of a plurality of openings that may occur at various locations of the first conduction segment CSG.

2 12 2 12 2 12 2 12 When the second opening OPoccurs in the second conduction segment CSG, the detection structure DS may be modeled as having a parasitic capacitance CPin the second conduction segment CSG, and the parasitic capacitance CPmay be coupled between the second conduction segment CSGand the ground voltage VSS. The second opening OPmay represent one of a plurality of openings that may occur at various locations of the second conduction segment CSG.

3 13 3 13 3 13 3 13 When the third opening OPoccurs in the third conduction segment CSG, the detection structure DS may be modeled as having a parasitic capacitance CPin the third conduction segment CSG, and the parasitic capacitance CPmay be coupled between the third conduction segment CSGand the ground voltage VSS. The third opening OPmay represent one of a plurality of openings that may occur at various locations of the third conduction segment CSG.

4 14 4 14 4 14 4 14 When the fourth opening OPoccurs in the fourth conduction segment CSG, the detection structure DS may be modeled as having a parasitic capacitance CPin the fourth conduction segment CSG, and the parasitic capacitance CPmay be coupled between the fourth conduction segment CSGand the ground voltage VSS. The fourth opening OPmay represent one of a plurality of openings that may occur at various locations of the fourth conduction segment CSG.

961 920 1 961 920 2 When the connection componentof the detection circuitis connected to the first end ET, a physical signal may be applied to the detection structure DS along a forward direction FWD of the detection structure DS and when the connection componentof the detection circuitis connected to the second end ET, a physical signal may be applied to the detection structure DS along a backward direction BWD of the detection structure DS.

5 FIG.A illustrates a semiconductor device including a detection circuit according to example embodiments.

5 FIG.A 1 FIG.A 1000 930 930 971 910 a Referring to, a semiconductor devicemay include a detection circuitand a semiconductor die including the detection structure DS. The semiconductor die may be substantially similar and/or the same as the semiconductor die in. The detection circuitmay be connected (e.g., coupled) to the detection structure DS through a lineand the switch.

930 931 933 935 The detection circuitmay include a charging transistor, a discharging transistor, and a comparator COMP.

931 1 931 1 1 2 971 910 The charging transistormay be coupled between a power supply voltage VDD and a first node ND, and may have a gate receiving a precharge signal PRE. The charging transistormay be a p-channel metal-oxide semiconductor (PMOS) transistor. The first node NDmay be coupled to the first end ETor the second end ETof the detection structure DS via the lineand the switch.

933 1 933 The discharging transistormay be coupled between the first node NDand a ground voltage VSS and may have a gate receiving a discharge signal DSCH. The discharging transistormay be an n-channel metal-oxide semiconductor (NMOS) transistor.

935 1 935 1 1 The comparatormay have a first input terminal coupled to the first node ND, a second input terminal coupled to a reference voltage VREF and an output terminal. The comparatormay provide an output signal TPOTat the output terminal by comparing a voltage at the first node NDwith the reference voltage VREF.

931 971 910 1 933 1 When the precharge signal PRE is activated at a logic low level, the charging transistormay precharge the detection structure DS through the lineand the switchbased on the power supply voltage VDD. When the discharge signal DSCH is activated at a logic high level, a precharged voltage in the detection structure DS may be discharged to the ground voltage VSS through the first node NDand the discharging transistorand the voltage of the first node NDmay be reduced. A time interval during which the voltage at the first node is discharged may vary depending on a location of the opening in the detection structure DS, and the location of the opening in the detection structure DS may be determined based on difference of the time interval during which the voltage at the first node is discharged.

5 FIG.A 1 1 971 910 In, it may be assumed that the first node NDis coupled the first end ETof the detection structure DS via the lineand the switch.

5 FIG.B 5 FIG.A is a timing diagram illustrating an operation of the detection circuit inaccording to example embodiments.

5 5 FIGS.A andB 10 11 931 971 910 11 1 933 1 Referring to, when the precharge signal PRE is activated at a logic low level during a second time interval TPCH from a time point tto a time point t, the charging transistormay precharge the detection structure DS through the lineand the switchbased on the power supply voltage VDD. When the discharge signal DSCH is activated at a logic high level at the time point t, a precharged voltage in the detection structure DS may be discharged to the ground voltage VSS through the first node NDand the discharging transistorand the voltage of the first node NDmay be reduced.

1 1 1 12 11 935 12 When a location of the opening in the detection structure DS is relatively near the first end ETas denoted by CASE, the voltage at the first node NDmay reach the reference voltage VREF at a time point t, and an output signal TPOTof the comparatormay transit to a logic high level at the time point t.

2 2 1 13 12 935 13 When a location of the opening in the detection structure DS is relatively near the second end ETas denoted by CASE, the voltage at the first node NDmay reach the reference voltage VREF at a time point t, and an output signal TPOTof the comparatormay transit to a logic high level at the time point t.

11 11 933 12 11 935 12 11 933 13 12 935 933 Because, based on a location of the opening in the detection structure DS, a time interval INTfrom the time point tat which the discharging transistoris turned-on based on the discharge signal DSCH to the time point tat which the output signal TPOTof the comparatortransits may differ from a time interval INTfrom the time point tat which the discharging transistoris turned-on based on the discharge signal DSCH to the time point tat which the output signal TPOTof the comparatortransits, the location of the opening in the detection structure DS may be determined based on a time interval from a time point at which the discharging transistoris turned-on to a time point at which the voltage of the first node reaches the reference voltage VREF.

1000 a For manufacturing the semiconductor device, a plurality of dies may be formed on a wafer through a fabrication (FAB) process. The plurality of dies may be singulated along a scribe line. The plurality of dies may be fabricated into individual unit chips or packages through an assembly process.

1000 a Between the FAB process and the assembly process, a wafer level test process and/or an electric die sorting (EDS) process may be performed. The electrical characteristics of a semiconductor device (e.g., the semiconductor device) formed in each of the plurality of dies may be tested during the wafer level test process and/or the EDS process. The wafer level testing process may be and/or may include a process in which test operation signals may be applied to a die of the plurality of dies formed on the wafer and test result signals output by the die in response to the test operation signals may be analyzed to determine whether the die has a defect.

The reference voltage VREF may be determined by measuring a discharging time interval after precharging the detection structure in each of the plurality of dies in the EDS process.

In addition, the method of detecting an opening of the semiconductor device, according to example embodiments, may be performed in the EDS process at a wafer level or may be performed after the assembly process. In addition, the method of detecting an opening of the semiconductor device, according to example embodiments, may be performed in an idle mode or a diagnostic mode of the semiconductor device during run of the semiconductor device after the semiconductor device is shipped as a product and is delivered to a user.

5 FIG.C is a circuit diagram illustrating a detection circuit, according to example embodiments.

5 FIG.C 930 931 932 933 935 933 930 a a. Referring to, a detection circuitmay include a charging transistor, an additional charging transistor, a discharging transistor, and a comparator COMP. In an embodiment, the discharging transistormay not be included in the detection circuit

931 1 931 1 1 2 971 910 The charging transistormay be coupled between a power supply voltage VDD and a first node NDand may have a gate receiving a precharge signal PRE. The charging transistormay be a PMOS transistor. The first node NDmay be coupled to the first end ETor the second end ETof the detection structure DS via the lineand the switch.

932 1 931 2 932 The additional charging transistormay be coupled between the power supply voltage VDD and the first node NDin parallel with the charging transistorand may have a gate receiving a second precharge signal PRE. The additional charging transistormay be a PMOS transistor.

933 1 933 The discharging transistormay be coupled between the first node NDand a ground voltage VSS and may have a gate receiving a discharge signal DSCH. The discharging transistormay be an NMOS transistor.

935 1 935 2 1 The comparatormay have a first input terminal coupled to the first node ND, a second input terminal coupled to a reference voltage VREF and an output terminal. The comparatormay provide an output signal TPOTat the output terminal by comparing a voltage at the first node NDwith the reference voltage VREF.

931 971 910 2 931 1 When the precharge signal PRE is activated at a logic low level, the charging transistormay precharge the detection structure DS through the lineand the switchbased on the power supply voltage VDD. When the second precharge signal PREis activated at a logic low level, the additional charging transistormay additionally precharge the detection structure DS based on the power supply voltage VDD and the voltage at the first node NDmay be increased.

A time interval during which the voltage at the first node is increased may vary depending on a location of the opening in the detection structure DS, and the location of the opening in the detection structure DS may be determined based on difference of the time interval during which the voltage at the first node is increased.

5 FIG.C 1 1 971 910 In, it may be assumed that the first node NDis coupled the first end ETof the detection structure DS via the lineand the switch.

5 FIG.D 5 FIG.C is a timing diagram illustrating an operation of the detection circuit inaccording to example embodiments.

5 5 FIGS.C andD 20 21 931 971 910 2 21 931 1 Referring to, when the precharge signal PRE is activated at a logic low level during a second time interval TPCH from a time point tto a time point t, the charging transistormay precharge the detection structure DS through the lineand the switchbased on the power supply voltage VDD. When the second precharge signal PREis activated at a logic high level at the time point t, the additional charging transistormay additionally precharge the detection structure DS based on the power supply voltage VDD and the voltage at the first node NDmay be increased.

1 1 1 22 21 935 22 When a location of the opening in the detection structure DS is relatively near the first end ETas denoted by CASE, the voltage at the first node NDreaches the reference voltage VREF at a time point t, and an output signal TPOTof the comparatormay transit to a logic high level at the time point t.

2 2 1 23 22 935 23 When a location of the opening in the detection structure DS is relatively near the second end ETas denoted by CASE, the voltage at the first node NDreaches the reference voltage VREF at a time point t, and an output signal TPOTof the comparatormay transit to a logic high level at the time point t.

21 21 932 2 22 21 935 22 21 932 2 23 22 935 932 1 Because, based on a location of the opening in the detection structure DS, a time interval INTfrom the time point tat which the additional charging transistoris turned-on based on the second precharge signal PREto the time point tat which the output signal TPOTof the comparatortransits may differ from a time interval INTfrom the time point tat which the additional charging transistoris turned-on based on the second precharge signal PREto the time point tat which the output signal TPOTof the comparatortransits, the location of the opening in the detection structure DS may be determined based on a time interval from a time point at which the additional charging transistoris turned-on to a time point at which the voltage of the first node NDreaches the reference voltage VREF.

5 FIG.E is a circuit diagram illustrating a detection circuit according to example embodiments.

5 FIG.E 930 931 932 932 933 934 934 935 b a j a k Referring to, a detection circuitmay include a charging transistor, additional charging transistors (e.g., a first additional charging transistorto a j-th additional charging transistor, where j is a positive integer greater than one (1)), a discharging transistor, additional discharging transistors (e.g., a first additional discharging transistorto a k-th additional charging transistor, where k is a positive integer greater than one (1)), and comparator COMP.

931 1 931 1 1 2 971 910 The charging transistormay be coupled between a power supply voltage VDD and a first node NDand may have a gate receiving a precharge signal PRE. The charging transistormay be a PMOS transistor. The first node NDmay be coupled to the first end ETor the second end ETof the detection structure DS via the lineand the switch.

932 932 1 931 21 2 932 932 a j j a j Each of the additional charging transistorstomay be coupled between the power supply voltage VDD and the first node NDin parallel with the charging transistorand may have a gate receiving respective one of second precharge signals (e.g., a first second precharge signal PCHto a j-th second precharge signal PRE). Each of the additional charging transistorstomay be a PMOS transistor.

933 1 933 The discharging transistormay be coupled between the first node NDand a ground voltage VSS and may have a gate receiving a discharge signal DSCH. The discharging transistormay be an NMOS transistor.

934 934 1 933 21 2 934 934 a k k a k Each of the additional discharging transistorstomay be may be coupled between the first node NDand the ground voltage VSS in parallel with the discharging transistorand may have a gate receiving respective one of second discharge signals (e.g., a first second discharge signal DSCHto a k-th second discharge signal DSCH). Each of the additional discharging transistorstomay be an NMOS transistor.

935 1 935 3 1 The comparatormay have a first input terminal coupled to the first node ND, a second input terminal coupled to a reference voltage VREF, and an output terminal. The comparatormay provide an output signal TPOTat the output terminal by comparing a voltage at the first node NDwith the reference voltage VREF.

1 932 932 1 934 934 a j a k. A charging slope (e.g., a slope of increase of voltage level at the first node ND) may be adjusted by the additional charging transistorstoand a discharging slope (e.g., a slope of decrease of voltage level at the first node ND) may be adjusted by the additional discharging transistorsto

5 FIG.F 5 FIG.C is a timing diagram illustrating an operation of the detection circuit inaccording to example embodiments.

5 5 FIGS.C andF 931 932 31 32 1 941 942 931 933 41 42 1 943 944 Referring to, with precharging the detection structure DS by using the charging transistorand additionally precharging the detection structure DS by using the additional charging transistor, time points tand tat which a voltage at the first node NDreaches the reference voltage VREF as reference numeralsandindicate, respectively. In addition, with precharging the detection structure DS by using the charging transistorand discharging the detection structure DS by using the discharging transistor, time points tand tat which a voltage at the first node NDreaches the reference voltage VREF as reference numeralsandindicate, respectively.

31 41 1 32 42 2 When the time point tis the same as the time point t, it may be determined that the opening occurs at a position that is relatively near the first end ETin the detection structure DS, and when the time point tis the same as the time point t, it may be determined that the opening occurs in a position that is relatively near the second end ETin the detection structure DS.

5 5 FIGS.G andH 5 FIG.A are timing diagrams illustrating an operation of the detection circuit inaccording to example embodiments.

5 5 5 FIGS.A,C, andF 31 51 52 931 971 910 32 52 53 1 933 1 Referring to, when the precharge signal PRE is activated at a logic low level during a time interval INTfrom a time point tto a time point t, the charging transistormay precharge the detection structure DS through the lineand the switchbased on the power supply voltage VDD. When the discharge signal DSCH is activated at a logic high level during a time interval INTfrom the time point tto a time point t, a precharged voltage in the detection structure DS may be discharged to the ground voltage VSS through the first node NDand the discharging transistorand the voltage of the first node NDmay be reduced.

1 1 945 2 1 946 When a location of the opening in the detection structure DS is relatively near the first end ET, the voltage at the first node NDmay decrease relatively slow as denoted by a reference numeral, and when a location of the opening in the detection structure DS is relatively near the second end ET, the voltage at the first node NDmay decrease relatively fast as denoted by a reference numeral.

935 Therefore, a location of the opening in the detection structure DS may be determined based on a transition of the output signal TPOT of the comparatorwith changing a voltage level of the reference voltage VREF.

53 In example embodiments, a position of the time point tmay be adaptively adjusted.

5 FIG.I illustrates metal segments included in the semiconductor device according to example embodiments.

51 FIG. 1 FIG.A 1000 4 5 6 Referring to, the semiconductor deviceofmay include metal segments (e.g., a first metal segment LM, a second metal segment LM, and a third metal segment LM).

5 4 6 5 The second metal segment LMmay be a portion of the detection structure DS and the first and third metal segments LMand LMmay be adjacent to the second metal segment LMin the third direction Z.

4 6 Before measuring a physical amount of the signal output from the end of the detection structure DS, a power supply voltage VDD or a ground voltage VSS may be applied to at least one of the first and third metal segments LMand LMsuch that the detection structure DS has a capacitance.

5 FIG.J illustrates metal segments included in the semiconductor device according to example embodiments.

5 FIG.J 1 FIG.A 1000 4 5 6 a a a Referring to, the semiconductor deviceofmay include metal segments (e.g., a first metal segment LM, a second metal segment LM, and a third metal segment LM).

5 4 6 5 4 6 5 a a a a a The second metal segment LMmay be a portion of the detection structure DS and the first and third metal segments LMand LMmay be adjacent to the second metal segment LMin the first direction X. In example embodiments, the first and third metal segments LMand LMmay be adjacent to the second metal segment LMin the second direction Y.

4 6 a a Before measuring a physical amount of the signal output from the end of the detection structure DS, a power supply voltage VDD or a ground voltage VSS may be applied to at least one of the first and third metal segments LMand LMsuch that the detection structure DS has a capacitance.

6 FIG.A 5 FIG.A is a flow chart illustrating a method of detecting an opening of a semiconductor device ofaccording to example embodiments.

5 5 6 FIGS.A,B, andA 931 930 210 Referring to, the detection structure DS is precharged during a second time interval TPCH by using the charging transistorof the detection circuit(operation S).

933 930 230 1 A precharged voltage in the detection structure DS may be discharged by using the discharging transistorof the detection circuit(operation S) and thus, the voltage of the first node NDis reduced.

11 933 12 13 1 935 930 250 270 A duration of the first time interval from a first time point tat which the discharging transistoris turned-on to a second time point tor tat which the voltage at the first node NDreaches the reference voltage VREF, is measured by using the comparatorof the detection circuit(operation S). Based on the duration, a location of the opening in the detection structure DS is determined (operation S).

6 FIG.A 3 FIG. 210 230 250 110 In, the operations S, Sand Smay correspond to the operation Sin.

6 FIG.B 5 FIG.C is a flow chart illustrating a method of detecting an opening of a semiconductor device including a detection circuit of, according to example embodiments.

5 5 6 FIGS.C,D, andB 931 930 310 a Referring to, the detection structure DS is precharged during a second time interval TPCH by using the charging transistorof the detection circuit(operation S).

932 930 330 1 a The detection structure DS is additionally precharged by using the additional charging transistorof the detection circuit(operation S). Therefore, the voltage at the first node NDcontinues to increase.

21 932 22 23 1 935 930 350 370 a A duration of the first time interval from a first time point tat which the additional charging transistoris turned-on to a second time point tor tat which the voltage at the first node NDreaches the reference voltage VREF, is measured by using the comparatorof the detection circuit(operation S). Based on the duration, a location of the opening in the detection structure DS is determined (operation S).

6 FIG.B 3 FIG. 310 330 350 110 In, the operations S, S, and Smay correspond to the operation Sin.

6 FIG.C 5 FIG.A is a flow chart illustrating a method of detecting an opening of a semiconductor device ofaccording to example embodiments.

5 5 6 FIGS.A,H, andC 21 51 52 931 930 410 Referring to, the detection structure DS is precharged during a second time interval INTfrom a time point tto a time point tby using the charging transistorof the detection circuit(operation S).

52 53 933 930 430 1 A precharged voltage in the detection structure DS may be discharged from the first time point tto the second time point tby using the discharging transistorof the detection circuit(operation S) and thus, the voltage of the first node NDis reduced.

1 53 935 930 450 The voltage at the first node NDat the second time point tis compared with the reference voltage VREF by using the comparatorof the detection circuit(operation S).

470 A location of the opening in the detection structure DS is determined which changing a voltage level of the reference voltage (operation S).

6 FIG.C 3 FIG. 410 430 450 110 In, the operations S, S, and Smay correspond to the operation Sin.

6 FIG.D 5 FIG.A is a flow chart illustrating a method of detecting an opening of a semiconductor device ofaccording to example embodiments.

5 6 FIGS.A andD 931 930 1 510 Referring to, the detection structure DS is precharged during a second time interval by connecting the charging transistorof the detection circuitto the first end ETof the detection structure DS (operation S).

933 930 1 520 1 A precharged voltage in the detection structure DS may be discharged by connecting the discharging transistorof the detection circuitto the first end ETof the detection structure DS (operation S) and thus, the voltage of the first node NDis reduced.

933 1 935 930 530 A first duration of the first time interval from a first time point at which the discharging transistoris turned-on to a second time point at which the voltage at the first node NDreaches the reference voltage VREF, may be measured by using the comparatorof the detection circuit(operation S).

930 2 540 The detection circuitmay be connected to the second end ETof the detection structure DS (operation S).

931 550 933 560 The detection structure DS may be precharged during a third time interval equal to the second time interval by using the charging transistor(operation S). A precharged voltage in the detection structure DS is discharged again by using the discharging transistor(operation S).

933 1 935 570 A second duration of a fourth time interval from a third time point at which the discharging transistoris turned-on to a fourth time point at which the voltage at the first node NDreaches the reference voltage VREF, may be measured by using the comparator(operation S).

580 Based on the first duration and the second duration, a location of the opening in the detection structure DS is determined (operation S).

1 2 When a sign of a result obtained by subtracting the second duration from the first duration is minus (negative), it may be determined that the opening occurs at a position (e.g., a location) that is relatively near the first end ET. When a sign of a result obtained by subtracting the second duration from the first duration is plus (positive), it may be determined that the opening occurs at a position that is relatively near the second end ET.

7 FIG.A is a top view illustrating a layout of a semiconductor device, according to example embodiments.

7 FIG.A 1 FIG.A In, descriptions repeated withmay be omitted for convenience of explanation.

7 FIG.A 100 950 b Referring to FIG., a semiconductor devicemay include a semiconductor die and a detection circuit.

975 950 910 950 975 950 1 2 1 2 910 A probeof the detection circuit(e.g., an oscilloscope circuit) may be contacted (e.g., connected, coupled) to an end of the detection structure DS through a switch. The detection circuitmay measure a period of a clock signal CLK that may be generated by contacting the probeof the detection circuitto the end of the detection structure DS and may determine a location of the opening in the detection structure DS by counting a number of periods of the clock signal CLK during a reference time interval. The detection structure DS may include a first end ETand a second end ET, the first conduction segment may include the first end ETand the fourth conduction segment may include the second end ET. The switchmay be provided in the external region EREG.

950 The detection circuitmay be referred to as a measuring circuit.

950 950 When an opening occurs in the detection structure DS, the period of the clock signal CLK may vary depending on a location at which the opening occurs (e.g., a location of the opening) and the number of periods of the clock signal CLK may vary depending on the location of the opening because the period of the clock signal CLK varies. When the opening occurs in the detection structure DS, a period of the clock signal CLK may be greater than a reference period determined by an intrinsic capacitance of the detection circuitand an intrinsic resistance of the detection circuit.

975 950 1 975 950 2 4 FIG.A 4 FIG.A When the probeof the detection circuitis connected to the first end ETof the detection structure DS of, the clock signal CLK may be generated in a forward direction FWD of the detection structure DS. When the probeof the detection circuitis connected to the second end ETof the detection structure DS of, the clock signal CLK may be generated in a backward direction BWD of the detection structure DS.

1 2 3 4 1 2 3 4 1 2 3 4 In some embodiments, all of the first opening OP, the second opening OP, the third opening OP, and the fourth opening OPmay exist in the detection structure DS. In some optional or additional embodiments, at least one of the first opening OP, the second opening OP, the third opening OP, and the fourth opening OPmay exist in the detection structure DS. That is, one or more of the first opening OP, the second opening OP, the third opening OP, and the fourth opening OPmay not exist in the detection structure DS.

1 2 3 4 When at least one of the first opening OP, the second opening OP, the third opening OPand the fourth opening OPoccurs in the detection structure DS, a period of the clock signal CLK output from the detection structure DS may be represented as an equation similar to Equation 1.

950 950 Referring to Eq. 1, T may represent a period of the clock signal CLK, Rosc may represent an intrinsic resistance of the detection circuit, Cosc may represent an intrinsic capacitance of the detection circuit, and Cmet may represent a second capacitance of the detection structure DS, which may vary based on the location of the opening in the detection structure DS.

When the opening occurs in the detection structure DS, the period T of the clock signal CLK may vary based on the location of the opening in the detection structure DS. As a result, the location of the opening may be determined by measuring the period T of the clock signal CLK and by counting a number of periods of the clock signal CLK during a reference number of time.

7 FIG.B is a flow chart illustrating a method of detecting an opening of a semiconductor device including a detection structure, according to example embodiments.

7 7 FIGS.A andB 975 950 910 610 630 650 Referring to, a period of the clock signal CLK that is generated by contacting the probeof the detection circuitto an end of the detection structure DS through the switchis measured (operation S). A number of periods of the clock signal CLK is counted during a reference time interval (operation S). A location of the opening in the detection structure DS is determined based on the counted number of periods of the clock signal CLK (operation S).

7 FIG.B 3 FIG. 3 FIG. 610 630 110 650 130 In, the operations Sand Smay correspond to the operation Sinand the operation Smay correspond to the operation Sin.

7 FIG.C is a flow chart illustrating a method of detecting an opening of a semiconductor device including a detection structure, according to example embodiments.

7 7 FIGS.A andC 975 950 1 1 910 710 975 950 2 1 910 730 Referring to, a first number is generated by counting first periods of a first clock signal that may be generated by contacting the probeof the detection circuitto a first end ETof the detection structure DS or DSthrough a switch, during a reference time interval (operation S). A second number may be generated by counting second periods of a second clock signal that may be generated by contacting the probeof the detection circuitto a second end ETof the detection structure DS or DSthrough the switch, during a reference time interval (operation S).

1 750 A location of the opening in the detection structure DS or DSmay be determined based on a difference between the first number and the second number, a first period of the first clock signal, and a second period of the second clock signal (operation S).

8 8 FIGS.A andB 4 FIG.B 9 FIG.A 4 FIG.B illustrate the clock signal measured in the detection structure of, respectively, according to example embodiments.illustrates an example of the number of periods of the clock signal depending on the location of the opening in the detection structure of, according to example embodiments.

8 FIG.A 8 FIG.B 9 FIG.A 4 FIG.B 8 FIG.A 975 950 1 975 950 2 illustrates an example of the clock signal when the probeof the detection circuitis contacted with the first end ETof the detection structure DS.illustrates an example of the clock signal when the probeof the detection circuitis contacted with the second end ETof the detection structure DS.illustrates an example of the number of periods of the clock signal depending on the location of the opening in the detection structure ofin case of.

9 FIG.A 950 Referring to, it may assumed that an intrinsic resistance Rosc of the detection circuitmay have a resistance value Rv.

4 8 9 FIGS.B,A, andA 1 11 11 1 1 1 1 Referring to, when the first opening OPoccurs in the first conduction segment CSGof the detection structure DS, the capacitance Cmet of the detection structure DS may correspond to a first capacitance Cand may vary according to a distance from the first end ETto the first opening OP. Consequently, the clock signal CLK may have a first period Tand a number of periods of the clock signal CLK during a reference time interval RINT may be a first number corresponding to a first counted value CV.

2 12 12 1 2 2 2 When the second opening OPoccurs in the second conduction segment CSGof the detection structure DS, the capacitance Cmet of the detection structure DS may correspond to a second capacitance Cand may vary according to a distance from the first end ETto the second opening OP. Therefore, the clock signal CLK may have a second period Tand a number of periods of the clock signal CLK during the reference time interval RINT may be a second number corresponding to a second counted value CV.

3 13 13 1 3 3 3 When the third opening OPoccurs in the third conduction segment CSGof the detection structure DS, the capacitance Cmet of the detection structure DS may correspond to a third capacitance Cand may vary according to a distance from the first end ETto the third opening OP. As a result, the clock signal CLK may have a third period Tand a number of periods of the clock signal CLK during the reference time interval RINT may be a third number corresponding to a third counted value CV.

4 14 14 1 4 4 4 When the fourth opening OPoccurs in the fourth conduction segment CSGof the detection structure DS, the capacitance Cmet of the detection structure DS may correspond to a fourth capacitance Cand may vary according to a distance from the first end ETto the fourth opening OP. Therefore, the clock signal CLK may have a fourth period Tand a number of periods of the clock signal CLK during the reference time interval RINT may be a fourth number corresponding to a fourth counted value CV.

1 As a distance from the first end ETto a position at which the opening occurs increases, the capacitance Cmet of the detection structure DS may increase based on Eq. 1 and the period T of the clock signal CLK may also increase. In addition, as the period T of the clock signal CLK increases, a number of periods of the clock signal CLK counted during the reference time interval RINT may decrease.

2 1 3 2 4 3 2 1 3 2 4 3 Accordingly, the second period Tmay be greater than the first period T, the third period Tmay be greater than the second period T, and the fourth period Tmay be greater than the third period T. The second counted value CVmay be smaller than the first counted value CV, the third counted value CVmay be smaller than the second counted value CV, and the fourth counted value CVmay be smaller than the third counted value CV.

6 7 FIGS.andB 1 11 1 4 2 1 1 a Referring to, when the first opening OPoccurs in the first conduction segment CSGof the detection structure DS, a clock signal CLKmay have a fourth period Tdue to the capacitance Cmet of the detection structure DS, according to a distance from the second end ETto the first opening OP, and a number of periods of the clock signal CLKduring the reference time interval RINT may be a fourth number.

2 12 1 3 2 2 1 a When the second opening OPoccurs in the second conduction segment CSGof the detection structure DS, the clock signal CLKmay have a third period Tdue to the capacitance Cmet of the detection structure DS, according to a distance from the second end ETto the second opening OP, and a number of periods of the clock signal CLKduring the reference time interval RINT may be a third number.

3 13 1 2 2 3 1 a When the third opening OPoccurs in the third conduction segment CSGof the detection structure DS, the clock signal CLKmay have a second period Tdue to the capacitance Cmet of the detection structure DS, according to a distance from the second end ETto the third opening OP, and a number of periods of the clock signal CLKduring the reference time interval RINT may be a second number.

4 14 1 1 2 4 1 a When the fourth opening OPoccurs in the fourth conduction segment CSGof the detection structure DS, the clock signal CLKmay have a first period Tdue to the capacitance Cmet of the detection structure DS, according to a distance from the second end ETto the fourth opening OP, and a number of periods of the clock signal CLKduring the reference time interval RINT may be a first number.

4 3 3 2 2 1 a a a a a a. The fourth period Tmay be greater than the third period T, the third period Tmay be greater than the second period Tand the second period Tmay be greater than the first period T

9 FIG.B 4 FIG.B illustrates an example of the number of periods of the clock signal and the period of the clock signal depending on the location of the opening in the detection structure of, according to example embodiments.

9 FIG.B 1 1 975 950 1 910 2 2 975 950 2 910 1 2 illustrates a first number # of CLKand a first period Ta of a first clock signal CLKwhich is generated by contacting the probeof the detection circuitto the first end ETof the detection structure DS through the switch, a second number # of CLKand a second period Tb of a second clock signal CLKwhich is generated by contacting the probeof the detection circuitto the second end ETof the detection structure DS through the switchand a difference between the first number # of CLKand the second number # of CLK.

1 11 1 1 11 2 2 12 11 12 11 12 11 12 920 11 8 FIG. When the first opening OPoccurs in the first conduction segment CSGof the detection structure DS, the first number # of CLKof the first clock signal CLKhas a first counted value CV, the second number # of CLKof the second clock signal CLKhas a second counted value CV, the first period Ta has a first value Tand the second period Tb has a second value T. As described with reference to, the first value Tmay be smaller than the second value T, a sign of a difference between the first counted value CVand the second counted value CVmay be positive and an absolute value of the sign may be greater than a reference value. Therefore, the detection circuitmay determine that the opening occurs in the first conduction segment CSG.

2 12 1 1 21 2 2 22 21 22 21 22 21 22 920 12 8 FIG. When the second opening OPoccurs in the second conduction segment CSGof the detection structure DS, the first number # of CLKof the first clock signal CLKhas a first counted value CV, the second number # of CLKof the second clock signal CLKhas a second counted value CV, the first period Ta has a first value Tand the second period Tb has a second value T. As described with reference to, the first value Tmay be smaller than the second value T, a sign of a difference between the first counted value CVand the second counted value CVmay be positive and an absolute value of the sign may be equal to or smaller than the reference value. Therefore, the detection circuitmay determine that the opening occurs in the second conduction segment CSG.

3 13 1 1 31 2 2 32 31 32 31 32 31 32 920 13 8 FIG. When the third opening OPoccurs in the third conduction segment CSGof the detection structure DS, the first number # of CLKof the first clock signal CLKhas a first counted value CV, the second number # of CLKof the second clock signal CLKhas a second counted value CV, the first period Ta has a first value Tand the second period Tb has a second value T. As described with reference to, the first value Tmay be greater than the second value T, a sign of a difference between the first counted value CVand the second counted value CVmay be negative and an absolute value of the sign may be equal to or smaller than the reference value. Therefore, the detection circuitmay determine that the opening occurs in the third conduction segment CSG.

4 14 1 1 41 2 2 42 41 42 41 42 41 42 920 14 8 FIG. When the fourth opening OPoccurs in the fourth conduction segment CSGof the detection structure DS, the first number # of CLKof the first clock signal CLKhas a first counted value CV, the second number # of CLKof the second clock signal CLKhas a second counted value CV, the first period Ta has a first value Tand the second period Tb has a second value T. As described with reference to, the first value Tmay be greater than the second value T, a sign of a difference between the first counted value CVand the second counted value CVmay be negative and an absolute value of the sign may be greater than the reference value. Therefore, the detection circuitmay determine that the opening occurs in the fourth conduction segment CSG.

950 1 1 1 975 950 1 910 950 2 2 2 975 950 2 910 950 1 2 1 2 Accordingly, the detection circuitmay generate the first number # of CLKof the first clock signal CLKby counting a number of periods of the first clock signal CLKduring the reference time interval, which may be generated by contacting the probeof the detection circuitto the first end ETof the detection structure DS through the switch. Additionally, the detection circuitmay generate the second number # of CLKof the second clock signal CLKby counting a number of periods of the second clock signal CLKduring the reference time interval, which may be generated by contacting the probeof the detection circuitto the second end ETof the detection structure DS through the switch. In such embodiments, the detection circuitmay determine a location of the opening in the detection structure DS based on the difference between the first number # of CLKand the second number # of CLK, the first period Ta of the first clock signal CLKand the second period Tb of the first clock signal CLK.

10 FIG. is a perspective view of a three-dimensional (3D) detection structure, according to example embodiments.

10 FIG. Referring to, a 3D detection structure DSa may include a single conduction loop. As described below, the semiconductor die may include a first conduction layer and a second conduction layer that may be provided under the first conduction layer. The conduction layers may include a metal layer in which metal line segments may be patterned and/or a polysilicon layer in which polysilicon line segments may be patterned. The 3D detection structure DSa may be expanded in the vertical direction Z through the first conduction layer and the second conduction layer.

1 2 The 3D detection structure DSa may include a plurality of top horizontal line segments HLT formed in the first conduction layer, a plurality of bottom horizontal line segments HLB formed in the second conduction layer, and a plurality of vertical line segments VL connecting the top horizontal line segments HLT and the bottom horizontal line segments HLB respectively to form the 3D detection structure DSa. The top horizontal line segments HLT, the bottom horizontal line segments HLB, and the vertical line segments VL may be disposed alternatingly along the 3D detection structure DSa, and may connect a first end ETand a second end ETin the annular shape to at least partially surround the central region of the semiconductor die.

971 930 975 950 1 2 971 930 975 950 1 2 In example embodiments, the method of detecting an opening according to example embodiments may be performed by connecting the lineof the detection circuitor the probeof the detection circuitto one of the first end ETand the second end ETor by connecting the lineof the detection circuitor the probeof the detection circuitto the first end ETand the second end ETsequentially.

11 12 13 FIGS.,, and are cross-sectional diagrams illustrating a vertical structure of a 3D detection structure, according to example embodiments.

11 FIG. 1 2 3 1 2 1 2 3 1 2 1 2 Referring to, a semiconductor die may include a semiconductor substrate SUB and a dielectric layer in which upper structures may be formed. The dielectric layer may include a plurality of conduction layers (e.g., a first metal layer ML, a second metal layer ML, a third metal layer ML, a gate polysilicon layer PL, and a bit-line polysilicon layer PL) in which conduction line patterns may be formed. The conduction layers may include one or more metal layers (e.g., the first metal layer ML, the second metal layer ML, and the third metal layer ML) and one or more polysilicon layers (e.g., the gate polysilicon layer PLand the bit-line polysilicon layer PL). The polysilicon layers may include the gate polysilicon layer PLin which gates of transistors in the semiconductor integrated circuit may be formed. If the semiconductor integrated circuit is a semiconductor memory device, the polysilicon layers may further include the bit-line polysilicon layer PLin which bit-lines in the semiconductor integrated circuit may be formed.

1 2 The 3D detection structure DSa may include a plurality of top horizontal line segments HLT formed in the first metal layer ML, a plurality of bottom horizontal line segments HLB formed in the bit-line polysilicon layer PLand a plurality of vertical line segments VL connecting the top horizontal line segments HLT and the bottom horizontal line segments HLB respectively to form the 3D detection structure DSb.

11 FIG. 1 1 3 2 1 3 1 1 2 As shown in, the first metal layer MLmay correspond to an uppermost metal layer among the first to third metal layers MLto MLthat may be formed over the semiconductor substrate SUB, and the bit-line polysilicon layer PLmay correspond to the bit-line polysilicon layer that may be formed between the semiconductor substrate SUB and the first to third metal layers MLto ML. The top horizontal line segments HLT may include first metal line patterns MPthat may be formed in the uppermost first metal layer ML, and the bottom horizontal line segments HLB may include polysilicon line patterns PP that may be formed in the bit-line polysilicon layer PL.

1 2 3 1 1 2 2 3 2 3 2 3 2 2 1 2 The vertical line segments VL may include vertical contacts (e.g., first vertical contact VC, second vertical contact VC, and third vertical contact VC) to provide an electrical connection between the first metal line patterns MPin the uppermost first metal layer MLand the polysilicon line patterns PP in the bit-line polysilicon layer PL. The vertical line segments VL may further include conduction line patterns (e.g., second metal line patterns MPand third metal line patterns MP) in the respective intermediate conduction layers (e.g., second metal layer MLand third metal layer ML). In some embodiments, the conduction line pattern in one or both of the intermediate conduction layers MLand MLmay be omitted. For example, the second metal line patterns MPin the intermediate second metal layer MLmay be omitted, and the two vertical contacts (e.g., first vertical contact VCand second vertical contact VC) may be combined as a longer vertical contact.

11 FIG. Hereinafter, repeated descriptions of the 3D detection structure DSa described with reference tomay be omitted for the sake of brevity.

12 FIG. 1 1 Referring to, the 3D detection structure DSa may include a plurality of top horizontal line segments HLT formed in the first metal layer ML, a plurality of bottom horizontal line segments HLB formed in the gate polysilicon layer PL, and a plurality of vertical line segments VL connecting the top horizontal line segments HLT and the bottom horizontal line segments HLB respectively to form the 3D detection structure DSa.

12 FIG. 1 1 3 1 1 3 1 1 1 1 As shown in, the first metal layer MLmay correspond to an uppermost metal layer from among the first to third metal layers MLto MLthat may be formed over the semiconductor substrate SUB, and the gate polysilicon layer PLmay correspond to the gate polysilicon layer that may be formed between the semiconductor substrate SUB and the first to third metal layers MLto ML. The top horizontal line segments HLT may include first metal line patterns MPthat may be formed in the uppermost first metal layer ML, and the bottom horizontal line segments HLB may include polysilicon line patterns PPthat may be formed in the gate polysilicon layer PL.

13 FIG. 1 Referring to, the 3D detection structure DSa may include a plurality of top horizontal line segments HLT that may be formed in the first metal layer ML, a plurality of bottom horizontal line segments HLB that may be formed in the second conduction layer MLB, and a plurality of vertical line segments VL connecting the top horizontal line segments HLT and the bottom horizontal line segments HLB respectively to form the 3D detection structure DSb.

13 FIG. 1 1 3 1 1 As shown in, the first metal layer MLmay correspond to an uppermost metal layer from among the first to third metal layers MLto MLthat may be formed over the semiconductor substrate SUB, and the bottom metal layer MLB correspond to a metal layer that may be formed on a bottom surface of the semiconductor substrate SUB. The top horizontal line segments HLT may include first metal line patterns MPformed in the uppermost first metal layer ML, and the bottom horizontal line segments HLB may include bottom metal line patterns MPB that may be formed in the bottom metal layer MLB on the bottom surface of the semiconductor substrate SUB.

11 12 13 FIGS.,, and As described with reference to, the 3D detection structure, according to example embodiments, may be expanded in the vertical direction Z to various depths. Using the 3D detection structure, the opening located at various location may be detected more accurately, when compared to related semiconductor devices.

11 12 13 FIGS.,, and 1 FIG.B 1 The 3D detection structure DSa ofmay be applicable to the detection structure DSof.

14 FIG. is a perspective view of a 3D crack detection structure according to example embodiments.

14 FIG. Referring to, a 3D detection structure DSb may include a first conduction loop LOOPa and a second conduction loop LOOPb. The semiconductor die may include a first conduction layer, a second conduction layer under the first conduction layer, and a third conduction layer under the second conduction layer. The conduction layers may include a metal layer in which metal line segments may be patterned and/or a polysilicon layer in which polysilicon line segments may be patterned. The first conduction loop LOOPa may be expanded in the vertical direction Z between the second conduction layer and the third conduction layer in a 3D shape. The second conduction loop LOOPb may be formed in the first conduction layer in a two-dimensional (2D) shape.

11 12 21 222 The first conduction loop LOOPa may include a plurality of first top horizontal line segments HLT that may be formed in the second conduction layer, a plurality of bottom horizontal line segments HLB that may be formed in the third conduction layer, and a plurality of vertical line segments VL connecting the first top horizontal line segments HLT and the bottom horizontal line segments HLB respectively to form the first conduction loop LOOPa. The second conduction loop LOOPb may include a plurality of second top horizontal line segments HL that may be formed on the first conduction layer. The first top horizontal line segments HLT, the bottom horizontal line segments HLB, and the vertical line segments VL may be disposed alternatively along the first conduction loop LOOPa and connect a first end ETand a second end ETin a ring shape to at least partially surround the central region of the semiconductor die. The second top horizontal line segments HL may connect a first end ETand a second end ETin a ring shape to at least partially surround the central region of the semiconductor die.

11 12 971 950 975 970 910 21 22 971 950 975 970 910 In example embodiments, a location of the opening in the first conduction loop LOOPa may be determined by connecting at least one of the first end ETand the second end ETto the lineof the detection circuitor the probeof the detection circuitthrough the switch. In example embodiments, a location of the opening in the second conduction loop LOOPb may be determined by connecting at least one of the first end ETand the second end ETto the lineof the detection circuitor the probeof the detection circuitthrough the switch.

15 16 FIGS.and 10 14 FIGS.through are cross-sectional diagrams illustrating a vertical structure of a 3D detection structure, according to example embodiments. Hereinafter, repeated descriptions of the 3D detection structures described with reference tomay be omitted for the sake of brevity.

15 FIG. 2 2 1 2 Referring to, the first conduction loop LOOPa may include a plurality of first top horizontal line segments HLT that may be formed in the second conduction layer ML, a plurality of bottom horizontal line segments HLB that may be formed in the second conduction layer PL, and a plurality of vertical line segments VL connecting the first top horizontal line segments HLT and the bottom horizontal line segments HLB respectively to form the first conduction loop LOOPa. The second conduction loop LOOPb may include a plurality of second top horizontal line segments HL that may be formed in the first metal layer MLover the second metal layer ML.

15 FIG. 1 1 3 2 1 2 1 3 2 2 2 1 1 In the embodiment of, the first metal layer MLmay correspond to an uppermost metal layer from among the first to third metal layer MLto MLthat are formed over the semiconductor substrate SUB, the second metal layer MLmay be a metal layer under the uppermost first metal layer ML, and the third conduction layer PLmay correspond to the bit-line polysilicon layer that may be formed between the semiconductor substrate SUB and the first to third metal layers MLto ML. The first top horizontal line segments HLT may include second metal line patterns MPthat may be formed in the second metal layer ML, and the bottom horizontal line segments HLB may include polysilicon line patterns PP that may be formed in the bit-line polysilicon layer PL. The second top horizontal line segments HL may include first metal line patterns MPthat may be formed in the first metal layer ML.

16 FIG. 2 1 1 2 Referring to, the first conduction loop LOOPa may include a plurality of first top horizontal line segments HLT that may be formed in the second conduction layer ML, a plurality of bottom horizontal line segments HLB that may be formed in the second conduction layer PL, and a plurality of vertical line segments VL connecting the first top horizontal line segments HLT and the bottom horizontal line segments HLB respectively to form the first conduction loop LOOPa. The second conduction loop LOOPb may include a plurality of second top horizontal line segments HL formed in the first metal layer MLover the second metal layer ML.

16 FIG. 1 1 3 2 1 3 1 3 2 2 1 1 1 1 As shown in, the first metal layer MLmay correspond to an uppermost metal layer from among the first to third metal layers MLto MLthat may be formed over the semiconductor substrate SUB, the second metal layer MLmay be a metal layer under the uppermost first metal layer ML, and the third metal layer MLmay correspond to the gate polysilicon layer that may be formed between the semiconductor substrate SUB and the first to third metal layers MLto ML. The first top horizontal line segments HLT may include second metal line patterns MPthat may be formed in the second metal layer ML, and the bottom horizontal line segments HLB may include polysilicon line patterns PPthat may be formed in the gate polysilicon layer PL. The second top horizontal line segments HL may include first metal line patterns MPthat may be formed in the first metal layer ML.

15 16 FIGS.and As described with reference to, the 3D detection structure, according to example embodiments, may be expanded in the vertical direction Z to the various depths. Using the 3D detection structure, the opening located at various location may be detected more accurately, when compared to related semiconductor devices.

14 15 16 FIGS.,, and 1 FIG.B 1 The 3D detection structure DSb ofmay be applicable to the detection structure DSdescribed with reference to.

17 FIG. is a perspective view of a 3D detection structure, according to example embodiments.

17 FIG. Referring to, a 3D detection structure DSc may include a first conduction loop LOOPc and a second conduction loop LOOPd. The semiconductor die may include a first conduction layer, a second conduction layer under the first conduction layer, and a third conduction layer under the second conduction layer. The conduction layers may include a metal layer in which metal line segments may be patterned and/or a polysilicon layer in which polysilicon line segments may be patterned. The first conduction loop LOOPc may be expanded in the vertical direction Z between the second conduction layer and the third conduction layer in a 3D shape. The second conduction loop LOOPd may be formed in the first conduction layer in a 2D shape.

1 2 3 4 1 2 17 FIG. The first conduction loop LOOPc may include a plurality of first top horizontal line segments HLT that may be formed in the second conduction layer, a plurality of bottom horizontal line segments HLB that may be formed in the third conduction layer, and a plurality of vertical line segments VL connecting the first top horizontal line segments HLT and the bottom horizontal line segments HLB respectively to form the first conduction loop LOOPc. The second conduction loop LOOPd may include a plurality of second top horizontal line segments HL that may be formed on the first conduction layer. The first top horizontal line segments HLT, the bottom horizontal line segments HLB, and the vertical line segments VL may be disposed alternatively along the first conduction loop LOOPc and connect a first end ETand a second end ETin an annular shape to at least partially surround the central region of the semiconductor die. As shown in, third node Nand fourth node Nof the first conduction loop LOOPc may be respectively connected to first node Nand second node Nof the second conduction loop LOOPd, such that the first and second conduction loops LOOPc and LOOPd may form a combined conduction loop.

1 2 921 920 1 2 921 920 910 920 In example embodiments, at least one of the first end ETand the second end ETmay be connected to the probeof the detection circuitand/or the first end ETand the second end ETmay be sequentially connected to the probeof the detection circuitthrough the switch. The clock signal CLK may be provided to the detection circuit.

17 FIG. 1 FIG.B 1 The description of the 3D detection structure DSc ofmay be applicable to the detection structure DSdescribed with reference to.

18 FIG. is a block diagram illustrating a semiconductor device, according to example embodiments.

100 100 18 FIG. In some embodiments, the semiconductor devicedescribed with reference tomay correspond to a non-volatile memory device. However, the present disclosure is not limited in this regard, and the semiconductor devicemay be and/or may include other types of devices without departing from the scope of the present disclosure.

18 FIG. 100 200 300 300 310 320 350 340 330 Referring to, a non-volatile memory devicemay include a memory cell arrayand a peripheral circuit. The peripheral circuitmay include a page buffer circuit, a data input/output (I/O) circuit, a control circuit, a voltage generator, and an address decoder.

200 330 The memory cell arraymay be coupled to the address decoderthrough a string selection line SSL, a plurality of word-lines WLs, and a ground selection line GSL.

200 310 200 The memory cell arraymay be coupled to the page buffer circuitthrough a plurality of bit-lines BLs. The memory cell arraymay include a plurality of non-volatile memory cells coupled to the plurality of word-lines WLs and the plurality of bit-lines BLs.

200 1 200 The memory cell arraymay include a plurality of memory blocks (e.g., first memory block BLKto z-th memory block BLKz, where z is a positive integer greater than or equal to two (2)). Each memory block of the plurality of memory blocks may have a 3D structure. The memory cell arraymay include a plurality of (vertical) cell strings (e.g., NAND strings) and each of the cell strings may include a plurality of memory cells stacked with respect to each other.

350 100 The control circuitmay receive a command CMD, an address ADDR, and a control signal CTRL from an external memory controller and may control, for example, an erase loop, a program loop and a read operation of the non-volatile memory device. The program loop may include a program operation and a program verification operation and the erase loop may include an erase operation and an erase verification operation.

350 340 310 350 330 320 340 310 In example embodiments, the control circuitmay generate control signals CTLs, which may be used for controlling the voltage generator, based on the command CMD, may generate a page buffer control signal PCTL for controlling the page buffer circuit, and may generate a row address R_ADDR and a column address C_ADDR based on the address ADDR. The control circuitmay provide the row address R_ADDR to the address decoder, may provide the column address C_ADDR to the data I/O circuit, may provide the control signals CTLs to the voltage generator, and may provide the page buffer control signal PCTL to the page buffer circuit.

330 200 330 The address decodermay be coupled to the memory cell arraythrough the string selection line SSL, the plurality of word-lines WLs, and the ground selection line GSL, During program operation or read operation, the address decodermay determine one of the plurality of word-lines WLs as a selected word-line based on the row address R_ADDR and may determine the rest of the plurality of word-lines WLs except the selected word-line as unselected word-lines.

340 100 350 330 The voltage generatormay generate word-line voltages VWLs associated with operations of the non-volatile memory deviceusing an external voltage EVC that may be provided from the memory controller based on control signals CTLs from the control circuit. The word-line voltages VWLs may be applied to the plurality of word-lines WLs through the address decoder.

340 340 For example, during the erase operation, the voltage generatormay apply an erase voltage to a well of a selected memory block and may apply a ground voltage to all word-lines of the selected memory block. During the erase verification operation, the voltage generatormay apply an erase verification voltage to all word-lines of the selected memory block and/or may apply the erase verification voltage to the word-lines of the selected memory block on a word-line basis.

340 340 340 As another example, during the program operation, the voltage generatormay apply a program voltage to the selected word-line and may apply a program pass voltage to the unselected word-lines. As another example, during the program verification operation, the voltage generatormay apply a program verification voltage to the selected word-line and may apply a verification pass voltage to the unselected word-lines. As another example, during the read operation, the voltage generatormay apply a read voltage to the selected word-line and may apply a read pass voltage to the unselected word-lines.

310 200 310 310 200 The page buffer circuitmay be coupled to the memory cell arraythrough the plurality of bit-lines BLs. The page buffer circuitmay include a plurality of page buffers PB. The page buffer circuitmay temporarily store data to be programmed in a selected page and/or data read out from the selected page of the memory cell array.

In example embodiments, page buffer units included in each of the plurality of page buffers PB (and cache latches included in each of the plurality of page buffers PB) may be spaced apart from each other, and may have separate structures. Accordingly, the degree of freedom of wirings on the page buffer units may be increased, and the complexity of a layout may be reduced. In addition, because the cache latches are adjacent to data I/O lines, the distance between the cache latches and the data I/O lines may be reduced, and thus, data I/O speed may be increased.

320 310 320 310 450 320 350 The data I/O circuitmay be coupled to the page buffer circuitthrough a plurality of data lines DLs. During the program operation, the data I/O circuitmay receive program data from the memory controller and may provide the program data to the page buffer circuitbased on the column address C_ADDR received from the control circuit. During the read operation, the data I/O circuitmay provide read data to the memory controller based on the column address C_ADDR received from the control circuit.

350 The above-discussed method of detecting an opening may be performed in an idle mode in which the control circuitdoes not receive any commands from a memory controller and/or does not perform operation based on command received from the memory controller or in a specific diagnostic mode.

19 FIG. 18 FIG. schematically illustrates a structure of the non-volatile memory device of, according to example embodiments.

19 FIG. 100 1 2 1 2 2 1 2 1 2 2 Referring to, the non-volatile memory devicemay include a first semiconductor layer Land a second semiconductor layer L. The first semiconductor layer Lmay be stacked in a vertical direction Z with respect to the second semiconductor layer L. The second semiconductor layer Lmay be disposed under the first semiconductor layer Lin the vertical direction Z, and accordingly, the second semiconductor layer Lmay be close to a substrate. For example, among the first semiconductor layer Land the second semiconductor layer L, the second semiconductor layer Lmay be disposed closer to a substrate.

200 1 300 2 18 FIG. 18 FIG. In example embodiments, the memory cell arrayinmay be formed (or provided) on the first semiconductor layer L, and the peripheral circuitinmay be formed (or provided) on the second semiconductor layer L.

100 200 300 100 100 Accordingly, the non-volatile memory devicemay have a structure in which the memory cell arrayis disposed on the peripheral circuit. That is, the non-volatile memory devicemay have a cell over periphery (COP) structure. The COP structure may effectively reduce an area in a horizontal direction and increase the degree of integration of the non-volatile memory device, when compared to related semiconductor devices.

2 300 2 300 2 1 200 200 300 2 In example embodiments, the second semiconductor layer Lmay include a substrate, and by forming transistors on the substrate and metal patterns for wiring transistors, the peripheral circuitmay be formed in the second semiconductor layer L. After the peripheral circuitis formed on the second semiconductor layer L, the first semiconductor layer Lincluding the memory cell arraymay be formed, and the metal patterns for connecting the word-lines WL and the bit-lines BL of the memory cell arrayto the peripheral circuitformed in the second semiconductor layer Lmay be formed. For example, the word-lines WL may extend in a first direction X and the bit-lines BL may extend in a second direction Y.

20 FIG. 18 FIG. is a block diagram illustrating an example of the memory cell array in, according to example embodiments.

20 FIG. 18 FIG. 200 1 1 330 330 1 Referring to, the memory cell arraymay include a plurality of memory blocks (e.g., first memory block BLKto z-th memory block BLKz) which may extend along a plurality of directions including a first direction X, a second direction Y, and a vertical direction. In an embodiment, the plurality of memory blocks BLKto BLKz may be selected by the address decoderin. For example, the address decodermay select a memory block BLK corresponding to a block address from among the plurality of memory blocks BLKto BLKz.

21 FIG. 20 FIG. is a circuit diagram illustrating one of the memory blocks of, according to example embodiments.

21 FIG. 1 The memory block BLKi ofmay be formed on a substrate SUB in a 3D structure (or a vertical structure). For example, a plurality of memory cell strings included in the memory block BLKi may be formed in the vertical direction VD substantially perpendicular to the substrate SUB. The memory block BLKi may correspond to any one of the memory blocks of the plurality of memory blocks BLKto BLKz.

21 FIG. 21 FIG. 11 33 1 2 3 11 33 1 8 11 33 1 8 11 33 Referring to, the memory block BLKi may include cell strings (or NAND strings) NSto NScoupled between bit-lines BL, BLand BLand a common source line CSL. Each of the cell strings NSto NSmay include a string selection transistor SST, a plurality of memory cells MCto MC, and a ground selection transistor GST. As shown in, each of the cell strings NSto NSis illustrated to include eight memory cells MCto MC. However, embodiments of the present disclosure are not limited thereto. For example, in some example embodiments, each of the cell strings NSto NSmay include any number of memory cells.

1 3 1 8 1 8 1 3 1 2 3 The string selection transistor SST may be connected to corresponding string selection lines SSLto SSL. The plurality of memory cells MCto MCmay be connected to corresponding word-lines WLto WL, respectively. The ground selection transistor GST may be connected to corresponding ground selection lines GSLto GSL. The string selection transistor SST may be connected to corresponding bit-lines BL, BLand BL, and the ground selection transistor GST may be connected to the common source line CSL.

1 1 3 1 3 Word-lines (e.g., WL) having a substantially similar and/or the same height may be commonly connected, and the ground selection lines GSLto GSLand the string selection lines SSLto SSLmay be separated.

22 FIG. 23 FIG. 22 FIG. is a layout diagram of a non-volatile memory device, according to example embodiments.is a cross-sectional view taken along a line I-I′ of, according to example embodiments.

22 FIG. 19 FIG. 19 FIG. 100 2 1 Referring to, the non-volatile memory devicemay include a peripheral logic structure PS, a horizontal conductive substrate USB, and an electrode structure ST. The peripheral logic structure PS may correspond to the second semiconductor layer Linand the stacked structure ST may correspond to the first semiconductor layer Lin. The stacked structure ST may include a cell array region CR and a cell extension region CER.

200 18 FIG. A memory cell array (e.g., the memory cell arrayin) including a plurality of memory cells may be formed in the cell array region CR. In an example embodiment, a vertical structure VS and a bit-line BL may be formed in the cell array region CR.

1 8 The cell extension region CER may be around the cell array region CR. In an example embodiment, the cell array region CR and the cell extension region CER may extend along a direction in which a word-line cut region WLC extends. In example embodiment, the cell array region CR and the cell extension region CER may extend along the first direction X. A plurality of electrode pads EPto EPmay be stacked stepwise in the cell extension region CER.

1 The electrode structure ST may include memory blocks (e.g., memory blocks BLKto BLKz) separated by the word-line cut region WLC.

22 FIG. In an example embodiment, the cell extension region CER may be on one side of the cell array region CR, as shown in. In an example embodiment, the cell extension region CER may be disposed on both sides of the cell array region CR with the cell array region CR interposed therebetween.

In an example embodiment, a single electrode structure ST may be on the peripheral logic structure PS. In an example embodiment, two or more electrode structures ST may be on the peripheral logic structure PS.

1 1 A first penetration electrode region THV_Rmay be delineated by a peripheral logic structure PS that may not overlap a horizontal conductive substrate USB in the vertical direction Z. The first penetration electrode region THV_Rmay extend in the second direction Y.

2 2 2 2 1 A second penetration electrode region THV_Rmay be delineated by the electrode structure ST. In an example embodiment, the second penetration electrode region THV_Rmay be referred to as a region extending in the first direction X. In an example embodiment, the second penetration electrode region THV_Rmay be designated only in the cell array region CR and not defined in the cell extension region CER. In an example embodiment, the second penetration electrode region THV_Rmay be defined in all the memory blocks BLKto BLKz.

1 A plate contact plug region PCC_R may be defined on the horizontal conductive substrate USB that may not overlap the electrode structure ST. The plate contact plug region PCC_R may extend along the second direction Y. The plate contact plug region PCC_R may be defined to be closer to the electrode structure ST than the first penetration electrode region THV_R.

1 2 1 2 1 1 2 23 FIG. 23 FIG. 23 FIG. The first penetration electrode region THV_Rand the second penetration electrode region THV_Rmay be regions in which the penetration electrodes (e.g., first through-electrode THVand second through-electrode THVof) are disposed. The plate contact plug region PCC_R may be a region in which the plate contact plug (e.g., first plate contact plug PCCof) is disposed. The first and second penetration electrode regions THV_Rand THV_Rmay be further described with reference to.

22 23 FIGS.and 100 Referring to, the non-volatile memory devicemay include a peripheral logic structure PS and a cell array structure CS.

110 101 310 330 18 FIG. 18 FIG. The peripheral logic structure PS may include a pass transistor PTR, a lower connection wiring body PW, and a peripheral logic insulation film. The pass transistor PTR may be on a substrate. The pass transistor PTR may be included in the page buffer circuitinor may be included in the address decoderin.

101 101 110 101 110 The substratemay be and/or may include bulk silicon and/or silicon-on-insulator (SOI). In an example embodiment, the substratemay be and/or may include a silicon substrate and/or may include another material. The peripheral logic insulation filmmay be formed on the substrate. The peripheral logic insulation filmmay include, but not be limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and/or a low dielectric constant material.

110 The lower connection wiring body PW may be in the peripheral logic insulation film. The lower connection wiring body PW may be connected to the pass transistor PTR.

The cell array structure CS may include a horizontal conductive substrate USB on the peripheral logic structure PS, and an electrode structure ST on the horizontal conductive substrate USB.

11 11 The horizontal conductive substrate USB may be on the peripheral logic structure PS. The horizontal conductive substrate USB may include a first opening OP. The first opening OPmay expose and/or be open to a part of the peripheral logic structure PS.

21 FIG. The horizontal conductive substrate USB may be a common source plate. In an example embodiment, the horizontal conductive substrate USB may serve as the common source line CSL of. The horizontal conductive substrate USB may include, but not be limited to, a conductive semiconductor film, a metal silicide film, and/or a metal film.

In an example embodiment, the horizontal conductive substrate USB may be formed as a plurality of layers or a single layer.

148 148 1 22 FIG. A filling insulation filmmay be on the peripheral logic structure PS. The filling insulation filmmay fill the first opening OP. The electrode structure ST may be on the horizontal conductive substrate USB. The electrode structure ST may cover a part of the horizontal conductive substrate USB. In an example embodiment, the horizontal conductive substrate USB may include a first region that may at least partially overlap the electrode structure ST in the vertical direction Z, and a second region that may not overlap the electrode structure ST in the vertical direction Z. The second region of the horizontal conductive substrate USB may include the plate contact plug region PCC_R in.

1 2 3 4 5 6 7 8 1 8 The electrode structure ST may include a plurality of electrode pads (e.g., first electrode pad EP, second electrode pad EP, third electrode pad EP, fourth electrode pad EP, fifth electrode pad EP, sixth electrode pad EP, seventh electrode pad EP, and eighth electrode pad EP) stacked in the vertical direction Z. The electrode structure ST may include an inter-electrode insulation film ILD between the plurality of electrode pads EPto EP.

1 2 22 FIG. The electrode structure ST may include an insulating mold part IMS. The insulating mold part IMS may at least partially overlap the first opening OPof the horizontal conductive substrate USB in the vertical direction Z. The insulating mold part IMS may include the second penetration electrode region THV_Rin. The insulating mold part IMS may include an inter-electrode insulation film ILD and a sacrificial mold insulation film ILD_SC having an etching selection ratio. The inter-electrode insulation film ILD and the sacrificial mold insulation film ILD_SC may be alternately stacked. For example, the inter-electrode insulation film ILD may include silicon oxide (SiO), and the sacrificial mold insulation film ILD_SC may include silicon nitride (SiN).

1 The word-line cut region WLC may be disposed in the electrode structure ST. The word-line cut region WLC may extend in the first direction X. Each word-line cut region WLC may be spaced apart from each other in the second direction Y. Each word-line cut region WLC may completely cut the electrode structure ST. The electrode structure ST cut by the two adjacent word-line cut region WLC may form one of the memory blocks BLKto BLKz.

A plurality of vertical structures VS may be on the horizontal conductive substrate USB. The plurality of vertical structures VS may at least partially penetrate the electrode structure ST. The plurality of vertical structures VS may be electrically connected to the horizontal conductive substrate USB. The vertical structures VS may include side wall parts that may extend in the vertical direction Z, and a bottom part that may connect the side wall parts of the vertical structure VS. The side wall parts of the vertical structures VS may have a pipe shape having a hollow space inside (e.g., a cylindrical shape or a macaroni shape).

142 142 144 146 142 144 A first interlayer insulation filmmay be on the peripheral logic structure PS. The first interlayer insulation filmmay at least partially cover the electrode structure ST and the horizontal conductive substrate USB. A second interlayer insulation filmand a third interlayer insulation filmmay be sequentially formed on the first interlayer insulation film. A part of the word-line cut region WLC may extend to the second interlayer insulation film.

The bit-lines BL may be on the stacked structure ST. The bit-lines BL may extend in the second direction Y. The bit lines BL may be electrically connected to at least one of the plurality of vertical structures VS.

146 The bit-lines BL may be on a third interlayer insulation film. The bit-lines BL may be electrically connected to the vertical structures VS via a bit-line pad BL_PAD and a bit-line plug BL_PG. The bit-lines BL, the bit-line pad BL_PAD, and the bit-line plug BL PG may each include a conductive material.

142 144 146 A plurality of electrode plugs WL_PG may be in the first to third interlayer insulation films (e.g., first interlayer insulation film, second interlayer insulation film, and third interlayer insulation film). The plurality of electrode plugs WL_PG may be in the cell extension region CER.

1 8 1 8 Each electrode plug WL_PG may be electrically connected to the respective electrode pads EPto EP. The respective electrode plugs WL_PG may connect the respective electrode pads EPto EPand a word line connection wiring WL_CW.

1 1 1 1 142 146 110 1 1 1 A first penetration electrode THVmay be in the first penetration electrode region THV_R. The first penetration electrode THVmay extend in the vertical direction Z. The first penetration electrode THVmay be in the first to third interlayer insulation filmstoand the peripheral logic insulation film. The first penetration electrode THVmay not completely penetrate the electrode structure ST. The first penetration electrode THVmay be connected to a lower connection wiring body PW and a first penetration electrode connection wiring THV_CW.

1 1 1 142 146 1 A first plate contact plug PCCmay be in a plate contact plug region PCC_R. The first plate contact plug PCCmay extend in the vertical direction Z. The first plate contact plug PCCmay be in the first to third interlayer insulation filmsto. The first plate contact plug PCCmay not completely penetrate the stacked structure ST.

1 1 1 1 1 The first plate contact plug PCCmay be connected to the horizontal conductive substrate USB. The first plate contact plug PCCmay be electrically connected to the horizontal conductive substrate USB in the second region of the horizontal conductive substrate USB. The first plate contact plug PCCmay be connected to the first plate contact connection wiring PCC_CW. A part of the first plate contact plug PCCmay be in the horizontal conductive substrate USB.

2 2 2 2 148 110 2 2 2 1 2 2 A second penetration electrode THVmay be in the second penetration electrode region THV_R. The second penetration electrode THVmay extend in the vertical direction Z. The second penetration electrode THVmay be in the insulating mold part IMS, the filling insulation film, and the peripheral logic insulation film. The second penetration electrode THVmay at least partially penetrate the stacked structure ST (e.g., the insulating mold part IMS). The second penetration electrode THVmay be in the cell array region CR. The second penetration electrode THVmay pass through the first opening OP. The second penetration electrode THVmay be connected to the lower connection wiring body PW and the second penetration electrode connection wiring THV_CW.

24 FIG. is a diagram for describing manufacturing processes of a stacked semiconductor device, according to example embodiments.

24 FIG. 24 FIG. 1 2 1 2 1 2 1 2 1 2 1 2 Referring to, respective integrated circuits may be formed in a first wafer WFand a second wafer WF. The same circuits may be integrated in the first wafer WFand the second wafer WFand/or different circuits may be integrated in the first wafer WFand the second wafer WF. For example, a memory cell array may be formed in the first wafer WFand other circuits may be formed in the second wafer WF. Even thoughillustrates the vertical stacking of the two wafers WFand WF(e.g., first wafer WFis stacked on second wafer WF), three or more wafers may be stacked vertically.

1 2 1 2 1 2 1003 1 2 1 2 1 1 2 2 After the integrated circuits are formed in the first and second wafers WFand WF, the first wafer WFand the second wafer WFmay be bonded. The bonded first and second wafers WFand WFmay be cut and divided into a plurality of chips, where each chip corresponds to a semiconductor deviceincluding a first semiconductor die SDand a second semiconductor die SDthat are stacked vertically (e.g., the first semiconductor die SDis stacked on the second semiconductor die SD). Each cut portion of the first wafer WFmay correspond to the first semiconductor die SDand each cut portion of the second wafer WFmay correspond to the second semiconductor die SD.

1003 1 2 1 2 1 1 2 According to example embodiments, the semiconductor devicemay include first and second semiconductor dies SDand SDthat may be stacked in the vertical direction. Each of the first and second semiconductor dies SDand SDmay include a central region and an external region at least partially surrounding the central region. A semiconductor integrated circuit may be formed in the central region of the first semiconductor die SD. A 3D detection structure may be formed in the external region of the first semiconductor die SDand the second semiconductor die SD. In some example embodiments, the 3D detection structure may include a single conduction loop, and/or may include two conduction loops as described above.

25 26 FIGS.and are cross-sectional diagrams illustrating a vertical structure of a 3D detection structure, according to example embodiments.

25 FIG. 1 2 1 2 2 2 2 2 1 2 1 1 2 2 2 1 2 1 2 2 Referring to, a 3D detection structure DSd may be formed in a first semiconductor die SDand a second semiconductor die SD. A memory cell structure may be formed in the first semiconductor die SDand a peripheral circuit may be formed in the second semiconductor die SD. The second semiconductor die SDmay include a semiconductor substrate SUBand a dielectric layer DLYin which upper structures of the second semiconductor substrate SUBmay be formed. The first and second semiconductor dies SDand SDmay include a plurality of conduction layers. For example, the first semiconductor die SDmay include a first metal layer ML, and the dielectric layer DLYmay include a second metal layer MLand a second polysilicon layer PL. The first and second metal layers MLand MLmay be the uppermost metal layers in the respective semiconductor dies SDand SD. The second polysilicon layer PLmay include a gate polysilicon layer in which gates of transistors in the semiconductor integrated circuits may be formed.

1 1 2 2 The 3D detection structure DSd may include a plurality of top horizontal line segments HLT formed in the first conduction layer MLof the first semiconductor die SD(e.g., the uppermost semiconductor die in the stacked structure), a plurality of bottom horizontal line segments HLB formed in the second conduction layer PLof the second semiconductor die SD(e.g., the lowest semiconductor die in the stacked structure) and a plurality of vertical line segments VL connecting the top horizontal line segments HLT and the bottom horizontal line segments HLB respectively to form the 3D detection structure DSd.

25 FIG. 1 1 2 2 1 1 1 2 2 2 In the embodiment of, the first conduction layer MLmay correspond to an uppermost metal layer from among the metal layers of the first semiconductor die SD, and the second conduction layer PLmay correspond to the polysilicon layer of the second semiconductor die SD. The top horizontal line segments HLT may include first metal line patterns MPformed in the metal layer MLof the first semiconductor die SD, and the bottom horizontal line segments HLB may include polysilicon line patterns PPformed in the polysilicon layer PLof the second semiconductor die SD.

1 2 1 1 2 1 2 2 25 FIG. The vertical line segments VL may include first vertical contacts VC, through-substrate vias TSV, and second vertical contacts VCto connect the metal line patterns MPin the first metal layer MLand the polysilicon line patterns PP in the polysilicon layer PL. As shown in, the vertical contacts may include the through-substrate vias TSV at least partially penetrating the first semiconductor die SD. The vertical line segments VL may further include second conduction line patterns MPformed in the intermediate second metal layers ML.

26 FIG. 1 1 2 Referring to, a 3D detection structure DSd may include a plurality of top horizontal line segments HLT that may be formed in the first conduction layer MLof the first semiconductor die SD(e.g., the uppermost semiconductor die in the stacked structure), a plurality of bottom horizontal line segments HLB that may be formed in the second conduction layer MLB of the second semiconductor die SD(e.g., the lowest semiconductor die in the stacked structure), and a plurality of vertical line segments VL connecting the top horizontal line segments HLT and the bottom horizontal line segments HLB respectively to form the 3D detection structure DSd.

26 FIG. 1 1 2 2 1 1 1 2 In the embodiment of, the first conduction layer MLmay correspond to an uppermost metal layer from among the metal layers of the first semiconductor die SD, and the second conduction layer PLmay correspond to the metal layer on the bottom surface of the second semiconductor die SD. The top horizontal line segments HLT may include metal line patterns MPthat may be formed in the metal layer MLof the first semiconductor die SD, and the bottom horizontal line segments HLB may include bottom metal line patterns MPB formed in the bottom metal layer MLB on the bottom surface of the second semiconductor die SD.

1 2 2 1 1 1 2 1 2 2 2 2 2 30 FIG. The vertical line segments VL may include vertical contacts first through-substrate vias TSV, second vertical contact VCand second through-substrate vias TSVto connect the first metal line patterns MPin the first metal layer MLand the bottom metal line patterns MPB in the bottom metal layer MLB. As shown in, the vertical contacts may include the first and second through-substrate vias TSVand TSVat least partially penetrating the first semiconductor die SDand the second semiconductor die SD, respectively. The vertical line segments VL may further include second conduction line patterns MPand PPrespectively formed in the intermediate conduction layers MLand PL.

25 26 FIGS.and As described with reference to, the 3D detection structure DSd, according to example embodiments, may be expanded in the vertical direction Z to various depths.

27 FIG. 1 FIG. is a block diagram illustrating an example of the semiconductor device in, according to example embodiments.

27 FIG. 500 510 520 530 700 540 550 560 570 610 585 590 650 625 235 620 Referring to, the semiconductor devicemay be a volatile memory device and may include the control logic circuit, an address register, a bank control logic, a refresh control circuit, a row address multiplexer, a column address latch, a row decoder, a column decoder, a memory cell array, a sense amplifier unit, an I/O gating circuit, an error correction code (ECC) engine, a clock buffer, a strobe signal generatorand a data I/O buffer.

610 610 610 560 560 560 610 610 570 570 570 610 610 585 585 585 610 610 a s a s a s a s a s a s a s. The memory cell arraymay include first to sixteenth bank arraysto. The row decodermay include first to sixteenth row decoderstorespectively coupled to the first to sixteenth bank arraysto, the column decodermay include first to sixteenth column decoderstorespectively coupled to the first to sixteenth bank arraysto, and the sense amplifier unitmay include first to sixteenth sense amplifierstorespectively coupled to the first to sixteenth bank arraysto

610 610 560 560 570 570 585 585 610 610 a s a s a s a s a s The first to sixteenth bank arraysto, the first to sixteenth row decodersto, the first to sixteenth column decoderstoand first to sixteenth sense amplifierstomay form first to sixteenth banks. Each of the first to sixteenth bank arraystomay include a plurality of memory cells MC that may be formed at intersections of a plurality of word-lines WL and a plurality of bit-lines BL.

520 520 530 540 550 The address registermay receive the address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from an external memory controller. The address registermay provide the received bank address BANK_ADDR to the bank control logic, may provide the received row address ROW_ADDR to the row address multiplexer, and may provide the received column address COL_ADDR to the column address latch.

530 560 560 570 570 a s a s The bank control logicmay generate bank control signals in response to the bank address BANK_ADDR. One of the first to sixteenth row decoderstocorresponding to the bank address BANK_ADDR may be activated in response to the bank control signals, and one of the first to sixteenth column decoderstocorresponding to the bank address BANK_ADDR may be activated in response to the bank control signals.

540 520 700 540 540 560 560 a s. The row address multiplexermay receive the row address ROW_ADDR from the address register, and may receive a refresh row address REF_ADDR from the refresh control circuit. The row address multiplexermay selectively output the row address ROW_ADDR and/or the refresh row address REF_ADDR as a row address SRA. The row address SRA that is output from the row address multiplexermay be applied to the first to sixteenth row decodersto

700 510 The refresh control circuitmay sequentially increase and/or decrease the refresh row address REF_ADDR in a normal refresh mode under control the control logic circuit.

560 560 530 540 a s The activated one of the first to sixteenth row decodersto, by the bank control logic, may decode the row address SRA that may be output from the row address multiplexer, and may activate a word-line corresponding to the row address SRA. For example, the activated bank row decoder may apply a word-line driving voltage to the word-line corresponding to the row address.

550 520 550 550 570 570 a s. The column address latchmay receive the column address COL_ADDR from the address register, and may temporarily store the received column address COL_ADDR. In some embodiments, in a burst mode, the column address latchmay generate column address COL_ADDR′ that increment from the received column address COL_ADDR. The column address latchmay apply the temporarily stored or generated column address COL_ADDR′ to the first to sixteenth column decodersto

570 570 590 a s The activated one of the first to sixteenth column decoderstomay activate a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the I/O gating circuit.

590 610 610 610 610 a s a s. The I/O gating circuitmay include a circuitry for gating I/O data, and may further include input data mask logic, read data latches for storing data that is output from the first to sixteenth bank arraysto, and write drivers for writing data to the first to sixteenth bank arraysto

610 610 620 650 620 a s Codeword CW that may be read from a selected one bank array of the first to sixteenth bank arraystomay be sensed by a sense amplifier coupled to the selected one bank array from which the data is to be read, and may be stored in the read data latches. The codeword CW stored in the read data latches may be provided to the data I/O bufferas data DTA after ECC decoding is performed on the codeword CW by the ECC engine. The data I/O buffermay convert the data DTA into the data signal DQ and may transmit the data signal DQ along with the data strobe signal DQS to the memory controller.

610 610 620 620 650 650 650 590 590 a s The data signal DQ to be written in a selected one bank array of the first to sixteenth bank arraystomay be provided to the data I/O bufferfrom the memory controller. The data I/O buffermay convert the data signal DQ to the data DTA and may provide the data DTA to the ECC engine. The ECC enginemay perform an ECC encoding on the data DTA to generate parity bits, and the ECC enginemay provide the codeword CW including data DTA and the parity bits to the I/O gating circuit. The I/O gating circuitmay write the codeword CW in a sub-page in the selected one bank array through the write drivers.

620 650 500 650 500 The data I/O buffermay provide the data signal DQ from the memory controller to the ECC engineby converting the data signal DQ to the data DTA in a write operation of the semiconductor device, may convert the data DTA to the data signal DQ from the ECC engine, and may transmit the data signal DQ and the data strobe signal DQS to the memory controller in a read operation of the semiconductor device.

650 2 510 The ECC enginemay perform an ECC encoding on the data DTA and may perform an ECC decoding on the codeword CW based on a second control signal CTLfrom the control logic circuit.

525 The clock buffermay receive the clock signal CK, may generate an internal clock signal ICK by buffering the clock signal CK, and may provide the internal clock signal ICK to circuit components processing the command CMD and the address ADDR.

535 620 The strobe signal generatormay receive the clock signal CK, may generate the data strobe signal DQS based on the clock signal CK, and may provide the data strobe signal DQS to the data I/O buffer.

510 500 510 500 510 511 512 500 The control logic circuitmay control operations of the semiconductor device. For example, the control logic circuitmay generate control signals for the semiconductor devicein order to perform a write operation, a read operation, a normal refresh operation. The control logic circuitmay include a command decoderthat may decode the command CMD received from the memory controller and a mode registerthat may set an operation mode of the semiconductor device.

511 510 1 590 2 650 For example, the command decodermay generate the control signals corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, and the like. The control logic circuitmay provide a first control signal CTLto the I/O gating circuit, and a second control signal CTLto the ECC engine.

510 The above-discussed method of detecting an opening may be performed in an idle mode in which the control logic circuitdoes not receive any commands from a memory controller and/or does not perform operation based on command received from the memory controller or in a specific diagnostic mode.

28 FIG. 27 FIG. illustrates an example of the first bank array in the semiconductor device of, according to example embodiments.

28 FIG. 610 0 0 0 0 0 0 0 1 a Referring to, the first bank arraymay include a plurality of word-lines WLto WLm−1 (where m is a positive integer greater than or equal to two (2)), a plurality of bit-lines BLto BLn−1 (where n is a positive integer greater than or equal to two (2)), and a plurality of memory cells MCs disposed at intersections between the word-lines WLto WLm−1 and the bit-lines BLto BLn−1. Each of the memory cells MCs may include a cell transistor coupled to each of the word-lines WLto WLm−1 and each of the bit-lines BLto BLn−1, and a cell capacitor coupled to the cell transistor. Each of the memory cells MCs may have a dynamic random-access memory (DRAM) cell structure. Each of the word-lines WLto WLm−1 may extend in a first direction X and each of the bit-lines BLto BLn−1 may extend in a second direction Y crossing the first direction X.

29 FIG. 30 FIG. 31 FIG. 30 FIG. is a plan view illustrating a semiconductor device, according to example embodiments.is a plan view illustrating a semiconductor device, according to example embodiments.is a cross-sectional view taken along a line III-III′ of, according to example embodiments.

29 FIG. Referring to, a wafer WF is illustrated for describing manufacturing processes of a semiconductor device according to example embodiments. A plurality of chip regions CPR and scribe lanes SL at least partially surrounding the chip regions CPR may be formed in the wafer WF. The wafer WF may be cut along the scribe lanes SL and may be divided into a plurality of dies.

30 FIG. A plurality of wafers may be bonded to form a plurality of semiconductor devices. A target portion TG in the wafer WF is described with reference to.

30 FIG. 29 FIG. is an enlarged diagram of a target portion TG infor describing a semiconductor device, according to example embodiments.

30 FIG. 800 820 850 820 850 800 830 830 831 832 Referring to, a semiconductor devicemay include a chip region CPR, a scribe lane SL along an edge of the chip region CPR, a detection structure, and a detection circuit OSCconnected to the detection structurethrough a switch SW. The detection circuitmay be an oscilloscope circuit. The semiconductor devicemay further include a dam region DM including a dam structure, which may be disposed between the chip region CPR and the scribe lane SL. The dam region DM may isolate the chip region CPR and the scribe lane SL and may have a ring shape or a close curve in planar view. The dam structureincluding at least one dam (e.g., first damand second dam) may be disposed in the dam region DM.

The chip region CPR may be a region in which elements operating on a chip may be formed. The chip region CPR may have a ring shape and/or a rectangular ring-shape, but the present disclosure is not limited thereto.

The scribe lane SL, at least partially surrounding the chip region CPR, may be an area having a space margin in case of a damaged part when dicing the wafer WF to a chip. The scribe lane SL may have a ring shape and/or a rectangular ring-shape that may correspond to a shape of the chip region CPR.

In the scribe lane SL, various patterns such as, but not limited to, a mark pattern, a key pattern and patterns may be formed for fabrication monitoring and device test.

861 861 820 820 a b 31 FIG. In example embodiments, bonding metal patterns including bonding metals (e.g., first bonding metalsand second bonding metalsof) associated with bonding chips may be formed in the scribe lane SL. The detection structuremay be disposed in the scribe lane SL and the bonding metal patterns may constitute the detection structure.

1 FIG.A 1 FIG.A 820 820 1 2 The chip region CPR may correspond to the central region CTREG in, the scribe lane SL may correspond to a portion of the external region EREG inand the detection structuremay be formed in the scribe lane SL around the chip region CPR in the external region. The detection structuremay include a first end ETand a second end ET.

800 1 2 1 2 31 FIG. The semiconductor devicemay have may have a chip-to-chip (C2C) structure in which a first chip CPis located on a second chip CP. In, a bonding surface BS is illustrated at which the first chip CPis coupled to the second chip CP.

31 FIG. 1 2 1 2 861 862 820 850 820 a a Referring to, in the scribe lane SL, the first chip CPmay include a first bonding metal pattern and the second chip CPmay include a second bonding metal pattern. The first chip CPand the second chip CPmay be coupled to each other by the first bonding metal and the second bonding metal being bonded to each other. When first bonding metalsconstituting the first bonding metal pattern and second bonding metalsconstituting the second bonding metal pattern are not properly connected to each other due to fabrication problems and/or openings, electrical signals may not be transferred to the detection structurein the scribe lane SL or abnormal phenomenon occurs in the electrical signals. Therefore, the detection circuitmay determine whether an opening occurs in the scribe lane SL based on the electrical signals in the detection structure.

31 FIG. 820 861 862 881 882 871 871 881 882 850 871 871 881 882 861 862 881 882 861 862 881 882 830 881 882 830 a a a a a b a a a b a a a a a a a a a a a a Continuing to refer to, the detection structuredisposed on the scribe lane SL may include the first bonding metals, the second bonding metals, first and second horizontal linesand, and first and second contact plugsand. The first and second horizontal linesandmay be electrically connected to the detection circuit OSC. The first and second contact plugsandmay connect the first and second horizontal linesandto the first and second bonding metalsand, respectively. At least one of the first and second horizontal linesandmay be connected to a connection wire structure extending from the chip region CPR to the scribe lane SL for electrical connection with the first and second bonding metalsand. For example, the at least one of the first and second horizontal linesandmay at least partially penetrate through the dam structure. The at least one of the first and second horizontal linesandmay be insulated from the dam structure.

830 830 830 1 2 830 830 The dam structuremay be a region that separates the chip region CPR and the scribe lane SL. The dam structuremay define the chip region CPR and the scribe lane SL by at least partially surrounding the chip region CPR. The dam structuremay separate the chip region CPR and the scribe lane SL by at least partially penetrating the first chip CPand the second chip CPvertically. The dam structuremay prevent a crack occurring in the scribe lane SL from entering the chip region CPR. The dam structuremay prevent external moisture from entering the chip region CPR.

830 830 831 832 831 832 831 831 832 The dam structuremay include at least one dam. For example, the dam structuremay include an inner damand an outer dam. The inner dammay at least partially surround the chip region CPR adjacently to the chip region CPR and the outer dammay at least partially surround the inner damadjacently to the scribe lane. Each of the inner damand the outer dammay have shape corresponding to a shape of the chip region CPR.

830 820 831 832 831 1 832 2 The dam structuremay include a through-electrode via (THV) through which the detection structuremay pass. For example, each of the inner damand the outer daminclude a THV. The inner dammay include a first THV THand the outer dammay include a second THV TH.

800 820 850 1 2 820 1 2 820 850 1 2 820 1 2 820 In the semiconductor device, a location of the opening in the scribe lane SL may be determined based on a discharging time interval of the detection structureby connecting a line of the detection circuitto at least one of the first end ETand the second end ETof the detection structureor to the first end ETand the second end ETof the detection structuresequentially through the switch SW. In addition, a location of the opening in the scribe lane SL may be determined based on a number based on a period of the clock signal and a number of periods of the clock signal during a reference time interval by generating the clock signal based on connecting a line of the detection circuitto at least one of the first end ETand the second end ETof the detection structureor to the first end ETand the second end ETof the detection structuresequentially

32 FIG. is a cross-sectional view of a semiconductor device, according to example embodiments.

32 FIG. 2000 2000 Referring to, a semiconductor devicemay be a non-volatile memory device and may have a C2C structure. Hereinafter, the semiconductor devicemay be referred to as a non-volatile memory device. The C2C structure may refer to a structure formed by manufacturing an upper chip including a memory cell region or a cell region CELL on a first wafer, manufacturing a lower chip including a peripheral circuit region PERI on a second wafer, separate from the first wafer, and then bonding the upper chip and the lower chip to each other. As used herein, the bonding process may include a method of electrically connecting a bonding metal formed on an uppermost metal layer of the upper chip and a bonding metal formed on an uppermost metal layer of the lower chip. For example, when the bonding metals include copper (Cu), the bonding process may use a Cu-to-Cu bonding. However, the present disclosure may not be limited thereto. For example, the bonding metals may also be formed of and/or may include, but not be limited to, aluminum (Al) or tungsten (W).

2000 Each of the peripheral circuit region PERI and the cell region CELL of the non-volatile memory devicemay include an external pad bonding area PA, a word-line bonding area WLBA, and a bit-line bonding area BLBA.

2210 2215 2220 2220 2220 2210 2230 2230 2230 2220 2220 2240 2240 2240 2230 2230 2230 2230 2240 2240 a b c a b c a c a b c a c a c a c The peripheral circuit region PERI may include a first substrate, an interlayer insulating layer, a plurality of circuit elements (e.g.,,, and) formed on the first substrate, first metal layers (e.g.,,, and) respectively connected to the plurality of circuit elementsto, and second metal layers (e.g.,,, and) formed on the first metal layersto. In an example embodiment, the first metal layerstomay be formed of and/or may include tungsten (W) having relatively high electrical resistivity, and the second metal layerstomay be formed of and/or may include copper (Cu) having relatively low electrical resistivity.

22 FIG. 2230 2230 2240 2240 2230 2230 2240 2240 2240 2240 2240 2240 a c a c a c a c a c a c. In an example embodiment shown in, although only the first metal layerstoand the second metal layerstoare shown and described, the example embodiment is not limited thereto, and one or more additional metal layers may be further formed on the first metal layerstoand/or the second metal layersto. At least a portion of the one or more additional metal layers formed on the second metal layerstomay be formed of aluminum or the like having a lower electrical resistivity than those of copper forming the second metal layersto

2215 2210 2220 2220 2230 2230 2240 2240 2215 a c a c a c The interlayer insulating layermay be disposed on the first substrateand at least partially cover the plurality of circuit elementsto, the first metal layersto, and the second metal layersto. The interlayer insulating layermay include an insulating material such as, but not limited to, silicon oxide (SiO), silicon nitride (SiN), or the like.

2271 2272 2240 2271 2272 2371 2372 2271 2272 2371 2372 2371 2372 2271 2272 b b b b b b b b b b b b b b b Lower bonding metalsandmay be formed on the second metal layerin the word-line bonding area WLBA. In the word-line bonding area WLBA, the lower bonding metalsandin the peripheral circuit region PERI may be electrically bonded to upper bonding metalsandof the cell region CELL. The lower bonding metalsandand the upper bonding metalsandmay be formed of and/or may include aluminum (Al), copper (Cu), tungsten (W), or the like. As used herein, the upper bonding metalsandin the cell region CELL may be referred to as first metal pads and the lower bonding metalsandin the peripheral circuit region PERI may be referred to as second metal pads.

2310 2320 2310 2331 2332 2333 2334 2335 2336 2337 2338 2330 2310 2330 2330 The cell region CELL may include at least one memory block. The cell region CELL may include a second substrateand a common source line. On the second substrate, a plurality of word-lines (e.g., first word-line, second word-line, third word-line, fourth word-line, fifth word-line, sixth word-line, seventh word-line, and eighth word-line, hereinafter generally referred to as “”) may be stacked in a vertical direction Z (e.g., a Z-axis direction), perpendicular to an upper surface of the second substrate. At least one string selection line and at least one ground selection line may be arranged on and below the plurality of word-lines, respectively, and the plurality of word-linesmay be disposed between the at least one string selection line and the at least one ground selection line.

2310 2330 2350 2360 2350 2360 2360 2310 c c c c c In the bit-line bonding area BLBA, a channel structure CH may extend in the vertical direction Z, perpendicular to the upper surface of the second substrate, and pass through the plurality of word-lines, the at least one string selection line, and the at least one ground selection line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, and the like, and the channel layer may be electrically connected to a first metal layerand a second metal layer. For example, the first metal layermay be a bit-line contact, and the second metal layermay be a bit-line. In an example embodiment, the bit-linemay extend in a second direction Y (e.g., a Y-axis direction), parallel to the upper surface of the second substrate.

32 FIG. 2360 2360 2220 2393 2360 2371 2372 2371 2372 2271 2272 2220 2393 c c c c c c c c c c c In an example embodiment shown in, an area in which the channel structure CH, the bit-line, and the like are disposed may be referred to as the bit-line bonding area BLBA. In the bit-line bonding area BLBA, the bit-linemay be electrically connected to the circuit elementsproviding a page bufferin the peripheral circuit region PERI. The bit-linemay be connected to upper bonding metalsandin the cell region CELL, and the upper bonding metalsandmay be connected to lower bonding metalsandconnected to the circuit elementsof the page buffer.

2330 2310 2341 2342 2343 2344 2345 2346 2347 2340 2330 2340 2330 2350 2360 2340 2330 2340 2371 2372 2271 2272 b b b b b b In the word-line bonding area WLBA, the plurality of word-linesmay extend in a first direction X (e.g., an X-axis direction), parallel to the upper surface of the second substrateand perpendicular to the second direction Y, and may be connected to a plurality of cell contact plugs (e.g. first cell contact plug, second cell contact plug, third cell contact plug, fourth cell contact plug, fifth cell contact plug, sixth cell contact plug, and seventh cell contact plug, hereinafter generally referred to as “”). The plurality of word-linesand the plurality of cell contact plugsmay be connected to each other in pads provided by at least a portion of the plurality of word-linesextending in different lengths in the first direction X. A first metal layerand a second metal layermay be connected to an upper portion of the plurality of cell contact plugsconnected to the plurality of word-lines, sequentially. The plurality of cell contact plugsmay be connected to the peripheral circuit region PERI by the upper bonding metalsandof the cell region CELL and the lower bonding metalsandof the peripheral circuit region PERI in the word-line bonding area WLBA.

2340 2220 2394 2220 2394 2220 2393 2220 2393 2220 2394 b b c c b The plurality of cell contact plugsmay be electrically connected to the circuit elementsforming a row decoderin the peripheral circuit region PERI. In an example embodiment, operating voltages of the circuit elementsforming the row decodermay be different than operating voltages of the circuit elementsforming the page buffer. For example, operating voltages of the circuit elementsforming the page buffermay be greater than operating voltages of the circuit elementsforming the row decoder.

2380 2380 2320 2350 2360 2380 2380 2350 2360 a a a a A common source line contact plugmay be disposed in the external pad bonding area PA. The common source line contact plugmay be formed of a conductive material such as, but not limited to, a metal, a metal compound, polysilicon, or the like, and may be electrically connected to the common source line. A first metal layerand a second metal layermay be stacked on an upper portion of the common source line contact plug, sequentially. For example, an area in which the common source line contact plug, the first metal layer, and the second metal layerare disposed may be referred to as the external pad bonding area PA.

2205 2305 2201 2210 2210 2205 2201 2205 2220 2220 2203 2210 2201 2203 2210 2203 2210 a c Input/output padsandmay be disposed in the external pad bonding area PA. A lower insulating filmat least partially covering a lower surface of the first substratemay be formed below the first substrate, and a first I/O padmay be formed on the lower insulating film. The first I/O padmay be connected to at least one of the plurality of circuit elementstodisposed in the peripheral circuit region PERI through a first I/O contact plug, and may be separated from the first substrateby the lower insulating film. In addition, a side insulating film may be disposed between the first I/O contact plugand the first substrateto electrically separate the first I/O contact plugand the first substrate.

2301 2310 2310 2305 2301 2305 2220 2220 2303 2271 2272 2305 2220 a c a a a. An upper insulating layerat least partially covering the upper surface of the second substratemay be formed on the second substrateand a second I/O padmay be disposed on the upper insulating layer. The second I/O padmay be connected to at least one of the plurality of circuit elementstodisposed in the peripheral circuit region PERI through a second I/O contact plugand/or lower bonding metalsand, and the like. In the example embodiment, the second I/O padmay be electrically connected to a circuit element

2310 2320 2303 2305 2330 2303 2310 2310 2315 2305 According to example embodiments, the second substrateand the common source linemay not be disposed in an area in which the second I/O contact plugis disposed. Alternatively or additionally, the second I/O padmay not overlap the word-linesin the vertical direction Z. The second I/O contact plugmay be separated from the second substratein the direction, parallel to the upper surface of the second substrate, and may pass through the interlayer insulating layerof the cell region CELL to be connected to the second I/O pad.

2205 2305 2000 2205 2210 2305 2310 2000 2205 2305 According to example embodiments, the first I/O padand the second I/O padmay be selectively formed. For example, the non-volatile memory devicemay include only the first I/O paddisposed on the first substrateor the second I/O paddisposed on the second substrate. Alternatively or additionally, the non-volatile memory devicemay include both the first I/O padand the second I/O pad.

A metal pattern provided in an uppermost metal layer may be provided as a dummy pattern or the uppermost metal layer may be absent, in each of the external pad bonding area PA and the bit-line bonding area BLBA, respectively included in the cell region CELL and the peripheral circuit region PERI.

2000 2273 2372 2372 2273 2372 2273 2273 2372 2371 2372 a a a a a a a a b b. In the external pad bonding area PA, the non-volatile memory devicemay include a lower metal pattern, corresponding to an upper metal patternformed in an uppermost metal layer of the cell region CELL, and having a substantially similar and/or the same cross-sectional shape as the upper metal patternof the cell region CELL so as to be connected to each other, in an uppermost metal layer of the peripheral circuit region PERI. In the peripheral circuit region PERI, the lower metal patternformed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a contact. Similarly, in the external pad bonding area PA, an upper metal pattern, corresponding to the lower metal patternformed in an uppermost metal layer of the peripheral circuit region PERI, and having a substantially similar and/or the same shape as a lower metal patternof the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL. The upper metal patternmay be included in upper bonding metalsand

2271 2272 2240 2271 2272 2371 2372 b b b b b b b The lower bonding metalsandmay be formed on the second metal layerin the word-line bonding area WLBA. In the word-line bonding area WLBA, the lower bonding metalsandof the peripheral circuit region PERI may be electrically connected to the upper bonding metalsandof the cell region CELL by a Cu-to-Cu bonding.

2392 2252 2252 2392 2252 2271 2272 b b. In the bit-line bonding area BLBA, an upper metal pattern, corresponding to a lower metal patternmay be formed in the uppermost metal layer of the peripheral circuit region PERI, and having a substantially similar and/or the same cross-sectional shape as the lower metal patternof the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL. A contact may not be formed on the upper metal patternformed in the uppermost metal layer of the cell region CELL. The lower metal patternmay be included in lower bonding metalsand

In an example embodiment, corresponding to a metal pattern formed in an uppermost metal layer in one of the cell region CELL and the peripheral circuit region PERI, a reinforcement metal pattern having a substantially similar and/or the same cross-sectional shape as the metal pattern, may be formed in an uppermost metal layer in the other one of the cell region CELL and the peripheral circuit region PERI. A contact may not be formed on the reinforcement metal pattern.

2271 2272 2371 2372 b b b b The word-line voltages may be applied to at least one memory block in the cell region CELL through the lower bonding metalsandin the peripheral circuit region PERI and upper bonding metalsandof the cell region CELL.

33 FIG. 32 FIG. is a plan view illustrating a peripheral circuit region in the semiconductor device of, according to example embodiments.

33 FIG. 1 2 3 1 1 1 2 2 1 2 3 3 2 4 4 2 3 1 3 Referring to, the peripheral circuit region PERI may include row decoder regions (e.g., first row decoder region RDR, second row decoder region RDR, and third row decoder region RDR) disposed in the first direction X, a first page buffer driver region PBD, a first page buffer region PGR, a first internal peripheral circuit region IPER, a second page buffer region PGR, and a second page buffer driver region PBDwhich are disposed in the second direction Y between the first and second row decoder regions RDRand RDR, a third page buffer driver region PBD, a third page buffer region PGR, a second internal peripheral circuit region IPER, a fourth page buffer region PGR, and a fourth page buffer driver region PBDwhich are disposed in the second direction Y between the second and third row decoder regions RDRand RDRand a pad region PDR adjacent to the first to third row decoder regions RDRto RDRin the second direction Y.

1 2 3 4 1 2 3 4 The first and second page buffer regions PGRand PGRmay be spaced apart from each other in the second direction Y and the page buffer regions PGRand PGRmay be spaced apart from each other in the second direction Y. The buffer regions PGRand PGRmay be spaced apart from the page buffer regions PGRand PGRin the first direction X.

1 3 1 4 1 4 1 2 A row decoder may be disposed in each of the first to third row decoder regions RDRto RDR, a page buffer circuit including a plurality of page buffers may be disposed in the first to fourth page buffer regions PGRto PGR, a page buffer driver may be disposed in each of the first to fourth page buffer driver regions PBDto PBD, and a pump and selection circuits may be disposed in each of the first and second internal peripheral circuit regions IPERand IPER.

1 3 1 4 1 4 1 2 The first to third row decoder regions RDRRDR, the first to fourth page buffer regions PGRto PGR, the first to fourth page buffer driver regions PBDto PBDand the first and second internal peripheral circuit regions IPERand IPERmay correspond to a central region of the peripheral circuit region PERI.

1 4 The first to fourth page buffer regions PGRto PGRmay be referred to as a first sub circuit region, a second sub circuit region, a third sub circuit region and a fourth sub circuit region, respectively.

1 4 32 FIG. The first to fourth page buffer regions PGRto PGRmay be disposed in a region corresponding to the bit-line bonding region in.

34 FIG. 33 FIG. illustrates detection structures that are disposed in the peripheral circuit region of, according to example embodiments.

34 FIG. 1 1 2 2 3 4 Referring to, a first detection structure DSmay be formed to at least partially surround the first and second page buffer regions PGRand PGRin the central region and may be connected to a first switch SWa disposed in the pad region PDR. A second detection structure DSmay be formed to at least partially surround the third and fourth page buffer regions PGRand PGRin the central region and may be connected to a second switch SWb disposed in the pad region PDR.

930 950 930 1 1 1 950 1 1 930 950 2 5 FIG.A 7 FIG.A 5 FIG.A 7 FIG.A a a a a a Each of the first switch SWa and the second switch SWb may be connected to the detection circuitinor to the detection circuitin. The detection circuitmay precharge the first detection structure DSthrough the first switch SWa, may discharge the first detection structure DS, and may determine a location of a first opening in the first detection structure DSbased on a time interval during which a voltage at a first node reaches a reference voltage. The detection circuitmay measure a period of a clock signal generated by connecting a probe to an end of the first detection structure DSand may determine a location of a first opening in the first detection structure DSbased on counting periods of the clock signal during a reference time interval. When the detection circuitinor to the detection circuitinis connected to the second detection structure DSthrough the second switch SWb, similar description may be applied.

35 FIG. 34 FIG. illustrates a portion of the first detection structure in, according to example embodiments.

35 FIG. 34 FIG. 1 2371 2360 2371 1 2 2271 2240 2271 1 2 1 1 a a a Referring to, the first detection structure DSmay be provided by connecting alternatingly an upper bonding metalof the cell region CELL to an upper metal layerabove the upper bonding metalin the first direction X or the second direction Y at edges of the page buffer region PGR(e.g., a first sub circuit region) and page buffer region PGR(e.g., a second sub circuit region) and by connecting alternatingly a lower bonding metalof the peripheral circuit region PERI to a lower metal layerbelow the lower bonding metalin the first direction X or the second direction Y at the edges of the page buffer region PGR(e.g., a first sub circuit region) and page buffer region PGR(e.g., a second sub circuit region). The first detection structure DSmay alternatingly pass via a boundary of the cell region CELL and the peripheral circuit region PERI such as a chain configuration. At least one of a first end and a second end of the first detection structure DSmay be connected to the first switch SWa in.

2 2371 2360 2371 3 4 2271 2240 2271 3 4 2 2 34 FIG. The second detection structure DSmay be provided by connecting alternatingly an upper bonding metalof the cell region CELL to an upper metal layerabove the upper bonding metalin the first direction X or the second direction Y at edges of the page buffer region PGR(e.g., a third sub circuit region) and page buffer region PGR(e.g., a fourth sub circuit region) and by connecting alternatingly a lower bonding metalof the peripheral circuit region PERI to a lower metal layerbelow the lower bonding metalin the first direction X or the second direction Y at the edges of the page buffer region PGR(e.g., a third sub circuit region) and page buffer region PGR(e.g., a fourth sub circuit region). The second detection structure DSmay alternatingly pass via a boundary of the cell region CELL and the peripheral circuit region PERI such as a chain configuration. At least one of a first end and a second end of the second detection structure DSmay be connected to the second switch SWb in.

A detection structure according to example embodiments may be may be applied to any electronic devices and systems formed using semiconductor dies. For example, the present disclosure may be applied to systems such as a personal computer (PC), a server computer, a data center, a workstation, a mobile phone, a smart phone, a tablet computer, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a portable game console, a music player, a camcorder, a video player, a navigation device, a wearable device, an internet of things (IoT) device, an internet of everything (IoE) device, an e-book reader, a virtual reality (VR) device, an augmented reality (AR) device, a robotic device, a drone, an automotive, or the like.

The foregoing description is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art may appreciate that many modifications may be possible in the example embodiments without materially departing from the teachings and advantages of the present disclosure. Accordingly, such modifications are intended to be included within the scope of the present disclosure as defined in the claims.